CN110297662A - Instruct method, processor and the electronic equipment of Out-of-order execution - Google Patents
Instruct method, processor and the electronic equipment of Out-of-order execution Download PDFInfo
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- CN110297662A CN110297662A CN201910600769.XA CN201910600769A CN110297662A CN 110297662 A CN110297662 A CN 110297662A CN 201910600769 A CN201910600769 A CN 201910600769A CN 110297662 A CN110297662 A CN 110297662A
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Abstract
The invention discloses a kind of method, processor and electronic equipments for instructing Out-of-order execution.It is the instruction distribution index label received by scoreboard, every instruction is set to have specific label, then there will be no the instructions of structural hazards and read-write venture to be preferentially sent to arithmetic unit execution, operation result is sent to again and resets sequence caching, reach after the term of delivery by index tab sequence delivery result to destination register, realizes that the Out-of-order execution of instruction is sequentially delivered.The disclosure resets sequence using scoreboard cooperation and caches, it eliminates the write-read venture in data hazard and writes venture, the applicable scene of Out-of-order execution is expanded, improve the utilization rate of arithmetic unit, waiting time by reducing instruction execution has accelerated the bulk velocity of instruction execution, reduces hardware cost.
Description
Technical field
The present invention relates to processor instruction execute field more particularly to it is a kind of instruct the method for Out-of-order execution, processor and
Electronic equipment.
Background technique
In the computer system that sequence executes, the time that different instruction needs is different, may result in during waiting
Arithmetic unit is vacant.In order to improve the operational efficiency of computer program, people need a kind of mode dynamic dispatching for planning as a whole optimization to refer to
The execution of order, executes completion in the shortest time.Out-of-order execution can reduce the arithmetic element waiting time, but may result in number
According to read-write violate the sequence of original instruction, that is, there is data hazard, call instruction operation result made not meet expection.It is existing general
Elimination write-read venture (Write-After-Read Hazard) and write venture (Write-After-Write Hazard)
Mode is register renaming (Register Renaming), but extra register required for this mode will cause chip
The increase of complexity, area and power consumption.A kind of implementation of dynamic dispatching is needed, at present to scheme the contradiction in performance and cost
It is middle to obtain good balance.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of method, processor and electronic equipment for instructing Out-of-order execution, use
In the write-read venture for solving the problems, such as to occur in instruction Out-of-order execution and write venture.
To achieve the above object, the technical solution adopted by the present invention is that: a kind of method instructing Out-of-order execution is provided, and is mentioned
For command memory, scoreboard, arithmetic unit, reset sequence caching, data storage and register.The method of the instruction Out-of-order execution
The following steps are included:
Step 101: the instruction in command memory sequentially enters scoreboard；
Step 102: scoreboard is each item instruction distribution index label received；It include the first finger in each item instruction
It enables；Scoreboard records the information of each item instruction, the index tab including recording each item instruction；Index tab sequence mode include
It is incremented by successively or successively successively decrease；
Step 103: scoreboard sequentially checks the read-write venture in the structural hazards and data hazard of each item instruction, when first
There are when structural hazards or read-write venture, the first instruction is arranged to wait state for instruction；Scoreboard can will also remove the first instruction
Except there is no structural hazards and read-write venture any item instruction be preferentially sent to corresponding arithmetic unit；When there is no structures
When venture and read-write venture or structural hazards disappear with read-write venture, then sends first and instructs to arithmetic unit,
Step 104: arithmetic unit executes the instruction received, and operation result write-in is reset in sequence caching and is received with this
The corresponding result storage locations of instruction；
Step 105: resetting sequence caching and arrange operation result by the sequence of line index label, and be sequentially finally delivered to and post
Storage.
The instruction distribution index label received is given by scoreboard, so that every instruction has distinctive mark, it will
Arithmetic unit is preferentially sent to there is no read-write venture and the instruction of structural hazards to execute, realizes Out-of-order execution, resets sequence caching
Operation result is sequentially delivered to destination register, improves the utilization rate of arithmetic unit, greatly reduces the waiting of instruction execution
Time.Scoreboard cooperation resets sequence caching, and the result of the instruction of Out-of-order execution is sequentially delivered, on scoreboard Hazard detection basis
On, it eliminates the write-read venture in data hazard or writes venture, the applicable scene of Out-of-order execution is expanded, to improve finger
Enable the bulk velocity executed.
Preferably, in step 103, scoreboard, should also to the instruction operation information for resetting each item instruction of sequence caching transmitting
Instruction operation information includes the index tab of each item instruction and the arithmetic unit information that each item instruction of execution needs to use.Instruction behaviour
Make information for ordering calculation result and index tab matching provide precondition, enable Out-of-order execution instruction result
It is mapped with index tab, ensure that instruction index tab can be correctly corresponding with ordering calculation result.It should be understood that note
It is distributional to be not limited to label information and concrete operation device information to the instruction operation information for resetting sequence caching transmitting, it can also be according to reality
Border situation transmits the necessary information that the domain in other scoreboards is stored.
It is further preferred that at step 104, after operation result write-in is reset sequence caching, resetting sequence caching according to instruction
The index tab of operation information, the operation result that each item is instructed and the instruction of each item corresponds.Operation result will be instructed
Storage corresponding with the index tab of instruction ensure that out-of-order calculated result can be according to the sequence weight predetermined in scoreboard
New arrangement, ensure that the correctness of data sequence when subsequent result is delivered.The introducing for resetting sequence caching avoids lengthy and jumbled post
Storage renaming and reservation station, from processor newly can from, not only reduce power consumption, but also reduce chip area, also reduction chip
Complexity.
Preferably, in step 105, the condition sequentially finally delivered are as follows: reset sequence caching in there are at least one instructions
Operation result and index tab, the index tab is identical with the index tab in scoreboard, the index tab include the first rope
Tendering label reset sequence caching and mark the first index when the first index tab is first index tab defined in scoreboard
The operation result of label is directly delivered to destination register, all index tabs sequence and scoreboard before the first index tab
In all index tabs it is identical, and corresponding operation result all delivered when, reset sequence caching and be delivered to operation result pair
The register answered.Ordering calculation result is delivered to destination register when meeting the term of delivery, when on the one hand ensure that delivery
Be not in deliver the label that calculated result is sky, on the other hand also ensure delivery sequence and the index tab in scoreboard
It is sequentially identical.Although, will be the most time-consuming by Out-of-order execution it sometimes appear that waiting the situation of calculated result when delivery
Calculating process be optimized to the form of parallel execution, it is this that deliver the time waited obvious compared to the time of parallel computation saving
It is more preferably solution.
Preferably, it resets sequence to be buffered in when delivery executes or after executing, exports the target information of delivery, and be finally transmitted to
Scoreboard, the target information include the index tab and register information of corresponding instruction；Scoreboard is updated according to the target information
The register occupied state of corresponding instruction.Scoreboard constantly updates the result phase of destination register, makes next and the target
The relevant instruction of register is able to execute in time after state updates, overall time needed for reducing instruction execution.It is this
Buffer status timely feedbacks mechanism, ensure that register is not vacant in use to the full extent, improves whole
Running body efficiency.
Preferably, further include the second instruction in scoreboard, when second instruction result delivered, and no longer with it is any other
When instruction is related, scoreboard removes the information of the second instruction；Scoreboard can also typing new command after removing the information that second instructs
Information.This timely design for removing the information using the instruction finished establishes the typing of old instruction elimination and new command
The articulating mechanism of optimization realizes the instruction stream aquation in scoreboard, improves the utilization rate of scoreboard, accelerate the entirety of instruction
Execute speed.
Preferably, the correspondence arithmetic unit and source operand register of each item instruction in scoreboard are being labeled occupancy for the first time
Afterwards, occupancy can not be labeled again before occupancy labeled for the first time releases, the destination register of each item instruction is marked for the first time
After note occupies, moreover it is possible to labeled to occupy at least once.The program occupies i.e. target deposit by repeatedly marking destination register
The occupied situation of the destination register having to wait in existing scheme, has been become the feelings of executable command by the scheme of device multiplexing
Shape, this expansion eliminate destination register and there is the situation write and need to wait when venture and write-read venture, be greatly enlarged
The range of executable command, so that Out-of-order execution has more realistic meaning.
It is another object of the present invention to provide a kind of processors for instructing Out-of-order execution, to solve hardware cost and property
The problem of energy contradiction.
To achieve the above object, the technical solution adopted by the present invention is that: provide it is a kind of instruct Out-of-order execution processor, packet
Arithmetic unit is included, further includes that scoreboard is cached with sequence is reset.
Scoreboard is each item instruction distribution index label received and the index tab for recording each item instruction；In scoreboard
Including indexing domain, which is used to record the index tab of each item instruction.
Resetting includes index domain in sequence caching, and index domain is used to record the index tab of each item instruction；Reset sequence caching also
In the operation result for receiving each item instruction.It resets sequence caching and is also used to the operation result of each item instruction being delivered to target and post
Storage.
Scoreboard is directly or indirectly connected with sequence caching is reset, and scoreboard finally sends out the instruction operation information that each item instructs
It send to sequence caching is reset, which includes the index tab of each item instruction and the fortune that each item instruction of execution needs to use
Calculate the concrete operation unit of device.It resets sequence caching and the target information of delivery is finally transmitted to scoreboard.The target information includes
The destination register information of instruction.Scoreboard occupies shape according to the register that target information updates instruction relevant to delivery operation
State.
Processor provided by the invention by scoreboard, arithmetic unit and is reset between sequence caching three directly or indirectly
Connection relationship, realize three between information exchange, eliminate write venture and write-read venture, realize the out of order instruction of instruction
Sequentially deliver.It does not need to greatly simplifie device composition by complex operations such as reservation station and register renamings, promoted
While the operational performance and execution efficiency of instruction, the hardware cost and wiring difficulty of processor are also reduced.
Preferably, it resets sequence caching to be directly or indirectly connected with arithmetic unit, the operation result that arithmetic unit instructs each item is most
It is transferred to eventually and resets sequence caching.Reset sequence caching according to instruction operation information by operation result input with index tab to corresponding
Operation result stores position.Sequence caching is reset by scoreboard cooperation, the result of the instruction of Out-of-order execution is sequentially delivered, was both ensured
The correct delivery of subsequent arithmetic result, and improve the bulk velocity of instruction execution.
The present invention also provides a kind of electronic equipment, which includes at least above-mentioned processor or has used above-mentioned finger
The method for enabling Out-of-order execution.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of processor for instructing Out-of-order execution provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of method for instructing Out-of-order execution provided in an embodiment of the present invention；
Fig. 3 is the state and information change figure in the embodiment of the present invention in execution process instruction；
Fig. 4 is the method combination processing device 100 that Out-of-order execution is instructed in the embodiment of the present invention and the stream of subprogram instruction
Cheng Tu；
Fig. 5 is the state table recorded in scoreboard in the embodiment of the present invention when instructing number to be greater than scoreboard capacity；
Fig. 6 is the state recorded in scoreboard in the embodiment of the present invention when instructing number to be less than or equal to scoreboard capacity
Table.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It should be noted that when an element be known as " being connected to " another element or an element with it is another
When a or multiple element " connection ", " connected ", it can be directly to another element or be indirectly connected to this another
Or in multiple element.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
Referenced herein " embodiment " is it is meant that a particular feature, structure, or characteristic described can wrap in conjunction with the embodiments
It is contained at least one embodiment of the application.Each position in the description occur the phrase might not each mean it is identical
Embodiment, nor the independent or alternative embodiment with other embodiments mutual exclusion.Those skilled in the art explicitly and
Implicitly understand, embodiment described herein can be combined with other embodiments.
The related embodiment that method, processor and the electronic equipment of instruction Out-of-order execution of the embodiment of the present invention are related to below
It is specifically described.
The embodiment of the invention provides a kind of processor for instructing Out-of-order execution, Fig. 1 is the structural representation of processor 100
Figure, the processor are only a kind of processing unit example for instructing Out-of-order execution provided in an embodiment of the present invention, in practical applications
The device is not limited to processor, is also possible to be able to achieve the other equipment etc. of instruction Out-of-order execution.The processor include with
Lower component: command memory 101, scoreboard 102, register 103, arithmetic unit 104, data storage 105 and reset sequence caching
106.Wherein, scoreboard 102 and reset sequence caching in include index domain, the index domain be used for recording instruction index tab.
As shown in Figure 1, one of input terminal of scoreboard 102 is connect with the output end of command memory 101, scoreboard
102 receive the instruction that command memory 101 exports, and the instruction distribution index label to receive；One of them of scoreboard 102
Output end is connected with one of input terminal of register 103, transmits control signal to register 103 for scoreboard 102；Note
Distributional 102 one of output end is also connected with one of input terminal of arithmetic unit 104, scoreboard 102 to instruct into
There will be no the instructions of structural hazards and read-write venture (or structural hazards and read-write venture disappear) to be sent to after row venture checks
Arithmetic unit executes；One of output end of scoreboard 102 is also connected with the one of input terminal for redirecting caching 106, uses
In scoreboard 102 to reset sequence caching 106 send instruction operation informations, the instruction operation information include instruction index tab and
Execute the concrete operation unit for the arithmetic unit that the instruction needs to use.
Arithmetic unit 104 is connected with scoreboard 102, also with register 103, data storage 105 and reset sequence caching 106
It is connected.After arithmetic unit 104 receives the instruction that scoreboard 102 is sent, in conjunction with the data in register 103 and data storage 105
To execute instruction, instruction execution result is transferred to resets sequence caching 106 later.It include at least one arithmetic in arithmetic unit 104
Logic unit assembly line and at least one load/store assembly line.
The one of input terminal for resetting sequence caching 106 is connected with one of output end of arithmetic unit 104, and it is slow to reset sequence
The instruction execution result of 106 reception arithmetic units 104 transmitting is deposited, the instruction operation information passed in conjunction with scoreboard 102 will refer to
Implementing result and the index tab of instruction is enabled to correspond；Reset the one of output end and register of sequence caching 106
103 one of input terminal is connected, and is delivered to register for resetting the operation result that sequence caching 106 is up to the term of delivery
103；The one of output end for resetting sequence caching 106 is also connected with one of input terminal of scoreboard 102, for resetting sequence
Target information is returned to scoreboard 102 by caching 106, and scoreboard 102 is according to from resetting 106 target information sent of sequence caching more
The destination register occupied state of new dependent instruction.
By scoreboard, arithmetic unit and connection relationship direct or indirect between sequence caching three is reset, realizes three
Between information exchange, it is ensured that ordering calculation result can eventually correctly be delivered to destination register, to realize the unrest of instruction
Sequence instruction is sequentially delivered, while also being eliminated write-read venture with lesser cost and being write venture.In the performance for improving instruction
While with execution efficiency, also in the hardware cost and wiring difficulty for reducing processor.
It should be appreciated that in embodiments of the present invention, alleged processor 100 can be central processing unit (Central
Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital
Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit,
ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic
Device, discrete gate or transistor logic, discrete hardware components etc..General processor can be microprocessor or this at
Reason device is also possible to any conventional processor etc..
In embodiments of the present invention, additionally provide it is a kind of instruct Out-of-order execution method, this method provide command memory,
Scoreboard, arithmetic unit, register, data storage and reset sequence caching, Fig. 2 be this method step flow chart, including with
Lower step:
Step 201: the instruction in command memory sequentially enters scoreboard.This sequentially can be the original order of instruction,
It is also possible to instruct according to sequence that is certain regularly arranged or being read.
Step 202: scoreboard receives each item instruction of command memory transmitting, and is its distribution index label, each item
It include the first instruction in instruction, scoreboard records the information of each item instruction, the index tab including recording each item instruction, the index
The sortord of label includes incremented by successively or successively successively decreases.The index tab is referred to as index value.Distribution index label
Rule there are many, can be through counter and realize, be also possible to realize by queue.Those skilled in the art exists
The index distribution method obtained under the premise of not making the creative labor, also belongs to protection scope of the present invention.Pass through counter
It realizes method particularly includes: every instruction sequentially sequentially enters scoreboard, and the initial value of counter is set first by scoreboard
The index tab of instruction, later every to enter an instruction, the value of counter is increased by or reduces, counter it is new be worth be exactly newly into
The index tab of the instruction entered.It is realized by queue method particularly includes: a queue is set, is from the beginning arrived after queue initialization
Tail successively sequentially stores the token for having 0,1,2 ... n, when having new command to enter scoreboard every time, takes out one from the head of queue
Its value is assigned to corresponding instruction by a token.When resetting sequence caching delivery instruction, the token is recycled, the tail portion of queue is put back to.
Step 203: scoreboard sequentially checks each item instruction with the presence or absence of structural hazards or read-write venture.This sequentially can be
According to index tab sequence, the enlightenment for being also possible to give according to the present invention obtain other sequence.The inspection can be to take turns
The mode of inquiry checks, is also possible to other test modes being applicable in practical application scene according to the present invention.If instruction is not
There are structural hazards and read-write venture, then follow the steps 205, if instruction has read-write venture and structural hazards, execute step
Rapid 204.Scoreboard sequentially carries out the venture inspection of each item instruction therein, can be and all refers in inspection scoreboard
It enables, the maximum value of all instructions depends on the maximum capacity of scoreboard, is also possible to successively check that the part in scoreboard refers to
It enables, specifically inspection all instructions still checks that part instruction depends on the demand to performance.When there is a plurality of instruction ready, practise
It is that arithmetic unit execution is successively sent to according to original instruction sequences on used.
Step 204: when some instruction is there are when structural hazards and read-write venture, which is to wait shape by scoreboard
State, until executing step 205 after structural hazards and read-write venture disappear.
Step 205: when instruction is there is no when structural hazards and read-write venture, it is corresponding that scoreboard sends instructions to instruction
Arithmetic unit also sends instruction operation information to resetting sequence caching, includes the index tab of instruction in the instruction operation information and holds
The arithmetic unit information used required for the row instruction.In addition, scoreboard will also instruct relevant register and arithmetic unit to be labeled as
It occupies, wherein the corresponding arithmetic unit of instruction and source operand register in scoreboard are after being marked as occupancy for the first time, at this
Occupancy cannot be labeled again by being labeled before occupying releasing for the first time, and any one destination register of the instruction in scoreboard
After being labeled occupancy for the first time, no matter occupy and whether be released from, all can also be labeled occupancy any time.It can be one this any time
It is secondary, it is also possible to 0 time, can also be that repeatedly, which depends on number of instructions involved in destination register.
Step 206: after arithmetic unit receives instruction, data needed for calling from associated data memory and register are held
The row instruction, result feeding resets sequence caching after being finished.Meanwhile scoreboard releases correlation operator and source operand deposit
The occupancy of device.It may be noted that only relieving the occupancy of arithmetic unit and source operand register herein, destination register is not released also
Occupied state.
Step 207: resetting the operation result that sequence caching receives arithmetic unit transmitting, letter is operated according to the instruction of scoreboard transmitting
Arithmetic unit result and index tab are corresponded by breath.When operation result meets the term of delivery, resetting sequence caching will fortune
It calculates result and is delivered to corresponding destination register.The term of delivery is: reset sequence caching in exist at least one instruct operation
As a result and index tab, the index tab is identical with the index tab in scoreboard, includes the first index mark in the index tab
Label, the sequence of the index tab before the first index tab and the index tab sequence before the first index tab in scoreboard
It is identical, and corresponding operation result all delivered when, reset sequence caching the corresponding operation result of the first index tab is delivered to
Corresponding register.It can be direct by the operation result of first index tab defined in scoreboard it may be noted that resetting sequence caching
It delivers.Reset sequence be buffered in execute delivery operation when or delivery operation execute after, can to scoreboard send target information, the target
Information includes corresponding index tab and register information.Scoreboard receives the target deposit of update corresponding instruction after target information
Device occupied state.
Step 208: when the result of any one in scoreboard instruction has been delivered, and the instruction and any other finger
When order does not all have data dependence, scoreboard will remove the information of the instruction；Scoreboard after removing the information can also typing it is new
Instruction, to realize the instruction stream aquation in scoreboard.
The method combination processing device 100 and subprogram instruction are briefly described below.Specifically, command memory
In existing four instructions, the maximum capacity in scoreboard is 3, i.e., three command informations can only be at most recorded in scoreboard.Fig. 3 is
State and information change figure in the embodiment of the present invention in execution process instruction.Fig. 4 is that instruction random ordering is held in the embodiment of the present invention
The flow chart of capable method combination processing device 100 and subprogram instruction.
(1) program instruction is as follows:
R0 <-mem [5] (reads data from the address memory mem 5, result is stored in register R0, occupies load/store stream
Waterline)；
R2 <-R0+R1 (reads register R0 and R1, result is stored in register R2, occupies arithmetic logic unit flowing water
Line)；
R0 <-R3+R4 (reads register R3 and R4, result is stored in register R0, occupies arithmetic logic unit flowing water
Line)；
R5 <-mem [6] (reads data from the address memory mem 6, result is stored in register R5, occupies load/store stream
Waterline).
(2) steps are as follows for execution, as shown in Figure 4:
Step 401: the above-metioned instruction in command memory enters scoreboard according to original order, and scoreboard passes through counter
For the instruction distribution index label received；Scoreboard records the information of first three instruction, including records its index tab；Herein
The sequence that index tab is arranged is positive sequence, and the mode of applicating counter is realized, the specific rules of use are as follows: the initial value of counter
It is set as 0, every instruction sequentially sequentially enters scoreboard, and scoreboard sets the initial value of counter to the index of first instruction
Label, later every to enter an instruction, the value of counter is increased by 1, and the new value of counter is exactly the index of the instruction newly entered
Label.The command status table as shown in Fig. 3 (a) is obtained after the completion of distribution index label.
Step 402: scoreboard checks that index tab is 0 instruction, needs to occupy loading/storage flowing water in arithmetic unit
Line, there are currently no instructions to occupy corresponding component, and scoreboard emits the instruction, and the instruction operation information of the instruction is sent to weight
Sequencing caching, includes the index tab 0 of instruction and arithmetic unit unit L/S used in executing instruction in instruction operation information,
As shown in Fig. 3 (b), wherein L/S indicates loading/storage assembly line.Scoreboard is also loaded onto/stores assembly line and register R0 mark
It is denoted as occupancy.
Step 403: scoreboard checks that index tab is 1 instruction, needs to occupy the arithmetic logic unit stream in arithmetic unit
Waterline ALU reads register R0 and R1, and present register R0 is occupied, can just be read after needing prior instruction to be written, i.e.,
It takes a risk in the presence of read-write, needs to wait, the arithmetic unit execution until venture is allowed for access after disappearing.
Step 404: the instruction that scoreboard inspection index is 2 needs to occupy the arithmetical logic assembly line in arithmetic unit, reads
Register R3 and R4, there are currently no instructions to occupy corresponding arithmetic unit and register.Scoreboard emits the instruction, by the instruction
Instruction operation information, which is sent to, resets sequence caching, and instruction operation information includes the index tab 1 of the instruction and executes instruction in the middle
Used arithmetic unit unit ALU, as shown in Fig. 3 (c), wherein ALU indicates arithmetic logic unit assembly line.Scoreboard will also be calculated
Art logic unit assembly line and register R0, R3 and R4 are labeled as occupancy.R0 register herein has been marked as in step 2
It occupies, still can be marked as occupying herein.
It should be noted that scoreboard carries out venture inspection to three instructions by index tab sequence.Due in arithmetic unit
Arithmetic logic unit assembly line delay be less than load/store assembly line delay, therefore index tab be 2 instruction than index
The instruction that label is 0, which first carries out, to be finished.Since the instruction that index tab is 1 has read-write venture, therefore the instruction is needed to wait and be emitted
Dangerous disappearance Shi Caineng is performed.
Step 405: the instruction that index tab is 2 is finished through arithmetic unit, as a result returns and resets sequence caching, it is slow to reset sequence
It deposits and operation result and index tab is mapped in conjunction with instruction operation information, as shown in Fig. 3 (e).Due to still there is instruction before
Result it is undetermined, so index tab be 2 instruction results can't be delivered to register R0, be in ready state.Index mark
Label for 2 instruction execution after, scoreboard release to corresponding arithmetic logic unit assembly line and source operand register R3,
The occupancy of R4.Note that it is occupancy that register R0, which is still indexed the cue mark that label is 0 and 2, at this time.
Step 406: after the instruction execution that index tab is 0, scoreboard is released to corresponding loading/storage assembly line
Occupancy, operation result return resets sequence caching.Since index tab 0 is first index tab that scoreboard defines, therefore its
Register R0 is directly delivered to after corresponding result is ready in redirecting caching.Delivery operation execute when, reset sequence cache to
Scoreboard transmits target information 0, and the target information is interior including the relevant index tab 0 of delivery operation and destination register R0, such as
Shown in Fig. 3 (i).Scoreboard receives the occupancy that instruction that index tab is 0 is released after target information 0 to register R0.At this time
It is occupancy that R0, which is also indexed the cue mark that label is 2,.At this point, in resetting sequence caching, as shown in Fig. 3 (f), although index mark
The operation result of all index tabs before label 2 has all been delivered, but the sequence of all index tabs before index tab 2
It is inconsistent with the sequence of all index tabs before index tab 2 in scoreboard, therefore it is unsatisfactory for the condition of result delivery.This
Outside, the source operand register for the instruction that the destination register in instruction for being 0 due to index tab is 1 with index tab exists
There are data dependence, scoreboard can't be removed for correlation or book.
Step 407: scoreboard continues checking the instruction that index tab is 1.The calculation in arithmetic unit is occupied without instruction at this time
Art logic unit assembly line and register R0.Scoreboard emits the instruction, and the instruction operation information of the instruction is sent to and is reset
Sequence caching includes the index tab 1 of the instruction and arithmetic logic unit stream used in executing instruction in instruction operation information
Waterline, as shown in Fig. 3 (d), wherein ALU indicates arithmetic logic unit assembly line.And by the arithmetic logic unit stream in arithmetic unit
Waterline and register R2, R0 and R1 are labeled as occupancy.At this time in resetting sequence caching, as shown in Fig. 3 (g), due to index tab
Undetermined for 1 instruction results, the result for the instruction that index tab is 2 still can not deliver.The instruction that index tab is 1 has been held
Row, the register R0 in instruction that index tab is 0 instruct non-correlation with any other in scoreboard, in other words data phase
Guan Xing, scoreboard removes the information of this instruction, and typing new command at this time, and setting index tab is 3, and scoreboard detects it and emits
Danger, it is eligible, it is sent to arithmetic unit execution, does not meet, waits, until venture disappears, subsequent execution process is herein no longer
It repeats.
Step 408: after the instruction execution that index tab is 1, as a result returning and reset sequence caching.Scoreboard releases index
The occupancy of instruction corresponding arithmetic logic unit assembly line and register R0, R1 that label is 1.At this point, as shown in Fig. 3 (h), rope
The sequence of all index tabs before tendering label 1 and all index tab sequence consensus before index tab 1 in scoreboard,
And result all delivereds are to corresponding registers, therefore the operation result of instruction that index tab is 1 meets the term of delivery, and it is slow to reset sequence
It deposits and the result is delivered to register R2, while resetting sequence and cache to scoreboard and returning to target information 1, include in the target information
The relevant index tab 1 of delivery operation and destination register R2, as shown in Fig. 3 (j).Scoreboard solves after receiving target information 1
Except index tab be 1 instruction to the occupancy of register R2.At this point, index tab is any other in 1 instruction and scoreboard
Non-correlation is instructed, in other words data dependence, scoreboard removes the information of this instruction at this time, due to not having new command to wait for
Typing, then no longer typing new command.In addition, result also all delivereds of all instructions before the instruction that index tab is 2, and
The sequence of index index tab before index tab 2 and all index tabs sequence before the index tab 2 in scoreboard
Unanimously, therefore the term of delivery has also been reached, has reset operation result of the sequence caching by index tab for 2 instruction at this time and be delivered to correspondence
Register R0, while resetting sequence and caching to scoreboard return target information 2, the interior target information includes the relevant rope of delivery operation
Tendering label 2 and destination register R0, as shown in Fig. 3 (k).Scoreboard releases the finger that index tab is 2 after receiving target information 2
Enable the occupancy to register R0.
Further, above-mentioned example can carry out being generalized in the Out-of-order execution of m item instruction, be given below and illustrate.Such as
Fig. 5 is the state table that records in scoreboard in the embodiment of the present invention when instructing number to be greater than scoreboard capacity.Specifically, refer to
Existing m item instruction in memory is enabled, most multipotency records n command information in scoreboard, and the maximum value of n depends on depositing for scoreboard
Store up maximum capacity.
When m is less than n, specific implementation procedure is as follows:
Preceding n item instruction is introduced into scoreboard according to instruction original order in command memory.Scoreboard receives n instruction simultaneously
For its distribution index label, the index method of salary distribution is described as in the previous example, and final entry is as shown in Figure 5.Scoreboard is according to index tab
Sequence poll check structural hazards and read-write venture detect that structural hazards are not present for the instruction of i in index tab and read-write emits
When dangerous, the instruction that index tab is i is sent to arithmetic unit；There is read-write venture in the instruction that index tab is j, be set to
Wait state, until venture disappears；Structural hazards and read-write venture are not present in the instruction that index tab is k, by its preferential transmission
To arithmetic unit.
In Fig. 5, when the destination register in the instruction that index is i and k is Rx, above-mentioned two instruction remains to be sent to
Arithmetic unit resets in sequence caching this is because calculated result will be temporarily stored in, can't directly be delivered to destination register.In result
When finally entering destination register, the label sequence that can also follow in scoreboard is delivered one by one, to obtain the knot that sequence is delivered
Fruit.It is apparent that the number that the destination register of instruction can be labeled occupancy is not limited to 2 times in the present embodiment.In other words, when
K indicates that identical with the i k item of destination register is taken a risk there is no read-write and when the data of structural hazards, theoretically the value range of k
It can be 1 between m-2.Accordingly it should be understood that in practical applications, the destination register of instruction can be according to actual operation demand
It is occupied by multiple label.
In one embodiment for applying of the present invention, the instruction of x item is provided and there is read-write venture and wherein suitable by index tab
First instruction index tab that there is read-write venture is y in sequence, and resetting at this time can only delivery instructions index tab in sequence caching
The instruction results for meeting the term of delivery less than y, remaining x-y-1 subsequent instructions will wait instruction index tab to be less than the instruction
All instructions in read-write venture can be delivered according to the term of delivery when completely disappearing.
After the result for the instruction that index tab is i is delivered, with other instructions in scoreboard non-correlation or nothing
When data dependence, scoreboard is removed, while by instruction thereafter toward Forward, the record of the new command of typing, which is placed in, scores
Board state table bottom end.It may be noted that the releasing in the above process occupies, operations and the previous embodiments such as sequence caching reception result are reset
Identical, details are not described herein again.
When m be less than or equal to n when, as Fig. 6 be in the embodiment of the present invention when instruct number be less than or equal to scoreboard capacity when
The state table recorded in scoreboard.M item instruction in command memory enters scoreboard according to instruction original order, and scoreboard is
Its distribution index label, as shown in Figure 6, wherein Fig. 6 (a) be m be less than n when the case where, Fig. 6 (b) be m be equal to n when the case where.
Carrying out Out-of-order execution later, sequentially the above-mentioned example of the detailed processes such as delivery operation has provided detailed description, and details are not described herein again.
It is noted that in this case, due to all instructions all typing scoreboards, therefore scoreboard is no longer recorded after removing old instruction
Enter new command.
Above-described embodiment gives the instruction distribution index label that receives by scoreboard so that every instruction have it is specific
Label, is preferentially sent to arithmetic unit there will be no the instruction of structural hazards and read-write venture and executes, then operation result sent out
Send to sequence caching is reset, reach after the term of delivery sequentially delivery result to destination register, realize the Out-of-order execution of instruction by
Sequence is delivered, and is improved the utilization rate of arithmetic unit, is greatly reduced the waiting time of instruction execution.It is slow that scoreboard cooperation resets sequence
It deposits, the result of the instruction of Out-of-order execution is sequentially delivered, on the basis of scoreboard Hazard detection, eliminate writing in data hazard
It reads venture or writes venture, the applicable scene of Out-of-order execution is expanded, to improve the bulk velocity of instruction execution.
In addition, the embodiment of the present invention further relates to a kind of electronic equipment, which includes above-mentioned processor 100, or
The method that its interior arrangement has used above-metioned instruction Out-of-order execution.The electronic equipment can be computer, server, data processing dress
Set, intelligent terminal, mobile phone, printer, sensor, wrist-watch, automobile data recorder, vehicle-mounted computer, navigator, household electrical appliance, and/or
Medical Devices.
It will be appreciated by those of ordinary skill in the art that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (10)
1. a kind of method for instructing Out-of-order execution, provides command memory, register and arithmetic unit, which is characterized in that also provide
Reset sequence caching and scoreboard, method the following steps are included:
Step 101: the instruction in described instruction memory sequentially enters the scoreboard；
Step 102: the scoreboard is each item instruction distribution index label received；It include the first finger in each item instruction
It enables；The scoreboard records the information of each item instruction, the index tab including recording each item instruction；The index mark
The mode of label sequence includes incremented by successively or successively successively decreases；
Step 103: the scoreboard is checked the structural hazards and read-write venture that each item instructs by index tab sequence, when described
When first instruction is taken a risk there are the structural hazards or the read-write, first instruction is set to wait for shape by the scoreboard
State, the scoreboard can also be by any items that the structural hazards and the read-write venture are not present in addition to first instruction
Instruction is preferentially sent to the corresponding arithmetic unit of instruction；When the structural hazards and the read-write is not present in first instruction
When venture or the structural hazards and read-write venture disappear, then the scoreboard sends first instruction to the fortune
Calculate device；
Step 104: the arithmetic unit executes the instruction received, and by operation result be written described in reset in sequence caching with it is described
The corresponding result storage locations of the instruction received；
Step 105: the sequence arrangement for resetting sequence caching by the operation result according to the index tab, and it is sequentially final
It is delivered to register.
2. the method for instruction Out-of-order execution according to claim 1, which is characterized in that in step 103, the scoreboard
Also to the instruction operation information for resetting sequence caching transmitting each item and instructing, described instruction operation information includes at least described
The arithmetic unit information that the index tab of each item instruction and execution each item instruction need to use.
3. the method for instruction Out-of-order execution according to claim 2, which is characterized in that at step 104, the operation knot
After resetting sequence caching described in fruit write-in, the sequence caching that resets is according to described instruction operation information, the fortune that each item is instructed
The index tab for calculating result and the instruction of each item corresponds.
4. the method for instruction Out-of-order execution according to claim 1, which is characterized in that in step 105, it is described sequentially most
The condition delivered eventually are as follows: it is described reset sequence caching in exist at least one instruct operation result and index tab, the index
Label is identical as index tab described in the scoreboard, and the index tab includes the first index tab, when first rope
When tendering label are first index tab defined in the scoreboard, the sequence caching that resets is by first index tab
Operation result is directly delivered to destination register, all index tabs sequence and scoreboard before first index tab
In all index tabs sequence before the first index tab it is identical, and all index tabs before first index tab
Corresponding operation result all delivered when, it is described reset sequence caching the corresponding operation result of first index tab is delivered to
Corresponding register.
5. the method for instruction Out-of-order execution according to claim 1, which is characterized in that the sequence that resets is buffered in the friendship
It pays when executing or after executing, exports the target information of delivery, and be finally transmitted to the scoreboard, the target information is at least wrapped
Include the index tab and register information of corresponding instruction；The scoreboard updates the deposit of corresponding instruction according to the target information
Device occupied state.
6. the method for instruction Out-of-order execution according to claim 1, which is characterized in that further include second in the scoreboard
Instruction, when the result delivered of second instruction, and it is no longer related to any other instruction when, described in scoreboard removing
The information of second instruction；The scoreboard remove it is described second instruction information after, can also typing new command information.
7. the method for instruction Out-of-order execution according to claim 1, which is characterized in that each item in the scoreboard
The correspondence arithmetic unit and source operand register of instruction are after being labeled occupancy for the first time, before the occupancy labeled for the first time releases
It can not be marked as occupying again, the destination register of each item instruction is after being labeled occupancy for the first time, moreover it is possible to labeled to account for
With.
8. a kind of processor for instructing Out-of-order execution, including arithmetic unit, which is characterized in that further include that scoreboard delays with sequence is reset
It deposits；
The scoreboard is that each item received instructs distribution index label and records the index tab of each item instruction,
It include index domain in the scoreboard, the index domain is used to record the index tab of each item instruction；
Described reset includes index domain in sequence caching, and the index domain is used to record the index tab of each item instruction；
The sequence caching that resets is for receiving the operation result of each item instruction；The sequence caching that resets is also used to refer to each item
The operation result of order is delivered to destination register；
The scoreboard is directly or indirectly connected with the sequence caching that resets, and the scoreboard grasps the instruction that each item instructs
It is eventually sent to the sequence that resets as information to cache, described instruction operation information includes at least the index of each item instruction
Arithmetic unit needed for label and execution each item instruction；The sequence that resets is buffered in when the delivery executes or after executing, will
The target information of delivery is finally transmitted to the scoreboard；The target information includes at least the target deposit of each item instruction
Device information；The scoreboard occupies shape according to the register that the target information updates instruction relevant to the delivery operation
State.
9. claim as claimed in claim 8, which is characterized in that described to reset sequence caching and the direct or indirect phase of arithmetic unit
Even, the arithmetic unit issues the operation result of each item instruction, and eventually enters into the sequence that resets and cache；The sequence that resets is delayed
Counterfoil finds the corresponding index tab position of the operation result according to described instruction operation information, and operation result is written
The operation result that the index tab is directed toward stores position.
10. a kind of electronic equipment, which is characterized in that used method as claimed in claim 1 to 7 or include right
It is required that any processor of 8-9.
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