CN105549952A - Two-stage buffer issue regulation and control device based on scoreboard principle - Google Patents
Two-stage buffer issue regulation and control device based on scoreboard principle Download PDFInfo
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The invention relates to a two-stage buffer issue regulation and control device based on a scoreboard principle; the device comprises a primary wait queue and a secondary issue queue; a universal regulation and control scoreboard is arranged between the primary wait queue and the secondary issue queue; the universal regulation and control scoreboard is used for regulating and controlling opportunities for issuing all commands from the primary wait queue to the secondary issue queue, wherein states, corresponding to effective positions of a source scoreboard of the commands, of the universal regulation and control scoreboard all are unlocked states, and are taken as one of the conditions for the commands allowed to issue from the primary wait queue to the secondary issue queue. According to the two-stage buffer issue regulation and control device disclosed by the invention, by enabling the commands to wait in the primary wait queue, the items in the secondary issue queue are prevented from being meaninglessly occupied.
Description
Technical field
The present invention relates to the instruction pipelining technical field of superscalar microprocessor, particularly relate to a kind of two-stage based on scoreboard principle and delay the regulation device putting transmitting.
Background technology
Modern superscalar processor generally comprises fetching, decoding, rename, launches, and performs, and the basic streamline platform such as to exit, and comprises multiple execution unit, allow many executing instructions.As the bridge of link order streamline and execution unit, emission element can the current running status of real-time judge processor, excavates the instruction that can walk abreast, and dynamic dispatching to execution unit performs from instruction window.Flowing water platform before emission element, instruction all order enters, and order flows out; And for emission element, instruction sequences enters, out of order outflow.
Whether, in order to support instruction dynamic dispatching, in superscalar processor, often adopt scoreboard technology, whether its principle is: the state of all current operation numbers of centralized recording in scoreboard state, indicate and can use, namely can be read by instruction and use.When instruction will carry out write operation to certain operand, block this operand, make it unavailable; After this instruction is complete, then this operand is unlocked, indicate that this operand can be used.Be blocked period at operand, the instruction being source operand with this operand can not be emitted to execution unit, and to eliminate read-after-write risk, the instruction ensuring data dependence performs in strict accordance with program sequence.And there is no the instruction of data dependence, scoreboard does not have linkability yet, out of orderly can be emitted to execution unit, Out-of-order execution.
Specifically, in system, comprise the information of n position for the scoreboard state table (follow-up referred to as scoreboard state table) of data dependence between maintenance instruction, centralized recording n operand whether can information, namely whether be blocked.Each corresponding operand, for " 0 " represents that this operand can be used, namely unlocks; For " 1 " represents that this operand is unavailable, be namely blocked.
Through every bar instruction of rename platform all with the source scoreboard of a n position, each corresponding operand.For the execution of this instruction of positional representation of " 0 " does not need corresponding operand to use in the scoreboard of source, the execution for this instruction of positional representation of " 1 " needs corresponding operand to use.The source scoreboard of every bar instruction, according to the number of its source operand, can have zero-bit or multidigit to be " 1 ".
Meanwhile, through every bar instruction of rename platform all with the target scoreboard of a n position, each corresponding operand.For this instruction of positional representation of " 0 " can not revise corresponding operand in target scoreboard, this instruction of positional representation for " 1 " can revise corresponding operand.The target scoreboard of every bar instruction, according to the number of its target operand, can have zero-bit or one for " 1 ".
When instruction enters emission element from upper level platform, if m position is 1 in its Target indication board, then by the m position set of scoreboard state table, block by it; Treat that this instruction is transmitted to execution unit, and complete after, by clear for the m position of scoreboard state table " 0 ", unlock by it.
For the instruction entering emission element, each cycle, as long as both have occurred " 1 " in identical position, just mean to there is data read-after-write risk, this instruction did not allow to be launched by the source scoreboard of oneself compared with scoreboard state table.
Under normal circumstances, the instruction due to buffer memory in emission element have passed through the process of the platform such as decoding, rename, comprises more information, and search, the steering logic such as judgement is comparatively complicated, when physics realization, wiring congestion, logic progression is many, postpones longer, is the difficult point of physical Design.Along with the lifting of processor frequencies and transmitted bandwidth, instruction issue logic easily becomes streamline critical path.Therefore emission element design needs to take into account performance and physics realization, just can reach best effects.
Therefore, in the design of emission element, traditional one-level delays the requirement installing meter and be often difficult to meet performance and sequential simultaneously.And install meter according to two-stage is slow, then instruction can being stored in respectively in two bufferings, under the prerequisite that the total number of instructions of buffer memory is suitable, launching compared with buffering with only having one-level, physics realization difficulty can be reduced, be conducive to the frequency of raising processor.
Delaying in two-stage puts in the design of transmitting, in order to the performance had as far as possible, give full play to the effect of two-stage buffering, always as much as possible the instruction that operand is not ready for is placed in the first-level buffer close to streamline upstream, and operand has been placed in the level 2 buffering close to streamline downstream close to ready instruction, both make full use of resource like this, can at utmost reduce the impact that performance is brought again.Therefore, the opportunity that steering order is emitted to level 2 buffering from first-level buffer seems most important.Wherein, the first-level buffer close to streamline upstream is referred to as one-level waiting list here, and the level 2 buffering close to streamline downstream is referred to as secondary and launches queue.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of two-stage based on scoreboard principle and delays the regulation device putting transmitting, and instruction is waited at one-level waiting list, avoids the meaningless secondary that takies to launch queue entries.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of two-stage based on scoreboard principle to delay the regulation device putting transmitting, comprise one-level waiting list and secondary transmitting queue, be provided with a general regulation and control scoreboard between described one-level waiting list and secondary transmitting queue, described general regulation and control scoreboard is sent to from one-level waiting list the opportunity that secondary launches queue for regulating and controlling all instructions; Wherein, the state of the general regulation and control scoreboard that the source scoreboard active position of and instruction is corresponding is all released state, is allowed to be emitted to secondary from one-level waiting list launches one of condition of queue as this instruction.
The width of described general regulation and control scoreboard is consistent with the width of the scoreboard state table for data dependence between maintenance instruction, and each has two states: for " 0 " represents released state, for " 1 " represents blockage.
For the instruction of LOAD class, the execution cycle number of described general regulation and control scoreboard is identical with execution cycle number during hit level one data buffer memory.The m position of the target scoreboard of presumptive instruction is active position, and execution cycle number is N, then, after this instruction enters one-level waiting list from rename platform, blocked the m position of general regulation and control scoreboard immediately; In N number of cycle after this instruction is emitted to secondary transmitting queue from one-level waiting list, the m position of general regulation and control scoreboard is unlocked.
Instruction enters one-level waiting list, the state that there is the general regulation and control scoreboard corresponding with the source scoreboard active position of this instruction if find has any one or several to be blockage, then instruction is prohibited to be emitted to secondary transmitting queue, can ensure that operand does not have ready instruction to wait at one-level waiting list certainly like this, and not take the entry that secondary launches queue.Be analyzed as follows:
Presumptive instruction j immediate data is relevant to instruction i, i.e. the result of instruction j meeting reference instruction i.If instruction i waits W1i cycle at one-level waiting list, launch queue at secondary and wait W2i cycle, the performance period is Ni, and the active position of target scoreboard is Mi position, wherein W1i >=1, W2i >=1, Ni >=1,0≤Mi < n.Enter the feature of emission element according to instruction sequences, instruction j is certainly than entering one-level waiting list after instruction i, and one may be that instruction j and instruction i entered in the same cycle, but position rearward; Another kind may be that instruction j and instruction i enters in the different cycles, and instruction j is more late.
The moment entering one-level waiting list with instruction i is the 0th cycle, then the moment that the Mi position of general regulation and control scoreboard is blocked is the 0th cycle, and the moment be unlocked is W1i+Ni-1 cycle.If mean, instruction j arrives one-level waiting list the 0th cycle between W1i+Ni-1 cycle, and because general regulation and control scoreboard relevant position does not unlock, instruction j just can may enter secondary and launch queue after W1i+Ni cycle.And scoreboard state table relevant position can unlock W1i+W2i+Ni-1 cycle, due to W2i >=1, W1i+W2i+Ni-1 >=W1i+Ni can be drawn, therefore instruction j W1i+Ni cycle advance into secondary launch queue nonsensical, can only meaningless increase its launch stand-by period in queue at secondary, the meaningless entry taking secondary transmitting queue, because before this, scoreboard state table relevant position does not unlock certainly.
On the other hand, if instruction j is just allowed to enter secondary after W1i+Ni cycle launch queue, then possible situation is: scoreboard state table relevant position unlocks, but instruction j does not also enter secondary launches queue, execution unit cannot be emitted in time, thus affect performance.
Therefore the meaning of general regulation and control scoreboard is just under operand does not have ready situation certainly, instruction is waited at one-level waiting list, the meaningless secondary that takies is avoided to launch queue entries, making the secondary entry of launching in queue always leave operand for close to being ready to or ready instruction use, being conducive to the concurrency improving instruction issue.In the ready situation of operand possibility, make instruction launch queue at secondary and wait, once scoreboard state table unlocks, can launch immediately, adverse effect not caused to performance.
A memory access regulation and control scoreboard is also provided with between described one-level waiting list and secondary transmitting queue, described memory access regulation and control scoreboard is used for launching when queue Empty Entry is less than the threshold value of setting at secondary (being set as Empty Entry number≤s, wherein 1≤s < secondary launches queue entries sum), forbid with before from one-level waiting list send but not complete LOAD class instruction has directly or the instruction of indirect data dependence, be emitted to secondary from one-level waiting list and launch queue; Wherein, when secondary transmitting queue Empty Entry is less than the threshold value of setting, the state of the memory access regulation and control scoreboard that the source scoreboard active position of and instruction is corresponding be all released state, is allowed to one of condition being emitted to secondary transmitting queue from one-level waiting list as this instruction.
The width of described memory access regulation and control scoreboard is consistent with the width of the scoreboard state table for data dependence between maintenance instruction, and each has two states: for " 0 " represents released state, for " 1 " represents blockage.
When instruction target scoreboard m position is active position, for the instruction of LOAD class, when this instruction is emitted to secondary transmitting queue from one-level waiting list, the m position of described memory access regulation and control scoreboard is blockage; For the instruction of non-LOAD class and memory access regulation and control scoreboard corresponding to its any one or more sources scoreboard active position when being blockage, after this instruction is emitted to secondary transmitting queue from one-level waiting list, immediately described memory access regulation and control scoreboard m position is blocked.
When instruction target scoreboard m position is active position, for the instruction of LOAD class, described memory access regulation and control scoreboard m position unlocks when execution unit really completes by this instruction; For the instruction of non-LOAD class, then after this instruction sends to execution unit from secondary transmitting queue, described memory access regulation and control scoreboard m position is unlocked.
The setting of memory access regulation and control scoreboard, is conducive to further improving the effective rate of utilization in secondary transmitting queue entries, is analyzed as follows:
Execution cycle number when supposing LOAD class instruction hit level one data Cache is H, then after the instruction of LOAD class is emitted to secondary transmitting queue from one-level waiting list, general regulation and control scoreboard relevant position can unlock by H cycle.The instruction of LOAD class and other cycles are performed the unified process of fixing non-LOAD instruction by general regulation and control scoreboard, have two reasons, and one is have like this to utilize unified realization, and two are LOAD class instruction hit level one data Cache is Great possibilities.But for the instruction of LOAD class, the situation of level one data Cache is not hit in total existence, in this case, its performance period is unfixed.Consider following situation:
Instruction i is the instruction of LOAD class, does not in fact hit level one data Cache, and instruction j data are relevant to instruction i, and the performance period of instruction j is Nj, and instruction k data are relevant to instruction j, and the performance period of instruction k is Nk.The moment entering secondary transmitting queue with instruction i is the 0th cycle, then H cycle, namely instruction j can enter secondary and launch queue; H+Nj cycle, instruction k also can enter secondary and launch queue.And due to instruction i be the instruction of not hitting level one data Cache, its deadline is uncertain but be certainly greater than H cycle.From instruction i enter secondary to launch after queue really complete to it H cycle before, during this period of time, the instruction that and instruction i immediate data is relevant, such as instruction j, may enter secondary and launch queue wait; The instruction that and instruction i indirect data is relevant, such as instruction k, also may enter secondary and launch queue wait.The execution time of instruction i is longer, the instruction direct to it or indirect data is relevant, the possibility entering secondary transmitting queue is larger, secondary can be caused like this to launch queue and to comprise more instructions that cannot be emitted to execution unit, cause secondary to launch queue blocking probability to increase, make follow-up with it incoherent, can executed in parallel instruction due to secondary launch queue obstruction and cannot enter, the degree of parallelism of such instruction dynamic dispatching can reduce.
And blockade and the unlocking manner of scoreboard is regulated and controled according to memory access, from the instruction of a LOAD class enters secondary transmitting queue, until this LOAD class instruction real complete time, the instruction that or indirect data relevant to this LOAD class instruction immediate data is relevant during this period, as long as enter secondary to launch queue, just according to the active position of its target scoreboard, correspondence position memory access being regulated and controled scoreboard blocks.Like this can memory access regulate and control scoreboard work time, when namely secondary Empty Entry number is less, forbid that having the instruction of direct or indirect data dependence to enter secondary with the LOAD class instruction do not completed launches queue.
The instruction of LOAD class real complete time, immediately memory access is regulated and controled scoreboard correspondence position unlock; The instruction of non-LOAD class, can regulate and control the unblock of scoreboard correspondence position as long as send from secondary transmitting queue by memory access.Like this, once LOAD instruction is really complete, associated memory access regulation and control scoreboard position can by quick release.
Memory access regulation and control scoreboard does not always work, and only have and just play effect of contraction when secondary transmitting queue Empty Entry is less time, the condition set here is that secondary launches queue Empty Entry≤s.When secondary launches queue Empty Entry > s, instruction is sent to secondary from one-level waiting list and launches queue, only need check general regulation and control scoreboard, now not limiting has the instruction of data dependence to enter secondary with the instruction of LOAD class to launch queue; When secondary launches queue Empty Entry≤s, when instruction is sent to secondary transmitting queue from one-level waiting list, need check general regulation and control scoreboard and memory access regulation and control scoreboard, as long as both any one scoreboard relevant positions are blocked, instruction all can not be launched from one-level waiting list simultaneously.
General regulation and control scoreboard and memory access regulation and control scoreboard combine, and Effective Regulation instruction can enter the opportunity that secondary launches queue, make it more reasonable, be conducive to the efficiency improving instruction dynamic dispatching, improve instruction-level concurrency further.
Beneficial effect
Owing to have employed above-mentioned technical scheme, the present invention compared with prior art, there is following advantage and good effect: the present invention launches the general regulation and control scoreboard and a memory access regulation and control scoreboard that arrange between queue at one-level waiting list and secondary, the opportunity that secondary launches queue is entered for the instruction controlled in one-level waiting list, make call instruction prematurely enter secondary launch queue and increase the probability that secondary launches queue obstruction, also make call instruction only enter secondary evening launch queue and affect execution opportunity of instruction, thus improve the efficiency of launching, increase the possibility of executing instructions, promote the performance of microprocessor.
Accompanying drawing explanation
Fig. 1 is the position view of the present invention in pipeline organization;
Fig. 2 is that secondary launches queue Empty Entry when being greater than threshold value, and instruction is allowed to be emitted to secondary from one-level waiting list and launches queue schematic diagram;
Fig. 3 is that secondary launches queue Empty Entry when being greater than threshold value, and instruction is not allowed to be emitted to secondary from one-level waiting list and launches queue schematic diagram;
Fig. 4 is that secondary launches queue Empty Entry when being less than or equal to threshold value, and instruction is allowed to be emitted to secondary from one-level waiting list and launches queue schematic diagram;
Fig. 5 is that secondary launches queue Empty Entry when being less than or equal to threshold value, and instruction is not allowed to be emitted to secondary from one-level waiting list and launches queue schematic diagram;
Fig. 6 is that general regulation and control scoreboard is blocked schematic diagram;
Fig. 7 is that general regulation and control scoreboard is unlocked schematic diagram;
Fig. 8 is that memory access regulation and control scoreboard is blocked schematic diagram by the instruction of LOAD class;
Fig. 9 is that memory access regulation and control scoreboard is blocked schematic diagram by non-LOAD class instruction;
Figure 10 is that memory access regulation and control scoreboard is unlocked schematic diagram by the instruction of LOAD class;
Figure 11 is that memory access regulation and control scoreboard is unlocked schematic diagram by non-LOAD class instruction.
Embodiment
Below in conjunction with specific embodiment, set forth the present invention further.Should be understood that these embodiments are only not used in for illustration of the present invention to limit the scope of the invention.In addition should be understood that those skilled in the art can make various changes or modifications the present invention, and these equivalent form of values fall within the application's appended claims limited range equally after the content of having read the present invention's instruction.
As shown in Figure 1, the present invention includes the general regulation and control scoreboard and a memory access regulation and control scoreboard that arrange between one-level waiting list and secondary transmitting queue, enter from one-level waiting list the opportunity that secondary launches queue for steering order, make call instruction prematurely enter secondary launch queue and increase the probability that secondary launches queue obstruction, also make call instruction only enter secondary evening launch queue and affect the execution of instruction, thus improve the efficiency of launching, increase the possibility of executing instructions, promote the performance of microprocessor.
Memory access regulation and control scoreboard just plays a role always launch the prerequisite of the idle entry number≤s of queue at secondary under, object is when secondary transmitting queue Empty Entry is less, the LOAD class instruction forbidden and do not complete before has the instruction of direct or indirect data dependence to enter secondary to launch queue, reduces secondary further and launches the probability that queue blocks.
As shown in Figure 2, when secondary launches queue free time entry number >s, instruction j enters secondary transmitting queue from one-level waiting list only need inquire about general regulation and control scoreboard.Be position 1 and position n-2 at the active position of the source scoreboard of instruction j, and the value of the position 1 of general regulation and control scoreboard is " 0 ", the value of position n-2 is " 0 ", is released state, and therefore instruction j is allowed to be sent to secondary from one-level waiting list and launches queue.
As shown in Figure 3, when secondary launches queue free time entry number >s, instruction j enters secondary transmitting queue from one-level waiting list only need inquire about general regulation and control scoreboard.Be position 1 and position n-2 at the active position of the source scoreboard of instruction j.And the value of the position 1 of general regulation and control scoreboard is " 1 ", it is blockage; The value of position n-2 is " 0 ", is released state.The position 1 of general regulation and control scoreboard and position n-2 are not all released state, and therefore instruction j is not allowed to be sent to secondary transmitting queue from one-level waiting list.
As shown in Figure 4, when secondary launches queue free time entry number≤s, instruction j enters secondary transmitting queue from one-level waiting list need inquire about general regulation and control scoreboard and memory access regulation and control scoreboard simultaneously.Be position 1 and position n-2 at the active position of the source scoreboard of instruction j.And the value of the position 1 of general regulation and control scoreboard is " 0 ", the value of position n-2 is " 0 ", is released state; The value of the position 1 of memory access regulation and control scoreboard is " 0 ", and the value of position n-2 is " 0 ", is also released state.Therefore instruction j is allowed to be sent to secondary transmitting queue from one-level waiting list.
As shown in Figure 5, when secondary launches queue free time entry number≤s, instruction j enters secondary transmitting queue from one-level waiting list need inquire about general regulation and control scoreboard and memory access regulation and control scoreboard simultaneously.Be position 1 and position n-2 at the active position of the source scoreboard of instruction j.And the value of the position 1 of general regulation and control scoreboard is " 0 ", the value of position n-2 is " 0 ", is released state; The value of the position 1 of memory access regulation and control scoreboard is " 0 ", is released state; The value of position n-2 is " 1 ", is blockage.The position of general regulation and control scoreboard and memory access regulation and control scoreboard is not all released state, and therefore instruction j is not allowed to be sent to secondary transmitting queue from one-level waiting list.
As shown in Figure 6, the active position of the target scoreboard of instruction j is position 2, after being emitted to one-level waiting list, immediately according to the active position of its target scoring plug, is blocked the position 2 of general regulation and control scoreboard from rename.
As shown in Figure 7, the active position of the target scoreboard of instruction j is position 2, and execution cycle number is N, in N number of cycle after being emitted to secondary transmitting queue, according to the active position of its target scoreboard, is unlocked the position 2 of general regulation and control scoreboard from one-level waiting list.
As shown in Figure 8, instruction j is the instruction of LOAD class, and the active position of target scoreboard is position 2, and after being emitted to secondary transmitting queue from one-level waiting list, immediately according to the active position of its target scoreboard, the position 2 memory access being regulated and controled scoreboard is blocked.
As shown in Figure 9, instruction j is the instruction of non-LOAD class, and the active position of source scoreboard is position 1 and position n-4, and the active position of target scoreboard is position 2, and the position 1 of now memory access regulation and control scoreboard is released state, and position n-4 is blockage.The state of the regulation and control scoreboard same position that the active position of the source scoreboard of instruction j is corresponding has one at least for blockage, meet the condition of blockade of visiting and investigating and depositing control scoreboard, therefore after instruction j is emitted to secondary transmitting queue from one-level waiting list, immediately according to the active position of its target scoreboard, the position 2 memory access being regulated and controled scoreboard is blocked.
As shown in Figure 10, instruction j is the instruction of LOAD class, and the active position of target scoreboard is position 2, and when instruction j really completes, according to the active position of its target scoreboard, the position 2 memory access being regulated and controled scoreboard unlocks.
As shown in figure 11, instruction j is the instruction of non-LOAD class, and the active position of target scoreboard is position 2, and after instruction j is emitted to execution unit from secondary transmitting queue, immediately according to the active position of its target scoreboard, the position 2 memory access being regulated and controled scoreboard unlocks.
Claims (7)
1. the two-stage based on scoreboard principle delays the regulation device putting transmitting, comprise one-level waiting list and secondary transmitting queue, it is characterized in that, be provided with a general regulation and control scoreboard between described one-level waiting list and secondary transmitting queue, described general regulation and control scoreboard is sent to from one-level waiting list the opportunity that secondary launches queue for regulating and controlling all instructions; Wherein, the state of the general regulation and control scoreboard that the source scoreboard active position of and instruction is corresponding is all released state, is allowed to be emitted to secondary from one-level waiting list launches one of condition of queue as this instruction.
2. the two-stage based on scoreboard principle according to claim 1 delays the regulation device putting transmitting, it is characterized in that, the width of described general regulation and control scoreboard is consistent with the width of the scoreboard state table for data dependence between maintenance instruction, and each has two states.
3. the two-stage based on scoreboard principle according to claim 1 delays the regulation device putting transmitting, it is characterized in that, for the instruction of LOAD class, the execution cycle number of described general regulation and control scoreboard is identical with execution cycle number during hit level one data buffer memory.
4. the two-stage based on scoreboard principle according to claim 1 delays the regulation device putting transmitting, it is characterized in that, a memory access regulation and control scoreboard is also provided with between described one-level waiting list and secondary transmitting queue, described memory access regulation and control scoreboard is used for when secondary transmitting queue Empty Entry is less than the threshold value of setting, forbid with before from one-level waiting list send but not complete LOAD class instruction has directly or the instruction of indirect data dependence, be emitted to secondary from one-level waiting list and launch queue; Wherein, when secondary transmitting queue Empty Entry is less than the threshold value of setting, the state of the memory access regulation and control scoreboard that the source scoreboard active position of and instruction is corresponding be all released state, is allowed to one of condition being emitted to secondary transmitting queue from one-level waiting list as this instruction.
5. the two-stage based on scoreboard principle according to claim 4 delays the regulation device putting transmitting, it is characterized in that, the width of described memory access regulation and control scoreboard is consistent with the width of the scoreboard state table for data dependence between maintenance instruction, and each has two states.
6. the two-stage based on scoreboard principle according to claim 4 delays the regulation device putting transmitting, it is characterized in that, when instruction target scoreboard m position is active position, for the instruction of LOAD class, when this instruction is emitted to secondary transmitting queue from one-level waiting list, the m position of described memory access regulation and control scoreboard is blockage; For the instruction of non-LOAD class and memory access regulation and control scoreboard corresponding to its any one or more sources scoreboard active position when being blockage, after this instruction is emitted to secondary transmitting queue from one-level waiting list, immediately described memory access regulation and control scoreboard m position is blocked.
7. the two-stage based on scoreboard principle according to claim 4 delays the regulation device putting transmitting, it is characterized in that, when instruction target scoreboard m position is active position, for the instruction of LOAD class, described memory access regulation and control scoreboard m position unlocks when execution unit really completes by this instruction; For the instruction of non-LOAD class, then after this instruction sends to execution unit from secondary transmitting queue, described memory access regulation and control scoreboard m position is unlocked.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110297662A (en) * | 2019-07-04 | 2019-10-01 | 深圳芯英科技有限公司 | Instruct method, processor and the electronic equipment of Out-of-order execution |
| CN110502279A (en) * | 2019-08-23 | 2019-11-26 | 中国人民解放军国防科技大学 | Intelligent adjustment method for emission queue based on markable instruction |
| CN110647362A (en) * | 2019-09-11 | 2020-01-03 | 上海高性能集成电路设计中心 | Two-stage buffering transmitting device based on scoreboard principle |
| CN110908798A (en) * | 2019-11-08 | 2020-03-24 | 丁剑明 | Multi-process cooperative network traffic analysis method and device |
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| CN110502279A (en) * | 2019-08-23 | 2019-11-26 | 中国人民解放军国防科技大学 | Intelligent adjustment method for emission queue based on markable instruction |
| CN110647362A (en) * | 2019-09-11 | 2020-01-03 | 上海高性能集成电路设计中心 | Two-stage buffering transmitting device based on scoreboard principle |
| CN110647362B (en) * | 2019-09-11 | 2023-03-31 | 上海高性能集成电路设计中心 | Two-stage buffering transmitting device based on scoreboard principle |
| CN110908798A (en) * | 2019-11-08 | 2020-03-24 | 丁剑明 | Multi-process cooperative network traffic analysis method and device |
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