CN101281513A - Stream processor IP core based on Avalon - Google Patents
Stream processor IP core based on Avalon Download PDFInfo
- Publication number
- CN101281513A CN101281513A CNA2008100312991A CN200810031299A CN101281513A CN 101281513 A CN101281513 A CN 101281513A CN A2008100312991 A CNA2008100312991 A CN A2008100312991A CN 200810031299 A CN200810031299 A CN 200810031299A CN 101281513 A CN101281513 A CN 101281513A
- Authority
- CN
- China
- Prior art keywords
- stream
- instruction
- nuclear
- data
- scalar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Advance Control (AREA)
Abstract
The invention discloses a stream processor IP core based on Avalon bus. The invention is characterized in that the IP core is composed of a scalar core and a stream processing core, which are connected by an Avalon bus, the scalar core includes a dynamic scheduler, i.e., a isomerous core middleware, which is connected both to a complier in the scalar core and to the stream processing core, realizes the link between the scalar core and the stream processing core, and provides a call interface for stream level programs; the stream processing core includes an execution component for stream level programs, i.e, a stream level execution unit, which is connected to a scalar core, as well as the microcontroller of the stream processing core, a memory controller, a stream register file and a network interface, buffers a stream instruction, selects the stream instruction, executes the stream instruction, transmits scalar data and provides the state of the stream level execution unit for the scalar core; the instruction is from an instruction set suitable for the architecture. The invention can meet the requirement of high processing speed in media application and science computing field, and has good universality.
Description
Technical field
The present invention relates to a kind of stream handle IP kernel, the stream handle IP kernel that especially adopts FPGA to realize based on the Avalon bus.
Background technology
Stream handle is the typical case representative of a new generation towards the high-performance microprocessor of intensive calculations, and the major function of stream handle is exactly a sequential processes ordered data record.Record is made up of the set of related data, and orderly record constitutes stream, and the length of stream is unfixing, and the stream record can be an arbitrary data types, but the record type in the same stream is identical.Stream handle is used towards stream specially.Stream is used and mainly is divided into two classes: a class is a media application; Another kind of is that science is calculated.Stream is used has following principal character: computation-intensive, to compare with traditional desktop application, and stream is used and all will be carried out a large amount of arithmetical operations to the data of taking out from internal memory at every turn; Concurrency with data level and behavior master, exists instruction-level and task level parallel simultaneously; Locality is meant the data reusing locality in the application.According to these characteristics, stream handle adopts stream level and core stage two-stage programming mode, and stream level program is responsible for the tissue of data, and the core stage program is responsible for data computing.
Stream handle is made up of stream process nuclear, host interface, scalar nuclear.The stream process nuclear is connected with scalar nuclear by host interface.The stream process nuclear is made up of stream controller, stream registers file SRF (Stream Register File), microcontroller, memory controller, a plurality of computing bunch, network interface.Stream controller links to each other with host interface, receives data and address signal.Stream controller is connected with network interface with memory controller, stream registers file SRF, microcontroller, sends the control signal that the stream instruction produces to them.Stream registers file SRF and memory controller and computing bunch link to each other, be used for the storage flow data: all leave among the stream registers file SRF with calculating relevant input traffic, output stream and intermediate data, guarantee that data can not produce the visit to outside DRAM memory in the utilization of processor inner loop.Microcontroller and computing bunch directly link to each other, and bunch send very long instruction word to computing.Stream in using all computations bunch finish by computing, comprise in each computing bunch between a plurality of ALU and ALU bunch in interconnection switches, guarantee communication between nonidentity operation bunch by communication unit between the computing bunch.The stream process nuclear is usually as coprocessor, need with the primary processor collaborative work, primary processor is commonly referred to scalar processor or scalar nuclear.When carrying out the stream application, scalar nuclear is compiled into rudimentary flow operation with the high level flow operation that the programmer writes, and re-sends in the stream process nuclear and carries out.
Programmable system on chip (SOPC, System on a Programmable Chip) be meant: central processing unit, digital signal processor, storer, mimic channel, signals collecting and change-over circuit etc. are integrated in the function of the system that realizes on the printed circuit board, and can carry out exploitation able to programme according to user's request.Along with the development of microelectric technique, chip piece inside can integrated a lot of devices, this on a programmable chip integrated system be called SOPC.Because the scale of SOPC is very huge, it is very big to relate to workload, therefore the module that has designed is reused very necessaryly, and a method that addresses this problem is to use IP kernel (Intellectual Property Core).IP kernel refers to through checking, integrated circuit modules that can reuse and that have definite function in integrated circuit fields.The use of IP kernel can reduce design time, cost greatly, improves design efficiency.The module of existing chip 70% more than 1,000,000 is the repeated use of IP kernel.
But the stream in fields such as media application and science calculating is used the requirement of processing speed and is increased day by day, because the architecture of general purpose microprocessor is not suitable for the extensive intensive calculations of high speed processing,, uses common general purpose microprocessor IP kernel so can not adapting to the stream in fields such as media application and science calculating.
If adopt the stream handle IP kernel of flowing system structure, the stream that then can adapt to fields such as media application and science calculating is used.The following two kinds of schemes that adopt are usually gone up in design at present: the one, and ASIC (special IC, Application-SpecificIntegrated Circuit) throws sheet; The 2nd, FPGA (field programmable gate array, Field Programmable Gate Array).Because the stream handle system scale reaches ten million gate leve, the logical resource and the interconnection resource of consumption are many, and the pressure of the placement-and-routing of design back is also very big, so adopt the ASIC scheme usually.But ASIC throws sheet needs a large amount of financial and manpower resources, and can not revise.Having dirigibility and adopt FPGA can obtain relevant hard-wired parameter, and overcome ASIC design cycle length and invested big shortcoming, is more satisfactory selection.Adopt the FPGA of Avalon bus standard to be widely adopted at present with its flexible ease for use, the EP2S180 of the StratixII of altera corp series wherein, single logic door number reaches ten million scale, be one of the fpga chip that adopts the maximum-norm of Avalon bus standard at present, but its scale relative current processor is still less.Therefore study a kind of stream handle IP kernel that can under existing monolithic FPGA scale, realize and remain the problem that those skilled in the art very are concerned about based on the Avalon bus.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of stream handle IP kernel based on the Avalon bus standard under existing monolithic FPGA scale, and this IP kernel adapts to the requirement of the stream application in fields such as media application and science calculating to higher processing speed.
Technical scheme of the present invention is: the stream handle IP kernel adopts FPGA to realize, form by scalar nuclear, stream process nuclear, Avalon bus, adopt the Avalon bus as high-speed bus on the sheet of stream handle system architecture, scalar nuclear, stream process nuclear are by the Avalon bus interconnection.The Avalon bus comprises data write signal line, read data line, write data line, address and data reading signal line.Design has an isomery nuclear middleware in the scalar nuclear, isomery nuclear middleware is a dynamic scheduler, compiler in its end and the scalar nuclear is connected, the other end is connected with the stream process nuclear by the Avalon bus, it finishes the link between scalar nuclear and the stream process nuclear, provides calling interface to compiling stream level program later; Design has a stream level performance element in the stream process nuclear, stream level performance element one end is connected with scalar nuclear by the Avalon bus, the other end is connected with microcontroller, memory controller, stream registers file SRF, the network interface of stream process nuclear with status signal lines by control, stream level performance element is stream grade program implementation parts, and its cache flow instructs, selects stream instruction execution, the instruction of execution stream, transmits scalar data, examines the level performance element state that flows that provides to scalar; Described stream instructs the new stream instruction set of this architecture of self-adaptation.
Because scalar nuclear, stream process nuclear have different instruction set or operational code, towards the operating load of different characteristic, structure is totally different separately, therefore is called as isomery nuclear.Based on the complete Avalon on-chip bus system that the embedded type bus standard design of altera corp realizes, the sequential of the internuclear data transmission of isomery and performance are guaranteed by the Avalon bus protocol.But comparatively complicated alternately between the internuclear particularly scalar of isomery nuclear and stream process nuclear, only use the Avalon bus can't guarantee the correctness and the high efficiency of the data transmission between the isomery nuclear, therefore design isomery nuclear middleware and stream level performance element and realize data transmission between the isomery nuclear.
Isomery nuclear middleware is made up of user's calling interface, steering logic, instruction array buffer memory, command status buffer memory, physical layer interface.
User's calling interface is a group interface function that calls isomery nuclear middleware function for user program, directly carry out data and instruction interaction with stream level program, it obtains the stream instruction and data that compiling generates from compiler, data and instruction are transferred to steering logic, and will return to user program from the control signal that steering logic obtains.
Command status is buffered in steering logic will flow the information of preserving the stream instruction when instruction sends to the stream process nuclear, the type that comprises instruction, parameters or the like, and receive and preserve the execution state information of current stream instruction from steering logic, according to the status information of the stream instruction of these state information updatings self inner buffer.
Instruction array buffer memory is that (rudimentary flow operation instruction is by flowing compiling according to automatic generation of high level flow operation in the stream level program in all rudimentary flow operation instructions in user program of buffer memory, can directly mail to the stream process nuclear, and the instruction of quilt stream process nuclear execution) parts, be connected with steering logic, inquire about rudimentary flow operation instruction for steering logic.
Steering logic is the critical component that other parts of control isomery nuclear middleware are finished various functions, and it all links to each other with user's calling interface, instruction array buffer memory, command status buffer memory, physical layer interface.When string routine called isomery nuclear middleware, steering logic received data and instruction from user's calling interface, reads current stream command status information from the command status buffer memory, received rudimentary flow operation from instruction array buffer memory simultaneously.According to data that receive and instruction, several different operations below steering logic is carried out: examine when the stream handle transport stream is instructed at scalar, steering logic obtains rudimentary flow operation from user's calling interface, obtain the current execution state information of stream instruction by physical layer interface from the stream process nuclear, decision is to transmit rudimentary flow operation by physical layer interface, still waits for again and transmitting; When scalar nuclear transport stream was instructed executing state, steering logic was read stream process nuclear current state by physical layer interface from the stream process nuclear, and the information in the update instruction state cache in the stream process nuclear; When between scalar nuclear and stream process nuclear, transmitting scalar data, the rudimentary flow operation that stream level program will be read scalar data by compiler sends user's calling interface to, steering logic is sent to the stream process nuclear by physical layer interface with rudimentary flow operation, after the stream process nuclear is finished, steering logic is read data from physical layer interface again from the stream process nuclear, and return to compiler by user's calling interface, use for stream level program; Between scalar nuclear and stream process nuclear, carry out flow data when transmitting (specially referring to into the transmission of blocks of data sequence), steering logic sends the required rudimentary flow operation of all data transmission by physical layer interface to the stream process nuclear, and the stream process nuclear is carried out these rudimentary flow operations makes flow data transmit between scalar nuclear and stream process nuclear.
Physical layer interface both was connected with steering logic, linked to each other with the stream process nuclear again, and it obtains instruction or data from steering logic, will send the stream process nuclear to from instruction or the data that steering logic obtains, and returns the status information of stream process nuclear to steering logic.
In order to finish mutual between the scalar nuclear cocurrent flow process nuclear, design has a stream level performance element in the stream process nuclear.Stream level performance element is made up of stream level performance element interface, status register, command memory RAM, scalar register file, instruction execution unit, command status message unit, state information updating logic and MUX.
Stream level performance element interface links to each other with the isomery nuclear middleware of scalar nuclear by the Avalon bus, by logic emission groove signal wire, first-class command signal line, write enable signal line and instruction memory RAM and link to each other, link to each other with scalar register file with the first data reading signal line by reading address signal line, link to each other with status register by stream level performance element status signal lines.Stream level performance element interface receives from scalar by the data write signal line in the Avalon bus and authorizes next stream instruction, to flow instruction and be forwarded to command memory RAM, and will write to the address of command memory RAM and send to command memory RAM by logic emission groove signal wire by first-class command signal line; Stream level performance element interface will be transmitted to scalar register file from the address signal of scalar nuclear, receive the data of returning from scalar register file that are stored in this address, return to scalar nuclear; Simultaneously, stream level performance element interface receives stream level performance element status information from status register, will flow level performance element status information and return to scalar nuclear.Because the data width of Avalon bus is 32, and the length of stream instruction is elongated, part flows instruction width above 32, therefore need a plurality of cycle transport stream instructions, therefore, a stream level performance element Interface design has the order fulfillment signal wire to indicate whether the transmission of a stream instruction finishes, and scalar nuclear sends 0 toward the order fulfillment signal wire and just represents that this stream instruction transmit, sends 1 and represents that this flows to instruct to transmit and finish.
Command memory RAM and stream level performance element interface by logic emission groove signal wire, first-class command signal line, write the enable signal line and link to each other, link to each other by address signal line with MUX, it is continuous to flow command signal line and instruction performance element by second.RAM obtains the address of instruction among RAM by logic emission groove signal wire from a stream level performance element interface, obtains the stream instruction by first-class command signal line from a stream level performance element interface, writes the instruction that becomes a mandarin writing under the situation that the enable signal line enables; And obtain from MUX and to read the address of instructing the RAM, the stream instruction that will read by the second stream command signal line sends to instruction execution unit.
The command status message unit links to each other with the state information updating logic with the asserts signal line by status signal lines, links to each other with MUX by selecting signal wire.The command status message unit is a registers group, each of registers group is corresponding to a stream instruction, store this stream instruction required information when carrying out, comprise ready bit, resource-niche, logic emission groove number three fields, ready bit represents whether the stream instruction of this correspondence can be carried out, required resource when resource-niche represents that the stream instruction of this correspondence is carried out, logic emission groove number are represented the logical number of the stream instruction of this correspondence.Each register of command status message unit obtains asserts signal by the asserts signal line from the state information updating logic, if asserts signal is high, the ready bit of then putting this register is a ready state, the stream of representing this correspondence instructs and can carry out, simultaneously, the command status message unit is launched groove number with logic and ready bit sends to MUX by selecting signal wire.
MUX links to each other by selecting signal wire and instruction status information element, links to each other by address signal line and instruction memory RAM.MUX is obtained each ready information of command status message unit by selecting signal wire, if a certain item is in ready state, then MUX selects this instruction to carry out, launch the address that RAM is read in the groove conduct by the logic of selecting signal wire to obtain this, pass to RAM by address signal line, if it is ready state that the command status message unit has the ready information of multinomial register, then select the instruction in numbering is minimum or numbering the is maximum register to carry out, the logic emission groove that it is corresponding number sends to RAM as the address.
The state information updating logic links to each other by busy not busy signal wire with network interface, microcontroller, stream registers file SRF, memory controller on the one hand, reception is from the busy not busy signal of these modules, link to each other by busy-idle condition signal wire and instruction performance element on the other hand, link to each other with asserts signal line and instruction status information element by status signal lines, link to each other with status register with state signalization line by the executing state signal wire simultaneously.The state information updating logic is obtained each resource information of command status message unit by status signal lines, thereby know the instruction execution required resource corresponding with this, obtain the busy not busy information of other module (being network interface, microcontroller, stream registers file SRF, memory controller) in the stream process nuclear according to busy not busy signal wire, if the required resource of instruction of this correspondence is idle, then the ready bit that this register is set by the asserts signal line is a ready state, otherwise ready bit is constant.
Scalar register file links to each other with data reading signal line and instruction performance element by the data write signal line, links to each other by reading address signal line, the first data reading signal line and flowing a level performance element interface.Scalar register file is a registers group, is used for scalar data in the storage flow process nuclear, and it receives data from instruction execution unit by the data write signal line, by the data reading signal line data is returned to instruction execution unit.Simultaneously, the scalar register file data that will read the address correspondence by the first data reading signal line return to a stream level performance element interface.
Instruction execution unit connects by the second stream command signal line and instruction memory RAM, link to each other with network interface, microcontroller, stream registers file SRF, memory controller by control signal wire, link to each other with scalar register file with the data reading signal line by the data write signal line, link to each other with the state information updating logic by the busy-idle condition signal wire.Instruction execution unit receives the stream instruction from RAM, the convection current instruction is deciphered, produce control signal and send to other module (being network interface, microcontroller, stream registers file SRF, memory controller) that flows in the process nuclear, start other module work.Simultaneously, instruction execution unit is by data write signal alignment scalar register file write data, by data reading signal line reading of data from scalar register file.In addition, the instruction execution unit not busy information of will hurrying is passed to the state information updating logic by the busy-idle condition signal wire.
Status register is a register of preserving stream level performance element state, links to each other with the state information updating logic with state signalization line by the executing state signal wire, links to each other with stream level performance element interface by stream level performance element status signal lines.If state signalization line is effective, then the configuration state register is an effective status, the content of status register is passed to the state information updating logic by the executing state signal wire on the one hand, passes to stream level performance element interface by stream level performance element status signal lines on the one hand.
Stream is used by the instruction of stream process nuclear execution stream and is finished, and therefore must design the new stream instruction set that adapts to architecture of the present invention.The stream instruction set is designed to variable length, carries out in stream level performance element.The stream instruction set comprises the instruction of four classes: the register read write command, the flow transmission instruction is carried out the kernel program instruction, other instructions.Every instruction is the multidigit binary number, and a plurality of territories are set in instruction, an operation or an operand of each territory representative instruction, and first territory of every instruction is instruction identification code territory.
1. the register read write command is that the register that is used for the convection cell architecture carries out the instruction of read-write operation.Such instruction comprises 2 instructions:
(1).MOVE?Dst_type，Dst_num，Src_type，Src_num，synch
Command function: with source-register Src_type[Src_num] content be written to destination register Dst_type[Dst_num].Wherein _ and type specify registers type, the numbering of _ num specify registers, synch represents the synchronous mark position, when this instruction is need be with other module synchronous, on this mark position.
(2).Write_Imm?Dst_type，Dst_num，Imm，synch
Command function: will count Imm immediately and be written to destination register Dst_type[Dst_num].Wherein _ and type specify registers type, the numbering of _ num specify registers, synch represents the synchronous mark position, when this instruction was need be with other module synchronous, this is masked as put.
2. the flow transmission instruction is used for the SRF on the outer DRAM storer of sheet, the sheet, the data transmission between the microcontroller, comprises 3 instructions.
(3).Memop?Data_sdr_num，dir，Data_mar
Command function: start the flow transmission between outer DRAM of sheet and the stream registers file.The stream address in the DRAM storer and memory access mode outside sheet are provided by register Data_mar, and address and the length of stream in SRF is provided by register Data_sdr_num, and direction is provided by dir.
(4).Load_ucode?Pgm_sdr_num，mpc
Command function: the microcode of kernel program is loaded into microcontroller in the mode of flow data from SRF, and position and the length of microcode in SRF is provided by register Pgm_sdr_num, and microcode is loaded into that start address is provided by mpc in the microcontroller.
(5).Netop?net_sdr_num，dir，Tag，NRR
Command function: start the flow network transmission between local stream registers file and the long-range stream registers file.Position and the length of flow data in local stream registers file is provided by register net_sdr_num, dir represents the transmission direction of data, be used for distinguishing the transmission and the reception of data, Tag is used for distinguishing the different messages that go to same network node, each message has different Tag values, and the required routing iinformation of network transmission process is provided by register NRR.
3. carry out the kernel program instruction
(6).Clustop?sdr_num，dir，mode，restartable，mpc
Command function: the notice microcontroller is carried out kernel program, core is pointed out by MPC in the start address of microcode memory, and core inlet flow and output stream position and length in SRF are provided by register sdr_num, transmission direction is provided by dir, transmission mode is provided by mode, and whether restartable indicates input and output needs to start once more.
(7).Clust_restart?sdr_num，dir，mode，restartable
Command function: restart the stream that inputs or outputs of core, use during length stream double buffering.Position and the length of stream in SRF is provided by sdr_num, and transmission direction is provided by dri, and transmission mode is provided by mode, and whether restartable indicates input and output needs to start once more.
4. other instruction
(8).END
Command function: last this instruction of execution before a complete string routine finishes, the notification streams processor program is finished.
(9).Barrier
Command function: because string routine has the scalar operational example as circulation, branch, in order to ensure the correct emission of stream instruction, insert the Barrier instruction, the function of obstruction is played in this instruction, promptly only will all be finished prior to all stream instructions of Barrier instruction according to procedure order, Barrier instruction and the later instruction of Barrier instruction just might be launched.
(10).Synch_uc
Command function: when microcontroller arrives the corresponding synchronous point in the process of execution kernel program, carry out this instruction, realization is synchronous with the kernel program execution.This instruction can send a synchronizing signal to microcontroller, makes microcontroller continue to carry out kernel program.
The stream instruction is positioned at scalar nuclear at first, enters into the stream process nuclear through isomery nuclear middleware, and carries out on the stream level performance element of stream process nuclear.In stream level performance element, the stream instruction is at first through overcurrent level performance element interface entry instruction storage RAM, select to be transmitted into instruction execution unit by MUX then, the stream instruction is carried out in instruction execution unit decoding, function according to the stream instruction, produce the control signal of other module in the control stream process nuclear, the operation of other module in the control stream process nuclear.
Adopt the present invention can reach following effect:
1, the invention provides a kind of stream handle IP kernel based on the Avalon bus.Because flowing system structure itself is fit to the application in the field of calculating with the media nuclear science, so this IP kernel is suitable as the operation platform of stream application of the computation-intensive in fields such as media and science calculating.
2, in IP kernel of the present invention inside, removed host interface between scalar nuclear and the stream process nuclear, using the interior high-speed bus of sheet instead is the interconnection of Avalon STD bus, and the Avalon bus standard is supported a plurality of peripheral hardwares, so the present invention is easy to expand on scale, make the bus standard and the FPGA Application and Development of IP kernel unified, better generality is arranged.
3, the indoor design of the nuclear of the scalar in the IP kernel of the present invention has isomery nuclear middleware, the indoor design of stream process nuclear has stream level performance element, they connect with the Avalon STD bus, make IP kernel can finish the cooperative mechanism of scalar nuclear cocurrent flow process nuclear, can carry out stream smoothly and use.
4, the present invention's design has the new stream instruction set that adapts to architecture of the present invention, the program that feasible stream is used can form the stream instruction in the stream instruction set through compiler, isomery nuclear middleware, stream grade performance element, and the stream application can be flowed process nuclear and be carried out in the mode that the stream instruction is carried out.
Description of drawings
Fig. 1 is the disclosed a kind of stream handle system assumption diagram of Stanford Univ USA.
Fig. 2 is the stream handle IP kernel structural drawing that the present invention is based on the Avalon bus.
Fig. 3 is the building-block of logic of isomery nuclear middleware in the IP kernel of the present invention.
Fig. 4 is the structural drawing of stream level performance element in the IP kernel of the present invention.
Embodiment
Fig. 1 is the disclosed a kind of stream handle IP kernel system assumption diagram of Stanford Univ USA.This IP kernel is formed by connecting by host interface by scalar nuclear and stream process nuclear.The stream process nuclear is made up of stream controller, stream registers file SRF, microcontroller, memory controller, a plurality of computing bunch, network interface.Stream controller links to each other with host interface, receives data and address signal.Stream controller is connected with network interface with memory controller, stream registers file SRF, microcontroller, sends the control signal that the stream instruction produces to them.Stream registers file SRF and memory controller and computing bunch link to each other, be used for the storage flow data: all leave among the stream registers file SRF with calculating relevant input traffic, output stream and intermediate data, guarantee that data can not produce the visit to outside DRAM memory in the utilization of processor inner loop.Microcontroller and computing bunch directly link to each other, and bunch send very long instruction word to computing.All computations bunch is finished by computing in the stream handle, comprise in each computing bunch between a plurality of ALU and ALU bunch in interconnection switches, guarantee communication between nonidentity operation bunch by communication unit between the computing bunch.When carrying out the stream application, scalar nuclear is compiled into rudimentary flow operation with the high level flow operation that the programmer writes, and re-sends in the stream process nuclear and carries out.
Fig. 2 is the stream handle IP kernel structural drawing that the present invention is based on the Avalon bus.Have the architecture of stream handle based on the stream handle IP kernel of Avalon bus, comprise scalar nuclear, stream process nuclear and Avalon bus.And the key distinction of original stream handle is: do not have host interface between scalar nuclear, the stream process nuclear, there is not stream controller in the stream process nuclear, its function realizes that by the stream level performance element in isomery nuclear middleware, Avalon bus and the stream process nuclear in the scalar nuclear data and control signal are no longer by host interface but by the Avalon bus transfer.
Fig. 3 is an isomery nuclear middleware building-block of logic in the IP kernel of the present invention.Isomery nuclear middleware is a dynamic scheduler, compiler in its end and the scalar nuclear is connected, the other end is connected with the stream process nuclear by the Avalon bus, and it finishes the link between scalar nuclear and the stream process nuclear, provides calling interface to compiling stream level program later.Isomery nuclear middleware is made up of user's calling interface, steering logic, instruction array buffer memory, command status buffer memory, physical layer interface.
User's calling interface is a group interface function that calls isomery nuclear middleware function for user program, directly carry out data and instruction interaction with stream level program, it obtains the stream instruction and data that compiling generates from compiler, data and instruction are transferred to steering logic, and will obtain control signal from steering logic and return to user program.
Command status is buffered in steering logic will flow the information of preserving these stream instructions when instruction sends to the stream process nuclear, the type that comprises instruction, parameters or the like, and receive and preserve the execution state information of current stream instruction from steering logic, according to the status information of the stream instruction of these state information updatings self inner buffer.
Instruction array buffer memory is the parts of all rudimentary flow operation instructions in user program of buffer memory, is connected with steering logic, inquires about rudimentary flow operation instruction for steering logic.
Steering logic is the critical component that isomery nuclear middleware is finished various functions, and it all links to each other with user's calling interface, instruction array buffer memory, command status buffer memory, physical layer interface.
Physical layer interface both was connected with steering logic, linked to each other with the stream process nuclear again, and it obtains instruction or data from steering logic, returns the status information that flows process nuclear to steering logic, and the instruction that will obtain from steering logic or data and stream process nuclear are mutual.
Fig. 4 is the structural drawing of stream level performance element in the IP kernel of the present invention.Stream level performance element one end is connected with scalar nuclear by the Avalon bus, and the other end is connected with microcontroller, memory controller, stream registers file SRF, the network interface of stream process nuclear with status signal lines by control.Stream level performance element is made up of stream level performance element interface, status register, command memory RAM, scalar register file, instruction execution unit, command status message unit, state information updating logic and MUX.
Stream level performance element interface links to each other with the isomery nuclear middleware of scalar nuclear by the Avalon bus, by logic emission groove signal wire, first-class command signal line, write enable signal line and instruction memory RAM and link to each other, link to each other with scalar register file with the first data reading signal line by reading address signal line, link to each other with status register by stream level performance element status signal lines.Stream level performance element interface receives from scalar by the data write signal line in the Avalon bus and authorizes next stream instruction, to flow instruction and be forwarded to command memory RAM, and will write to the address of command memory RAM and send to command memory RAM by logic emission groove signal wire by first-class command signal line; Stream level performance element interface will be transmitted to scalar register file from the address signal of scalar nuclear, receive the data of returning from scalar register file that are stored in this address, return to scalar nuclear; Simultaneously, stream level performance element interface receives stream level performance element status information from status register, will flow level performance element status information and return to scalar nuclear.A stream level performance element Interface design has the order fulfillment signal wire to indicate whether the transmission of a stream instruction finishes, and scalar nuclear sends 0 toward the order fulfillment signal wire and just represents that this stream instruction transmit, sends 1 and represents that this flows to instruct to transmit and finish.
Command memory RAM and stream level performance element interface by logic emission groove signal wire, first-class command signal line, write the enable signal line and link to each other, link to each other by address signal line with MUX, it is continuous to flow command signal line and instruction performance element by second.RAM obtains the address of instruction among RAM by logic emission groove signal wire from a stream level performance element interface, obtains the stream instruction by first-class command signal line from a stream level performance element interface, writes the instruction that becomes a mandarin writing under the situation that the enable signal line enables; And obtain from MUX and to read the address of instructing the RAM, the stream instruction that will read by the second stream command signal line sends to instruction execution unit.
The command status message unit links to each other with the state information updating logic with the asserts signal line by status signal lines, links to each other with MUX by selecting signal wire.The command status message unit is a registers group, each of registers group is corresponding to a stream instruction, store this stream instruction required information when carrying out, comprise ready bit, resource-niche, logic emission groove number three fields, ready bit represents whether the stream instruction of this correspondence can be carried out, required resource when resource-niche represents that the stream instruction of this correspondence is carried out, logic emission groove number are represented the logical number of the stream instruction of this correspondence.Each register of command status message unit obtains asserts signal by the asserts signal line from the state information updating logic, if asserts signal is high, the ready bit of then putting this register is a ready state, the stream of representing this correspondence instructs and can carry out, simultaneously, the command status message unit is launched groove number with logic and ready bit sends to MUX by selecting signal wire.
MUX links to each other by selecting signal wire and instruction status information element, links to each other by address signal line and instruction memory RAM.MUX is obtained each ready information of command status message unit by selecting signal wire, if a certain item is in ready state, then MUX selects this instruction to carry out, launch the address that RAM is read in the groove conduct by the logic of selecting signal wire to obtain this, pass to RAM by address signal line, if it is ready state that the command status message unit has the ready information of multinomial register, then select the instruction in numbering is minimum or numbering the is maximum register to carry out, the logic emission groove that it is corresponding number sends to RAM as the address.
The state information updating logic links to each other by busy not busy signal wire with network interface, microcontroller, stream registers file SRF, memory controller on the one hand, reception is from the busy not busy signal of these modules, link to each other by busy-idle condition signal wire and instruction performance element on the other hand, link to each other with asserts signal line and instruction status information element by status signal lines, link to each other with status register with state signalization line by the executing state signal wire simultaneously.The state information updating logic is obtained each resource information of command status message unit by status signal lines, thereby know the instruction execution required resource corresponding with this, obtain the busy not busy information of other module (being network interface, microcontroller, stream registers file SRF, memory controller) in the stream process nuclear according to busy not busy signal wire, if the required resource of instruction of this correspondence is idle, then the ready bit that this register is set by the asserts signal line is a ready state, otherwise ready bit is constant.
Scalar register file links to each other with data reading signal line and instruction performance element by the data write signal line, links to each other by reading address signal line, the first data reading signal line and flowing a level performance element interface.Scalar register file is a registers group, is used for scalar data in the storage flow process nuclear, and it receives data from instruction execution unit by the data write signal line, by the data reading signal line data is returned to instruction execution unit.Simultaneously, the scalar register file data that will read the address correspondence by the first data reading signal line return to a stream level performance element interface.
Instruction execution unit connects by the second stream command signal line and instruction memory RAM, link to each other with network interface, microcontroller, stream registers file SRF, memory controller by control signal wire, link to each other with scalar register file with the data reading signal line by the data write signal line, link to each other with the state information updating logic by the busy-idle condition signal wire.Instruction execution unit receives the stream instruction from RAM, the convection current instruction is deciphered, produce control signal and send to other module (being network interface, microcontroller, stream registers file SRF, memory controller) that flows in the process nuclear, start other module work.Simultaneously, instruction execution unit is by data write signal alignment scalar register file write data, by data reading signal line reading of data from scalar register file.In addition, the instruction execution unit not busy information of will hurrying is passed to the state information updating logic by the busy-idle condition signal wire.
Status register is a register of preserving stream level performance element state, links to each other with the state information updating logic with state signalization line by the executing state signal wire, links to each other with stream level performance element interface by stream level performance element status signal lines.If state signalization line is effective, then the configuration state register is an effective status, the content of status register is passed to the state information updating logic by the executing state signal wire on the one hand, passes to stream level performance element interface by stream level performance element status signal lines on the one hand.
Claims (5)
1. stream handle IP kernel based on the Avalon bus, examine by scalar, the stream process nuclear is formed, it is characterized in that entire I P nuclear adopts FPGA to realize, scalar nuclear, the stream process nuclear, peripherals is by the Avalon bus interconnection, the Avalon bus comprises the data write signal line, read data line, write data line, address and data reading signal line, design has an isomery nuclear middleware in the scalar nuclear, isomery nuclear middleware is a dynamic scheduler, compiler in its end and the scalar nuclear is connected, the other end is connected with the stream process nuclear by the Avalon bus, and it finishes the link between scalar nuclear and the stream process nuclear, provides calling interface to compiling stream level program later; Design has a stream level performance element in the stream process nuclear, stream level performance element one end is connected with scalar nuclear by the Avalon bus, the other end is connected with microcontroller, memory controller, stream registers file SRF, the network interface of stream process nuclear with status signal lines by control, stream level performance element is stream grade program implementation parts, and its cache flow instructs, selects stream instruction execution, the instruction of execution stream, transmits scalar data, examines the level performance element state that flows that provides to scalar; The stream instruction comes the new stream instruction set of this architecture of self-adaptation.
2. the stream handle IP kernel based on the Avalon bus as claimed in claim 1 is characterized in that described isomery nuclear middleware is made up of user's calling interface, steering logic, instruction array buffer memory, command status buffer memory, physical layer interface:
2.1 user's calling interface is a group interface function that calls isomery nuclear middleware function for user program, directly carry out data and instruction interaction with stream level program, it obtains the stream instruction and data that compiling generates from compiler, data and instruction are transferred to steering logic, and will return to user program from the control signal that steering logic obtains;
2.2 being buffered in steering logic, command status will flow the type and the parameters of preserving the stream instruction when instruction sends to the stream process nuclear, and receive and preserve the execution state information of current stream instruction from steering logic, according to the status information of the stream instruction of these state information updatings self inner buffer;
2.3 instruction array buffer memory is the parts of all rudimentary flow operation instructions in user program of buffer memory, be connected with steering logic, inquire about rudimentary flow operation instruction for steering logic, rudimentary flow operation instruction is to be generated automatically according to the high level flow operation in the stream level program by the stream compiling, can directly mail to the stream process nuclear, and by the instruction of stream process nuclear execution;
2.4 steering logic is the parts that other parts of control isomery nuclear middleware are finished various functions, it all links to each other with user's calling interface, instruction array buffer memory, command status buffer memory, physical layer interface; When string routine called isomery nuclear middleware, steering logic received data and instruction from user's calling interface, reads current stream command status information from the command status buffer memory, received rudimentary flow operation from instruction array buffer memory simultaneously; According to data that receive and instruction, several different operations below steering logic is carried out: examine when the stream handle transport stream is instructed at scalar, steering logic obtains rudimentary flow operation from user's calling interface, obtain the current execution state information of stream instruction by physical layer interface from the stream process nuclear, decision is to transmit rudimentary flow operation by physical layer interface, still waits for again and transmitting; When scalar nuclear transport stream was instructed executing state, steering logic was read stream process nuclear current state by physical layer interface from the stream process nuclear, and the information in the update instruction state cache in the stream process nuclear; When between scalar nuclear and stream process nuclear, transmitting scalar data, the rudimentary flow operation that stream level program will be read scalar data by compiler sends user's calling interface to, steering logic is sent to the stream process nuclear by physical layer interface with rudimentary flow operation, after the stream process nuclear is finished, steering logic is read data from physical layer interface again from the stream process nuclear, and return to compiler by user's calling interface, use for stream level program; When between scalar nuclear and stream process nuclear, carrying out the flow data transmission, steering logic sends the required rudimentary flow operation of all data transmission by physical layer interface to the stream process nuclear, and the stream process nuclear is carried out these rudimentary flow operations makes flow data transmit between scalar nuclear and stream process nuclear;
2.5 physical layer interface both was connected with steering logic, linked to each other with the stream process nuclear again, it obtains instruction or data from steering logic, will send the stream process nuclear to from instruction or the data that steering logic obtains, and returns the status information of stream process nuclear to steering logic.
3. the stream handle IP kernel based on the Avalon bus as claimed in claim 1 is characterized in that described stream level performance element is made up of a stream level performance element interface, status register, command memory RAM, scalar register file, instruction execution unit, command status message unit, state information updating logic and MUX:
3.1 stream level performance element interface links to each other with the isomery nuclear middleware of scalar nuclear by the Avalon bus, by logic emission groove signal wire, first-class command signal line, write enable signal line and instruction memory RAM and link to each other, link to each other with scalar register file with the first data reading signal line by reading address signal line, link to each other with status register by stream level performance element status signal lines; Stream level performance element interface receives from scalar by the data write signal line in the Avalon bus and authorizes next stream instruction, to flow instruction and be forwarded to command memory RAM, and will write to the address of command memory RAM and send to command memory RAM by logic emission groove signal wire by first-class command signal line; Stream level performance element interface will be transmitted to scalar register file from the address signal of scalar nuclear, receive the data of returning from scalar register file that are stored in this address, return to scalar nuclear; Simultaneously, stream level performance element interface receives stream level performance element status information from status register, will flow level performance element status information and return to scalar nuclear;
3.2 command memory RAM and stream level performance element interface by logic emission groove signal wire, first-class command signal line, write the enable signal line and link to each other, link to each other by address signal line with MUX, link to each other by the second stream command signal line and instruction performance element; RAM obtains the address of instruction among RAM by logic emission groove signal wire from a stream level performance element interface, obtains the stream instruction by first-class command signal line from a stream level performance element interface, writes the instruction that becomes a mandarin writing under the situation that the enable signal line enables; And obtain from MUX and to read the address of instructing the RAM, the stream instruction that will read by the second stream command signal line sends to instruction execution unit;
3.3 the command status message unit links to each other with the state information updating logic with the asserts signal line by status signal lines, links to each other with MUX by selecting signal wire; The command status message unit is a registers group, each of registers group is corresponding to a stream instruction, store this stream instruction required information when carrying out, comprise ready bit, resource-niche, logic emission groove number three fields, ready bit represents whether the stream instruction of this correspondence can be carried out, required resource when resource-niche represents that the stream instruction of this correspondence is carried out, logic emission groove number are represented the logical number of the stream instruction of this correspondence; Each register of command status message unit obtains asserts signal by the asserts signal line from the state information updating logic, if asserts signal is high, the ready bit of then putting this register is a ready state, the stream of representing this correspondence instructs and can carry out, simultaneously, the command status message unit is launched groove number with logic and ready bit sends to MUX by selecting signal wire;
3.4 MUX links to each other by selecting signal wire and instruction status information element, links to each other by address signal line and instruction memory RAM; MUX is obtained each ready information of command status message unit by selecting signal wire, if a certain item is in ready state, then MUX selects this instruction to carry out, launch the address that RAM is read in the groove conduct by the logic of selecting signal wire to obtain this, pass to RAM by address signal line, if it is ready state that the command status message unit has the ready information of multinomial register, then select the instruction in numbering is minimum or numbering the is maximum register to carry out, the logic emission groove that it is corresponding number sends to RAM as the address;
3.5 the state information updating logic links to each other by busy not busy signal wire with network interface, microcontroller, stream registers file SRF, memory controller on the one hand, reception is from the busy not busy signal of these modules, link to each other by busy-idle condition signal wire and instruction performance element on the other hand, link to each other with asserts signal line and instruction status information element by status signal lines, link to each other with status register with state signalization line by the executing state signal wire simultaneously; The state information updating logic is obtained each resource information of command status message unit by status signal lines, thereby know the instruction execution required resource corresponding with this, according to busy not busy signal wire obtain stream process nuclear in other module be the busy not busy information of network interface, microcontroller, stream registers file SRF, memory controller, if the required resource of instruction of this correspondence is idle, then the ready bit that this register is set by the asserts signal line is a ready state, otherwise ready bit is constant;
3.6 scalar register file links to each other with data reading signal line and instruction performance element by the data write signal line, links to each other by reading address signal line, the first data reading signal line and flowing a level performance element interface; Scalar register file is a registers group, be used for scalar data in the storage flow process nuclear, it is by the data of data write signal line reception from instruction execution unit, by the data reading signal line data are returned to instruction execution unit, the data that will read the address correspondence by the first data reading signal line return to stream level performance element interface;
3.7 instruction execution unit connects by the second stream command signal line and instruction memory RAM, link to each other with network interface, microcontroller, stream registers file SRF, memory controller by control signal wire, link to each other with scalar register file with the data reading signal line by the data write signal line, link to each other with the state information updating logic by the busy-idle condition signal wire; Instruction execution unit receives the stream instruction from RAM, the convection current instruction is deciphered, produce control signal and send to network interface, microcontroller, stream registers file SRF, memory controller, start network interface, microcontroller, stream registers file SRF, memory controller work; Simultaneously, instruction execution unit is by data write signal alignment scalar register file write data, and by data reading signal line reading of data from scalar register file, and the not busy information of will hurrying is passed to the state information updating logic by the busy-idle condition signal wire;
3.8 status register is a register of preserving stream level performance element state, links to each other with the state information updating logic with state signalization line by the executing state signal wire, links to each other with stream level performance element interface by stream level performance element status signal lines; If state signalization line is effective, then the configuration state register is an effective status, the content of status register is passed to the state information updating logic by the executing state signal wire on the one hand, passes to stream level performance element interface by stream level performance element status signal lines on the one hand.
4. the stream handle IP kernel based on the Avalon bus as claimed in claim 1, it is characterized in that described stream instruction set comprises the instruction of four classes: the register read write command, the flow transmission instruction, the instruction of execution kernel program, other instructions, every instruction is the multidigit binary number, and a plurality of territories are set in instruction, an operation or an operand of each territory representative instruction, first territory of every instruction is instruction identification code territory:
Carry out the instruction of read-write operation 4.1 the register read write command is the register that is used for the convection cell architecture, such instruction comprises 2 instructions:
(1).MOVE?Dst_type，Dst_num，Src_type，Src_num，synch
Command function: with source-register Src_type[Src_num] content be written to destination register Dst_type[Dst_num], wherein _ type specify registers type, the numbering of _ num specify registers, synch represents the synchronous mark position, when this instruction is need be with other module synchronous, on this mark position;
(2).Write_Imm?Dst_type，Dst_num，Imm，synch
Command function: will count Imm immediately and be written to destination register Dst_type[Dst_num], wherein _ and type specify registers type, the numbering of _ num specify registers, synch represents the synchronous mark position, when this instruction was need be with other module synchronous, this is masked as put;
4.2 the flow transmission instruction is used for the SRF on the outer DRAM storer of sheet, the sheet, the data transmission between the microcontroller, comprises 3 instructions:
(3).Memop?Data_sdr_num，dir，Data_mar
Command function: start the flow transmission between outer DRAM of sheet and the stream registers file, the stream address in the DRAM storer and memory access mode outside sheet are provided by register Data_mar, address and the length of stream in SRF is provided by register Data_sdr_num, and direction is provided by dir;
(4).Load_ucode?Pgm_sdr_num，mpc
Command function: the microcode of kernel program is loaded into microcontroller in the mode of flow data from SRF, and position and the length of microcode in SRF is provided by register Pgm_sdr_num, and microcode is loaded into that start address is provided by mpc in the microcontroller;
(5).Netop?net_sdr_num，dir，Tag，NRR
Command function: start the flow network transmission between local stream registers file and the long-range stream registers file, position and the length of flow data in local stream registers file is provided by register net_sdr_num, dir represents the transmission direction of data, be used for distinguishing the transmission and the reception of data, Tag is used for distinguishing the different messages that go to same network node, each message has different Tag values, and the required routing iinformation of network transmission process is provided by register NRR;
4.3 carry out the kernel program instruction
(6).Clustop?sdr_num，dir，mode，restartable，mpc
Command function: the notice microcontroller is carried out kernel program, core is pointed out by MPC in the start address of microcode memory, core inlet flow and output stream position and length in SRF are provided by register sdr_num, transmission direction is provided by dir, transmission mode is provided by mode, and whether restartable indicates input and output needs to start once more;
(7).Clust_restart?sdr_num，dir，mode，restartable
Command function: the stream that inputs or outputs of restarting core, use during length stream double buffering, position and the length of stream in SRF is provided by sdr_num, and transmission direction is provided by dri, transmission mode is provided by mode, and whether restartable indicates input and output needs to start once more;
4.4 other instruction
(8).END
Command function: last this instruction of execution before a complete string routine finishes, the notification streams processor program is finished;
(9).Barrier
Command function: because string routine has the scalar operational example as circulation, branch, in order to ensure the correct emission of stream instruction, insert the Barrier instruction, the function of obstruction is played in this instruction, promptly only will all be finished prior to all stream instructions of Barrier instruction according to procedure order, Barrier instruction and the later instruction of Barrier instruction just might be launched;
(10).Synch_uc
Command function: when microcontroller arrives the corresponding synchronous point in the process of execution kernel program, carry out this instruction, it is synchronous that realization and kernel program are carried out, and this instruction meeting make microcontroller continue the execution kernel program to synchronizing signal of microcontroller transmission.
5. the stream handle IP kernel based on the Avalon bus as claimed in claim 3, it is characterized in that described stream level performance element Interface design has the order fulfillment signal wire to indicate whether the transmission of a stream instruction finishes, scalar nuclear sends 0 toward the order fulfillment signal wire and just represents that this stream instruction transmit, sends 1 and represents that this flows to instruct to transmit and finish.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008100312991A CN100573500C (en) | 2008-05-15 | 2008-05-15 | Stream handle IP kernel based on the Avalon bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008100312991A CN100573500C (en) | 2008-05-15 | 2008-05-15 | Stream handle IP kernel based on the Avalon bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101281513A true CN101281513A (en) | 2008-10-08 |
| CN100573500C CN100573500C (en) | 2009-12-23 |
Family
ID=40013993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2008100312991A Expired - Fee Related CN100573500C (en) | 2008-05-15 | 2008-05-15 | Stream handle IP kernel based on the Avalon bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100573500C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270268A (en) * | 2010-12-31 | 2011-12-07 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN101996156B (en) * | 2009-08-10 | 2013-01-16 | 北京多思科技发展有限公司 | Universal processor for supporting recombinable polycaryon IP (Internet Protocol) and method thereof |
| CN103986660A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Device and method for loading microcodes |
| CN104656741A (en) * | 2015-03-13 | 2015-05-27 | 浪潮集团有限公司 | Sequential control method for different partitions of server system based on nios II |
| CN110502279A (en) * | 2019-08-23 | 2019-11-26 | 中国人民解放军国防科技大学 | Intelligent adjustment method for emission queue based on markable instruction |
| CN112463018A (en) * | 2019-09-06 | 2021-03-09 | 群联电子股份有限公司 | Instruction transmission method, memory control circuit unit and memory storage device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104243979B (en) * | 2014-09-30 | 2016-04-13 | 广东威创视讯科技股份有限公司 | Based on method for supervising and the system of the image procossing exception of QSYS system |
-
2008
- 2008-05-15 CN CNB2008100312991A patent/CN100573500C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996156B (en) * | 2009-08-10 | 2013-01-16 | 北京多思科技发展有限公司 | Universal processor for supporting recombinable polycaryon IP (Internet Protocol) and method thereof |
| CN102270268A (en) * | 2010-12-31 | 2011-12-07 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN102270268B (en) * | 2010-12-31 | 2014-02-26 | 北京谊安医疗系统股份有限公司 | Information communication method and system, and medical equipment |
| CN103986660A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Device and method for loading microcodes |
| CN104656741A (en) * | 2015-03-13 | 2015-05-27 | 浪潮集团有限公司 | Sequential control method for different partitions of server system based on nios II |
| CN104656741B (en) * | 2015-03-13 | 2017-05-31 | 浪潮集团有限公司 | Sequential control method for different partitions of server system based on nios II |
| CN110502279A (en) * | 2019-08-23 | 2019-11-26 | 中国人民解放军国防科技大学 | Intelligent adjustment method for emission queue based on markable instruction |
| CN112463018A (en) * | 2019-09-06 | 2021-03-09 | 群联电子股份有限公司 | Instruction transmission method, memory control circuit unit and memory storage device |
| CN112463018B (en) * | 2019-09-06 | 2022-11-08 | 群联电子股份有限公司 | Instruction transmission method, memory control circuit unit and memory storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100573500C (en) | 2009-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100573500C (en) | Stream handle IP kernel based on the Avalon bus | |
| Jones et al. | GRIP—a high-performance architecture for parallel graph reduction | |
| US8055881B2 (en) | Computing nodes for executing groups of instructions | |
| TW581950B (en) | Multiple logical interfaces to a shared coprocessor resource | |
| US20110231616A1 (en) | Data processing method and system | |
| US11550750B2 (en) | Memory network processor | |
| CN105512088B (en) | A kind of restructural processor architecture and its reconstructing method | |
| CN101799750B (en) | Data processing method and device | |
| US20130054939A1 (en) | Integrated circuit having a hard core and a soft core | |
| JP2006509306A (en) | Cell engine for cross-referencing data processing systems to related applications | |
| CN111433758A (en) | Programmable operation and control chip, design method and device thereof | |
| JPH05205005A (en) | Host-interface for logic-simulation-machine | |
| CN107005492B (en) | System for multicast and reduced communication over a network on a chip | |
| CN100489830C (en) | 64 bit stream processor chip system structure oriented to scientific computing | |
| US10659396B2 (en) | Joining data within a reconfigurable fabric | |
| CN102073480B (en) | Method for simulating cores of multi-core processor by adopting time division multiplex | |
| CN104216681A (en) | CPU instruction processing method and processor | |
| CN109582364B (en) | Simplified instruction set processor based on memristor | |
| CN104035898B (en) | A kind of memory access system based on VLIW type processors | |
| US8631173B2 (en) | Semiconductor device | |
| WO2021212045A1 (en) | Synchronization of processing elements and software managed memory hierarchy in a machine learning accelerator | |
| US10203911B2 (en) | Content addressable memory (CAM) implemented tuple spaces | |
| CN116113940A (en) | Graph calculation device, graph processing method and related equipment | |
| JP4149360B2 (en) | Data-driven information processing apparatus and data flow program execution control method | |
| CN112802527B (en) | Method for realizing high-speed programming of embedded flash memory and programming system of embedded flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091223 Termination date: 20110515 |