CN104243979B - Based on method for supervising and the system of the image procossing exception of QSYS system - Google Patents
Based on method for supervising and the system of the image procossing exception of QSYS system Download PDFInfo
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Abstract
Does the invention provides a kind of method for supervising and system of the image procossing exception based on QSYS system, its method comprise step: the Avalon detecting the IP module at the corresponding levels of QSYS system? whether the echo signal in ST traffic spike is low level; If so, be carry out timing the low level time to obtain the duration to described echo signal; When the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels, adopt the solution of the present invention, the extension death situation state detecting IP module in QSYS system that can be instant, improve Postprocessing technique efficiency.
Description
Technical field
The present invention relates to technical field of image processing, particularly relate to a kind of method for supervising and system of the image procossing exception based on QSYS system.
Background technology
In technical field of image processing, by decoding chip, view data is gathered, use FPGA (FieldProgrammableGateArray again, field programmable gate array) chip carries out buffer memory or algorithm computing as data processing centre to view data, then MCU (SingleChipMicrocomputer, one chip microcomputer) or CPU (CentralProcessingUnit, central processing unit) normally work as control centre's control fpga chip and peripheral circuit, finally make view data normally output in display to show, a kind of data processing mode is like this more and more general.Current Altera is as the large manufacturer of fpga chip, there is provided based on the development platform (QSYS system predecessor for SOPC system) under QSYS system, its function is quite powerful and convenient, can automatically generate interconnected logic, the IP module called needed for connection is (also known as intellectual property or IP kernel, the English full name of IP kernel is IntellectualPropertycore, it is one section of hardware description language program with particular electrical circuit function, this program can be transplanted in different semiconductor technologies and go production integrated circuit (IC) chip) and subsystem, thus save considerably the time, alleviate FPGA design efforts would.
In the image processing process based on QSYS system, between the IP module called, AvalonST (AvalonStreamingInterface) data stream format and AvalonMomeryMap bus protocol (a kind of bus on chip agreement) is often adopted to design; Ideally, view data enters in fpga chip through decoding collection, is efficiently processed in QSYS system, demonstrates smooth video pictures over the display.But, under this mechanism, Problems existing is, when some extreme exception, such as, the moment that video signal source resolution switches or signal source plugs, decoding chip occasional exports the view data of some resolution pole exception to fpga chip, enter in QSYS system again, arrive some IP module to process, due to the problem such as misarrangement or filtering function imperfection of IP module itself, IP module is made to enter a state that cannot recover voluntarily, namely " death situation state is hung ", show as picture over the display and block situation that is motionless or flower screen, due to IP module by manufacturer is provided, for developer, be equivalent to a black box, above-mentioned problem cannot be solved by the internal code of revising and debugging IP module.When practical application, can only manually reset or restarting equipment to make Postprocessing technique normal; Quite machinery is not with intelligent for this method, and owing to not having specific aim, can waste the plenty of time, Postprocessing technique efficiency is low, and for the application scenario that some is important, such as monitoring or demonstration occasion etc., be a quite serious problem.
Summary of the invention
The object of the present invention is to provide a kind of method for supervising and system of the image procossing exception based on QSYS system, the extension death situation state detecting IP module in QSYS system that can be instant, improve Postprocessing technique efficiency.
Object of the present invention is achieved through the following technical solutions:
Based on a method for supervising for the image procossing exception of QSYS system, comprise the steps:
Whether the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system is low level;
If so, be carry out timing the low level time to obtain the duration to described echo signal;
When the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels.
Based on a supervisory control system for the image procossing exception of QSYS system, comprising:
Whether detection module is low level for the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system;
Timing module, for when described AvalonST traffic spike occurs abnormal, is carry out timing the low level time to obtain the duration to described echo signal;
Reseting module, for when the described duration is greater than default time threshold, carries out recovery operation to described IP module at the corresponding levels.
According to the scheme of the invention described above, whether it is the echo signal in the AvalonST traffic spike of the IP module at the corresponding levels detecting QSYS system is low level, if, be carry out timing the low level time to obtain the duration to described echo signal, when the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels, realize whether the judgement of hanging death situation state is in IP module based on to the detection of target signal level height, the echo signal duration in the AvalonST of IP module at the corresponding levels is when being greater than default time threshold, just can judge that IP module at the corresponding levels is in and hang death situation state, and recovery operation is carried out to described IP module at the corresponding levels, pointed, improve Postprocessing technique efficiency, simultaneously, signal different classes of in AvalonST traffic spike can also be selected as echo signal, monitoring mode is flexible.
Accompanying drawing explanation
Fig. 1 is the structural representation of the existing image processing apparatus based on QSYS system;
Fig. 2 is the schematic flow sheet of the method for supervising embodiment one of the image procossing exception based on QSYS system of the present invention;
Fig. 3 is timing schematic diagram;
Fig. 4 is the schematic flow sheet of the method for supervising embodiment two of the image procossing exception based on QSYS system of the present invention;
Fig. 5 is the schematic flow sheet of the method for supervising embodiment three of the image procossing exception based on QSYS system of the present invention;
Fig. 6 is the structural representation of the supervisory control system embodiment of the image procossing exception based on QSYS system of the present invention;
Schematic diagram when Fig. 7 is for being applied to shown in Fig. 1 by the tool in an embodiment of invention based on the supervisory control system of the image procossing exception of QSYS system the image processing apparatus based on QSYS system;
Schematic diagram when Fig. 8 is for being applied to shown in Fig. 1 by the tool in another embodiment of invention based on the supervisory control system of the image procossing exception of QSYS system the image processing apparatus based on QSYS system.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is described in further detail.Should be appreciated that embodiment described herein only in order to explain the present invention, do not limit protection scope of the present invention.
For the ease of better understanding the solution of the present invention, first introduce the existing function and efficacy based on modules in the image processing apparatus of QSYS system shown in Fig. 1.
As shown in Figure 1, image processing apparatus based on QSYS system comprises decoding chip 110, the QSYS system 120 of fpga chip, MCU control centre 130, DDR chip 140, I2C (Inter-IntegratedCircuit, twin wire universal serial bus) bus interface 150, SPI (SerialPeripheralInterface, Serial Peripheral Interface (SPI)) bus interface 160, DDR (DoubleDataRate, Double Data Rate synchronous dynamic random stores) controller 170, 181, 182...18n be the module in QSYS system 120, wherein, 182...18n be the IP module called, 181 also have other module to be the functional module that user oneself develops, wherein, spi bus interface 160 is also comprised in QSYS system 120, function Shi Shi MCU control centre 130 is communicated by spi bus with each module in QSYS system 120, I2C bus interface 150, for making MCU control centre 130 communicate with decoding chip 110, DDR controller 170 is communicated by AvalonMM bus with the 2nd module 182,
In QSYST system, 181, the data stream format processed between 182...18n module is AvalonST stream format, at this, AvalonST traffic spike (namely data stream format is the signal of AvalonST stream format) is simply introduced, AvalonST signal is made up of this several signal of data, data_valid, sop, eop, st_ready, wherein:
Data: the data format such as YC444 or 24 bit RGB444 that can be the YC422 of 16 bits, 24 bits;
Data_valid: data effective index signal, only have when it is high level, namely during data_valid=1, corresponding data data also has other index signal to be only effectively;
Sop: unwrap beginning index signal, work as sop=1, and just effective during data_valid=1, at this moment, when minimum 4 bit of data are the F of 16 systems, namely during data [4:0]=F, represent the beginning controlling bag, control to include the information such as video resolution, when minimum 4 bit of data are 0, namely, time data [4:0]=0, the beginning of packet is represented;
Eop: end-of-packet index signal; Work as eop=1, and just effective during data_valid=1, represent the end controlling bag or packet;
St_ready: ready signal, its port direction and data, data_valid, sop, eop tetra-kinds of senses are just contrary, the flow direction of these four signals of data, data, valid, sop, eop is that upper level module exports to module at the corresponding levels, and the flow direction of st_ready signal is module at the corresponding levels exports to upper level module; It is only had to be high level, namely, as st_ready=1, just represent that module at the corresponding levels is ready to receive data, upper level module receives st_ready when being high level, just send these four kinds of signals of data, data_valid, sop, eop to module at the corresponding levels, by that analogy;
The present invention realizes whether being in the judgement of hanging death situation state to IP module based on the detection whether abnormal to AvalonST traffic spike, and the present invention is described in detail below.
In the following description, each embodiment first for the method for supervising of the image procossing exception based on QSYS system of the present invention is described, then is described each embodiment of the supervisory control system of the image procossing exception based on QSYS system of the present invention.
Embodiment one
Shown in Figure 2, be the schematic flow sheet of the method for supervising embodiment one of the image procossing exception based on QSYS system of the present invention.As shown in Figure 2, the method for supervising of the image procossing exception based on QSYS system in the present embodiment comprises the steps:
Step S201: whether the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system is low level, if so, enters step S202;
Wherein, echo signal comprises any one or multi-signal in above-mentioned any data_valid, sop, eop, st_ready, but for the ease of detecting, general selection is detected a kind of signal in data_valid, st_ready;
Step S202: be carry out timing the low level time to obtain the duration to described echo signal, when the described duration is greater than default time threshold, enters step S203;
Timing from when detecting that echo signal becomes low level, timing mode can adopt the mode that can realize arbitrarily, such as, realized by the counter being arranged on fpga chip inside, the initial value of counter is 0, counting is started when detecting that echo signal becomes when low level occurs abnormal, work due to fpga chip inside is the input needing clock source, generally, as shown in Figure 3, the counting of counter is cumulative in the hopping edge of clock signal, such as, a rising edge clock arrives, counter just adds 1, the count value that rolling counters forward obtains can convert the duration to, but, mode the easiest is, with the duration described in count value direct representation,
It should be noted that, the duration is only and is continuously the low level time when time detect that echo signal becomes, and when each echo signal becomes high level, this duration can be updated to 0;
Time threshold can be arranged by the mode of debugging, and when using tricks the numeric representation duration, time threshold also needs to adjust accordingly;
Step S103: recovery operation is carried out to described IP module at the corresponding levels;
Wherein, recovery operation comprises reset operation or initialization operation, or other can make IP module recovery at the corresponding levels operate normally;
Duration and the time threshold preset can be compared, when the described duration is greater than default time threshold, then can think that IP module at the corresponding levels enters and hang death situation state, need to carry out recovery operation to described IP module at the corresponding levels, a time threshold is set and the duration compares, consider, sometimes echo signal can become low level within the shorter time (as 200 milliseconds), but can high level be returned to again very soon, at this moment not need to carry out recovery operation to described IP module at the corresponding levels.
Accordingly, according to the scheme of above-mentioned the present embodiment, whether it is the echo signal in the AvalonST traffic spike of the IP module at the corresponding levels detecting QSYS system is low level, if, be carry out timing the low level time to obtain the duration to described echo signal, when the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels, realize whether the judgement of hanging death situation state is in IP module based on to the detection of target signal level height, the echo signal duration in the AvalonST of IP module at the corresponding levels is when being greater than default time threshold, just can judge that IP module at the corresponding levels is in and hang death situation state, and recovery operation is carried out to described IP module at the corresponding levels, pointed, improve Postprocessing technique efficiency, simultaneously, signal different classes of in AvalonST traffic spike can also be selected as echo signal, monitoring mode is flexible.
Embodiment two
Shown in Figure 4, be the schematic flow sheet of the method for supervising embodiment two of the image procossing exception based on QSYS system of the present invention.In the present embodiment, be take echo signal as st_ready signal, be described based on realizing whether being in the judgement of hanging death situation state for example to IP module to the detection of st_ready signal.
Consider, when the IP module that ST flows link is normally run, in its most of the time, st_ready signal is all high level, even without vision signal input QSYS system, st_ready signal also can remain high level always, be in the state of moment wait-receiving mode data, when IP inside modules is in calculation process process during unripe reception data, the st_ready signal short time becomes low level (by mostly being most within 200 milliseconds in situation), and when internal arithmetic is disposed, st_ready signal will be automatically restored to high level, continue to receive data to process, and after a certain IP module goes wrong, when being in " hanging death situation state ", now this IP module exports to the st_ready signal of upper level IP module is 0 by perseverance, cannot 1 be reverted to, namely the state never preparing to receive data is in, upper level module cannot receive the signal of st_ready=1, also just never module at the corresponding levels is sent data to, be equivalent to data link break, image shows the state being also just in and blocking, therefore, can based on the monitoring realized the detection of st_ready signal in AvalonST signal the image procossing exception of QSYS system, below the solution of the present invention is described in detail.
As shown in Figure 4, the method for supervising of the image procossing exception based on QSYS system in the present embodiment comprises the steps:
Step S301: detect whether the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level, if so, enters described step S302;
Detect whether st_ready signal is low level, whether the value also namely detecting st_ready signal is zero;
It should be noted that, the alternative of this step can also be detect whether the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is high level, if not, enters described step S302, does not repeat them here;
Step S302: be carry out timing the low level time to obtain the described duration to described st_ready signal, when the described duration is greater than default time threshold, enters step S303;
Timing mode as described in embodiment one, can not repeat them here;
Step S303: recovery operation is carried out to described IP module at the corresponding levels.
Whether adopt the scheme in the present embodiment, be st_ready signal be low level due to what detect, be only the detection of the value of st_ready signal, easily realize, efficiency is high.
Embodiment three
Shown in Figure 5, be the schematic flow sheet of the method for supervising embodiment three of the image procossing exception based on QSYS system of the present invention.The difference of the present embodiment and embodiment two is, be take echo signal as data_valid signal, be described based on realizing whether being in the judgement of hanging death situation state for example to IP module to the detection of data_valid signal.
As shown in Figure 5, the method for supervising of the image procossing exception based on QSYS system in the present embodiment comprises the steps:
Step S401: obtain the information whether QSYS system has the input of signal source by reading decoding chip, if there is signal source to input, detect whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level, if low level, enter described step S402;
In the present embodiment, detecting before whether data_valid signal that IP module at the corresponding levels outputs to next stage IP module be low level, also need to obtain by reading decoding chip the information whether QSYS system has the input of signal source, be because when QSYS system does not have signal source to input, the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is also low level;
As shown in Figure 1, obtain QSYS system whether have the information specific implementation process of the input of signal source to be by reading decoding chip: MCU control centre 130 reads the decoding chip 110 of front end by I2C bus interface 150, whether obtain has signal source to input this information, then fpga chip is notified by spi bus interface 160, after fpga chip obtains this information, can determine that QSYS system has signal source to input;
Detect whether data_valid signal is low level, whether the value also namely detecting st_ready is zero;
It should be noted that, the alternative of this step can also be detect whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is high level, if not, enters described step S402, does not repeat them here;
In the present embodiment, need when ensureing that QSYS system has the input of signal source, just detect whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level, this is because, QSYS system is also low level when the input not having signal source, but this situation can not be used for judging that IP module at the corresponding levels is in extension death situation state;
Step S402: be carry out timing the low level time to obtain the described duration to described data_valid signal, when the described duration is greater than default time threshold, enters step S403;
Timing mode as described in embodiment one, can not repeat them here;
Step S403: recovery operation is carried out to described IP module at the corresponding levels.
Whether adopt the scheme in the present embodiment, be data_valid signal be low level due to what detect, be only the detection of the value of data_valid signal, easily realize, efficiency is high.
Wherein in an embodiment, above-mentioned when the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels and comprises the steps: to judge whether the described duration is greater than default timing threshold value; If be greater than timing threshold value, then identifying default exception monitoring by the first identification renewal is the second mark; Detect described exception monitoring mark every set time section, if detect, the number of times that exception monitoring is designated the second mark exceedes default frequency threshold value, carries out recovery operation to described IP module at the corresponding levels;
Wherein, timing threshold value, frequency threshold value can by debugging suitable value is set, set time section can be arranged according to actual needs, set time section be 500 milliseconds, frequency threshold value be 3 times time, monitoring effect is better;
First mark, the second mark can be arbitrary two different marks, and can be numeral or alphabetical, also can be numeral and alphabetical combination, such as, first be designated 0, and second is designated 1;
When the number of times detecting that exception monitoring is designated the second mark exceedes default frequency threshold value, then can judge whether IP module at the corresponding levels is in and hang death situation state, and recovery operation is carried out to described IP module at the corresponding levels.
In the present embodiment, by judging whether the described duration is greater than timing threshold value, judges to detect whether number of times that exception monitoring is designated the second mark exceedes the mode of frequency threshold value, judge whether IP module at the corresponding levels is in and hang death situation state, although be also equivalent to foregoing by judging that the mode whether duration be greater than default time threshold judges whether IP module at the corresponding levels is in extension death situation state, but owing to can debug two values, relative to only debugging a value, more easily debugging is to suitable value, and improves Detection results.
It should be noted that, in above-described embodiment, elaboration be all that IP module at the corresponding levels is monitored, but the IP modules at different levels of QSYS system can adopt the mode in as above any one embodiment to monitor as IP module at the corresponding levels.
In addition, it should be noted that, various technical characteristics in above execution mode can combine arbitrarily, as long as there is not conflict or contradiction in the combination between feature, but as space is limited, describe one by one, the carrying out arbitrarily combining of the various technical characteristics therefore in above-mentioned execution mode also belongs to this specification scope of disclosure.
According to the method for supervising of the image procossing exception based on QSYS system of the invention described above, the present invention also provides a kind of supervisory control system of the image procossing exception based on QSYS system, and just the embodiment of the supervisory control system of the image procossing exception based on QSYS system of the present invention is described in detail below.The structural representation of the embodiment of the supervisory control system of the image procossing exception based on QSYS system of the present invention has been shown in Fig. 6.For convenience of explanation, part related to the present invention is merely illustrated in figure 6.
As shown in Figure 6, the supervisory control system of the image procossing exception based on QSYS system of the present invention, comprises detection module 501, timing module 502, reseting module 503, wherein:
Whether detection module 501 is low level for the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system;
Timing module 502, for when described AvalonST traffic spike occurs abnormal, is carry out timing the low level time to obtain the duration to described echo signal;
Reseting module 503, for when the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels, if described recovery operation comprises reset operation, in order to reset to IP module at the corresponding levels, need IP module at the corresponding levels that the reset signal opening of its correspondence is controlled to the supervisory control system of the image procossing exception based on QSYS system of the present invention.
Wherein in an embodiment, described echo signal is st_ready signal; Detection module 501 can detect whether the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level; When timing module 502 can be low level at the st_ready signal that IP module at the corresponding levels outputs to upper level IP module, be carry out timing the low level time to obtain the described duration to described st_ready signal.
Shown in Figure 7, be the schematic diagram during image processing apparatus based on QSYS system that the tool in the present embodiment is applied to shown in Fig. 1 based on the supervisory control system of the image procossing exception of QSYS system.In the figure 7, that to monitor the 2nd module 182 be example, namely for the 2nd module as IP module at the corresponding levels as above, when specific implementation, for traditional image processing apparatus based on QSYS system, corresponding each IP module can arrange the supervisory control system of an image procossing exception based on QSYS system of the present invention respectively, to realize the monitoring to each IP module.
Wherein in an embodiment, described echo signal is data_valid signal; Detection module 501 can obtain by reading decoding chip the information whether QSYS system have the input of signal source, if there is signal source to input, detects whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level; When timing module 502 can be low level at the data_valid signal that IP module at the corresponding levels outputs to next stage IP module, be carry out timing the low level time to obtain the described duration to described data_valid signal.
Shown in Figure 7, be the schematic diagram during image processing apparatus based on QSYS system that the tool in the present embodiment is applied to shown in Fig. 1 based on the supervisory control system 601 of the image procossing exception of QSYS system.In the figure 7, that to monitor the 2nd module 182 be example, namely for the 2nd module as IP module at the corresponding levels as above, when specific implementation, for traditional image processing apparatus based on QSYS system, corresponding each IP module can arrange the supervisory control system 601 of an image procossing exception based on QSYS system of the present invention respectively, to realize the monitoring to each IP module.
Wherein in an embodiment, reseting module 503 can judge whether the described duration is greater than default timing threshold value, if be greater than timing threshold value, then identifying default exception monitoring by the first identification renewal is the second mark, described exception monitoring mark is detected every set time section, if detect, the number of times that exception monitoring is designated the second mark exceedes default frequency threshold value, carries out recovery operation to described IP module at the corresponding levels.
Shown in Figure 8, be the schematic diagram during image processing apparatus based on QSYS system that the tool in the present embodiment is applied to shown in Fig. 1 based on the supervisory control system 602 of the image procossing exception of QSYS system.In the figure 7, that to monitor the 2nd module 182 be example, namely for the 2nd module as IP module at the corresponding levels as above, when specific implementation, for traditional image processing apparatus based on QSYS system, corresponding each IP module can arrange the supervisory control system 602 of an image procossing exception based on QSYS system of the present invention respectively, to realize the monitoring to each IP module.
Wherein in an embodiment, described set time section is 500 milliseconds, and described frequency threshold value is 3 times.
The supervisory control system of the image procossing exception based on QSYS system of the present invention and the method for supervising one_to_one corresponding of the image procossing exception based on QSYS system of the present invention, the technical characteristic of setting forth in the embodiment of the method for supervising of the above-mentioned image procossing exception based on QSYS system and beneficial effect thereof are all applicable to, in the embodiment of the supervisory control system of the image procossing exception based on QSYS system, hereby state.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1., based on a method for supervising for the image procossing exception of QSYS system, it is characterized in that, comprise the steps:
Whether the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system is low level;
If so, be carry out timing the low level time to obtain the duration to described echo signal;
When the described duration is greater than default time threshold, recovery operation is carried out to described IP module at the corresponding levels.
2. the method for supervising of the image procossing exception based on QSYS system according to claim 1, is characterized in that:
Described echo signal is st_ready signal;
Whether the echo signal in the AvalonST traffic spike of the IP module at the corresponding levels of described detection QSYS system is that low level step comprises step: detect whether the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level;
The described time changed to described echo signal carries out timing and obtains the duration and comprise step: when the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level, be carry out timing the low level time to obtain the described duration to described st_ready signal.
3. the method for supervising of the image procossing exception based on QSYS system according to claim 1, is characterized in that:
Described echo signal is data_valid signal;
Whether the echo signal in the AvalonST traffic spike of the IP module at the corresponding levels of described detection QSYS system is that low level step comprises step: obtain by reading decoding chip the information whether QSYS system has the input of signal source, if there is signal source to input, detect whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level;
The described time changed to described echo signal carries out timing and obtains the duration and comprise step: when the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level, be carry out timing the low level time to obtain the described duration to described data_valid signal.
4. the method for supervising of the image procossing exception based on QSYS system according to claim 1, is characterized in that, when the described duration is greater than default time threshold, carries out recovery operation comprise the steps: described IP module at the corresponding levels
Judge whether the described duration is greater than default timing threshold value;
If be greater than timing threshold value, then identifying default exception monitoring by the first identification renewal is the second mark;
Detect described exception monitoring mark every set time section, if detect, the number of times that exception monitoring is designated the second mark exceedes default frequency threshold value, carries out recovery operation to described IP module at the corresponding levels.
5. the method for supervising of the image procossing exception based on QSYS system according to claim 4, is characterized in that:
Described set time section is 500 milliseconds, and described frequency threshold value is 3 times.
6., based on a supervisory control system for the image procossing exception of QSYS system, it is characterized in that, comprising:
Whether detection module is low level for the echo signal detected in the AvalonST traffic spike of the IP module at the corresponding levels of QSYS system;
Timing module, for when described AvalonST traffic spike occurs abnormal, is carry out timing the low level time to obtain the duration to described echo signal;
Reseting module, for when the described duration is greater than default time threshold, carries out recovery operation to described IP module at the corresponding levels.
7. the supervisory control system of the image procossing exception based on QSYS system according to claim 6, is characterized in that:
Described echo signal is st_ready signal;
Described detection module detects whether the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level;
Described timing module, when the st_ready signal that IP module at the corresponding levels outputs to upper level IP module is low level, is carry out timing the low level time to obtain the described duration to described st_ready signal.
8. the supervisory control system of the image procossing exception based on QSYS system according to claim 6, is characterized in that:
Described echo signal is data_valid signal;
Described detection module obtains by reading decoding chip the information whether QSYS system has the input of signal source, if there is signal source to input, detects whether the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level;
Described timing module, when the data_valid signal that IP module at the corresponding levels outputs to next stage IP module is low level, is carry out timing the low level time to obtain the described duration to described data_valid signal.
9. the supervisory control system of the image procossing exception based on QSYS system according to claim 6, is characterized in that:
Described reseting module judges whether the described duration is greater than default timing threshold value, if be greater than timing threshold value, then identifying default exception monitoring by the first identification renewal is the second mark, described exception monitoring mark is detected every set time section, if detect, the number of times that exception monitoring is designated the second mark exceedes default frequency threshold value, carries out recovery operation to described IP module at the corresponding levels.
10. the supervisory control system of the image procossing exception based on QSYS system according to claim 9, is characterized in that:
Described set time section is 500 milliseconds, and described frequency threshold value is 3 times.
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