CN101996156B - Universal processor for supporting recombinable polycaryon IP (Internet Protocol) and method thereof - Google Patents
Universal processor for supporting recombinable polycaryon IP (Internet Protocol) and method thereof Download PDFInfo
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Abstract
The invention discloses a universal processor for supporting a recombinable polycaryon IP (Internet Protocol) and a method thereof. The universal processor comprises a plurality of IP core modules, an instruction analyzing unit and an IP core configuration unit, wherein the instruction analyzing unit is configured into an input instruction and is used for analyzing an instruction, the instruction comprises at least one configuration domain data and at least one operation domain data, and the instruction analyzing unit is used for respectively outputting the configuration domain data and the operation domain data; the IP core configuration unit comprises first input, a plurality of second input, a plurality of second output and third output, wherein the first input is used for inputting the configuration domain data, the plurality of second output are respectively coupled to the output of the plurality of IP core modules, the plurality of second output are respectively coupled to the input of the plurality of IP core modules, and the third output is coupled to the output of the universal processor; the IP core configuration unit is configured into a connection mode among the plurality of first input, second output and third output according to the configuration domain data, and the plurality of IP modules execute operation based on the operation domain data.
Description
Technical field
The present invention relates to processor, specifically, relate to a kind of general processor and a kind of method for the multinuclear IP that can recombinate general processor support for the multinuclear IP that supports to recombinate.
Background technology
Processor is a vitals in the computing machine, and its performance often determines the performance of computing machine.The exploitation of processor is the major issue that people are concerned about with research.
Fig. 2 shows the general structure of the general processor of prior art.
As shown in Figure 2, general processor 2000 comprises instruction decoding device 2010 and general arithmetic and logic unit 2020.
Instruction decoding device 2010 receives instruction, and the Instruction decoding operation is carried out in instruction, and produces the Instruction decoding result.
General arithmetic and logic unit 2020 according to the Instruction decoding result to pending data executable operations, with produce output result.
General processor 2000 can also comprise many other parts, for example, and clock unit 2030, storer 2040, test cell 2050 etc.
Fig. 2 illustration the implementation of general processor of prior art.In the implementation of prior art, model a general structure, that is, and general arithmetic and logic unit 2020.This general structure is carried out various operations according to the control signal (that is, the Instruction decoding result) that offers it to pending data.Provide control signal by instruction decoding device 2010.
For this general structure, system's receive data and control signal, and produce output.Like this, for each new program (application), the programmer only need to provide one group of new control signal (instruction), and does not need to reconnect hardware.
There are many problems in the structure of this general processor.It exchanges versatility for take the sacrifice performance as cost.
For example, in the general processor structure of prior art, all processing finally all need to carry out by general arithmetic and logic unit 2020.Therefore, with regard to this point, the general processor of prior art be serial or centralized.And in fact, may there be many processing can executed in parallel.In the general processor of prior art, the processing that these originally can executed in parallel must wait for that general arithmetic and logic unit 2020 sequentially carries out them.Like this, the speed of processing has been lowered.
In addition, because general arithmetic and logic unit 2020 is fixed, therefore, for data being carried out various operations, therefore, need to there be a powerful instruction decoding device 2010 to come to provide various control signals for it.This has increased the realization complexity and difficulties of instruction decoding device.In the situation that have, instruction decoding device is loaded owing to need to bearing too much processing, and becomes the bottleneck of restriction processor performance.
In addition, in order to be applicable to various application, for originally can by the one step completed processing of specialized hardware, in the general processor of prior art, often needing it is split as a plurality of processing.In fact this greatly reduce the handling property of processor.
Fig. 3 shows the another kind of structure of the general processor of prior art.
As shown in Figure 3, general processor 3000 comprises allocation units 3010, instruction decoding device 3020, specialized processing units 3030 and general arithmetic and logic unit 3040.
Specialized processing units 3030 is used for realizing special processing capacity.
General arithmetic and logic unit 3050 according to the Instruction decoding result to pending data executable operations, with produce output result.
Because existing defective in the general processor as previously described, therefore, in some cases, general processor shown in Figure 2 can't satisfy the demand of some application.Therefore, in the structure of general processor shown in Figure 3, provide the processing unit of special use to satisfy this part demand.
In fact, the structure of general processor shown in Figure 3 only is the simple superposition of dedicated processes hardware and general processor, and the structure of general processor shown in Figure 2 is not made any substantial change.
For example, the resource in the chip is limited, can not a specialized processing units be set for every kind of application.If for every kind of application a specialized processing units is set, general arithmetic and logic unit has also just lost the meaning that exists.
In addition, even if in the situation that be provided with specialized processing units, the hard wire structure of specialized processing units and general arithmetic and logic unit is also all fixed.Therefore, be difficult to configure neatly the annexation between the unit, thereby dynamically the result with a unit offers another unit use, and perhaps the result with another unit offers a unit use, perhaps carries out concurrently processing by different unit.These often also are the importances that improves processor performance.
In addition, if only adopt the dedicated processes hardware circuit, although can be for a certain optimizing application circuit, thereby reach desirable performance,, the scope of its application but is limited by very large.
In addition, the present inventor notices, the technician has developed the many IP kernels that are used for realizing various functions.These IP kernels are optimized hardware for the processing that will carry out.They often can take resource seldom, and very high processing speed is provided.These IP kernels often can reach very high handling property.But because the restriction of this structure of the general processor of prior art, these IP kernels are difficult to be utilized by general processor, perhaps only can be used as specialized processing units attached in the general processor.
In addition, although in the prior art, can use field programmable device (FPGA) etc. to realize some application functions,, after hardware configuration program was downloaded among the FPGA, the function of this FPGA also just had been fixed.On the one hand, can not be every kind of application function download configuration program again all.On the other hand, if realize multiple application function when seeking common ground, then in the prior art, FPGA can only be configured to have the structure of foregoing general processor.This still can't solve the problems of the technologies described above.
Therefore, need to propose a kind of new technology and solve above-mentioned any problem of the prior art.
Summary of the invention
One object of the present invention is to solve at least in part at least one technical matters in the problems of the prior art recited above.
Another object of the present invention is to provide a kind of general processor of supporting multinuclear IP.
Another object of the present invention is the IP resource in the dynamic-configuration general processor.
According to a first aspect of the invention, provide a kind of general processor for the multinuclear IP that supports to recombinate, having comprised: a plurality of IP kernel modules; The instruction resolution unit, it is configured to input instruction and instruction is resolved, and wherein, this instruction comprises at least one configuration numeric field data and at least one operation domain data, wherein, this instruction resolution unit also is configured to export respectively described configuration numeric field data and operation domain data; And IP kernel dispensing unit, comprise be used to the first input of inputting described configuration numeric field data, a plurality of the second input, a plurality of the second output and the 3rd output, wherein these a plurality of second inputs are coupled to respectively the output of described a plurality of IP kernel modules, these a plurality of the second outputs are coupled to respectively the input of described a plurality of IP kernel modules, and the 3rd output is coupled to the output of described general processor.Wherein, described IP kernel dispensing unit be configured to according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output and the 3rd output between connected mode.Wherein, described a plurality of IP kernel module is carried out the operation based on described operation domain data.
Preferably, described general processor also comprises: command decoder, it is configured to receive the operation domain data from described instruction resolution unit output, and described operation domain data are carried out the Instruction decoding operation, and the output order decode results.Wherein, described IP kernel dispensing unit also comprises the 4th input, is used for receiving described Instruction decoding result.Wherein, described IP kernel dispensing unit also be configured to according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output and the 4th the input between connected mode.
Preferably, described IP kernel dispensing unit also comprises: the 5th input is used for receiving pending data.Wherein, described IP kernel dispensing unit also be configured to according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output, the 4th the input and the 5th the input between connected mode.
Preferably, described configuration numeric field data comprises the information that is used to indicate connected mode, and described operation domain data comprise the information that is used to indicate the operation that will realize.
Preferably, described IP kernel dispensing unit comprises a plurality of gating circuits, each gating circuit comprises a plurality of input ends and output terminal, wherein, described a plurality of input end is connected to respectively described a plurality of the second input, the 4th input and the 5th input, described output terminal is connected in described a plurality of the second output and the 3rd output, wherein, each gating circuit is configured to select and export selected results from described a plurality of the second inputs, the 4th input and the 5th input according to described configuration numeric field data.
Preferably, each gating circuit also comprises control end, and each gating circuit is configured to select and export selected results from described a plurality of the second inputs, the 4th input and the 5th input according to the signal on the control end.Wherein, the signal on the control end of each gating circuit is set up according to described configuration numeric field data.
Preferably, described IP kernel dispensing unit is controllable switching array.
Preferably, described controllable switching array comprises transistor or CMOS pipe.
Preferably, the on-off element in the described controllable switching array has control end, is used for the turn-on and turn-off of gauge tap element.Preferably, the control signal on the control end is set up according to described configuration numeric field data.
Preferably, described connected mode comprises: the array mode of series system or parallel way or series and parallel connections.
Preferably, described a plurality of IP kernel module comprises general processor IP kernel module.
Preferably, described a plurality of IP kernel module comprises Instruction decoding IP kernel module and arithmetic and logic unit IP kernel module.
Preferably, described a plurality of IP kernel module is arranged in identical chip.
Preferably, described a plurality of IP kernel module is located in the different chips.
According to a second aspect of the invention, provide a kind of method for the multinuclear IP that can recombinate general processor support, comprising: first step configures a plurality of IP kernel modules; Second step, the input instruction is also resolved instruction, and wherein, this instruction comprises at least one configuration numeric field data and at least one operation domain data; Third step is exported respectively described configuration numeric field data and operation domain data; The 4th step, described configuration numeric field data is inputted in configuration first; The 5th step configures a plurality of the second outputs of inputting to be coupled to described a plurality of IP kernel modules; The 6th step configures a plurality of the second inputs of exporting to be coupled to described a plurality of IP kernel modules; The 7th step configures the 3rd output of exporting to be coupled to described general processor; The 8th step, according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output and the 3rd output between connected mode; And the 9th step, carry out operation based on described operation domain data by described a plurality of IP kernel modules.
Preferably, described method also comprises: described operation domain data are carried out the Instruction decoding operation, and the output order decode results; Configure the 4th and input to receive described Instruction decoding result, wherein, described the 8th step comprises: according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output and the 4th the input between connected mode.
Preferably, described method also comprises: configure the 5th and input to receive pending data, wherein, described the 8th step comprises: according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output, the 4th the input and the 5th the input between connected mode.
Preferably, described configuration numeric field data comprises the information that is used to indicate connected mode, and described operation domain data comprise the information that is used to indicate the operation that will realize.
Preferably, carry out described the 8th step by a plurality of gating circuits, wherein, each gating circuit comprises a plurality of input ends and output terminal, wherein, described a plurality of input ends are connected respectively to described a plurality of the second input, the 4th input and the 5th input, described output terminal is connected in exporting one of described a plurality of the second output and the 3rd, wherein, each gating circuit is selected and export selected results from described a plurality of the second inputs, the 4th input and the 5th input according to described configuration numeric field data.
Preferably, each gating circuit also comprises control end, and each gating circuit is selected and export selected results from described a plurality of the second inputs, the 4th input and the 5th input according to the signal on the control end, and wherein, the signal on the control end of each gating circuit is set up according to described configuration numeric field data.
Preferably, carry out described the 8th step by controllable switching array.
Preferably, described controllable switching array comprises transistor or CMOS pipe.
Preferably, the on-off element in the described controllable switching array has control end, is used for the turn-on and turn-off of gauge tap element.Preferably, the control signal on the control end is set up according to described configuration numeric field data.
Preferably, described connected mode comprises: the array mode of series system or parallel way or series and parallel connections.
Preferably, described a plurality of IP kernel module comprises general processor IP kernel module.
Preferably, described a plurality of IP kernel module comprises Instruction decoding IP kernel module and arithmetic and logic unit IP kernel module.
Preferably, described a plurality of IP kernel module is arranged in identical chip.
Preferably, described a plurality of IP kernel module is located in the different chips.
According to a third aspect of the invention we, provide a kind of computing equipment that comprises according to general processor of the present invention.
An advantage of the present invention is, can support a plurality of IP kernels in general processor.
An advantage of the present invention is, neatly the configure generic processor.
Another advantage of the present invention is, can configure neatly the connected mode of IP kernel.
Another advantage of the present invention is, can dynamically configure by instruction the connected mode of IP kernel.
By referring to the detailed description of accompanying drawing to exemplary embodiment of the present invention, it is clear that further feature of the present invention and advantage thereof will become.
Description of drawings
The accompanying drawing that consists of the part of instructions has been described embodiments of the invention, and is used for explaining principle of the present invention together with the description.
With reference to accompanying drawing, according to following detailed description, can more be expressly understood the present invention, wherein:
Fig. 1 illustrates the block diagram that can use computing equipment of the present invention.
Fig. 2 is the block diagram that a kind of general processor of prior art is shown.
Fig. 3 is the block diagram that the another kind of general processor of prior art is shown.
Fig. 4 is the block diagram that illustrates according to the general processor of the first embodiment of the present invention.
Fig. 5 shows the structure of the instruction of adopting among the present invention.
Fig. 6 is the process flow diagram that illustrates according to the method for the first embodiment of the present invention.
Fig. 7 is the block diagram of the IP kernel dispensing unit in the general processor that illustrates according to a second embodiment of the present invention.
Fig. 8 is the block diagram that the IP kernel dispensing unit in the general processor of a third embodiment in accordance with the invention is shown.
Fig. 9 is the block diagram that an example of a third embodiment in accordance with the invention is shown.
Embodiment
Describe various exemplary embodiment of the present invention in detail now with reference to accompanying drawing.It should be noted that: unless specify in addition, the parts of setting forth in these embodiments and positioned opposite, numeral expression formula and the numerical value of step do not limit the scope of the invention.
Below be illustrative to the description only actually of at least one exemplary embodiment, never as any restriction to the present invention and application or use.
May not discuss in detail for the known technology of person of ordinary skill in the relevant, method and apparatus, but in suitable situation, described technology, method and apparatus should be regarded as the part of instructions.
In all examples with discussing shown here, it is exemplary that any occurrence should be construed as merely, rather than as restriction.Therefore, other example of exemplary embodiment can have different values.
It should be noted that: represent similar terms in similar label and the letter accompanying drawing below, therefore, in case be defined in a certain Xiang Zaiyi accompanying drawing, then in accompanying drawing subsequently, do not need it is further discussed.
In addition, need to prove, be well known that for those skilled in the art, can (instruction) be stored in the identical storer and uses for processor with program with data.Therefore, although what describe in this manual is " director data ", it will be appreciated by those skilled in the art that described " director data " comprises instruction or data or instruction and data.
In addition, need to prove, in the accompanying drawings, only connect by a line between two modules, still, those skilled in the art should know, width according to the data path between two modules, may have many hardware wirings, and this line in the accompanying drawing only is schematically, and not as any limitation of the invention.
＜hardware configuration 〉
Fig. 1 is the block diagram that the hardware configuration of the computer system 1000 that can realize embodiments of the invention is shown.
As shown in Figure 1, computer system comprises computing machine 1110.Computing machine 1110 comprises processing unit 1120, system storage 1130, fixed non-volatile memory interface 1140, mobile non-volatile memory interface 1150, user's input interface 1160, network interface 1170, video interface 1190 and the output peripheral interface 1195 that connects via system bus 1121.
Fixed non-volatile memory 1141 such as hard disk is connected to fixed non-volatile memory interface 1140.Fixed non-volatile memory 1141 for example can storage operating system 1144, application program 1145, other program module 1146 and some routine data 1147.
Mobile nonvolatile memory such as floppy disk 1151 and CD-ROM drive 1155 is connected to mobile non-volatile memory interface 1150.For example, floppy disk can be inserted in the floppy disk 1151, and CD (CD) can be inserted in the CD-ROM drive 1155.
Input equipment such as mouse 1161 and keyboard 1162 is connected to user's input interface 1160.
It will be appreciated by those skilled in the art that computer system shown in Figure 1 only is illustrative and never means any restriction to the present invention, its application or use.
The＜the first embodiment 〉
Illustrate according to the first embodiment of the present invention below with reference to Fig. 4, Fig. 5 and Fig. 6.Fig. 4 shows according to can the recombinate block diagram of general processor of multinuclear IP of the support of the first embodiment of the present invention.Fig. 5 schematically shows the general structure of the instruction of adopting in the present invention.Fig. 6 shows being used at can the recombinate process flow diagram of method of multinuclear IP of general processor support according to the first embodiment of the present invention.
As shown in Figure 4, according to the first embodiment of the present invention be used for to support can recombinate the general processor 4000 of multinuclear IP comprise instruction resolution unit 4100, IP kernel dispensing unit 4200 and a plurality of IP kernel module 1,2 ..., n, wherein, n is more than or equal to 1.
IP kernel dispensing unit 4200 comprises the first input I
1, a plurality of second the input I
2-1, I
2-2..., I
2-n, a plurality of second output O
2-1, O
2-2... O
2-nAnd the 3rd output O
3, wherein, n is more than or equal to 1.
As shown in Figure 4, described the first input I
1Input is from the configuration numeric field data of instruction resolution unit 4100.Described a plurality of the second input I
2-1, I
2-2..., I
2-nBe coupled to respectively a plurality of IP kernel modules 1,2 ..., the output of n.Described a plurality of the second output O
2-1, O
2-2... O
2-nBe coupled to respectively described a plurality of IP kernel module 1,2 ..., the input of n.Described the 3rd output O
3Be coupled to the output of described general processor 4000
Described IP kernel dispensing unit 4200 can be adjusted described a plurality of the second input I according to described configuration numeric field data
2-1, I
2-2..., I
2-n, a plurality of second output O
2-1, O
2-2... O
2-nWith the 3rd output O
3Between connected mode.
For example, as shown in Figure 4, general processor 4000 can also comprise command decoder 4030.Command decoder 4030 receives from the operation domain data of described instruction resolution unit 4010 outputs.The operation domain data that 4030 pairs of command decoders receive are carried out the Instruction decoding operation, and the output order decode results.The Instruction decoding operation is well known in the art, therefore, here is not further described in more detail.
Described IP kernel dispensing unit 4020 can also comprise the 4th input I
4The 4th input I
4Be used for receiving the Instruction decoding result from command decoder 4030 outputs.
Certainly, it will be apparent to one skilled in the art that can directly be imported into the 4th from the operation domain data of instruction resolution unit 4100 outputs inputs I
4, and without command decoder 4030.Perhaps, a part directly is imported into the 4th input I in the described operation domain
4, and another part is imported into the 4th input I through command decoder 4030
4
In this case, described IP kernel dispensing unit 4020 can be adjusted described a plurality of the second input I according to the configuration numeric field data
2-1, I
2-2..., I
2-n, a plurality of second output O
2-1, O
2-2... O
2-n, the 3rd output O
3With the 4th input I
4Between connected mode.
For example, as shown in Figure 4, general processor 4000 is also processed data.Pending data are imported into the 5th input I of IP kernel dispensing unit
5
In this case, described IP kernel dispensing unit 4020 can also be adjusted described a plurality of the second input I according to described configuration numeric field data
2-1, I
2-2..., I
2-n, a plurality of second output O
2-1, O
2-2... O
2-n, the 3rd output O
3, the 4th the input I
4With the 5th input I
5Between connected mode.
Described IP kernel dispensing unit 4020 by adjust connected mode between each input and output configure described a plurality of IP kernel module 1,2 ... n.
For example, described IP kernel dispensing unit 4020 can which IP kernel module of choice for use.For example, described IP kernel dispensing unit 4020 can configure employed IP kernel module with array mode of series system or parallel way or series and parallel connections etc.
Described a plurality of IP kernel module 1,2 ..., n carries out the operation based on described operation domain data.For example, some in described a plurality of IP kernel module or all can directly operate based on the operation domain data.For example, some in described a plurality of IP kernel module or all can come executable operations according to the Instruction decoding result who is obtained by the operation domain data.
Described a plurality of IP kernel module can comprise general processor IP kernel module, realizes general processor in this module.In this case, this general processor IP kernel module can be positioned at identical chip with universal processor module 4000 according to an embodiment of the invention.Perhaps, this general processor IP kernel module can be positioned at different chips from universal processor module 4000 according to an embodiment of the invention.For example, this general processor IP kernel module can be the chip that another piece comprises general processor.
In addition, described a plurality of IP kernel module can comprise arithmetic and logic unit IP kernel module.Like this, the Instruction decoding result of command decoder 4300 is imported into this arithmetic sum logical ip core module by IP kernel dispensing unit 4200, thereby can carry out the general processor operation of prior art.
For example, described a plurality of IP kernel module can also comprise instruction decoding device IP kernel module.In this case, can omit the instruction decoding device 4030 shown in Fig. 4.
For example, described a plurality of IP kernel module can comprise arithmetic and logic unit IP kernel module and instruction decoding device IP kernel module.In this case, can pass through IP kernel dispensing unit 4020, connect described arithmetic and logic unit IP kernel module and instruction decoding device IP kernel module, thereby can realize the function of the general processor of prior art.This provides a kind of mode of flexible configuration processor.
As previously described, part or all in described a plurality of IP kernel module can be arranged in identical chip.For example, part or all in described a plurality of IP kernel module can be positioned at general processor 4000 and be positioned at identical chip.
Perhaps, part or all in described a plurality of IP kernel module can be arranged in different chips.For example, part or all in described a plurality of IP kernel module can be positioned at from general processor 4000 and be positioned at different chips.
Below with reference to Fig. 5 employed instruction 5000 among the present invention is described.
For example, as shown in Figure 5, instruction 5000 comprise at least one configuration numeric field data 1,2 ..., m and at least one operation domain data 1,2 ..., m, wherein, m is more than or equal to 1.
Described configuration numeric field data comprises the information that is used to indicate connected mode.As previously described, described connected mode such as array mode that can comprise series system or parallel way or series and parallel connections etc.
Described operation domain data comprise the information that is used to indicate the operation that will realize.
As previously described, these operation domain data for example can be the objects that will be processed by command decoder 4300.In this case, these operation domain data for example with instruction class of the prior art seemingly.
Perhaps, these operation domain data can be directly inputted in the IP kernel module, for the IP kernel module.Control data that these operation domain data can be the IP kernel modules or can be by the data of IP kernel resume module.
Below, with reference to Fig. 6 described being used in can the recombinate method 6000 of multinuclear IP of general processor support according to the first embodiment of the present invention.
Fig. 6 shows the process flow diagram according to the method 6000 of the first embodiment of the present invention.
As shown in Figure 6, at first step s6100, configure a plurality of IP kernel modules.For example, a plurality of IP kernel modules are set in general processor.
At second step s6200, instruction is input in the processor and to instruction resolves.This instruction comprises at least one configuration numeric field data and at least one operation domain data.
At third step s6300, output configures numeric field data and operation domain data respectively.
At the 4th step s6400, configuration is used for inputting the first input of described configuration numeric field data.
At the 5th step s6500, configure a plurality of the second inputs.These a plurality of the second inputs are coupled to respectively the output of described a plurality of IP kernel modules.
At the 6th step s6600, configure a plurality of the second outputs.These a plurality of the second outputs are coupled to respectively the input of described a plurality of IP kernel modules.
At the 7th step s6700, configure the 3rd output.The 3rd output is coupled to the output of general processor.
At the 8th step s6800, according to the configuration numeric field data adjust described a plurality of second the input, a plurality of second output and the 3rd output between connected mode.
In addition, for example in an embodiment of the present invention, can also carry out the Instruction decoding operation to the operation domain data, and the output order decode results.In addition, can also configure be used to the 4th input that receives described Instruction decoding result.
In this case, can according to the configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output and the 4th the input between connected mode.
In addition, for example in an embodiment of the present invention, can also configure the 5th input, to receive pending data.
In this case, can according to described configuration numeric field data adjust described a plurality of second the input, a plurality of second output, the 3rd output, the 4th the input and the 5th the input between connected mode.
As previously described, described connected mode such as array mode that can comprise series system or parallel way or series and parallel connections etc.
The 9th step is by the operation of described a plurality of IP kernel modules execution based on described operation domain data.
As previously described, for example, described a plurality of IP kernel modules can comprise general processor IP kernel module.For example, described a plurality of IP kernel module can comprise arithmetic and logic unit IP kernel module.For example, described a plurality of IP kernel module can be arranged in identical chip.For example, described a plurality of IP kernel module can be located in the different chips.
The＜the second embodiment 〉
Describe according to a second embodiment of the present invention below with reference to Fig. 7.A kind of implementation of the IP kernel dispensing unit among the first embodiment is provided in a second embodiment.Because the difference of the second embodiment and the first embodiment only is the IP kernel dispensing unit, therefore, for brevity, only describes below this unit, and omit the description to other parts.
Fig. 7 only shows IP kernel dispensing unit 4200-a.The other parts of general processor can be with shown in Figure 4 identical.
In a second embodiment, realize the IP kernel dispensing unit by gating circuit.
As shown in Figure 7, IP kernel dispensing unit 4200-a comprise a plurality of gating circuit 4200-a-1,4200-a-1 ..., 4200-a-1 and 4200-a-o.
Each gating circuit comprises a plurality of input ends and output terminal.
A plurality of input ends of each gating circuit are connected to respectively a plurality of the second input I of IP kernel dispensing unit 4200-a
2-1, I
2-2..., I
2-n, the 4th the input I
4With the 5th input I
5
The output terminal of each gating circuit is connected to a plurality of the second output O
2-1, O
2-2... O
2-nWith the 3rd output O
3In one.The output terminal of described a plurality of gating circuits is connected respectively to a plurality of the second output O of IP kernel dispensing unit 4200-a
2-1, O
2-2... O
2-nWith the 3rd output O
3
Each gating circuit also comprises control end.For example, according to the configuration numeric field data control signal on the control end of each gating circuit is set.
Each gating circuit is inputted I according to the control signal on the control end from described a plurality of second
2-1, I
2-2..., I
2-n, the 4th the input I
4With the 5th input I
5In select and export selected results.
For example, can realize described gating circuit by transistor, CMOS pipe etc.This is known for those skilled in the art, therefore, no longer it is further described in more detail.
The＜the three embodiment 〉
Below with reference to Fig. 8 a third embodiment in accordance with the invention is described.The another kind of implementation of the IP kernel dispensing unit among the first embodiment is provided in the 3rd embodiment.Because the difference of the 3rd embodiment and the first embodiment only is the IP kernel dispensing unit, therefore, for brevity, only describes below this unit, and omit the description to other parts.
Fig. 8 only shows IP kernel dispensing unit 4200-b.The other parts of general processor can be with shown in Figure 4 identical.
In the 3rd embodiment, realize the IP kernel dispensing unit by controllable switching array.
As shown in Figure 8, by the controllable switch element S in the controllable switching array
1-21, S
1-22, S
1-23, S
1-4, S
1-5, S
2-21, S
2-22, S
2-23, S
2-4, S
2-5..., S
N-21, S
N-22, S
N-23, S
N-4, S
N-5, S
O-21, S
O-22, S
O-23, S
O-4, S
O-5, with a plurality of the second input I
2-1, I
2-2..., I
2-n, the 4th the input I
4With the 5th input I
5Be connected respectively to a plurality of the second output O
2-1, O
2-2... O
2-nWith the 3rd output O
3
Control annexation between described each input and output by the on off state of described controllable switch element.
Described controllable switching array comprises transistor or CMOS pipe.On-off element in the described controllable switching array for example can have control end, is used for the turn-on and turn-off of gauge tap element.For example, the control signal on the control end can be set up according to described configuration numeric field data.
In the situation that realize described controllable switch element by transistor, two links of on-off element for example are transistorized collector and emitter-base bandgap grading, and its control end for example is transistorized base stage.
In the situation that realize described controllable switch element by the CMOS pipe, and source electrode and drain electrode that two links of on-off element for example are the CMOS pipes, its control end for example is transistorized grid.
The＜the four embodiment 〉
In the fourth embodiment of the present invention, for example, can be used on the general processor that adopts in the computing equipment according to the first to the 3rd embodiment of the present invention.
＜example 1 〉
Fig. 9 shows an example of a third embodiment in accordance with the invention.Fig. 9 A shows the connected mode of the IP kernel dispensing unit of a third embodiment in accordance with the invention.Fig. 9 A shows through the simplified electrical circuit diagram after connecting.
In the present example, suppose to exist 3 IP kernel modules, that is, and totalizer IP kernel module, multiplier IP kernel module and divider IP kernel module.
In Fig. 9 A, according to the configuration of configuration numeric field data, controllable switch element S
1-4, S
2-5, S
3-21, S
3-22, S
O-23Conducting.
Fig. 9 B shows the circuit of final realization.In Fig. 9 B, pending data are imported into totalizer IP kernel module, and the Instruction decoding result is imported into multiplier IP kernel module.The result of totalizer IP kernel module and multiplier IP kernel module is imported into divider IP kernel module.The result of divider IP kernel module is output as Output rusults.
Fig. 9 only is an example of the explanation third embodiment of the present invention, rather than any limitation of the invention.
May realize in many ways method of the present invention and processor.For example, can realize method of the present invention and processor by any combination of software, hardware, firmware or software, hardware, firmware.The said sequence that is used for the step of described method only is in order to describe, and the step of method of the present invention is not limited to above specifically described order, unless otherwise specify.In addition, in certain embodiments, can be the program that is recorded in the recording medium with the invention process also, these programs comprise for the machine readable instructions that realizes the method according to this invention.Thereby the present invention also covers the recording medium that storage is used for the program of executive basis method of the present invention.
Although by example specific embodiments more of the present invention are had been described in detail, it should be appreciated by those skilled in the art, above example only is in order to describe, rather than in order to limit the scope of the invention.It should be appreciated by those skilled in the art, can in the situation that do not depart from the scope of the present invention and spirit, above embodiment be made amendment.Scope of the present invention is limited by claims.
Claims (25)
1. the general processor of the multinuclear IP that be used for to support to recombinate comprises:
A plurality of IP kernel modules;
The instruction resolution unit, it is configured to input instruction and instruction is resolved, wherein, this instruction comprises at least one configuration numeric field data and at least one operation domain data, wherein, this instruction resolution unit also is configured to export respectively described configuration numeric field data and operation domain data, wherein, described configuration numeric field data comprises the information that is used to indicate connected mode, and described operation domain data comprise the information that is used to indicate the operation that will realize; And
The IP kernel dispensing unit comprises:
The first input is used for inputting described configuration numeric field data,
A plurality of the second inputs, these a plurality of the second inputs are coupled to respectively the output of described a plurality of IP kernel modules,
A plurality of the second outputs, these a plurality of the second outputs are coupled to respectively the input of described a plurality of IP kernel modules, and
The 3rd output, the 3rd output is coupled to the output of described general processor,
Wherein, described IP kernel dispensing unit be configured to according to described configuration numeric field data adjust described the 3rd output, described a plurality of second the input and described a plurality of second output between connected mode, wherein, described connected mode comprises: the array mode of series system or parallel way or series and parallel connections
Wherein, described a plurality of IP kernel module is carried out the operation based on described operation domain data.
2. general processor as claimed in claim 1 also comprises:
Command decoder, it is configured to receive the operation domain data from described instruction resolution unit output, and described operation domain data are carried out the Instruction decoding operation, and the output order decode results,
Wherein, described IP kernel dispensing unit also comprises the 4th input, is used for receiving described Instruction decoding result,
Wherein, described IP kernel dispensing unit also be configured to according to described configuration numeric field data adjust described the 3rd output, described the 4th the input, described a plurality of second the input and described a plurality of second output between connected mode.
3. general processor as claimed in claim 2, wherein, described IP kernel dispensing unit also comprises: the 5th input, be used for receiving pending data,
Wherein, described IP kernel dispensing unit also be configured to according to described configuration numeric field data adjust described the 3rd output, described the 4th the input, described the 5th the input, described a plurality of second the input and a plurality of second output between connected mode.
4. general processor as claimed in claim 3,
Wherein, described IP kernel dispensing unit comprises a plurality of gating circuits, each gating circuit comprises output terminal and a plurality of input end, wherein, described a plurality of input end is connected to respectively described the 4th input, described the 5th input and described a plurality of the second input, described output terminal is connected in described the 3rd output and described a plurality of the second output, wherein, each gating circuit is configured to select and export selected results from described the 4th input, described the 5th input and described a plurality of the second input according to described configuration numeric field data.
5. general processor as claimed in claim 4,
Wherein, each gating circuit also comprises control end, and each gating circuit is configured to select and export selected results from described the 4th input, described the 5th input and described a plurality of the second input according to the signal on the control end, and
Wherein, the signal on the control end of each gating circuit is set up according to described configuration numeric field data.
6. such as any one the described general processor among the claim 1-3,
Wherein, described IP kernel dispensing unit is controllable switching array.
7. general processor as claimed in claim 6,
Wherein, described controllable switching array comprises transistor or CMOS pipe.
8. general processor as claimed in claim 6,
Wherein, the on-off element in the described controllable switching array has control end, is used for the turn-on and turn-off of gauge tap element,
Wherein, the control signal on the control end is set up according to described configuration numeric field data.
9. such as any one the described general processor among the claim 1-3,
Wherein, described a plurality of IP kernel module comprises general processor IP kernel module.
10. such as any one the described general processor among the claim 1-3,
Wherein, described a plurality of IP kernel module comprises Instruction decoding IP kernel module and arithmetic and logic unit IP kernel module.
11. such as any one the described general processor among the claim 1-3,
Wherein, described a plurality of IP kernel module is arranged in identical chip.
12. such as any one the described general processor among the claim 1-3,
Wherein, described a plurality of IP kernel module is arranged in different chips.
13. the method for the multinuclear IP that can recombinate general processor support comprises:
First step configures a plurality of IP kernel modules;
Second step, the input instruction is also resolved instruction, wherein, this instruction comprises at least one configuration numeric field data and at least one operation domain data, wherein, described configuration numeric field data comprises the information that is used to indicate connected mode, and described operation domain data comprise the information that is used to indicate the operation that will realize;
Third step is exported respectively described configuration numeric field data and operation domain data;
The 4th step, described configuration numeric field data is inputted in configuration first;
The 5th step configures a plurality of the second outputs of inputting to be coupled to described a plurality of IP kernel modules;
The 6th step configures a plurality of the second inputs of exporting to be coupled to described a plurality of IP kernel modules;
The 7th step configures the 3rd output of exporting to be coupled to described general processor;
The 8th step, according to described configuration numeric field data adjust described the 3rd output, described a plurality of second the input and described a plurality of second output between connected mode, wherein, described connected mode comprises: the array mode of series system or parallel way or series and parallel connections; And
The 9th step is by the operation of described a plurality of IP kernel modules execution based on described operation domain data.
14. method as claimed in claim 13 also comprises:
Described operation domain data are carried out the Instruction decoding operation, and the output order decode results;
Configure the 4th and input to receive described Instruction decoding result;
Wherein, described the 8th step comprises: according to described configuration numeric field data adjust described the 3rd output, described the 4th the input, described a plurality of second the input and described a plurality of second output between connected mode.
15. method as claimed in claim 14 also comprises:
Configure the 5th and input to receive pending data,
Wherein, described the 8th step comprises: according to described configuration numeric field data adjust described the 3rd output, described the 4th the input, described the 5th the input, described a plurality of second the input and a plurality of second output between connected mode.
16. method as claimed in claim 15,
Wherein, carry out described the 8th step by a plurality of gating circuits, wherein, each gating circuit comprises output terminal and a plurality of input end, wherein, described a plurality of input ends are connected respectively to described the 4th input, described the 5th input and described a plurality of the second input, described output terminal is connected in exporting one of described the 3rd output and described a plurality of second, wherein, each gating circuit is selected and export selected results from described the 4th input, described the 5th input and described a plurality of the second input according to described configuration numeric field data.
17. method as claimed in claim 16,
Wherein, each gating circuit also comprises control end, and each gating circuit selects and export selected results from described the 4th input, described the 5th input and described a plurality of the second input according to the signal on the control end, and
Wherein, the signal on the control end of each gating circuit is set up according to described configuration numeric field data.
18. such as any one the described method among the claim 13-15,
Carry out described the 8th step by controllable switching array.
19. method as claimed in claim 18,
Wherein, described controllable switching array comprises transistor or CMOS pipe.
20. method as claimed in claim 18,
Wherein, the on-off element in the described controllable switching array has control end, is used for the turn-on and turn-off of gauge tap element,
Wherein, the control signal on the control end is set up according to described configuration numeric field data.
21. such as any one the described method among the claim 13-15,
Wherein, described a plurality of IP kernel module comprises general processor IP kernel module.
22. such as any one the described method among the claim 13-15,
Wherein, described a plurality of IP kernel module comprises Instruction decoding IP kernel module and arithmetic and logic unit IP kernel module.
23. such as any one the described method among the claim 13-15,
Wherein, described a plurality of IP kernel module is arranged in identical chip.
24. such as any one the described method among the claim 13-15,
Wherein, described a plurality of IP kernel module is arranged in different chips.
25. one kind comprises the computing equipment such as any one the described general processor among the claim 1-12.
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| CN101281513A (en) * | 2008-05-15 | 2008-10-08 | 中国人民解放军国防科学技术大学 | Stream processor IP core based on Avalon |
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| CN101131715A (en) * | 2007-10-15 | 2008-02-27 | 北京航空航天大学 | Micro-processor IP nuclear design method for navigation system |
| CN101281513A (en) * | 2008-05-15 | 2008-10-08 | 中国人民解放军国防科学技术大学 | Stream processor IP core based on Avalon |
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