CN101131715A - Micro-processor IP nuclear design method for navigation system - Google Patents
Micro-processor IP nuclear design method for navigation system Download PDFInfo
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Abstract
The invention provides a kind of design method of micro-processor IP core which is used for navigator system specially. With the design method in this invention we can not only design FPGA systematic device used for navigator system, but also can design the processor IP core in the navigator chip. The invention is characterized in short design cycle, low investment and good design effect. The device designed and IP consume little power, take small area, have few peripheral devices and occupy low memory resource. At first, cutting up a smallest hardware system composed of processor inner core, hardware floating-point arithmetic unit and communication port on the base of the initial micro-processor; secondly, compiling Linux inner core and the application program, fixing the application program on the Linux inner core, downloading it into the hardware system, at last, allocating and wiring integrated with professional integrated-circuit design tool, and finishing designing the IP core.
Description
Technical field
The invention belongs to field of navigation systems, relate to a kind of IP kernel method for designing, be specifically related to a kind of method for designing of micro-processor IP nuclear of navigational system.
Background technology
In survey of deep space and field of navigation systems,, use SOC design incidence of criminal offenses in survey of deep space and the navigational system more and more for characteristics such as portable, the low power consumption of better realization system and high integrations.
SOC (System-on-chip---system level chip) can be integrated into total system on the chip, SOC has not only comprised hardware systems such as processor cores, storer, also contain corresponding embedded software simultaneously, constituted real soft, a integral framework that hardware all possesses.Wherein key is the core processor technology, has determined the overall performance and the range of application of total system.
But for survey of deep space and navigational system, the general micro controller kernel can't satisfy its performance requirement.Survey of deep space and navigational system require its SOC system to have higher security, use each base part of research and development voluntarily as far as possible, guarantee system data safety; Arithmetic speed is finished the processing and the transmission of data in the specific time faster; Stronger fault-tolerant ability can operate as normal under abominable external condition.Therefore require the core processor of SOC to have more little processing in features such as high-performance, high reliability, extensibilities.The microprocessor IP kernel that on survey of deep space and navigational system, uses at present, all exist some defective: 1) buy with the form of IP kernel, need a large amount of funds, and the IP kernel area occupied of buying is bigger, can increases greatly and make integrated circuit and cost chip production.2) in deep space instrumentation system (DSIS), existing IP kernel power consumption is bigger on the market, is not suitable for the requirement of the energy savings as much as possible in this field.
Summary of the invention
The object of the present invention is to provide a kind of micro-processor IP nuclear design method of navigational system, this method comes microprocessor architecture is optimized by adopting the minimum system that only comprises microprocessor and AMBA (Advanced Microcontroller BusArchitecture) bus, utilize unique software solidification mode that software is cured, and the mode of using ASIC (Application Specific IntergratedCircuits) special IC to design, it is smaller to have obtained an area occupied and power consumption, satisfies the microprocessor IP kernel of operational performance simultaneously again.The design's method has proposed minimum microprocessor system designs mode and software solidification mode, solved in survey of deep space and the navigation chip design about the area occupied and the power problems of little Treatment Design, can effectively reduce the manufacturing of integrated circuit and the cost of chip production.
A kind of micro-processor IP nuclear design method of navigational system is characterized in that this method comprises the steps:
Step 1: on the basis of former microprocessor, reduce out the minimum system that constitutes by microprocessor and AMBA bus, use VHDL language to finish system design;
Step 2: will reduce good system and realize hardware debug at FPGA;
Step 3: will reduce good system and after hardware debug finishes, select for use linux operating system to carry out software debugging;
Step 4: in cross compilation environment,, and generate application program, be placed on application program under the linux catalogue and be mounted on the former catalogue of linux, realize powering on self-starting with the source program cross compile, the debugging that design;
Step 5: the software document under the linux is cured on the chip, carries out the design of integrated circuit by the ASIC design cycle.
Minimum system in the described step 1 comprises microprocessor, AMBA bus, AHB controller, AHB/APB bridge, Memory Management Unit and PROM (but range ROM (read-only memory)); Peripherals is all by AMAB bus and system communication; The AHB controller is controlled ahb bus; Microprocessor carries out distribution and the scheduling of PROM by AHB (Advanced High performance Bus) bus with Memory Controller; The AHB/APB bridge is the APB bus signals with the ahb bus conversion of signals; The APB interface uses for the low speed peripheral hardware.
In the described step 1, the structure of microprocessor comprises the real arithmetic unit, the internal storage control module, register, track buffer, interruptive port, command memory and data-carrier store, and independent the interpolation by taking advantage of/floating point processing unit that divider constitutes, be used for the processing of floating data.The real arithmetic unit adopts pipeline organization or superpipelined architecture to realize the fast processing of data, and instruction and data is cushioned by instruction cache and data caching, make real arithmetic unit and storage inside control module carry out the interaction process of data, result is by ahb bus and peripheral communication.Interruptive port is an output DMA signal, and the control interruptable controller is used for handling interrupt information.Track buffer is used to hold instruction and instruct the result who carries out.
In the described step 4, at first the application program with cross compile copies under the catalogue of linux kernel, adds application program to the self-starting catalogue in self-starting file/etc/rc.d/init.d.Then on virtual machine, compile the image file image.dsu that the linux kernel obtains comprising application program.Under the environment of cygwin, select compiler GCC compiling Image.dsu file then.At last the file that obtains is downloaded in the ROM FPGA Debugging, the correctness of authentication function.
A kind of minimum system chip structure, comprise AMBA bus, AHB controller, AHB/APB bridge, Memory Management Unit and PROM, peripherals is all by AMAB bus and system communication, the AHB controller is controlled ahb bus, the AHB/APB bridge is the APB bus signals with the ahb bus conversion of signals, and the APB interface uses for the low speed peripheral hardware; Also comprise microprocessor, microprocessor carries out distribution and the scheduling of PROM by ahb bus with Memory Controller.
Microprocessor comprises the real arithmetic unit, the internal storage control module, and register, track buffer, interruptive port, command memory and data-carrier store, and independent the interpolation by taking advantage of/floating point processing unit that divider constitutes are used for the processing of floating data.
The real arithmetic unit adopts pipeline organization or superpipelined architecture to realize the fast processing of data, and instruction and data is cushioned by instruction cache and data caching, make real arithmetic unit and storage inside control module carry out the interaction process of data, result is by ahb bus and peripheral communication.Interruptive port is an output DMA signal, and the control interruptable controller is used for handling interrupt information.Track buffer is used to hold instruction and instruct the result who carries out.
The compiling curing of source program under a kind of linux is characterized in that this method comprises following steps:
A, cross compile source program;
B, modification control self-starting file/etc/rc.d/init.d, the application program that the interpolation cross compile obtains is to the self-starting catalogue;
C, compiling linux kernel obtain file image.dsu;
D, will compile the image.dsu that the linux kernel obtains and be transplanted under the simulated environment, select compiler GCC compiling, obtain binary file;
E, binary file is downloaded in the flash with software.
The advantage of the micro-processor IP nuclear design method of a kind of navigational system of the present invention is:
(1) owing to optimized the structure of system and the structure of microprocessor, make the micro-processor IP nuclear of designing according to this method, area occupied is little, and the expense of making chip and integrated circuit is low, has better economic to be worth.
(2) in the system architecture after optimizing that proposes in this method, the system architecture after the optimization wants that to simply, RAM uses fewer, makes system's operational system more stable.
(3) this method is on the basis of optimizing original IP disposal system, in microprocessor, be optimized, obtain new microprocessor architecture, and the floating point processing unit that integration independently is made of multiplier and divider in this little Processing Structure, make microprocessor can handle floating-point operation, accelerated arithmetic speed.Can distinguish separate integration by various floating point processing units and microprocessor architecture, the microprocessor architecture that obtains is portable strong.
Description of drawings
Fig. 1 is a kind of design flow diagram of micro-processor IP nuclear design method of navigational system;
Fig. 2 is the composition structural drawing of a kind of minimum system chip structure of step 1 in a kind of micro-processor IP nuclear design method of navigational system;
Fig. 3 is that a kind of microprocessor of micro-processor IP nuclear design method of navigational system is formed structural drawing;
Fig. 4 is the compiling curing design flow diagram of source program under a kind of linux of step 4 in a kind of micro-processor IP nuclear design method of navigational system.
Embodiment
The object of the present invention is to provide a kind of micro-processor IP nuclear design method of navigational system, this method is on the basis of former microprocessor, reduce out the minimum system that constitutes by microprocessor and AMBA bus, and propose a kind of new microprocessor architecture, optimize to improve system performance; Select the cross compilation environment cross compile application program of GCC or RCC for use, application program is placed under the catalogue of linux, and is mounted on the linux, so that can realize the self-starting that powers on.Solved in survey of deep space and the navigation chip design about area occupied and the power problems of little Treatment Design, excellent application value has been arranged.
Present embodiment is used among " two generations of the Big Dipper " navigational system, is used for handling accepting data.According to system requirements and overall performance, as follows to the performance requirement of processor IP nuclear: (1) data-handling capacity: per second carries out the floating-point operation of 50 double bytes.(2) application program of operation linux operating system and algorithm relative complex.(3) use the least possible logical resource and memory resource to reduce area of chip, economize on the use of funds.(4) space environment is abominable, and system should have stronger fault-tolerant ability, and the correctness that guarantees data transmission is with reliable.
According to the design's method, select the Leon3 microprocessor in the design for use.Leon CPU is a 32 of proposing of GaislerResearch company, meet the microprocessor of increasing income of IEEE1754 (SPARCV8) structure, very strong configurability is arranged, allow design to carry out the optimization of each side: to comprise performance of processors, power consumption, the expansion of I/O, area on the sheet and consumption.
As shown in Figure 1, a kind of micro-processor IP nuclear design method of navigational system, this method comprises the steps:
Step 1: on the basis of former microprocessor, according to the minimum system principle, reduce out the minimum system that is made of microprocessor and AMBA bus, other all peripherals are all by AMAB bus and system communication.Use VHDL language to finish system design.
As shown in Figure 2, described minimum system comprises microprocessor, AMBA bus, AHB controller, AHB/APB bridge, APB (Advanced Peripheral Bus) interface, Memory Controller and PROM (but range ROM (read-only memory)); Peripherals is all by AMAB bus and system communication; The AHB controller comprises AHB primary module, AHB moderator, AHB status register and AHBram control module, and ahb bus is controlled; Microprocessor carries out distribution and the scheduling of PROM by AHB (Advanced High performance Bus) bus with Memory Controller; The AHB/APB bridge is the APB bus signals with the ahb bus conversion of signals; The APB interface uses for peripheral hardware.
The AMBA bus has two kinds of ahb bus and APB buses, and the AHB controller in the system is used for the exchanges data of DMA control and front end in system.Port signal comprises enable signal, clock, ahbmi, ahbmo, tbi and tbo etc.The AHB controller is selected fixing preferential arbitration algorithm, and promptly bus request bus index preferential and master equates, as minimum preferential index.If do not have master request bus, be with the bus index and will be performed.At the impulse duration that increases gradually, AHB master keeps the uncertain visit to the last of bus request, otherwise it may discharge bus entitlement.For the pulse of regular length, AHB master will be authorized to bus at impulse duration completely, and can be after visit beginning for the first time.AHB slave uses the method for plug and play to realize.A slave can account for the address space that any scale-of-two is arranged, and size is from 1～4096MB.A specific I/O zone is also decoded, will capture 256B～1MB.The default addresses for use in I/O zone is 0xFFF00000, and no address is conducted interviews will cause an AHB mistake response.And the data of master are placed on first 2KB of section 0xFFFFF000～0xFFFFF800, and the data of slave are placed on second 2KB section simultaneously.The bus index has defined the address of plug and play data, as a specific unit.The address of master is 0xFFFFF000+n * 32, and 0xFFFFF800+n * 32 that for slave then are.Simultaneously, define four kinds of data type: AHB_Mst_In_Type, AHB_Mst_Out_Type, AHB_Slv_In_Type and AHB_Slv_Out_Type, be convenient to the signal transmission between the module and call according to existing AMBA 2.0 bus standards.Memory Management Unit is carried out data write by AMBA bus management SDRAM (synchronous DRAM) and PROM (but range ROM (read-only memory)).Carry out the standard of all SPARC V8 MMU simultaneously, realized 32 the virtual address and the mapping of 36 physical storages.
As shown in Figure 3, the structure of microprocessor comprises the real arithmetic unit, the internal storage control module, register, track buffer, interruptive port, command memory and data-carrier store, and add by taking advantage of/floating point processing unit that divider constitutes, be used for the processing of floating data.The real arithmetic unit adopts pipeline organization or superpipelined architecture to realize the fast processing of data, and instruction and data is cushioned by instruction cache and data caching, make real arithmetic unit and storage inside control module carry out the interaction process of data, result has so just reached a kind of scheme of high speed processing data by ahb bus and peripheral communication.Interruptive port is an output DMA signal, and the control interruptable controller is used for handling interrupt information.Track buffer is used to hold instruction and instruct the result who carries out.Leon3 always has 13 of 15 interruptive ports and can use for the deviser, and application program is carried out data processing by this look-at-me and microprocessor.All temporary transient storage instruction of command memory, data-carrier store and impact damper and data.
In survey of deep space and navigational system, use, then need to use this structure of hardware Float Point Unit (FPU), be used for the processing of floating data.Realizing the operand computing of byte and double byte precision, and carry out all SPARC V8 FPU instructions, reach the double byte computing of per second 500,000 times.The FPU module is passed through clock, the data input, and data output, the instruction scan pattern scans the exchange that signals such as importing and scan output and real number unit carry out data and instruction, and most floating point arithmetic instruction can be finished in 3 clock period.
Step 2: will reduce good system and realize hardware debug at FPGA;
Use the EP2C35 series of Cyclone II under the 50M clock, taking the FPGA resource is 9000 LE.For hardened operating system and application program,, select for use 2 HY57V561620 simultaneously, connect into 32 data width, select for use 1 EPM7256AETC100 simultaneously as EPROM as SDRAM in the design phase of FPGA.
Step 3: will reduce good system and after hardware debug finishes, select for use linux operating system to carry out software debugging;
Take the design philosophy of substep, first design debug application program, compiling contains the operating system nucleus of application program again, after the successful graft procedure system, transplants the operating system that comprises application program again.The software debugging platform is the Redhat9 of virtual machine.
Operating system is linux, and the kernel version is 2.6.11.In the design, the transplanting key of operating system is to use minimum resource to realize the function of operating system.The configuration of linux kernel and VHDL hardware configuration are to mate mutually, and the configuration of linux kernel comprises two parts, the configuration of LEON3 microprocessor self configuration and peripheral device drivers.Microprocessor mainly carries out following configuration: it is 50MHz that system clock is set, and selects the MMU of LEON3, comprises hardware multiplication/divider and Float Point Unit, and it is 32Mbyte that flash memory Flash is set.
Step 4: in cross compilation environment,, and generate application program, be placed on application program under the linux catalogue and be mounted on the former catalogue of linux, realize powering on self-starting with the source program cross compile, the debugging that design;
As shown in Figure 4, concrete steps are as follows:
A, cross compile source program.
Selection is suitable for the instrument chain RCC of LEON3 cross compile, and version is RCC-1.0.12.Use following compile option to finish the compiling of floating-point arithmetic routine.
1.-and msoft-float: software simulation FPU in the system that does not have hardware FPU is used to compile the source program of test macro class.
2.-and mv8: what generate SPARC V8 takes advantage of/removes instruction; Add to change after the compile option that when containing the source program of taking advantage of/removing in compiling, processor directly calls hardware multiplication/division, the travelling speed of faster procedure.
3.-and o3: the optimizer code; This option application programs mainly plays the effect of optimization, makes program use few hardware resource of trying one's best, and finishes the work with the fastest travelling speed.
B, select to be fit to the linux kernel linux-2.6.11 of IP kernel, the application program of cross compile is mounted to/home/user below; Revise control self-starting file/etc/rc.d/init.d simultaneously, add application program to the self-starting catalogue.
C, compiling comprise the linux kernel of the application program that had compiled among the step B, obtain image file image.dsu.
D, image.dsu file are selected compiler GCC compiling under the environment of cygwin 1.0.2-1.Order as follows:
sparc-elf-mkprom-freq?50-baud?38400-rmw-romsize?131072-nosram-sdrambanks?1?image.dsu
sparc-elf-objcopy-O?binary?prom.out?prom.bin
The prom.bin binary file that obtains.
E, the existing method of basis at first use the instrument that the carries SOPC Builder of 5.1 li of quatus II to set up target version, distribute download address, then use Nios II to set up engineering, and compiling downloads to binary file in the flash.Then adopt GRMON software debugging FPGA, the correctness of verification system function.
Step 5: the software document under the linux is cured on the chip, carries out the design of integrated circuit by the ASIC design cycle.
Because integrated circuit (IC) design has the kinds of processes storehouse, and different technology library methods for designing can be slightly different with system performance.The design uses under the technology of UMC 0.13 μ m, at first carries out comprehensively, and it is that area is selected minimum that constraint condition is set, and it is the poorest that environmental baseline is selected, and the sequential default setting gets final product.Then enter back end design.Because design has certain requirement to system frequency, therefore to design clock number, fundamental significance is to adjust the time that clock signal arrives each terminal, and it is reached unanimity as far as possible.Specific practice is to give a plurality of buffer with the load balancing among the buffer of band heavy load, to reduce time-delay greatly.The constraint of clock trees comprises: maximum-delay, minimum delay, maximum rise time and maximum switching time etc.After setting constraint, in fact the building process of clock trees is exactly that to select maximum difference in the minimum delay scope for use at maximum-delay be that some time-delays of maximum rise time are as the time-delays from rootpin to each leafcell.
The last maximum operation frequency as a result that comprehensively obtains can reach 400MHz, in the ASIC design, has obtained one and has taken less area and less power consumption, and can satisfy the IP kernel of survey of deep space and navigational system demand.And can obtain different performances according to different technologies.Under the technology of UMC 0.18 μ m, maximum operation frequency is 250MHz, takies 13000gates; Under the technology of UMC 0.13 μ m, maximum operation frequency can reach 400MHz, takies 13000 gates.
Claims (6)
1. the micro-processor IP nuclear design method of a navigational system is characterized in that, this method comprises the steps:
Step 1: on the basis of former microprocessor, reduce out the minimum system that constitutes by microprocessor and AMBA bus, use VHDL language to finish system design;
Step 2: will reduce good system and realize hardware debug at FPGA;
Step 3: will reduce good system and after hardware debug finishes, select for use linux operating system to carry out software debugging;
Step 4: in cross compilation environment,, and generate application program, be placed on application program under the linux catalogue and be mounted on the former catalogue of linux, realize powering on self-starting with the source program cross compile, the debugging that design;
Step 5: the software document under the linux is cured on the chip, carries out the design of integrated circuit by the ASIC design cycle.
2. the micro-processor IP nuclear design method of a kind of navigational system according to claim 1, it is characterized in that: the minimum system in the described step 1 comprises microprocessor, AMBA bus, AHB controller, AHB/APB bridge, Memory Management Unit and PROM; Peripherals is all by AMAB bus and system communication; The AHB controller is controlled ahb bus; Microprocessor carries out distribution and the scheduling of PROM by ahb bus with Memory Controller; The AHB/APB bridge is the APB bus signals with the ahb bus conversion of signals; The APB interface uses for the low speed peripheral hardware.
3. according to the micro-processor IP nuclear design method of claim 1 and 2 described a kind of navigational system, it is characterized in that: in the described step 1, the structure of microprocessor comprises the real arithmetic unit, the internal storage control module, register, track buffer, interruptive port, command memory and data-carrier store, and independent the interpolation by taking advantage of/floating point processing unit that divider constitutes, be used for the processing of floating data; The real arithmetic unit adopts pipeline organization or superpipelined architecture to realize the fast processing of data, and instruction and data is cushioned by instruction cache and data caching, make real arithmetic unit and storage inside control module carry out the interaction process of data, result is by ahb bus and peripheral communication; Interruptive port is an output DMA signal, and the control interruptable controller is used for handling interrupt information; Track buffer is used to hold instruction and instruct the result who carries out.
4. the micro-processor IP nuclear design method of a kind of navigational system according to claim 1, it is characterized in that: in the described step 4, at first the application program with cross compile copies under the catalogue of linux kernel, adds application program to the self-starting catalogue in self-starting file/etc/rc.d/init.d; Then on virtual machine, compile the image file image.dsu that the linux kernel obtains comprising application program; Under the environment of cygwin, select compiler GCC compiling Image.dsu file then; At last the file that obtains is downloaded in the ROM FPGA Debugging, the correctness of authentication function.
5. minimum system chip structure, comprise AMBA bus, AHB controller, AHB/APB bridge, Memory Management Unit and PROM, peripherals is all by AMAB bus and system communication, the AHB controller is controlled ahb bus, the AHB/APB bridge is the APB bus signals with the ahb bus conversion of signals, and the APB interface uses for the low speed peripheral hardware; It is characterized in that also comprise microprocessor, microprocessor carries out distribution and the scheduling of PROM by ahb bus with Memory Controller;
Microprocessor comprises the real arithmetic unit, the internal storage control module, and register, track buffer, interruptive port, command memory and data-carrier store, and independent the interpolation by taking advantage of/floating point processing unit that divider constitutes are used for the processing of floating data;
The real arithmetic unit adopts pipeline organization or superpipelined architecture to realize the fast processing of data, and instruction and data is cushioned by instruction cache and data caching, make real arithmetic unit and storage inside control module carry out the interaction process of data, result is by ahb bus and peripheral communication; Interruptive port is an output DMA signal, and the control interruptable controller is used for handling interrupt information; Track buffer is used to hold instruction and instruct the result who carries out.
6. the compiling curing of source program under the linux is characterized in that this method comprises following steps:
A, cross compile source program;
B, modification control self-starting file/etc/rc.d/init.d, the application program that the interpolation cross compile obtains is to the self-starting catalogue;
C, compiling linux kernel obtain file image.dsu;
D, will compile the image.dsu that the linux kernel obtains and be transplanted under the simulated environment, select compiler GCC compiling, obtain binary file;
E, binary file is downloaded in the flash with software.
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| CN112347008A (en) * | 2020-11-02 | 2021-02-09 | 珠海零边界集成电路有限公司 | Data access method and data access bridge |
| CN116341481A (en) * | 2023-05-26 | 2023-06-27 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
| CN116341481B (en) * | 2023-05-26 | 2023-08-22 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
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