CN112347008A - Data access method and data access bridge - Google Patents

Data access method and data access bridge Download PDF

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Publication number
CN112347008A
CN112347008A CN202011212967.8A CN202011212967A CN112347008A CN 112347008 A CN112347008 A CN 112347008A CN 202011212967 A CN202011212967 A CN 202011212967A CN 112347008 A CN112347008 A CN 112347008A
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module
access
target
bus
signal
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CN202011212967.8A
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CN112347008B (en
Inventor
谭卢海
陈定昌
温浪明
陈恒
易冬柏
马颖江
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)

Abstract

The application relates to a data access method and a data access bridge, wherein the method comprises the following steps: acquiring an access request of a CPU (Central processing Unit) for accessing a corresponding target IP module through an APB (advanced peripheral bus); determining an access type according to the access request, wherein the access type comprises a write operation and a read operation; and if the access type is write operation, returning a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access other IP modules through the APB bus after acquiring the first release bus signal. Through the method and the device, the IP module can release the APB bus in advance on the basis of not improving the frequency of the IP module during write operation, the utilization rate of the APB bus is improved, the overall power consumption of a system is reduced, and the problem of screen flashing caused by the fact that the IP module occupies the APB bus for a long time during write operation is well solved.

Description

Data access method and data access bridge
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a data access method and a data access bridge.
Background
At present, two methods for solving the synchronization between the APB bus and the low-speed IP are mainly available in the market. Firstly, when a CPU (processor in a computer) needs to write a low-speed IP, the CPU sends a write signal, a write address and write data, then makes a low-speed IP clock (referring to a module internal clock) beat two times to synchronize, and returns a PREADY signal after the actual write operation of the low-speed IP is completed, which indicates that the write operation is completed. Since the IP Clock is typically at least a few hundred thousandths of the frequency of the APB Clock, this allows the APB bus to be occupied only by that IP until the low speed IP returns a PREADY (indicating whether APB bus access to the IP block is complete) signal that the APB bus cannot be used by other IPs. This approach has two disadvantages: firstly, the efficiency of APB use is significantly reduced; secondly, when some writing operations of the low-speed IP affect the display of the display, such as a Watchdog (timer) module and an RTC (perpetual calendar) module, if they use the method, the display will be in a flashing state all the time until the writing operation is completed, which brings a bad experience to the user.
Since some low speed IPs will affect the display, some users directly connect the low speed IP clock to the APB clock, so that the low speed IP is not at low speed and the frequency is increased to the APB frequency, which can really solve the problem of display flashing, but since the low speed IP clock is increased by hundreds of times, this method increases the power consumption while improving the performance, and the power consumption is also a very critical point for the embedded chip.
Disclosure of Invention
In order to solve the problems of low utilization rate of the APB bus, screen flashing and high power consumption, the embodiment of the application provides a data access method and a data access bridge.
In a first aspect, an embodiment of the present application provides a data access method, where the method includes:
acquiring an access request of a CPU (Central processing Unit) for accessing a corresponding target IP module through an APB (advanced peripheral bus);
determining an access type according to the access request, wherein the access type comprises a write operation and a read operation;
and if the access type is write operation, returning a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access other IP modules through the APB bus after acquiring the first release bus signal.
Optionally, the method further comprises:
generating an access prohibition signal before the write operation is not completed;
and returning an access prohibition signal to the CPU to prohibit the CPU from accessing the target IP module again.
Optionally, before the write operation is not completed, generating an access disable signal includes:
receiving a first IP _ PREADY signal returned by a target IP module before the write operation is not finished;
an access inhibit signal is generated based on the first IP _ PREADY signal.
Optionally, the method further comprises:
and if the access type is write operation, writing the write data in the access request into the target IP module.
Optionally, if the access type is a write operation, writing write data in the access request into the target IP module includes:
if the access type is write operation, caching write data in the access request;
synchronizing write data to a clock domain of the target IP module;
and writing the synchronized write data into the target IP module.
Optionally, if the access type is a write operation, after a first release bus signal is returned to the CPU through the APB bus to cause the target IP module to release the APB bus, the method further includes:
generating a write completion signal after the write operation is completed;
a write complete signal is returned to the CPU over the APB bus to allow the CPU to access the target IP block again.
Optionally, generating a write completion signal after the write operation is completed comprises:
receiving a second IP _ PREADY signal returned by the target IP module after the write operation is completed;
a write completion signal is generated from the second IP _ PREADY signal.
Optionally, the method further comprises:
if the access type is read operation, reading target read data from the target IP module according to the access request;
returning the target read data to the APB bus to enable the CPU to read the target read data through the APB bus;
and if the target read data is returned to the APB bus, returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access any IP module through the APB bus after acquiring the second release bus signal.
Optionally, returning the target read data to the APB bus, and enabling the CPU to read the target read data through the APB bus includes:
synchronizing target read data to a clock domain corresponding to an APB bus;
and returning the synchronized target read data to an APB cache region corresponding to the APB bus, so that the CPU reads the target read data through the APB bus.
In a second aspect, an embodiment of the present application provides a data access bridge, where the data access bridge performs data transmission with a CPU through an APB interface and an APB bus in sequence, and the data access bridge further performs data transmission with a corresponding target IP module through an IP interface; the data access bridge includes: the device comprises an access request processing module and a first signal generating module;
the access request processing module acquires an access request of a CPU (Central processing Unit) for accessing a corresponding target IP (Internet protocol) module through an APB (advanced peripheral bus), and determines an access type according to the access request, wherein the access type comprises write operation and read operation;
if the access type is write operation, the access request processing module controls the first signal generation module to generate a first release bus signal;
the first signal generation module returns a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access other IP modules through the APB bus after acquiring the release bus signal.
Optionally, the data access bridge further comprises: a second signal generation module;
and the second signal generation module is used for generating an access prohibition signal before the write operation is not finished, returning the access prohibition signal to the CPU and enabling the CPU to be prohibited from accessing the target IP module again.
Optionally, the data access bridge further comprises: a write control module;
and if the access type is write operation, the write control module writes the write data in the access request into the target IP module.
Optionally, the second signal generating module is further configured to generate a write completion signal after the write operation is completed, and return the write completion signal to the CPU through the APB bus, so as to allow the CPU to access the target IP module again.
Optionally, the write control module comprises: the system comprises a cache module, a first synchronization module and an access request processing module;
if the access type is write operation, the cache module is used for caching write data and write addresses in the access request;
the first synchronization module is used for synchronizing a control signal in the access request received by the access request processing module to a clock domain of the target IP module, so that after the control signal is synchronized to the clock domain of the target IP module, the target IP module reads write data according to the write address to write the write data into the target IP module.
Optionally, the data access bridge further comprises: a second synchronization module;
the second synchronization module is used for receiving a first IP _ PREADY signal returned by the target IP module before the write operation is not finished, and synchronizing the first IP _ PREADY signal to a clock domain corresponding to the data access bridge or the APB bus;
the second signal generating module is specifically configured to generate an access prohibition signal according to the synchronized first IP _ PREADY signal.
Optionally, the second synchronization module is further configured to receive a second IP _ PREADY signal returned by the target IP module after the write operation is completed, and synchronize the second IP _ PREADY signal to a clock domain corresponding to the data access bridge or the APB bus;
the second signal generating module is further specifically configured to generate a write completion signal according to the synchronized second IP _ PREADY signal.
Optionally, the data access bridge further comprises: a read control module;
if the access type is read operation, the read control module is used for reading target read data from the target IP module according to the access request;
the second synchronization module is also used for synchronizing the target read data to a clock domain corresponding to the APB bus and then returning the target read data to the APB bus, so that the CPU reads the target read data through the APB bus;
and if the target read data is returned to the APB bus, the first signal generation module is also used for returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access any IP module through the APB bus after acquiring the second release bus signal.
Optionally, the second synchronization module is further configured to receive an error signal when the target IP module encounters an error during access, synchronize the error signal to a clock domain corresponding to the APB bus, and then return the clock domain to the APB bus, so that the CPU obtains the error signal through the APB bus.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
in the embodiment of the application, an access request of a CPU (Central processing Unit) for accessing a corresponding target IP module is acquired through an APB (advanced peripheral bus); determining an access type according to the access request, wherein the access type comprises a write operation and a read operation; and if the access type is write operation, returning a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access other IP modules through the APB bus after acquiring the first release bus signal. Through the method and the device, the IP module can release the APB bus in advance on the basis of not improving the frequency of the IP module during write operation, the utilization rate of the APB bus is improved, the overall power consumption of a system is reduced, and the problem of screen flashing caused by the fact that the IP module occupies the APB bus for a long time during write operation is well solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a flow diagram illustrating a method for data access according to an embodiment;
FIG. 2 is a block diagram of a data access system, according to an embodiment;
FIG. 3 is a block diagram of a data access system, according to an embodiment;
fig. 4 is a block diagram of a data access system according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
FIG. 1 is a flow diagram illustrating a method for data access according to an embodiment; the execution subject of the data access method is a data access bridge, and the method comprises the following steps:
s100: acquiring an access request of the CPU for accessing a corresponding target IP module through an APB bus S200: determining an access type according to the access request, wherein the access type comprises a write operation and a read operation
In particular, the apb (advanced Peripheral bus) bus is a type of Peripheral bus. The bus protocol is one of AMBA bus structures, and has become almost a standard on-chip bus structure. APBs are mainly used for connection between low-bandwidth peripheral peripherals, such as UARTs, 1284, etc.
The IP module is a sub-module on the chip, and is used for connection or signal transmission with peripheral peripherals with low bandwidth, such as a UART module, an SPI module, an SRAM module, a DRAM module, and the like.
The CPU carries out data transmission with a plurality of data access bridges through an APB bus, each data access bridge corresponds to one IP module, and each data access bridge carries out data transmission with the corresponding IP module. Namely, the CPU carries out data transmission or communication with the IP module through the APB bus and the data access bridge in sequence.
The CPU sends an access request for accessing a certain target IP module, wherein the access request comprises an access address and a control signal, the control signal comprises an access type and an identification of the target IP module, and if the access request is write operation, the access request also comprises write data. And the data access bridge corresponding to the target IP module acquires the access request through the APB bus and extracts the access type information in the access request. The access type includes a write operation and a read operation.
S300: and if the access type is write operation, returning a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access other IP modules through the APB bus after acquiring the first release bus signal.
Specifically, if the access type is write operation, the data access bridge returns a first release bus signal to the CPU through the APB bus, the CPU does not continue to access the target IP module after receiving the first release bus signal, and the first release bus signal temporarily prohibits (disallows) the CPU from continuing to access the target IP module through the APB bus, so that the target IP module does not continue to occupy the APB bus, and the purpose of releasing the APB bus in advance is achieved. After the APB bus is released, the CPU can access other IP modules through the free APB bus and other data access bridges, or can wait. The method achieves the purpose of distributing the APB bus to other IP modules, and improves the utilization rate of the APB bus.
Meanwhile, although the target IP module releases the APB bus, the target IP module continues to complete the write operation. Because the data of the target IP module completing the write operation is cached in the cache region of the corresponding data access bridge, the target IP module completes the write operation independently of the APB bus without continuously occupying the APB bus.
The first release bus signal is equivalent to a false PREADY signal, and is intended to inform the CPU of completion of write operation through the false PREADY signal after the CPU successfully transmits an access request to a data access bridge corresponding to a target IP module through an APB bus during write operation, so that the CPU does not continue to access the target IP module through the APB bus, thereby enabling the target IP module to release the APB bus in advance before the write operation is really completed, and avoiding the target IP module from continuously occupying the APB bus during write operation to cause waste of APB bus resources.
Preferably, the first release bus signal may be automatically generated by the data access bridge according to the access type in the access request and transmitted to the CPU through the APB bus.
Of course, the first release bus signal may also be generated by the target IP module during a write operation and transmitted to the CPU through the data access bridge and the APB bus.
In addition, by the method of releasing the APB bus in advance, the utilization rate of the APB bus is improved, and the display of the display is affected by the write operation of some low-speed IPs, such as a Watchdog (timer) module and an RTC (perpetual calendar) module. By the method for releasing the APB bus in advance, the CPU can access other IP modules through the idle APB bus while the target IP module continues to write, so that data received by the display screen cannot be interrupted, the problem of screen flashing of the display screen is well solved, and the user experience is improved.
In one embodiment, the data access method further comprises the steps of:
s400: generating an access prohibition signal before the write operation is not completed;
s500: and returning an access prohibition signal to the CPU to prohibit the CPU from accessing the target IP module again.
Specifically, although the data access bridge generates a false PREADY signal to release the APB bus for the target IP block, the target IP block continues to perform write operations, and therefore, the CPU needs to be prohibited from continuing to access the target IP block. Specifically, before the write operation of the target IP module is not completed, the data access bridge generates an access prohibition signal and returns the access prohibition signal to the CPU, and the CPU does not continue to access the target IP module according to the access prohibition signal. The access-prohibited signal may be stored by the data access bridge into a register from which it is read by the CPU.
Preferably, step S400 specifically includes:
s410: receiving a first IP _ PREADY signal returned by a target IP module before the write operation is not finished;
s420: an access inhibit signal is generated based on the first IP _ PREADY signal.
The disable access signal may be generated by the data access bridge from a first IP _ PREADY signal returned by the target IP block before the write operation is not complete. The first IP _ PREADY signal is a PREADY signal generated by the target IP block before the write operation is not complete.
In one embodiment, the data access method further includes step S600: and if the access type is write operation, writing the write data in the access request into the target IP module.
Specifically, when the access type is a write operation, the access request further includes write data. Since the IP block is a low speed IP block, the clock of the IP block is typically at least a few hundred thousandths of the frequency of the APB clock, and the APB bus is very high speed for the IP block. Therefore, the clock of the APB bus and the clock of the IP module are not the same clock, and the APB bus cannot directly transmit signals or data to the IP module, otherwise, the signals are unstable, and even the chip may be burned. The data access bridge is a bridge for communicating the APB bus with the low-speed IP module. And the APB bus transmits the write data to a data access bridge corresponding to the target IP module in a clock domain of the APB bus, and the data access bridge caches the write data to a storage area of the data access bridge. After the data access bridge returns a first bus releasing signal to the CPU to enable the target IP module to release the APB bus, the data access bridge continues to write the cached write data into the low-speed target IP module. Thus, even if the CPU no longer continues to access the target IP block, the target IP block can continue to complete the write operation.
In this embodiment, the IP module still maintains the original low-speed clock, and the write operation can still be normally performed, so that not only the APB bus is released in advance to improve the performance, but also the power consumption of the original low-speed clock of the IP module can be maintained. The embedded chip can keep low power consumption while improving performance, and the embedded chip can achieve an optimal result.
In a specific embodiment, step S600 specifically includes:
s610: if the access type is write operation, caching write data in the access request;
s620: synchronizing write data to a clock domain of the target IP module;
s630: and writing the synchronized write data into the target IP module.
Specifically, the data access bridge buffers write data in the access request, and synchronizes the write data in the APB clock domain to the clock domain of the target IP module, so that the write data synchronized with the clock domain of the target IP module can be directly written into the target IP module by the data access bridge.
The data access bridge is used for assisting the target IP module to release the APB bus in advance in the writing operation process and is also used as a bridge of the APB bus and the IP module for signal synchronization.
In one embodiment, after step S300, the data access method further comprises:
s700: generating a write completion signal after the write operation is completed;
s800: a write complete signal is returned to the CPU over the APB bus to allow the CPU to access the target IP block again.
Specifically, the data access bridge generates a write completion signal after the write operation is really completed, and returns the write completion signal to the CPU through the APB bus, and the CPU learns that the target IP module can be accessed again after receiving the write completion signal, that is, the CPU can access the target IP module through the APB bus again. Of course, the CPU may not immediately access the target IP module when receiving the write completion signal, and the CPU does not affect the CPU to continue accessing other IP modules through the APB bus when receiving the write completion signal.
Of course, the write completion signal may also be generated by the target IP module when the write operation is completed, and the data access bridge synchronizes the write completion signal transmitted by the target IP module to the clock domain of the APB bus and transmits the write completion signal to the CPU through the APB bus.
In one embodiment, step S700 includes:
s710: receiving a second IP _ PREADY signal returned by the target IP module after the write operation is completed;
s720: generating a write completion signal according to the second IP _ PREADY signal;
specifically, the second IP _ PREADY signal is the PREADY signal that the target IP block returns to the corresponding data access bridge after the write operation is actually completed.
The first and second IP _ PREADY signals are two signals representing a high level and a low level, respectively.
The ready signal is a communication signal for transmitting data between the CPU and the peripheral or between two external devices. When PREADY is active, it indicates that the peripheral has made a ready job for input/output data, and the CPU can perform a read operation or a write operation. When PREADY is not valid, indicating that the peripheral is not ready, the CPU enters a wait cycle until PREADY is valid.
In one embodiment, the data access method further comprises:
s900: if the access type is read operation, reading target read data from the target IP module according to the access request;
s1000: returning the target read data to the APB bus to enable the CPU to read the target read data through the APB bus;
s1100: and if the target read data is returned to the APB bus, returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access any IP module through the APB bus after acquiring the second release bus signal.
Specifically, if the data access bridge acquires that the current access type is read operation according to the access request, the access request includes an access address and a control signal, and the control signal includes an identifier of the target IP module, the access type, and a read instruction. And the data access bridge reads target read data from the target IP module according to the read instruction and returns the target read data to the APB bus, and the APB bus comprises the APB bus, an APB cache region corresponding to the APB bus and a related structure. Since the APB bus is configured with a corresponding APB buffer, the target read data is buffered in the APB buffer. The CPU only needs to read target read data from the APB buffer area.
If the data access bridge returns all target read data from the target IP module to the APB bus, the target IP module finishes the read operation, and the target IP module can release the APB bus. Specifically, after the target read data are all returned to the APB buffer area corresponding to the APB bus, the data access bridge returns a second release bus signal to the CPU through the APB bus, and after the CPU receives the second release bus signal, the CPU can access any IP module including the target IP module through the APB bus again.
Preferably, the second release bus signal may be generated automatically by the data access bridge when the target read data is all returned to the APB buffer area corresponding to the APB bus and transmitted to the CPU through the APB bus.
Of course, the second release bus signal may also be generated by the target IP module when all the target read data return to the APB buffer area corresponding to the APB bus and transmitted to the CPU through the data access bridge and the APB bus.
In a specific embodiment, step S1000 specifically includes:
s1010: synchronizing target read data to a clock domain corresponding to an APB bus;
s1020: and returning the synchronized target read data to an APB cache region corresponding to the APB bus, so that the CPU reads the target read data through the APB bus.
Specifically, the target read data in the target IP module is located in the clock domain of the target IP module, and the data access bridge needs to synchronize the target read data located in the clock domain of the target IP module to the clock domain corresponding to the APB bus before the synchronized target read data can be transmitted to the APB buffer corresponding to the APB bus for storage.
The data access bridge can be used as a synchronization module between the APB bus and the IP module during read operation and write operation, and plays a role in signal synchronization.
The APB cache regions corresponding to the APB buses are arranged in series in the data transmission channel of the APB buses and used for caching data of the APB buses.
FIG. 2 is a block diagram of a data access system, according to an embodiment; referring to fig. 2, the data access system includes a CPU, an APB bus, an APB buffer and related modules, an APB interface module, a data access bridge 1, a data access bridge 2, and a data access bridge 3.. data access bridge n, an IP interface module 1, an IP interface module 2, and an IP interface module 3.. IP interface module n, and an IP module 1, an IP module 2, and an IP module 3.. IP module n. The CPU is respectively connected with the data access bridge 1, the data access bridge 2 and the data access bridge 3.. the data access bridge n through the APB bus, the APB cache region, the related modules and the APB interface module, and each data access bridge (the data access bridge 1, the data access bridge 2 and the data access bridge 3.. the data access bridge n) is connected with the corresponding IP module (the IP module 1, the IP interface module 2 and the IP interface module 3.. the IP interface module n) through the corresponding IP interface module (the IP module 1, the IP interface module 2 and the IP interface module 3.. the IP interface module n). The data access bridge, the IP interface module and the IP module are in one-to-one correspondence.
The APB interface module is an interface for data transmission or communication between the APB bus and the data access bridge, and the APB bus writes Control signals, addresses and PWDATA into the data access bridge corresponding to the target IP module through the APB interface module, wherein the access Address corresponds to the target IP module. At the same time, the APB bus also reads PRDATA (read data) from the data access bridge via the APB interface module.
The IP interface module is an interface between the data access bridge and the low-speed IP module, the data access bridge writes IP Control signals, IP addresses and IP PWDATA into the low-speed IP module through the IP interface module, and the data access bridge reads IP PRDATA from the low-speed IP module through the IP interface module.
The data access bridge can be used as a data transmission bridge between an APB bus and an IP module, and can be used as an intermediate bridge to be applied to data receiving and transmitting ends or data interaction ends with different clock domains.
For example, the data access bridge of the present application may also be disposed between the AHB bus and the APB bus, and is used as a bridge between the AHB bus and the APB bus, and is configured to synchronize signals or data transmitted from the AHB bus to a clock domain corresponding to the APB bus and transmit the signals or data to the APB bus, or synchronize signals or data transmitted from the APB bus to a clock domain corresponding to the AHB bus and transmit the signals or data to the AHB bus.
Fig. 3 is a block diagram of a data access system according to an embodiment. The data access bridge performs data transmission with the CPU through the APB interface and the APB bus (including the APB bus, the APB cache region and related modules) in sequence, and also performs data transmission with the corresponding target IP module through the IP interface module; the data access bridge includes: the device comprises an access request processing module and a first signal generating module;
referring to fig. 3, the CPU sends an access request for accessing a corresponding target IP module to the data access bridge through the APB bus and the APB interface module in sequence, where the access request includes a control signal, write data, and an access address. An access request processing module (Select Generator) receives the control signal in the access request and determines an access type according to the control signal in the access request, wherein the access type comprises a write operation and a read operation.
Taking a write operation as an example, when the access request processing module determines that the access type is a write operation, the access request processing module provides a release bus signal generation instruction to the first signal generation module, and the first signal generation module generates the first release bus signal PREADY1 according to the release bus signal generation instruction.
The first signal generation module returns a first release bus signal PREADY1 to the CPU through the APB interface module and the APB bus in sequence, so that the CPU does not access the target IP module any more, and further the target IP module releases the APB bus, and at the same time, the CPU is allowed to access other IP modules through the APB bus after acquiring the first release bus signal PREADY 1.
The control signals include a PSEL signal, a PENABLE signal, and a PWRITE signal. The PSEL signal is used for selecting a target IP module; the PENABLE signal indicates read and write availability, i.e., indicates the validity of read or write; the PWRITE signal is used to control whether the operation is a read or a write, where a 1 indicates a write and a 0 indicates a read. The access request processing module is used for generating a new control signal from three signals, namely a PSEL signal, a PENABLE signal and a PWRITE signal. When the data access bridge is in a write operation, the access request processing module gives a bus signal release generation instruction to the first signal generation module, and simultaneously sends the PSEL, PENABLE and PWRITE signals to a first synchronization module (Sync0 for signal synchronization) in the data access bridge for synchronization, namely, synchronizes the PSEL, PENABLE and PWRITE signals to a clock domain of the target IP module to control the delay of write data in the write data delay module and a write address in the address delay module in the data access bridge. The write data delay module is specifically configured to receive and cache write data in the access request, and the address delay module is configured to receive an access address in the access request. The writing data delay module and the address delay module are both caching modules. And after the synchronization is finished, the target IP module reads the write data according to the write address so as to write the write data into the target IP module.
Preferably, the first signal generation block is an OR logic gate (OR block), and the release bus signal generation command is a signal of 1 when it is a write operation, OR the logic gate generates a false PREADY signal (first release bus signal PREADY1) of 1 according to the release bus signal generation command of 1. That is, the dummy PREADY signal equals 1 (the first release bus signal PREADY1 equals 1). The CPU receives a false PREADY signal of 1 to prematurely release the APB bus. Because of the OR logic gate (OR block), the false PREADY signal may still be 1 even though the first IP _ PREADY signal provided by the target IP block is 0 when the write operation is not completed.
When the read operation is performed, the access request processing module does not send a release bus signal generation instruction with 1 to the OR logic gate (OR module), but sends the PSEL signal, the enable signal and the PWRITE signal to the first synchronization module (Sync0) for synchronization and controls the delay of the read address. Since the or logic gate does not receive the release bus signal generation command of 1, it cannot generate the PREADY signal of 1, and thus the APB bus is not immediately released in advance when it is determined as a read operation.
And if the second synchronization module of the data access bridge finishes returning the target read data to the APB bus, the first signal generation module is also used for returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access any IP module through the APB bus after acquiring the second release bus signal.
The second synchronization module of the data access bridge is used for synchronizing target read data to a clock domain corresponding to the APB bus and then returning the target read data to the APB bus, so that the CPU reads the target read data through the APB bus;
and if the target read data is returned to the APB bus, the first signal generation module is also used for returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access any IP module through the APB bus after acquiring the second release bus signal.
Specifically, if the target read data is returned to the APB bus, the second synchronization module receives a read completion signal provided by the target IP module, synchronizes the read completion signal to a clock domain corresponding to the APB bus, and transmits the read completion signal to the first signal generation module, and the first signal generation module generates a second release bus signal according to the synchronized read completion signal.
Specifically, when the target read data is actually read all the way to the APB buffer corresponding to the APB bus in the read operation, the target IP block generates a third IP _ PREADY signal of 1, and synchronizes the third IP _ PREADY signal to the OR logic gate (OR block) through the second synchronization block (Sync1), that is, the third IP _ PREADY signal is 1. The OR logic gate generates a second release bus signal PREADY2 of 1 based on the third IP _ PREADY signal of 1. That is, the second release bus signal PREADY2 is 1. The CPU receives the second release bus signal PREADY2 of 1 to release the APB bus and the CPU can access any IP block.
When the target read data is not read to the APB buffer area corresponding to the APB bus in the read operation, the target IP module generates a fourth IP _ PREADY signal of 0. So that the APB bus cannot be released.
When the PREADY signal is 1, it represents that the APB bus can be released, and when the PREADY signal is 0, it represents that the APB bus cannot be released.
The data access bridge further comprises: a second signal generation module;
and the second signal generation module is used for generating an access prohibition signal before the write operation is not finished, returning the access prohibition signal to the CPU and prohibiting the CPU from accessing the target IP module again.
Specifically, the data access bridge further comprises: a second synchronization module;
the second synchronization module is used for receiving a first IP _ PREADY signal returned by the target IP module before the write operation is not finished, and synchronizing the first IP _ PREADY signal to a clock domain corresponding to the data access bridge or the APB bus;
the second signal generating module is specifically configured to generate an access prohibition signal according to the synchronized first IP _ PREADY signal.
Specifically, during a write operation, although the data access bridge generates the first release bus signal through the first signal generation module to enable the target IP module to release the APB bus in advance, the target IP module continues the write operation and cannot be accessed by the CPU, so that the CPU needs to be prohibited from continuing to access the target IP module before the target IP module does not complete the write operation. Before the write operation is not completed, the target IP module sends a first IP _ PREADY signal of 0 to the second signal generation module through the second synchronization module, the second signal generation module generates an access prohibition signal of 1 according to the first IP _ PREADY signal of 0 and stores the access prohibition signal into the register, the CPU learns that the target IP module cannot be accessed any more through accessing the access prohibition signal of 1 in the register, and then accesses other IP modules through an idle APB bus or waits until a command or a signal capable of accessing the target IP module is received.
The second signal generation module is an inversion module.
In one embodiment, the second signal generating module is further configured to generate a write completion signal after the write operation is completed, and return the write completion signal to the CPU through the APB bus to allow the CPU to access the target IP module again.
Specifically, the second synchronization module is further configured to receive a second IP _ PREADY signal returned by the target IP module after the write operation is completed, and synchronize the second IP _ PREADY signal to a clock domain corresponding to the data access bridge or the APB bus;
the second signal generating module is further specifically configured to generate a write completion signal according to the synchronized second IP _ PREADY signal.
Specifically, when a write operation is performed, the target IP block generates a second IP _ PREADY signal of 1 to the second signal generation block through the second synchronization block (Sync1) whenever the write operation is completed, i.e., the second IP _ PREADY signal is 1. The second signal generation block generates a write done signal (write done signal) of 0, that is, the write done signal is 0, from the second IP _ PREADY signal of 1. The CPU receives a write completion signal of 0 to release the APB bus and the CPU can access any IP block. The second signal generation module is specifically an inversion logic module. when the write done signal is 1, it represents that the target IP module is being accessed, and when the write done signal is 0, it represents that the target IP module is completely accessed. The write done signal with access signal 1 is prohibited.
Whether the write operation or the read operation is performed, before the write operation is not really completed or the target read data is not really read to the APB buffer area corresponding to the APB bus, IP _ PREADY is 0. When IP _ PREADY is 0, PREADY output by OR logic gate (OR block) according to IP _ PREADY being 0 is 0.
However, at the time of the write operation, since the access request processing module sends a release bus signal generation command of 1 to the OR logic gate (OR module), even if IP _ PREADY is 0, when the access request processing module judges that the current access type is the write operation, the OR logic gate (OR module) can still output a false PREADY signal of 1 according to the release bus signal generation command of 1. Thus, a write operation may prematurely release the APB bus.
In the read operation, the target read data is not actually read all the way to the APB buffer area corresponding to the APB bus, OR the OR gate (OR module) only obtains that IP _ PREADY is 0, so according to the IP _ PREADY being 0, the output of the OR gate (OR module) is 0, that is, PREADY is 0, and therefore, the read operation will release the APB bus only before the target read data is actually read all the way to the APB buffer area corresponding to the APB bus.
In one embodiment, the data access bridge further comprises: a read control module;
if the access type is read operation, the read control module is used for reading target read data from the target IP module according to the access request;
the second synchronization module is further configured to synchronize the target read data to a clock domain corresponding to the APB bus and then return the target read data to the APB bus, so that the CPU reads the target read data through the APB bus.
In an embodiment, the second synchronization module is further configured to receive an error signal PSLVERR when the target IP module encounters an error during access, synchronize the error signal PSLVERR to a clock domain corresponding to the APB bus, and return the clock domain to the APB bus, so that the CPU obtains the error signal PSLVERR through the APB bus.
Specifically, the second synchronization module returns the synchronized error signal PSLVERR to the CPU through the APB interface and the APB bus.
When the error signal PSLVERR is equal to 1, it represents that an error occurs in the current access, and when the error signal PSLVERR is equal to 0, it represents that no error occurs in the current access.
The address delay module and the write data delay module in the data access bridge are respectively connected with the access request processing module. The access request processing module is used for controlling the delay of the write data and the write address by controlling the address delay module and the write data delay module during write operation, or controlling the delay of the read address by controlling the address delay module during read operation.
The Address Delay module (Address Delay) is used for controlling Address Delay, and if the access before the current read/write operation is not ended, the Delay-to-IP _ PREADY signal is 1; otherwise, the Address is directly transmitted to the low-speed IP module for normal read/write access.
The Write Data Delay module (Write Data Delay) is used for controlling the Delay of Write Data (Data written into low-speed IP), if access (access) before the current read/Write operation is not finished, the Delay is carried out until an IP _ PREADY (Write completion signal of low-speed IP) signal is 1; otherwise, directly transmitting the Write Data to the low-speed IP module for normal read/Write access.
The first synchronization module is used for synchronizing signals such as PSEL, PENABLE, PWRITE and the like transmitted by an APB bus (APB bus) to a clock domain of the target IP module when the CPU accesses the target IP module so as to be used by the target IP module.
The second synchronization module is used for synchronizing the signals such as PRDATA (read data), IP _ PREADY (PREADY signal provided by the IP module), PSLVERR and the like returned by the target IP module to the corresponding clock domain of the APB bus when the CPU accesses the target IP module, and then transmitting the signals to the APB bus.
Fig. 4 is a block diagram of a data access system based on fig. 3. Referring to fig. 3 and 4, the Control signal is Control Signals, the access request processing module is a Select Generator module, the first synchronization module is a Sync0 module, the second synchronization module is a Sync1 module, the Address Delay module is an Address Delay module, the Write Data Delay module is a Write Data Delay module, the first signal generation module is an OR module (OR logic gate), and the second signal generation module is an INV module (inverting logic gate).
The specific procedure is as follows:
1. first, the CPU sends control signals and access addresses to the data access bridge via the APB bus, and in the case of a write access, PWDATA (write data) needs to be transferred to the data access bridge.
2. Secondly, the data access bridge will determine whether there is an access in progress (current access is not completed) according to the IP _ advance signal sent by the target IP module, and if the last access is not completed, and IP _ advance is set to 0, then this access will be delayed (delay) until the last access is completed.
3. When the last access is finished, the IP _ PREADY is set to 1, and the access can be performed only this time. If the access is write access, the access request processing module controls the first signal generation module to generate a false PREADY signal to be sent to the APB bus, so that the target IP module releases the APB bus in advance, then the target IP module slowly writes until the write is finished finally, and the data access bridge returns a write completion signal (write done signal) through the second signal generation module.
4. If the access is read access, the APB bus (APB bus) waits until all the final PRDATA data (read data) are returned to the APB bus, and the target IP module can release the APB bus.
5. Finally, when the current access is finished, the target IP module returns a PSLVERR signal to indicate whether the current access is wrong, if the current access is wrong, the PSLVERR signal is set to 1, and if the current access is not wrong, the PSLVERR signal is set to 0.
Through releasing the APB bus in advance, the problem of screen flashing of the CPU when the CPU writes the low-speed IP is solved, but the inside of the low-speed target IP module is written substantially all the time until a write completion signal (write done signal) of 0 is returned, the low-speed target IP module really completes the write operation, and the CPU is allowed to access the target IP module again.
The method reduces power consumption, improves performance, keeps low power consumption, and is an optimal result for the embedded chip. Because the IP clock is also the original low-speed IP clock, but the APB bus is released in advance, the performance is improved, and the power consumption of the original low-speed IP clock can be maintained.
The application improves the utilization rate of the APB bus, and the CPU can allocate the APB bus to other IPs for use due to the fact that the APB bus is released in advance, so that the utilization rate of the APB bus is greatly improved, and even before the write operation is not completed, the APB bus can be idle to be used by the CPU for accessing other IP modules.
This application has released the APB bus in advance through using write done signal hardware mechanism, when solving the display flashing, has also reduced the chip consumption, has improved chip wholeness ability, has improved the utilization ratio of APB bus, has reduced the complexity of design simultaneously, has simplified the work of rear end design territory when the overall arrangement wiring.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (11)

1. A method of data access, the method comprising:
acquiring an access request of a CPU (Central processing Unit) for accessing a corresponding target IP module through an APB (advanced peripheral bus);
determining an access type according to the access request, wherein the access type comprises a write operation and a read operation;
and if the access type is write operation, returning a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and allowing the CPU to access other IP modules through the APB bus after acquiring the first release bus signal.
2. The method of claim 1, further comprising:
generating an access prohibition signal before the write operation is not completed;
and returning the access prohibition signal to the CPU to prohibit the CPU from accessing the target IP module again.
3. The method of claim 1, further comprising:
and if the access type is write operation, writing the write data in the access request into the target IP module.
4. The method of claim 3, wherein if the access type is a write operation, writing write data in the access request into the target IP module comprises:
if the access type is write operation, caching write data in the access request;
synchronizing the write data to a clock domain of the target IP module;
and writing the synchronized write data into the target IP module.
5. The method of claim 1, wherein after returning a first release bus signal to the CPU via the APB bus to cause the target IP module to release the APB bus if the access type is a write operation, the method further comprises:
generating a write completion signal after the write operation is completed;
and returning the write completion signal to the CPU through the APB bus so as to allow the CPU to access the target IP module again.
6. The method of claim 1, further comprising:
if the access type is read operation, reading target read data from the target IP module according to the access request;
returning the target read data to the APB bus to enable the CPU to read the target read data through the APB bus;
and if the target read data is returned to the APB bus, returning a second release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access any IP module through the APB bus after acquiring the second release bus signal.
7. The method of claim 6, wherein returning the target read data to the APB bus, causing the CPU to read the target read data through the APB bus, comprises:
synchronizing the target read data to a clock domain corresponding to the APB bus;
and returning the synchronized target read data to an APB cache region corresponding to the APB bus, so that the CPU reads the target read data through the APB bus.
8. A data access bridge is characterized in that the data access bridge sequentially carries out data transmission with a CPU through an APB interface and an APB bus, and the data access bridge also carries out data transmission with a corresponding target IP module through an IP interface; the data access bridge includes: the device comprises an access request processing module and a first signal generating module;
the access request processing module acquires an access request of the CPU for accessing a corresponding target IP module through the APB bus, and determines an access type according to the access request, wherein the access type comprises write operation and read operation;
if the access type is write operation, the access request processing module controls the first signal generation module to generate a first release bus signal;
the first signal generation module returns a first release bus signal to the CPU through the APB bus, so that the target IP module releases the APB bus, and the CPU is allowed to access other IP modules through the APB bus after acquiring the release bus signal.
9. The data access bridge of claim 7, further comprising: a second signal generation module;
and the second signal generation module is used for generating an access prohibition signal before the write operation is not finished, returning the access prohibition signal to the CPU, and prohibiting the CPU from accessing the target IP module again.
10. The data access bridge of claim 7, further comprising: a write control module;
and if the access type is write operation, the write control module writes write data in the access request into the target IP module.
11. The data access bridge of claim 9, wherein the second signal generating module is further configured to generate a write complete signal after the write operation is completed, and return the write complete signal to the CPU through the APB bus to allow the CPU to access the target IP block again.
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