JPWO2020149886A5 - - Google Patents

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JPWO2020149886A5
JPWO2020149886A5 JP2021541297A JP2021541297A JPWO2020149886A5 JP WO2020149886 A5 JPWO2020149886 A5 JP WO2020149886A5 JP 2021541297 A JP2021541297 A JP 2021541297A JP 2021541297 A JP2021541297 A JP 2021541297A JP WO2020149886 A5 JPWO2020149886 A5 JP WO2020149886A5
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memory cells
synapses
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JP7270746B2 (en
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ニューラルネットワークデバイスであって、
第１の複数の入力を受信するように、かつ該第１の複数の入力から第１の複数の出力を生成するように構成された、第１の複数のシナプスを備え、該第１の複数のシナプスは、
複数のメモリセルであって、該メモリセルのそれぞれは、半導体基板内に形成され、間にチャネル領域が延在する離間したソース領域及びドレイン領域と、前記チャネル領域の第１の部分の上方に配設され、前記チャネル領域の前記第１の部分から絶縁された浮遊ゲートと、前記チャネル領域の第２の部分の上方に配設され、前記チャネル領域の前記第２の部分から絶縁された第１の部分を有する第１のゲートと、を含み、
前記複数のメモリセルのそれぞれは、前記浮遊ゲートの電子の数に対応する重み値を格納するように構成され、
前記複数のメモリセルは、前記第１の複数の入力及び格納された前記重み値に基づいて、前記第１の複数の出力を生成するように構成された、複数のメモリセルを含み、
前記第１の複数のシナプスの前記メモリセルは、行及び列に配置され、前記第１の複数のシナプスは、
前記メモリセルの前記行のうちの１つにおいて前記第１のゲートをそれぞれ電気的に接続する複数の第１の線と、
前記メモリセルの前記行のうちの１つにおいて前記ソース領域をそれぞれ電気的に接続する複数の第２の線と、
前記メモリセルの前記列のうちの１つにおいて前記ドレイン領域をそれぞれ電気的に接続する複数の第３の線と、を含み、
前記第１の複数のシナプスは、前記複数の第３の線の電圧として前記第１の複数の入力を受信するように、かつ前記複数の第２の線の電流として前記第１の複数の出力を提供するように構成された、ニューラルネットワークデバイス。 A neural network device,
a first plurality of synapses configured to receive a first plurality of inputs and to generate a first plurality of outputs from the first plurality of inputs; The synapses of
A plurality of memory cells, each memory cell formed in a semiconductor substrate and having spaced apart source and drain regions with a channel region extending therebetween and over a first portion of the channel region. a floating gate disposed above and insulated from said first portion of said channel region; and a second floating gate disposed above said second portion of said channel region and insulated from said second portion of said channel region. a first gate having a portion of 1;
each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons in the floating gate;
the plurality of memory cells includes a plurality of memory cells configured to generate the first plurality of outputs based on the first plurality of inputs and the stored weight values;
the memory cells of the first plurality of synapses arranged in rows and columns, the first plurality of synapses comprising:
a plurality of first lines respectively electrically connecting the first gates in one of the rows of the memory cells;
a plurality of second lines respectively electrically connecting the source regions in one of the rows of the memory cells;
a plurality of third lines respectively electrically connecting the drain regions in one of the columns of the memory cells;
The first plurality of synapses receives the first plurality of inputs as voltages on the third plurality of lines and the first plurality of outputs as currents on the second plurality of lines. A neural network device configured to provide a 前記複数のメモリセルのそれぞれについて、前記第１のゲートは、前記浮遊ゲートの上方で上に延在する第２の部分を含む、請求項１に記載のニューラルネットワークデバイス。 2. The neural network device of claim 1, wherein for each of said plurality of memory cells said first gate includes a second portion extending above said floating gate. 前記第１の複数の出力を受信するように構成された第１の複数のニューロンを更に含む、請求項１に記載のニューラルネットワークデバイス。 2. The neural network device of Claim 1, further comprising a first plurality of neurons configured to receive said first plurality of outputs. 前記第１の複数のニューロンから第２の複数の入力を受信するように、かつ該第２の複数の入力から第２の複数の出力を生成するように構成された第２の複数のシナプスを更に備え、前記第２の複数のシナプスは、
複数の第２のメモリセルであって、前記第２のメモリセルのそれぞれは、前記半導体基板内に形成され、間に第２のチャネル領域が延在する離間した第２のソース領域及び第２のドレイン領域と、前記第２のチャネル領域の第１の部分の上方に配設され、前記第２のチャネル領域の前記第１の部分から絶縁された第２の浮遊ゲートと、前記第２のチャネル領域の第２の部分の上方に配設され、前記第２のチャネル領域の前記第２の部分から絶縁された第１の部分を有する第２のゲートと、を含み、
前記複数の第２のメモリセルのそれぞれは、前記第２の浮遊ゲートの電子の数に対応する第２の重み値を格納するように構成され、
前記複数の第２のメモリセルは、前記第２の複数の入力及び格納された前記第２の重み値に基づいて、前記第２の複数の出力を生成するように構成された、複数の第２のメモリセルを含み、
前記第２の複数のシナプスの前記第２のメモリセルは、行及び列に配置され、前記第２の複数のシナプスは、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のゲートをそれぞれ電気的に接続する複数の第４の線と、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のソース領域をそれぞれ電気的に接続する複数の第５の線と、
前記第２のメモリセルの前記列のうちの１つにおいて前記第２のドレイン領域をそれぞれ電気的に接続する複数の第６の線と、を含み、
前記第２の複数のシナプスは、前記複数の第６の線の電圧として前記第２の複数の入力を受信するように、かつ前記複数の第５の線の電流として前記第２の複数の出力を提供するように構成された、請求項３に記載のニューラルネットワークデバイス。 a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate a second plurality of outputs from the second plurality of inputs; Further comprising, the second plurality of synapses comprising:
a plurality of second memory cells, each of said second memory cells being formed in said semiconductor substrate and having spaced apart second source and second source regions with a second channel region extending therebetween; a second floating gate disposed over a first portion of the second channel region and insulated from the first portion of the second channel region; a second gate having a first portion disposed over a second portion of the channel region and insulated from the second portion of the second channel region;
each of the plurality of second memory cells is configured to store a second weight value corresponding to the number of electrons on the second floating gate;
The plurality of second memory cells are configured to generate the second plurality of outputs based on the second plurality of inputs and the stored second weight value. 2 memory cells,
the second memory cells of the second plurality of synapses arranged in rows and columns, the second plurality of synapses comprising:
a plurality of fourth lines respectively electrically connecting the second gates in one of the rows of the second memory cells;
a plurality of fifth lines respectively electrically connecting the second source regions in one of the rows of the second memory cells;
a plurality of sixth lines respectively electrically connecting the second drain regions in one of the columns of the second memory cells;
The second plurality of synapses receives the second plurality of inputs as voltages on the sixth plurality of lines and the second plurality of outputs as currents on the fifth plurality of lines. 4. The neural network device of claim 3, configured to provide a 前記複数の第２のメモリセルのそれぞれについて、前記第２のゲートは、前記第２の浮遊ゲートの上方で上に延在する第２の部分を含む、請求項４に記載のニューラルネットワークデバイス。 5. The neural network device of claim 4, wherein for each of said plurality of second memory cells said second gate includes a second portion extending upwardly above said second floating gate. 前記第２の複数の出力を受信するように構成された第２の複数のニューロンを更に含む、請求項４に記載のニューラルネットワークデバイス。 5. The neural network device of Claim 4, further comprising a second plurality of neurons configured to receive said second plurality of outputs. ニューラルネットワークデバイスであって、
第１の複数の入力を受信するように、かつ該第１の複数の入力から第１の複数の出力を生成するように構成された、第１の複数のシナプスを備え、前記第１の複数のシナプスは、
複数のメモリセルであって、前記メモリセルのそれぞれは、半導体基板内に形成され、間にチャネル領域が延在する離間したソース領域及びドレイン領域と、前記チャネル領域の第１の部分の上方に配設され、前記チャネル領域の前記第１の部分から絶縁された浮遊ゲートと、前記チャネル領域の第２の部分の上方に配設され、前記チャネル領域の前記第２の部分から絶縁された第１の部分を有する第１のゲートと、を含み、
前記複数のメモリセルのそれぞれは、前記浮遊ゲートの電子の数に対応する重み値を格納するように構成され、
前記複数のメモリセルは、前記第１の複数の入力及び格納された前記重み値に基づいて、前記第１の複数の出力を生成するように構成された、複数のメモリセルを含み、
前記第１の複数のシナプスの前記メモリセルは、行及び列に配置され、前記第１の複数のシナプスは、
前記メモリセルの前記行のうちの１つにおいて前記第１のゲートをそれぞれ電気的に接続する複数の第１の線と、
前記メモリセルの前記行のうちの１つにおいて前記ソース領域をそれぞれ電気的に接続する複数の第２の線と、
前記メモリセルの前記列のうちの１つにおいて前記ドレイン領域をそれぞれ電気的に接続する複数の第３の線と、を含み、
前記第１の複数のシナプスは、前記複数の第２の線の電圧として前記第１の複数の入力を受信するように、かつ前記複数の第３の線の電流として前記第１の複数の出力を提供するように構成された、ニューラルネットワークデバイス。 A neural network device,
a first plurality of synapses configured to receive a first plurality of inputs and to generate a first plurality of outputs from the first plurality of inputs; The synapses of
a plurality of memory cells, each memory cell formed in a semiconductor substrate over spaced apart source and drain regions with a channel region extending therebetween and a first portion of the channel region; a floating gate disposed above and insulated from said first portion of said channel region; and a second floating gate disposed above said second portion of said channel region and insulated from said second portion of said channel region. a first gate having a portion of 1;
each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons in the floating gate;
the plurality of memory cells includes a plurality of memory cells configured to generate the first plurality of outputs based on the first plurality of inputs and the stored weight values;
the memory cells of the first plurality of synapses arranged in rows and columns, the first plurality of synapses comprising:
a plurality of first lines respectively electrically connecting the first gates in one of the rows of the memory cells;
a plurality of second lines respectively electrically connecting the source regions in one of the rows of the memory cells;
a plurality of third lines respectively electrically connecting the drain regions in one of the columns of the memory cells;
The first plurality of synapses receives the first plurality of inputs as voltages on the second plurality of lines and the first plurality of outputs as currents on the third plurality of lines. A neural network device configured to provide a 前記複数のメモリセルのそれぞれについて、前記第１のゲートは、前記浮遊ゲートの上方で上に延在する第２の部分を含む、請求項７に記載のニューラルネットワークデバイス。 8. The neural network device of claim 7, wherein for each of said plurality of memory cells said first gate includes a second portion extending above said floating gate. 前記第１の複数の出力を受信するように構成された第１の複数のニューロンを更に含む、請求項７に記載のニューラルネットワークデバイス。 8. The neural network device of Claim 7, further comprising a first plurality of neurons configured to receive said first plurality of outputs. 前記第１の複数のニューロンから第２の複数の入力を受信するように、かつ該第２の複数の入力から第２の複数の出力を生成するように構成された第２の複数のシナプスを更に備え、前記第２の複数のシナプスは、
複数の第２のメモリセルであって、前記第２のメモリセルのそれぞれは、前記半導体基板内に形成され、間に第２のチャネル領域が延在する離間した第２のソース領域及び第２のドレイン領域と、前記第２のチャネル領域の第１の部分の上方に配設され、前記第２のチャネル領域の前記第１の部分から絶縁された第２の浮遊ゲートと、前記第２のチャネル領域の第２の部分の上方に配設され、前記第２のチャネル領域の前記第２の部分から絶縁された第１の部分を有する第２のゲートと、を含み、
前記複数の第２のメモリセルのそれぞれは、前記第２の浮遊ゲートの電子の数に対応する第２の重み値を格納するように構成され、
前記複数の第２のメモリセルは、前記第２の複数の入力及び格納された前記第２の重み値に基づいて、前記第２の複数の出力を生成するように構成された、複数の第２のメモリセルを含み、
前記第２の複数のシナプスの前記第２のメモリセルは、行及び列に配置され、前記第２の複数のシナプスは、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のゲートをそれぞれ電気的に接続する複数の第４の線と、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のソース領域をそれぞれ電気的に接続する複数の第５の線と、
前記第２のメモリセルの前記列のうちの１つにおいて前記第２のドレイン領域をそれぞれ電気的に接続する複数の第６の線と、を含み、
前記第２の複数のシナプスは、前記複数の第５の線の電圧として前記第２の複数の入力を受信するように、かつ前記複数の第６の線の電流として前記第２の複数の出力を提供するように構成された、請求項９に記載のニューラルネットワークデバイス。 a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate a second plurality of outputs from the second plurality of inputs; Further comprising, the second plurality of synapses comprising:
a plurality of second memory cells, each of said second memory cells being formed in said semiconductor substrate and having spaced apart second source and second source regions with a second channel region extending therebetween; a second floating gate disposed over a first portion of the second channel region and insulated from the first portion of the second channel region; a second gate having a first portion disposed over a second portion of the channel region and insulated from the second portion of the second channel region;
each of the plurality of second memory cells is configured to store a second weight value corresponding to the number of electrons on the second floating gate;
The plurality of second memory cells are configured to generate the second plurality of outputs based on the second plurality of inputs and the stored second weight value. 2 memory cells,
the second memory cells of the second plurality of synapses arranged in rows and columns, the second plurality of synapses comprising:
a plurality of fourth lines respectively electrically connecting the second gates in one of the rows of the second memory cells;
a plurality of fifth lines respectively electrically connecting the second source regions in one of the rows of the second memory cells;
a plurality of sixth lines respectively electrically connecting the second drain regions in one of the columns of the second memory cells;
said second plurality of synapses to receive said second plurality of inputs as voltages on said plurality of fifth lines and said second plurality of outputs as currents on said plurality of sixth lines; 10. The neural network device of claim 9, configured to provide a 前記複数の第２のメモリセルのそれぞれについて、前記第２のゲートは、前記第２の浮遊ゲートの上方で上に延在する第２の部分を含む、請求項１０に記載のニューラルネットワークデバイス。 11. The neural network device of claim 10, wherein for each of said plurality of second memory cells said second gate includes a second portion extending upwardly above said second floating gate. 前記第２の複数の出力を受信するように構成された第２の複数のニューロンを更に含む、請求項１０に記載のニューラルネットワークデバイス。 11. The neural network device of Claim 10, further comprising a second plurality of neurons configured to receive said second plurality of outputs. ニューラルネットワークデバイスであって、
第１の複数の入力を受信するように、かつ該第１の複数の入力から第１の複数の出力を生成するように構成された、第１の複数のシナプスを備え、前記第１の複数のシナプスは、
複数のメモリセルであって、前記メモリセルのそれぞれは、半導体基板内に形成され、間にチャネル領域が延在する離間したソース領域及びドレイン領域と、前記チャネル領域の第１の部分の上方に配設され、前記チャネル領域の前記第１の部分から絶縁された浮遊ゲートと、前記チャネル領域の第２の部分の上方に配設され、前記チャネル領域の前記第２の部分から絶縁された第１の部分を有する第１のゲートと、を含み、
前記複数のメモリセルのそれぞれは、前記浮遊ゲートの電子の数に対応する重み値を格納するように構成され、
前記複数のメモリセルは、前記第１の複数の入力及び格納された前記重み値に基づいて、前記第１の複数の出力を生成するように構成された、複数のメモリセルを含み、
前記第１の複数のシナプスの前記メモリセルは、行及び列に配置され、前記第１の複数のシナプスは、
前記メモリセルの前記行のうちの１つにおいて前記第１のゲートをそれぞれ電気的に接続する複数の第１の線と、
前記メモリセルの前記行のうちの１つにおいて前記ソース領域をそれぞれ電気的に接続する複数の第２の線と、
前記メモリセルの前記列のうちの１つにおいて前記ドレイン領域をそれぞれ電気的に接続する複数の第３の線と、
前記第３の線のうちの１つと直列にそれぞれ電気的に接続された複数のトランジスタと、を含み、
前記第１の複数のシナプスは、前記複数のトランジスタのゲートの電圧として前記第１の複数の入力を受信するように、かつ前記複数の第２の線の電流として前記第１の複数の出力を提供するように構成された、ニューラルネットワークデバイス。 A neural network device,
a first plurality of synapses configured to receive a first plurality of inputs and to generate a first plurality of outputs from the first plurality of inputs; The synapses of
a plurality of memory cells, each memory cell formed in a semiconductor substrate over spaced apart source and drain regions with a channel region extending therebetween and a first portion of the channel region; a floating gate disposed above and insulated from said first portion of said channel region; and a second floating gate disposed above said second portion of said channel region and insulated from said second portion of said channel region. a first gate having a portion of 1;
each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons in the floating gate;
the plurality of memory cells includes a plurality of memory cells configured to generate the first plurality of outputs based on the first plurality of inputs and the stored weight values;
the memory cells of the first plurality of synapses arranged in rows and columns, the first plurality of synapses comprising:
a plurality of first lines respectively electrically connecting the first gates in one of the rows of the memory cells;
a plurality of second lines respectively electrically connecting the source regions in one of the rows of the memory cells;
a plurality of third lines respectively electrically connecting the drain regions in one of the columns of the memory cells;
a plurality of transistors each electrically connected in series with one of the third lines;
The first plurality of synapses receives the first plurality of inputs as voltages on gates of the plurality of transistors and outputs the first plurality of outputs as currents on the plurality of second lines. A neural network device configured to provide 前記複数のメモリセルのそれぞれについて、前記第１のゲートは、前記浮遊ゲートの上方で上に延在する第２の部分を含む、請求項１３に記載のニューラルネットワークデバイス。 14. The neural network device of claim 13, wherein for each of said plurality of memory cells said first gate includes a second portion extending above said floating gate. 前記第１の複数の出力を受信するように構成された第１の複数のニューロンを更に含む、請求項１３に記載のニューラルネットワークデバイス。 14. The neural network device of Claim 13, further comprising a first plurality of neurons configured to receive said first plurality of outputs. 前記第１の複数のニューロンから第２の複数の入力を受信するように、かつ該第２の複数の入力から第２の複数の出力を生成するように構成された第２の複数のシナプスを更に備え、前記第２の複数のシナプスは、
複数の第２のメモリセルであって、前記第２のメモリセルのそれぞれは、前記半導体基板内に形成され、間に第２のチャネル領域が延在する離間した第２のソース領域及び第２のドレイン領域と、前記第２のチャネル領域の第１の部分の上方に配設され、前記第２のチャネル領域の前記第１の部分から絶縁された第２の浮遊ゲートと、前記第２のチャネル領域の第２の部分の上方に配設され、前記第２のチャネル領域の前記第２の部分から絶縁された第１の部分を有する第２のゲートと、を含み、
前記複数の第２のメモリセルのそれぞれは、前記第２の浮遊ゲートの電子の数に対応する第２の重み値を格納するように構成され、
前記複数の第２のメモリセルは、前記第２の複数の入力及び格納された前記第２の重み値に基づいて、前記第２の複数の出力を生成するように構成された、複数の第２のメモリセルを含み、
前記第２の複数のシナプスの前記第２のメモリセルは、行及び列に配置され、前記第２の複数のシナプスは、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のゲートをそれぞれ電気的に接続する複数の第４の線と、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のソース領域をそれぞれ電気的に接続する複数の第５の線と、
前記第２のメモリセルの前記列のうちの１つにおいて前記第２のドレイン領域をそれぞれ電気的に接続する複数の第６の線と、
前記第６の線のうちの１つと直列にそれぞれ電気的に接続された第２の複数のトランジスタと、を含み、
前記第２の複数のシナプスは、前記第２の複数のトランジスタのゲートの電圧として前記第２の複数の入力を受信するように、かつ前記複数の第５の線の電流として前記第２の複数の出力を提供するように構成された、請求項１５に記載のニューラルネットワークデバイス。 a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate a second plurality of outputs from the second plurality of inputs; Further comprising, the second plurality of synapses comprising:
a plurality of second memory cells, each of said second memory cells being formed in said semiconductor substrate and having spaced apart second source and second source regions with a second channel region extending therebetween; a second floating gate disposed over a first portion of the second channel region and insulated from the first portion of the second channel region; a second gate having a first portion disposed over a second portion of the channel region and insulated from the second portion of the second channel region;
each of the plurality of second memory cells is configured to store a second weight value corresponding to the number of electrons on the second floating gate;
The plurality of second memory cells are configured to generate the second plurality of outputs based on the second plurality of inputs and the stored second weight value. 2 memory cells,
the second memory cells of the second plurality of synapses arranged in rows and columns, the second plurality of synapses comprising:
a plurality of fourth lines respectively electrically connecting the second gates in one of the rows of the second memory cells;
a plurality of fifth lines respectively electrically connecting the second source regions in one of the rows of the second memory cells;
a plurality of sixth lines respectively electrically connecting the second drain regions in one of the columns of the second memory cells;
a second plurality of transistors each electrically connected in series with one of the sixth lines;
The second plurality of synapses receives the second plurality of inputs as voltages on the gates of the second plurality of transistors and the second plurality of synapses as currents in the fifth line of the plurality of transistors. 16. The neural network device of claim 15, configured to provide an output of . 前記複数の第２のメモリセルのそれぞれについて、前記第２のゲートは、前記第２の浮遊ゲートの上方で上に延在する第２の部分を含む、請求項１６に記載のニューラルネットワークデバイス。 17. The neural network device of claim 16, wherein for each of said plurality of second memory cells said second gate includes a second portion extending upwardly above said second floating gate. 前記第２の複数の出力を受信するように構成された第２の複数のニューロンを更に含む、請求項１６に記載のニューラルネットワークデバイス。 17. The neural network device of Claim 16, further comprising a second plurality of neurons configured to receive said second plurality of outputs. ニューラルネットワークデバイスであって、
第１の複数の入力を受信するように、かつ該第１の複数の入力から第１の複数の出力を生成するように構成された、第１の複数のシナプスを備え、前記第１の複数のシナプスは、
複数のメモリセルであって、前記メモリセルのそれぞれは、半導体基板内に形成され、間にチャネル領域が延在する離間したソース領域及びドレイン領域と、前記チャネル領域の第１の部分の上方に配設され、前記チャネル領域の前記第１の部分から絶縁された浮遊ゲートと、前記チャネル領域の第２の部分の上方に配設され、前記チャネル領域の前記第２の部分から絶縁された第１の部分を有する第１のゲートと、を含み、
前記複数のメモリセルのそれぞれは、前記浮遊ゲートの電子の数に対応する重み値を格納するように構成され、
前記複数のメモリセルは、前記第１の複数の入力及び格納された前記重み値に基づいて、前記第１の複数の出力を生成するように構成された、複数のメモリセルを含み、
前記第１の複数のシナプスの前記メモリセルは、行及び列に配置され、前記第１の複数のシナプスは、
前記メモリセルの前記列のうちの１つにおいて前記第１のゲートをそれぞれ電気的に接続する複数の第１の線と、
前記メモリセルの前記行のうちの１つにおいて前記ソース領域をそれぞれ電気的に接続する複数の第２の線と、
前記メモリセルの前記列のうちの１つにおいて前記ドレイン領域をそれぞれ電気的に接続する複数の第３の線と、を含み、
前記第１の複数のシナプスは、前記複数の第１の線の電圧として前記第１の複数の入力を受信するように、かつ前記複数の第２の線の電流として前記第１の複数の出力を提供するように構成された、ニューラルネットワークデバイス。 A neural network device,
a first plurality of synapses configured to receive a first plurality of inputs and to generate a first plurality of outputs from the first plurality of inputs; The synapses of
a plurality of memory cells, each memory cell formed in a semiconductor substrate over spaced apart source and drain regions with a channel region extending therebetween and a first portion of the channel region; a floating gate disposed above and insulated from said first portion of said channel region; and a second floating gate disposed above said second portion of said channel region and insulated from said second portion of said channel region. a first gate having a portion of 1;
each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons in the floating gate;
the plurality of memory cells includes a plurality of memory cells configured to generate the first plurality of outputs based on the first plurality of inputs and the stored weight values;
the memory cells of the first plurality of synapses arranged in rows and columns, the first plurality of synapses comprising:
a plurality of first lines respectively electrically connecting the first gates in one of the columns of the memory cells;
a plurality of second lines respectively electrically connecting the source regions in one of the rows of the memory cells;
a plurality of third lines respectively electrically connecting the drain regions in one of the columns of the memory cells;
The first plurality of synapses receives the first plurality of inputs as voltages on the plurality of first lines and the first plurality of outputs as currents on the plurality of second lines. A neural network device configured to provide a 前記複数のメモリセルのそれぞれについて、前記第１のゲートは、前記浮遊ゲートの上方で上に延在する第２の部分を含む、請求項１９に記載のニューラルネットワークデバイス。 20. The neural network device of claim 19, wherein for each of said plurality of memory cells said first gate includes a second portion extending upwardly above said floating gate. 前記第１の複数の出力を受信するように構成された第１の複数のニューロンを更に含む、請求項１９に記載のニューラルネットワークデバイス。 20. The neural network device of Claim 19, further comprising a first plurality of neurons configured to receive said first plurality of outputs. 前記第１の複数のニューロンから第２の複数の入力を受信するように、かつ該第２の複数の入力から第２の複数の出力を生成するように構成された第２の複数のシナプスを更に備え、前記第２の複数のシナプスは、
複数の第２のメモリセルであって、前記第２のメモリセルのそれぞれは、前記半導体基板内に形成され、間に第２のチャネル領域が延在する離間した第２のソース領域及び第２のドレイン領域と、前記第２のチャネル領域の第１の部分の上方に配設され、前記第２のチャネル領域の前記第１の部分から絶縁された第２の浮遊ゲートと、前記第２のチャネル領域の第２の部分の上方に配設され、前記第２のチャネル領域の前記第２の部分から絶縁された第１の部分を有する第２のゲートと、を含み、
前記複数の第２のメモリセルのそれぞれは、前記第２の浮遊ゲートの電子の数に対応する第２の重み値を格納するように構成され、
前記複数の第２のメモリセルは、前記第２の複数の入力及び格納された前記第２の重み値に基づいて、前記第２の複数の出力を生成するように構成された、複数の第２のメモリセルを含み、
前記第２の複数のシナプスの前記第２のメモリセルは、行及び列に配置され、前記第２の複数のシナプスは、
前記第２のメモリセルの前記列のうちの１つにおいて前記第２のゲートをそれぞれ電気的に接続する複数の第４の線と、
前記第２のメモリセルの前記行のうちの１つにおいて前記第２のソース領域をそれぞれ電気的に接続する複数の第５の線と、
前記第２のメモリセルの前記列のうちの１つにおいて前記第２のドレイン領域をそれぞれ電気的に接続する複数の第６の線と、を含み、
前記第２の複数のシナプスは、前記複数の第４の線の電圧として前記第２の複数の入力を受信するように、かつ前記複数の第５の線の電流として前記第２の複数の出力を提供するように構成された、請求項２１に記載のニューラルネットワークデバイス。 a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate a second plurality of outputs from the second plurality of inputs; Further comprising, the second plurality of synapses comprising:
a plurality of second memory cells, each of said second memory cells being formed in said semiconductor substrate and having spaced apart second source and second source regions with a second channel region extending therebetween; a second floating gate disposed over a first portion of the second channel region and insulated from the first portion of the second channel region; a second gate having a first portion disposed over a second portion of the channel region and insulated from the second portion of the second channel region;
each of the plurality of second memory cells is configured to store a second weight value corresponding to the number of electrons on the second floating gate;
The plurality of second memory cells are configured to generate the second plurality of outputs based on the second plurality of inputs and the stored second weight value. 2 memory cells,
the second memory cells of the second plurality of synapses arranged in rows and columns, the second plurality of synapses comprising:
a plurality of fourth lines respectively electrically connecting the second gates in one of the columns of the second memory cells;
a plurality of fifth lines respectively electrically connecting the second source regions in one of the rows of the second memory cells;
a plurality of sixth lines respectively electrically connecting the second drain regions in one of the columns of the second memory cells;
The second plurality of synapses receives the second plurality of inputs as voltages on the fourth plurality of lines and the second plurality of outputs as currents on the fifth plurality of lines. 22. The neural network device of claim 21, configured to provide a . 前記複数の第２のメモリセルのそれぞれについて、前記第２のゲートは、前記第２の浮遊ゲートの上方で上に延在する第２の部分を含む、請求項２２に記載のニューラルネットワークデバイス。 23. The neural network device of claim 22, wherein for each of said plurality of second memory cells said second gate includes a second portion extending upwardly above said second floating gate. 前記第２の複数の出力を受信するように構成された第２の複数のニューロンを更に含む、請求項２２に記載のニューラルネットワークデバイス。

23. The neural network device of Claim 22, further comprising a second plurality of neurons configured to receive said second plurality of outputs.
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