CN104615909B - Izhikevich neuroid synchronous discharge emulation platforms based on FPGA - Google Patents
Izhikevich neuroid synchronous discharge emulation platforms based on FPGA Download PDFInfo
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Abstract
The present invention provides a kind of Izhikevich neuroid synchronous discharge emulation platforms based on FPGA, the emulation platform includes the FPGA neuroids computation processor and host computer of interconnection, wherein FPGA neuroids computation processor includes fpga chip, chip external memory array, ethernet communication module, fpga chip receives the PC control signal of chip external memory array output, and receives the presynaptic membrane electric potential signal exported by chip external memory array；Host computer is communicated by VB programming realizations man machine operation interface and by ethernet communication module and fpga chip and chip external memory array, and neural network model is built by Verilog HDL Programming with Pascal Language on fpga chip.Beneficial effect is the FPGA neuron network experimental platforms without zoopery, based on high-speed computation as biological neural network, the hardware modeling to phenotype and bion neuron models is realized, and can reach consistent with true biological neuron in time scale.
Description
Technical field
The present invention relates to biomedical engineering technology, particularly a kind of Izhikevich neuroids based on FPGA are same
Step electric discharge emulation platform.
Background technology
Brain there are about 100,000,000,000 neurons, and each neuron is carried out by cynapse and other about 100,000,000,000 neurons
Information transmission, the special neural circuit of various functions is formed between neuron, pass through various neurotransmitters and its acceptor transmission is believed
Breath, produce the Premium Features of brain.Processing of the brain to nerve information is completed by the neuron collaboration of Different brain region, and same
The classic manifestations as neuron colony discharge activities are walked, are the important mechanisms of Neural information processing.Between neuron
Synchronous movement plays the effect of key in Different brain region nerve information transmission and processing procedure, and it can integrate and coordinate to transport
Various information needed for dynamic control.But up to the present in brain between Different brain region all kinds of neuron synchronous movements shape
It is still unintelligible into mechanism.Therefore, furtheing investigate the synchronous dynamics of neuroid has important physiological significance.
Bioexperiment is had some limitations due to the constraint of its high cost and ethics；Computer is soft
Part simulation work troublesome calculation speed is slow, lacks real-time, and for the analog circuit of a certain specific neuron structure, experiment
Scalability and flexibility have limitation, are not easy to the operation and development of simulation work.Therefore neuroid synchronia
High-performance hardware is realized, is a brand-new research direction.
Field programmable gate array (Field Programmable Gate Array, FPGA) technology is special integrated electricity
A kind of semi-custom circuit engineering in road (ASIC) field, which solve the insufficient and conventional programming device door of custom circuit
The problem of circuit number is limited, gradually favored in the computational neuroscience field using biological nervous system as object.Relative to
The shortcomings of analog circuit platform development cycle is long, FPGA is because of its integrated level height, small volume, parallel computation, repeatable configuration, programming
Flexibly, the emulation of neuron bioelectrical activity and spy under actual time yardstick can be realized the advantages that good reliability, low-power consumption
Property analysis.Using the FPGA for being capable of concurrent operation, can complete under actual time yardstick the emulation of neuroid synchronous movement and
Specificity analysis, operation efficiency is improved, is had in neuron behavior research, synchronia mechanism, bionics, intelligence system etc.
Important application value.
Existing technology still suffers from following shortcoming also in foundation phase：It there is no special neuroid synchronously imitative
True FPGA experiment porch；The simulation hardware neural network model scale is smaller realized with FPGA, scale is immutable, and network connects
It is flexible poor to connect；Man-machine interface is not perfect enough, can not carry out real-time control operation and data analysis, therefore neuroid is moved
The FPGA simulation analysis of step response are relatively difficult.
The content of the invention
For insufficient present in above-mentioned technology, it is an object of the invention to provide a kind of neuroid synchronization simulation FPGA
Experiment porch, researcher is flexibly easily completed the correlation of neuroid synchronia under heterogeneous networks scale and imitate
True operation, electric discharge observation and further theory analysis are carried out by man machine operation interface, showed to study the synchronization of neuroid
As providing Important Theoretic Foundation.
To achieve the above object, the technical solution adopted by the present invention is to provide a kind of Izhikevich nerves based on FPGA
Metanetwork synchronous discharge emulation platform, it is characterized in that：The FPGA neuroids that the emulation platform includes interconnection calculate
Processor and host computer, wherein FPGA neuroids computation processor include fpga chip, chip external memory array, ether
Net communication module, the fpga chip receives the PC control signal of chip external memory array output, and receives by piece external memory
The presynaptic membrane electric potential signal of memory array output；Host computer is by VB programming realizations man machine operation interface and passes through ether Netcom
News module is communicated with fpga chip and chip external memory array, passes through Verilog HDL Programming with Pascal Language on fpga chip
Build neural network model.
Neural network model is coupled with cynapse computing module using neuron computing module and drawn, neuron models calculate
Module, cynapse computing module, network size multiplexer and interface multiplexer are programmed using VHDL language, and are compiled and downloaded to
In fpga chip, host computer is by VB programming realizations man machine operation interface and passes through ethernet communication module and fpga chip and piece
External memory array is communicated.
The signal of the man machine operation interface input is passed in fpga chip by ethernet communication module, is realized to FPGA
The configuration of computing module parameter is calculated by neuron computing module and produced with the control calculated, Izhikevich neuron models
Film potential signal and network dynamics information network is carried out into man machine operation interface by ethernet communication module transfer
Characteristic is shown to be operated with Data Analysis Services, while film potential signal and the storage of network dynamics information are believed to neuroid
In breath storage SDRAM, cynapse computing module is made up of parallel M block synaptic currents modules, and each synaptic currents module receives prominent
Touch cephacoria electric potential signal and carry out ODE calculating, neuron computing module, which receives parameter transfer bus transmission data, is joined
Number configuration.
Man machine operation interface is responsible for configuring PC control signal, and PC control signal includes network size control letter
Number, changing interface signal, the parameter signal of interface 2, the parameter signal of interface 3, network size multiplexer receive network size control letter
Number, and network size configuration is carried out to neural network model, interface multiplexer reception interface switching signal carries out interface selection.
The beneficial effects of the invention are as follows the Izhikevich neuroids modeling that the experiment porch realizes complexity, design
Have visualization and the man-machine interface of operability concurrently, improve flexibility and the operability of system, can be in time scale
Interior pair emulates with biological neuron mathematical modeling；Meanwhile the experiment porch is neuroid under research electric field action
Synchronia provides the visualized experiment platform in actual time yardstick, the important mechanisms research to understanding Neural information processing
There is important practical value.The FPGA neuroid characteristic Simulations calculated based on high-speed parallel are a kind of solution neuroids
Synchronizing characteristics dynamic mechanism worldwide belongs to a forward position without animal experiment method, the application study of its experiment porch
Sciemtifec and technical sphere.This programme innovation proposes neuroid synchronia high velocity experiments platform, and it has, and following some is excellent
Gesture：1st, designed hardware simulation model can be kept and the uniformity of true biological neuron, its SMIS in time scale
Piece maximum operation frequency is 200MHz, and concurrent operation ensures film potential output frequency within 1 millisecond, when meeting actual nerve member
Between scale requirement, provide quicker, portable hardware experiment platform for the research of neuroid synchronia；2nd, this is flat
Neuroid scale, neuron models parameter etc. can complete by upper computer software interface configurations and utilize meter in platform
Calculation machine user interface configures the various characteristics of experimental facilities；3rd, man machine operation interface can be with real-time monitored Neural spike train shape
State and the dynamic characteristic of network activity, and the amplitude and energy for measuring signal can be quantified, while carry out neuroid synchronization
Specificity analysis, data storage function are easy to the analysis work of follow-up data, and the research for neuroid synchronia provides
More preferable visualized experiment research platform.
Brief description of the drawings
Fig. 1 is the experimental platform system structural representation of the present invention；
Fig. 2 is Izhikevich stream of neuron waterline models；
Fig. 3 is synaptic currents computation model；
Fig. 4 is the schematic diagram of human-machine operation operation interface I of the present invention；
Fig. 5 is the schematic diagram of human-machine operation operation interface II of the present invention；
Fig. 6 is the schematic diagram of human-machine operation operation interface III of the present invention.
In figure：
The chip external memory array 5. of 2. host computer 3.FPGA chips of 1.FPGA neuroids computation processor 4. with
Too the film potential of 6. neuron models computing module of net communication module, 7. man machine operation interface, 8. neural network model 9. is believed
The parameter storage of number 10. network dynamics information, 11. 13. interface of neuron computation delay 12. cynapse computing module of link 2
The neuroid film potential storage SDRAM 17.500 of 14. interfaces of RAM 3,15. network weight ROM of parameter storage RAM 16.200
The neuroid film potential storage SDRAM 18.1000 neuroid film potential storage neuroids of SDRAM 19.2000
The parameter transfer bus of 22. variable u streamlines of film potential storage 20. network weight ROM of SDRAM, 21. variable V streamlines 23.
24. the data transmission bus of 26. synaptic currents module of presynaptic membrane electric potential signal 25.Izhikevich neuron models 27.
28. the boundary of 31. interface of PC control signal 29. network size control signal, 30. changing interface signal, 2 parameter signal 32.
The neuroid information of face 3 parameter signal, 33. network size multiplexer, 34. interface multiplexer 35. storage SDRAM 36. joins
The data buffer storage of 39. parameter d numerical signals of number a numerical signal 37. parameter b numerical signals, 38. parameter c numerical signals 40.
The postsynaptic membrane current potential of II 43. man machine operation interface of SDRAM 41. man machine operation interface, I 42. man machine operation interfaces III 44. is believed
The network parameter configuration of number network of 45. mirrored storage dual port RAM, 46. synaptic delay module 47. electric discharge grid figure display interface 48.
The general parameter of 49. basic operation frame of option 50. configures 51. degree of distributed constants and sets 52. degree of distribution curve display interfaces
53. the parameter section of synchronization factor assay surface 54. sets frame
Embodiment
Below in conjunction with the accompanying drawings to the Izhikevich neuroid synchronous discharge emulation platforms based on FPGA of the present invention
Structure is illustrated.
The design philosophy of the Izhikevich neuroid synchronous discharge emulation platforms based on FPGA of the present invention is first
The neural network model of parallel computation is first built on fpga chip；Then set on FPGA independently of neural network model
The chip external memory of different memory spaces is counted, storage and calling for the neuroid information intermediate data of different scales；
Ethernet communication module is used for host computer and slave computer data transfer, the biography according to upper computer software interface input instruction to data
It is defeated to select the corresponding control operation of progress；Finally design upper computer software interface, upper computer software interface by arrange parameter simultaneously
Fpga chip is transferred to, the configuration to neuron models key parameter and network reconnection probability parameter is realized, passes through option window
Selection can select network size, while Neural spike train dynamic data in fpga chip can be uploaded to host computer, upper
Position machine software interface carries out the display of electric discharge dynamic waveform.The experiment porch is by the FPGA development boards being connected with each other and upper unit
Into.Wherein FPGA portion is used for realizing different scales neuroid, host computer be used for designing man machine operation interface and by with
Too net communication module is communicated with FPGA.
The neuron models use Euler method discretization in FPGA, and are built using pipelining, make complexity
ODE parallel computation.Streamline thought substantially makes mathematical modeling be divided into several sub- computings using delay register
Journey, within each clock cycle, every sub- calculating process can carry out different neural clusters, computing at different moments, mould simultaneously
Type data cross preserves outside piece in SDRAM registers, and is transmitted with clock.In neuron models, different model parameters
Different types of discharge mode can be produced, model parameter is inputted by man machine operation interface, is stored in peripheral hardware register SDRAM,
Synchronization call during calculating, the parameter adjustment and Neural spike train pattern that can so realize independent neuron change.Calculating process
In to improve network calculations speed, using modular concurrent method, logical resource extends as far as possible under conditions of allowing in piece
Network size.
The synaptic currents computing module 12：The synaptic currents computing module uses parallel modules method, receives nerve
The film potential information that metanetwork model is calculated, calculate generation synaptic currents signal by the coupling of synaptic currents and return to god
Through in metanetwork model, so as to complete being of coupled connections between each neuron in network.
The man machine operation interface 7：Writing for man machine operation interface realizes that development process is convenient straight using VB language developments
See, be visualization, object-oriented, by event driven high-level programming language, it is final present in front of the user be with very
The similar operation interface of real laboratory apparatus, it can realize that real-time data acquisition, waveform are shown and Data Analysis Services.
The Izhikevich neuroid synchronous discharge emulation platforms based on FPGA of the present invention are by being connected with each other
FPGA neuroids computation processor 1 and host computer 2 form.Wherein FPGA neuroids computation processor 1 is used for realizing
Parallel neuron models computing module 6 and cynapse computing module 12, host computer 2 are used for designing man machine operation interface 10 and passing through
Ethernet communication module 5 realizes the communication with FPGA development boards 1, and data communication is realized by data transmission bus 27.Below plus
With explanation：
Neural network model 8
As shown in figure 1, hardware experiment platform is designed, the Cyclone that fpga chip 3 is produced using altera corp
IV EP4CGX110DF31C7 chips, according to the mathematical modeling of neuron, using Euler method discretization and build Izhikevich
Stream of neuron waterline model 25.Synaptic currents computing module 12 includes parallel synaptic currents module 26.Parameter transfer bus 23
The data set by man machine operation interface 7 are received into hardware system, membrane potential of neurons signal 9 and network dynamics letter
The breath critical datas such as 10 are uploaded in host computer 2 by parameter transfer bus 23 carries out the aobvious in real time of neuroid synchronia
Show and analyze, while be stored in neuroid information storage SDRAM35.
Neural network model 8 is made up of neuron models computing module 6 and cynapse computing module 12, neuron models meter
Calculate module and realize that all data paths are synchronously transported under unified clock by parallel Izhikevich streams of neuron waterline model 25
OK, and according to FPGA structure, the conversion of hardware description language is realized by the softwares of QUARTUS II.It is illustrated in figure 2
Izhikevich neuron models 25, it is mainly made up of addition, multiplication and shift register, the Izhikevich neurons
The mathematical modeling of model 25 is：
If v >=30,
Wherein v represents the membrane voltage of neuron, and u, which is represented, recovers variable, reacts K+,Na+Activity, and to membrane voltage with negative
Feedback, a, b, c, d are equation group constant.Model comprising variable v streamlines 21 and two streamlines of variable u, neuron calculate
Time delay process 11 is used for the handling capacity for increasing system.Izhikevich neuron models 25 receive to be set by man machine operation interface 7
Parameter a numerical signals 36, parameter b numerical signals 37, parameter c numerical signals 38, parameter d numerical signals 39, set by parameter
Change Neural spike train pattern and state are put, while receives the presynaptic membrane electric potential signal 24 of the transmission of chip external memory array 4, is entered
Row ODE calculates, and obtains network dynamics information and is output in data buffer storage SDRAM40.
As shown in figure 3, each synaptic currents module 26 includes network weight ROM 15, network weight ROM 20, mirror image is deposited
Dual port RAM 45 is stored up, synaptic delay module 46, wherein multiplexer select data and network weight in mirrored storage dual port RAM 45
Data in weight ROM 15 carry out coupling calculating, and acquired results carry out further coupling meter with the data storages of network weight ROM 20
Calculate, calculate gained postsynaptic membrane electric potential signal 44 and be input in neuron models computing module 6, in the reception of synapse delay module 46
The film potential signal 44 of one step, calculate progress logic with this step and couple, and throughput of system can be increased.Synaptic currents module
Number M is more than the number N of Izhikevich neuron models to ensure parallelization computing.
Chip external memory array 4 includes 200 neuroid film potentials storage SDRAM16,500 neuroid film potentials
SDRAM17,1000 neuroid film potentials storage SDRAM18,2000 neuroid film potentials storage SDRAM19 are stored,
The network dynamics information 10 that reception is calculated output by neural network model 8 is stored, and outputs signals to network size
In multiplexer 33, network size multiplexer 33 receives the network size control signal 29 that host computer 2 inputs and carries out channel selecting, most
Presynaptic membrane electric potential signal 24 is output to progress network coupling in neural network model 8 afterwards.Neuron number is by host computer 2
Chip external memory array 4 is configured in digital form, so as to realize the configuration of network size.
The parameter storage of interface 2 RAM13, the parameter of interface 3 storage RAM14 receive what is transmitted by ethernet communication module 5 respectively
The parameter signal 31 of interface 2, the parameter signal 32 of interface 3 are stored, and numerical value are output in interface multiplexer 34, interface multiplexer
34, which receive the changing interface signal 30 inputted by host computer 2, carries out changing interface, and data are inputted by parameter transfer bus 23
Calculated and configured into neural network model 8.
Man machine operation interface 7
Man machine operation interface 7 includes three tabs：Human-machine operation operation interface I 41, human-machine operation operation interface II 42
With human-machine operation operation interface III 43, man machine operation interface 7 is designed with VB Programming with Pascal Language mode in host computer 2, it is upper
Machine 2 exports PC control signal 28 into FPGA neuroids computation processor 1.Fpga chip 3 passes through ethernet communication
Module 5 realizes that data communicate with man machine operation interface 7, and man machine operation interface 7 is received from FPGA cores by ethernet communication module 5
The data that piece 3, ethernet communication module 5 are transmitted；The arrange parameter of man machine operation interface 7 inputs number by ethernet communication module 5
According into fpga chip 3, parameter configuration and signal behavior are carried out to neural network model 8.
The man machine operation interface I 41 by tab as shown in figure 4, switched, and wherein including degree distribution curve shows boundary
The display degree distribution curve of face 52, degree distributed constant sets 51 setting degree distributed constants, to carry out Network Synchronization specificity analysis.People
The result that machine operation interface includes cluster coefficients, worldlet degree, the average number of degrees and shortest path length is shown, is easy to intuitively observe
Network characteristic.
The man machine operation interface II 42 is as shown in figure 5, it includes network electric discharge grid figure interface 47, network parameter configuration choosing
Item 48：Network electric discharge grid Figure 47 is used for the synchronizing characteristics for showing neuroid；Network parameter config option 48 is used to configure net
Network parameter, including network size and sampling number.
The man machine operation interface III 43 by tab as shown in fig. 6, switched, wherein including synchronization factor assay surface
53, for showing synchronization factor analysis result, parameter section sets frame 54 to be used for configuration parameter section, so as to synchronize the number of coefficient
Credit is analysed.
The man machine operation interface I 41, man machine operation interface II 42, the man machine operation interface III 43 include basic operation
Frame 49, for realizing the basic operation to man machine operation interface 7；Comprising general parameter configuration block 50, so as to carry out FPGA nerves
The parameter configuration of metanetwork computation processor 1.
FPGA emulation platforms
Discrete, fixed step size, fixed-point number computing neural network model based on module is write by VHDL language,
Through the software programming complete operation logical sum program structures of QUARTUS II；Compiling, analysis integrated, placement-and-routing, download to
Run in fpga chip.Neuron number evidence caused by fpga chip computing is uploaded through Ethernet, in the man-machine behaviour that VB language is write
Make interface 7 to analyze and research to neuroid synchronizing characteristics, the tab by switching man machine operation interface 7 is realized different
The dynamic analysis of angle.
Claims (3)
1. a kind of Izhikevich neuroid synchronous discharge emulation platforms based on FPGA, the emulation platform include mutually
The FPGA neuroids computation processor (1) and host computer (2) of connection, the FPGA neuroids computation processor (1)
Include fpga chip (3), chip external memory array (4), ethernet communication module (5), outside fpga chip (3) receiving sheet
The PC control signal of memory array (4) output, and receive the presynaptic membrane current potential exported by chip external memory array (4)
Signal, it is characterized in that：
Neural network model (8) is coupled with cynapse computing module (12) using neuron computing module (6) and drawn, neuron mould
Type computing module (6), cynapse computing module (12), network size multiplexer (33) and interface multiplexer (34) use VHDL
Programming with Pascal Language, and compile and download in fpga chip (3), host computer (2) is by VB programming realizations man machine operation interface (7) and leads to
Ethernet communication module (5) is crossed to be communicated with fpga chip (3) and chip external memory array (4)；
The signal of man machine operation interface (7) input is passed in fpga chip (3) by ethernet communication module (5), is realized
The control of configuration and calculating to FPGA computing module parameters, Izhikevich neuron models (25) calculate mould by neuron
Film potential signal (9) caused by block (6) calculating is transferred to network dynamics information (10) by ethernet communication module (5)
Progress network characteristic is shown in man machine operation interface (7) operates with Data Analysis Services, while film potential signal (9) and network move
Step response information (10) storage is into neuroid information storage SDRAM (35), and cynapse computing module (12) is by parallel M blocks
Synaptic currents module (26) forms, and each synaptic currents module (26) receives presynaptic membrane electric potential signal (24) and carries out ordinary differential side
Journey calculates, and neuron computing module (6) receives parameter transfer bus (23) transmission data and carries out parameter configuration；
Man machine operation interface (7) is responsible for configuration PC control signal (28), and PC control signal (28) includes network size
Control signal (29), changing interface signal (30), the parameter signal of interface 2 (31), the parameter signal of interface 3 (32), network size is multiple
Network size control signal (29) is received with device (33), and network size configuration is carried out to neural network model (8), interface is multiple
Interface selection is carried out with device (34) reception interface switching signal (30)；
The chip external memory array (4) includes four pieces of 56MB models DDR2-533 SDRAM chips, is respectively used to storage not
With membrane potential of neurons signal (9) data under network size, four pieces of SDRAM chips are respectively that 200 neuroid film potentials are deposited
Store up SDRAM (16), 500 neuroid film potentials storage SDRAM (17), 1000 neuroid film potentials storage SDRAM
(18), 2000 neuroid film potentials storage SDRAM (19), for according to experiment demand switching neural network model (8)
Network size size, so as to realize the simulation work of neuroid synchronia；
The neuron computing module (6) includes the Izhikevich neuron models (25) of N number of parallel connection, and neuron calculates
The associated parameter data that module (6) receives parameter transfer bus (23) input carries out neuron parameter tuning, and receives cynapse meter
The presynaptic membrane electric potential signal (24) for calculating module (12) output carries out being of coupled connections for neuroid, cynapse computing module (12)
Comprising M parallel synaptic currents modules (26), the number M of synaptic currents module is more than the number of Izhikevich neuron models
For mesh N to ensure parallelization computing, Izhikevich neuron models (25) use VHDL language with synaptic currents module (26)
Write.
2. the Izhikevich neuroid synchronous discharge emulation platforms based on FPGA according to claim 1, its feature
It is：The ethernet communication module (5) receives the PC control signal (28) of data transmission bus (27) input, and exports net
Network scale control signal (29), changing interface signal (30), the parameter signal of interface 2 (31), the parameter signal of interface 3 (32), respectively
It is output to network size multiplexer (33), interface multiplexer (34), the parameter of interface 2 storage RAM (13), the parameter of interface 3 storage RAM
(14) in, so as to complete control of the host computer (2) to FPGA neuroids computation processor (1).
3. the Izhikevich neuroid synchronous discharge emulation platforms based on FPGA according to claim 1, its feature
It is：The neuron models computing module (6) arrives neuroid information by calculating output network dynamics information (10)
Store and data buffer storage is carried out in SDRAM (35), then be transferred in ethernet communication module (5), pass through parameter transfer bus (23)
It is transferred in host computer (2), so as to carry out the display of neuroid dynamic characteristic and analysis operation.
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| CN110598857A (en) * | 2019-05-14 | 2019-12-20 | 河北工业大学 | Method for displaying Izhikevich neuron model |
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