CN104615909A - Izhikevich neural network synchronous discharging simulation platform based on FPGA - Google Patents
Izhikevich neural network synchronous discharging simulation platform based on FPGA Download PDFInfo
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Abstract
The invention provides an Izhikevich neural network synchronous discharging simulation platform based on an FPGA. The simulation platform comprises an FPGA neural network computing processor and an upper computer which are connected with each other. The FPGA neural network computing processor comprises an FPGA chip, an off-chip memorizer array and an Ethernet communication module, wherein the FPGA chip receives an upper computer control signal output by the off-chip memorizer array, and receives a presynaptic membrane potential signal output by the off-chip memorizer array. The upper computer is in communication with the FPGA chip and the off-chip memorizer array through a VB programming realization man-machine operating interface and the Ethernet communication module, and a neural network model is established on the FPGA chip through Verilog HDL language programming. The Izhikevich neural network synchronous discharging simulation platform has the advantages that the hardware modeling of the phenotype and physiological type neural network model is achieved through an animal-free experiment serving as a biological neural network on the basis of an FPGA neural network experiment platform conducting computation at a high speed, and the consistency with true biological nerve cells on the time scale can be achieved.
Description
Technical field
The present invention relates to biomedical engineering technology, particularly a kind of Izhikevich neuroid synchronous discharge emulation platform based on FPGA.
Background technology
Brain about has 1,000 hundred million neurons, each neuron carries out information transmission by cynapse and other about 1,000 hundred million neurons, form the neural circuit that various function is special between neuron, by various neurotransmitter and acceptor transmission of information thereof, produce the Premium Features of brain.The process of brain to nerve information has been worked in coordination with by the neuron of Different brain region, and synchronously as the classic manifestations of neuron colony discharge activities, be the important mechanisms of Neural information processing.Synchronous movement between neuron plays crucial effect in Different brain region nerve information transmission and processing procedure, and it can be integrated and the various information needed for coordinated movement of various economic factors control.But up to the present in brain, between Different brain region, the Forming Mechanism of all kinds of neuron synchronous movement is still unintelligible.Therefore, the synchronous dynamics furtheing investigate neuroid has important physiological significance.
Bioexperiment due to its high cost and ethics constraint and have some limitations; Emulation of the computer software intricate operation computing velocity is slow, shortage real-time, and for the mimic channel that a certain specific neuron builds, experiment extensibility and dirigibility have limitation, are not easy to the operation of simulation work and carry out.Therefore the high-performance hardware of neuroid synchronia realizes, and is a brand-new research direction.
Field programmable gate array (Field Programmable Gate Array, FPGA) technology is a kind of semi-custom circuit engineering in special IC (ASIC) field, which solve the deficiency of custom circuit and programming device gate circuit number is limited in the past problem, favored gradually in the computational neuroscience field taking biological nervous system as object.The shortcoming such as long relative to the mimic channel platform development cycle, FPGA because its integrated level is high, volume is little, parallel computation, the advantage such as repeated configuration, flexible in programming, good reliability, low-power consumption can realize the emulation of neuron bioelectrical activity and specificity analysis under yardstick actual time.Application can the FPGA of concurrent operation, under can completing yardstick actual time, neuroid synchronous movement emulates and specificity analysis, improve operation efficiency, in neuron behavior research, synchronia mechanism, bionics, intelligent system etc., have important using value.
Existing technology is also in foundation phase, therefore still there is following shortcoming: there is no special neuroid synchronization simulation FPGA experiment porch; The simulation hardware neural network model scale using FPGA to realize is less, and scale is immutable, and network connects flexible poor; Man-machine interface is not yet perfect, cannot carry out real-time control operation and data analysis, therefore more difficult to the FPGA simulation analysis of neuroid dynamic perfromance.
Summary of the invention
For the deficiency existed in above-mentioned technology, the object of this invention is to provide a kind of neuroid synchronization simulation FPGA experiment porch, make researchist can complete the relevant simulation operations of neuroid synchronia under heterogeneous networks scale flexibly easily, electric discharge observation and further theoretical analysis is carried out, for the synchronia studying neuroid provides Important Theoretic Foundation by man machine operation interface.
For achieving the above object, the technical solution used in the present invention is to provide a kind of Izhikevich neuroid synchronous discharge emulation platform based on FPGA, it is characterized in that: this emulation platform includes interconnective FPGA neuroid computation processor and host computer, wherein FPGA neuroid computation processor includes fpga chip, chip external memory array, ethernet communication module, the PC control signal that described fpga chip receiving sheet external storage array exports, and receive the presynaptic membrane electric potential signal exported by chip external memory array; Host computer is by VB programming realization man machine operation interface and carry out communication by ethernet communication module and fpga chip and chip external memory array, and fpga chip builds neural network model by Verilog HDL Programming with Pascal Language.
Neural network model adopts neuron computes module to be coupled with cynapse computing module and draws, neuron models computing module, cynapse computing module, network size multiplexer and interface multiplexer all adopt VHDL language to programme, and compiling downloads in fpga chip, host computer is by VB programming realization man machine operation interface and carry out communication by ethernet communication module and fpga chip and chip external memory array.
The signal of described man machine operation interface input passes in fpga chip by ethernet communication module, realize the configuration of FPGA computing module parameter and the control of calculating, Izhikevich neuron models calculate the film potential signal and the network dynamics information that produce by carrying out network characteristic in ethernet communication module transfer to man machine operation interface and show and Data Analysis Services operating by neuron computes module, film potential signal and network dynamics information are stored in neuroid information storage SDRAM simultaneously, cynapse computing module is made up of the M block synaptic currents module walked abreast, each synaptic currents module receives presynaptic membrane electric potential signal and carries out ordinary differential equation calculating, neuron computes module receiving parameter transfer bus transmission data carry out parameter configuration.
Man machine operation interface is responsible for configuration PC control signal, PC control signal comprises network size control signal, changing interface signal, interface 2 parameter signal, interface 3 parameter signal, network size multiplexer receives network size control signal, and network size configuration is carried out to neural network model, interface multiplexer reception interface switching signal carries out interface selection.
The invention has the beneficial effects as follows that this experiment porch achieves complicated Izhikevich neuroid modeling, devise and have man-machine interface that is visual and operability concurrently, improve dirigibility and the operability of system, can emulate with biological neuron mathematical model in time scale; Meanwhile, this experiment porch is that under research electric field action, the synchronia of neuroid provides the visualized experiment platform in yardstick actual time, has important practical value to the important mechanisms research understanding Neural information processing.Based on high-speed parallel calculate FPGA neuroid characteristic Simulation be a kind of solve neuroid synchronizing characteristics dynamic mechanism without animal experiment method, the applied research of its experiment porch worldwide belongs to the sciemtifec and technical sphere in a forward position.What this programme was innovated proposes neuroid synchronia high velocity experiments platform, it has some advantage following: 1, designed hardware simulation model can keep the consistance with true biological neuron in time scale, its chips maximum operation frequency is 200MHz, concurrent operation ensures that film potential output frequency is within 1 millisecond, meet actual nerve elementary time scale requirement, the research for neuroid synchronia provides quicker, portable hardware experiment platform; 2, in this platform, neuroid scale, neuron models parameter etc. can pass through upper computer software interface configurations, complete the various characteristics utilizing computer user's operation interface configuration experimental facilities; 3, man machine operation interface can the dynamic perfromance of real-time monitored Neural spike train state and network activity, and quantitatively can record amplitude and the energy of signal, carry out the analysis of neuroid synchronizing characteristics simultaneously, data storage function is convenient to the analytical work of follow-up data, and the research for neuroid synchronia provides better visualized experiment research platform.
Accompanying drawing explanation
Fig. 1 is experimental platform system structural representation of the present invention;
Fig. 2 is Izhikevich stream of neuron waterline model;
Fig. 3 is synaptic currents computation model;
Fig. 4 is human-machine operation operation interface I schematic diagram of the present invention;
Fig. 5 is human-machine operation operation interface II schematic diagram of the present invention;
Fig. 6 is human-machine operation operation interface III schematic diagram of the present invention.
In figure:
1.FPGA neuroid computation processor, 2. host computer, 3.FPGA chip, 4. chip external memory array, 5. ethernet communication module, 6. neuron models computing module, 7. man machine operation interface, 8. neural network model, 9. film potential signal, 10. network dynamics information, 11. neuron computes time delay processes, 12. cynapse computing modules, 13. interface 2 parameters store RAM, 14. interface 3 parameters store RAM, 15. network weight ROM, 16.200 neuroid film potential stores SDRAM, 17.500 neuroid film potential stores SDRAM, 18.1000 neuroid film potential stores SDRAM, 19.2000 neuroid film potential stores SDRAM, 20. network weight ROM, 21. variable V streamlines, 22. variable u streamline, 23. parameter transmission buses, 24. presynaptic membrane electric potential signals, 25.Izhikevich neuron models, 26. synaptic currents modules, 27. data transmission bus, 28. PC control signals, 29. network size control signals, 30. changing interface signals, 31. interface 2 parameter signals, 32. interface 3 parameter signals, 33. network size multiplexers, 34. interface multiplexers, 35. neuroid information store SDRAM, 36. parameter a numerical signals, 37. parameter b numerical signals, 38. parameter c numerical signals, 39. parameter d numerical signals, 40. data buffer storage SDRAM, 41. man machine operation interfaces I, 42. man machine operation interfaces II, 43. man machine operation interfaces III, 44. postsynaptic membrane electric potential signals, 45. mirrored storage dual port RAMs, 46. synaptic delay modules, 47. network electric discharge grid figure display interfaces, 48. network parameter config options, 49. basic operation frames, 50. general parameter configurations, 51. degree of distribution parameters are arranged, 52. degree of distribution curve display interfaces, 53. synchronization factor assay surfaces, 54. parameter sections arrange frame
Embodiment
Below in conjunction with accompanying drawing, the Izhikevich neuroid synchronous discharge simulation platform structure based on FPGA of the present invention is illustrated.
The design philosophy of the Izhikevich neuroid synchronous discharge emulation platform based on FPGA of the present invention is on fpga chip, first build the neural network model of parallel computation; Then on FPGA, design the chip external memory of different storage space independent of neural network model, for the neuroid information intermediate data of different scales storage with call; Ethernet communication module is used for host computer and slave computer data are transmitted, and carries out corresponding control operation according to the input instruction of upper computer software interface to the transmission of data to selection; Finally design upper computer software interface, upper computer software interface is by parameters and be transferred to fpga chip, realize configuration neuron models key parameter and network being reconnected to probability parameter, select to select network size by option window, Neural spike train dynamic data in fpga chip can be uploaded to host computer simultaneously, carry out the display of electric discharge dynamic waveform at upper computer software interface.This experiment porch is made up of interconnective FPGA development board and host computer.Wherein FPGA part is used for realizing different scales neuroid, and host computer is used for designing man machine operation interface and carrying out communication by ethernet communication module and FPGA.
Described neuron models adopt Euler method discretize in FPGA, and adopt pipelining to build, and make complicated ordinary differential equation parallel computation.Streamline thought utilizes delay register to make mathematical model be divided into several sub-calculating processes in essence, within each clock period, every sub-calculating process can carry out different neural cluster, not computing in the same time simultaneously, model data intersects in the outer SDRAM register of sheet and preserves, and transmits with clock.In neuron models, different model parameter can produce different types of discharge mode, and model parameter is inputted by man machine operation interface, is stored in peripheral hardware register SDRAM, synchronization call during calculating, so just can realize independent neuronic parameter adjustment and Neural spike train pattern changes.For improving network calculations speed in computation process, adopt modular concurrent method, extended network scale as far as possible under the condition that logical resource allows in sheet.
Described synaptic currents computing module 12: described synaptic currents computing module adopts parallel modules method, receive the film potential information that neural network model calculates, coupling calculating generation synaptic currents signal through synaptic currents returns in neural network model, thus completes being of coupled connections in network between each neuron.
Described man machine operation interface 7: writing of man machine operation interface adopts VB language development to realize, performance history is intuitively convenient, visual, object-oriented, by event driven high-level programming language, finally present in front of the user be the operation interface similar with real experimental apparatus, can realize real-time data acquisition, waveform display and Data Analysis Services.
Izhikevich neuroid synchronous discharge emulation platform based on FPGA of the present invention is made up of interconnective FPGA neuroid computation processor 1 and host computer 2.Wherein FPGA neuroid computation processor 1 is used for realizing parallel neuron models computing module 6 and cynapse computing module 12, host computer 2 is used for designing man machine operation interface 10 and realizes the communication with FPGA development board 1 by ethernet communication module 5, and data communication is realized by data transmission bus 27.Below be illustrated:
Neural network model 8
As shown in Figure 1, hardware experiment platform is designed, the Cyclone IV EP4CGX110DF31C7 chip that fpga chip 3 adopts altera corp to produce, according to neuronic mathematical model, adopts Euler method discretize and builds Izhikevich stream of neuron waterline model 25.Synaptic currents computing module 12 comprises parallel synaptic currents module 26.Parameter transmission bus 23 receives the data that arranged by man machine operation interface 7 in hardware system, the critical datas such as membrane potential of neurons signal 9 and network dynamics information 10 upload in host computer 2 the real-time display and analysis of carrying out neuroid synchronia by parameter transmission bus 23, be stored in neuroid information simultaneously and store in SDRAM35.
Neural network model 8 is made up of neuron models computing module 6 and cynapse computing module 12, neuron models computing module is realized by the Izhikevich stream of neuron waterline model 25 walked abreast, the synchronous operation under unified clock of all data paths, and according to the structure of FPGA, by the conversion of QUARTUS II software simulating hardware description language.Be illustrated in figure 2 Izhikevich neuron models 25, it forms primarily of addition, multiplication and shift register, and the mathematical model of described Izhikevich neuron models 25 is:
If v >=30, then
Wherein v represents neuronic membrane voltage, and u representative recovers variable, reaction K
+, Na
+activity, and give membrane voltage with negative feedback, a, b, c, d are system of equations constant.This model comprises variable v streamline 21 and variable u two streamlines, and neuron computes time delay process 11 is for increasing the handling capacity of system.Izhikevich neuron models 25 receive the parameter a numerical signal 36, parameter b numerical signal 37, parameter c numerical signal 38, the parameter d numerical signal 39 that are arranged by man machine operation interface 7, by optimum configurations change Neural spike train pattern and state, the presynaptic membrane electric potential signal 24 of receiving sheet external storage array 4 transmission simultaneously, carry out ordinary differential equation calculating, obtain network dynamics information and output in data buffer storage SDRAM40.
As shown in Figure 3, each synaptic currents module 26 comprises network weight ROM 15, network weight ROM 20, mirrored storage dual port RAM 45, synaptic delay module 46, data wherein in multiplexer selection mirrored storage dual port RAM 45 are carried out being coupled with the data in network weight ROM 15 and are calculated, acquired results and network weight ROM 20 store data and are coupled further and calculate, calculating gained postsynaptic membrane electric potential signal 44 is input in neuron models computing module 6, synapse delay module 46 receives the film potential signal 44 of previous step, logic couples is carried out with the calculating of this step, and can throughput of system be increased.The number M of synaptic currents module is greater than the number N of Izhikevich neuron models to ensure parallelization computing.
Chip external memory array 4 comprises 200 neuroid film potentials and stores SDRAM16, 500 neuroid film potentials store SDRAM17, 1000 neuroid film potentials store SDRAM18, 2000 neuroid film potentials store SDRAM19, the network dynamics information 10 that reception calculates output by neural network model 8 stores, output signal is in network size multiplexer 33, the network size control signal 29 that network size multiplexer 33 receives host computer 2 input carries out channel selecting, finally presynaptic membrane electric potential signal 24 is outputted in neural network model 8 and carry out network coupling.Neuron number is configured chip external memory array 4 in digital form by host computer 2, thus realizes the configuration of network size.
Interface 2 parameter stores RAM13, interface 3 parameter stores RAM14 and receives interface 2 parameter signal 31, interface 3 parameter signal 32 that are transmitted by ethernet communication module 5 respectively and store, numerical value is outputted in interface multiplexer 34, interface multiplexer 34 receives the changing interface signal 30 inputted by host computer 2 and carries out changing interface, data is input in neural network model 8 by parameter transmission bus 23 and carries out calculating and configure.
Man machine operation interface 7
Man machine operation interface 7 comprises three tab: human-machine operation operation interface I 41, human-machine operation operation interface II 42 and human-machine operation operation interface III 43, in host computer 2, use VB Programming with Pascal Language mode to design man machine operation interface 7, host computer 2 exports PC control signal 28 in FPGA neuroid computation processor 1.Fpga chip 3 realizes data communication by ethernet communication module 5 and man machine operation interface 7, and man machine operation interface 7 receives the data transmitted from fpga chip 3, ethernet communication module 5 by ethernet communication module 5; Man machine operation interface 7 parameters inputs data in fpga chip 3 by ethernet communication module 5, carries out parameter configuration and signal behavior to neural network model 8.
Described man machine operation interface I 41 as shown in Figure 4, is switched by tab, wherein including degree distribution curve display interface 52 display degree distribution curve, and degree distribution parameter arranges 51 setting degree distribution parameters, to carry out Network Synchronization specificity analysis.The result that man machine operation interface comprises cluster coefficients, worldlet degree, the average number of degrees and shortest path length shows, and is convenient to observation grid characteristic directly perceived.
As shown in Figure 5, it comprises network electric discharge grid figure interface 47, network parameter config option 48 to described man machine operation interface II 42: network electric discharge grid Figure 47 is for showing the synchronizing characteristics of neuroid; Network parameter config option 48, for configuration network parameter, comprises network size and sampling number.
Described man machine operation interface III 43 as shown in Figure 6, is switched by tab, wherein comprises synchronization factor assay surface 53, and for showing synchronization factor analysis result, parameter section arranges frame 54 for configuration parameter section, thus carries out the mathematical analysis of synchronization factor.
Described man machine operation interface I 41, man machine operation interface II 42, described man machine operation interface III 43 comprise basic operation frame 49, for realizing the basic operation to man machine operation interface 7; Comprise general parameter configuration block 50, thus carry out the parameter configuration of FPGA neuroid computation processor 1.
FPGA emulation platform
The neural network model of discrete, fixed step size, the fixed-point number computing based on module is write, through QUARTUS II software programming complete operation logic and program structure by VHDL language; Compiling, analysis integrated, placement-and-routing, download in fpga chip and run.Upload the neuron number certificate of fpga chip computing generation through Ethernet, analyze and research in man machine operation interface 7 pairs of neuroid synchronizing characteristicss of VB language compilation, realized the dynamic analysis of different angles by the tab switching man machine operation interface 7.
Claims (5)
1. the Izhikevich neuroid synchronous discharge emulation platform based on FPGA, it is characterized in that: this emulation platform includes interconnective FPGA neuroid computation processor (1) and host computer (2), wherein FPGA neuroid computation processor (1) includes fpga chip (3), chip external memory array (4), ethernet communication module (5), the PC control signal that described fpga chip (3) receiving sheet external storage array (4) exports, and receive the presynaptic membrane electric potential signal exported by chip external memory array (4), host computer (2) is by VB programming realization man machine operation interface (7) and carry out communication by ethernet communication module (5) and fpga chip (3) and chip external memory array (4), and fpga chip (3) builds neural network model (8) by Verilog HDL Programming with Pascal Language,
Neural network model (8) adopts neuron computes module (6) to be coupled with cynapse computing module (12) and draws, neuron models computing module (6), cynapse computing module (12), network size multiplexer (33) and interface multiplexer (34) all adopt VHDL language to programme, and compiling downloads in fpga chip (3), host computer (2) is by VB programming realization man machine operation interface (7) and carry out communication by ethernet communication module (5) and fpga chip (3) and chip external memory array (4);
The signal that described man machine operation interface (7) inputs passes in fpga chip (3) by ethernet communication module (5), realize the configuration of FPGA computing module parameter and the control of calculating, Izhikevich neuron models (25) are calculated the film potential signal (9) and the network dynamics information (10) that produce and are transferred in man machine operation interface (7) by ethernet communication module (5) and carry out network characteristic and show and Data Analysis Services operates by neuron computes module (6), film potential signal (9) and network dynamics information (10) are stored in neuroid information storage SDRAM (35) simultaneously, cynapse computing module (12) is made up of M block synaptic currents module (26) walked abreast, each synaptic currents module (26) receives presynaptic membrane electric potential signal (24) and carries out ordinary differential equation calculating, neuron computes module (6) receiving parameter transfer bus (23) transmission data carry out parameter configuration,
Man machine operation interface (7) is responsible for configuration PC control signal (28), PC control signal (28) comprises network size control signal (29), changing interface signal (30), interface 2 parameter signal (31), interface 3 parameter signal (32), network size multiplexer (33) receives network size control signal (29), and network size configuration is carried out to neural network model (8), interface multiplexer (34) reception interface switching signal (30) carries out interface selection.
2. according to claim 1 based on the Izhikevich neuroid synchronous discharge emulation platform of FPGA, it is characterized in that: described chip external memory array (4) comprises the SDRAM chip that four pieces of 56MB models are DDR2-533, be respectively used to store membrane potential of neurons signal (9) data under heterogeneous networks scale, four pieces of SDRAM chips are respectively 200 neuroid film potentials and store SDRAM (16), 500 neuroid film potentials store SDRAM (17), 1000 neuroid film potentials store SDRAM (18), 2000 neuroid film potentials store SDRAM (19), the network size size of neural network model (8) is switched for experimentally demand, thus realize the simulation work of neuroid synchronia.
3. according to claim 1 based on the Izhikevich neuroid synchronous discharge emulation platform of FPGA, it is characterized in that: described ethernet communication module (5) receives the PC control signal (28) that data transmission bus (27) inputs, and output network scale control signal (29), changing interface signal (30), interface 2 parameter signal (31), interface 3 parameter signal (32), output to network size multiplexer (33) respectively, interface multiplexer (34), interface 2 parameter stores RAM (13), interface 3 parameter stores in RAM (14), thus complete the control of host computer (2) to FPGA neuroid computation processor (1).
4. according to claim 1 based on the Izhikevich neuroid synchronous discharge emulation platform of FPGA, it is characterized in that: described neuron computes module (6) comprises the Izhikevich neuron models (25) of N number of parallel join, the associated parameter data that neuron computes module (6) receiving parameter transfer bus (23) inputs carries out neuron parameter tuning, and receive the presynaptic membrane electric potential signal (24) that cynapse computing module (12) exports and carry out being of coupled connections of neuroid, cynapse computing module (12) comprises M parallel synaptic currents module (26), the number M of synaptic currents module is greater than the number N of Izhikevich neuron models to ensure parallelization computing, Izhikevich neuron models (25) and synaptic currents module (26) all adopt VHDL language to write.
5. according to claim 1 based on the Izhikevich neuroid synchronous discharge emulation platform of FPGA, it is characterized in that: described neuron models computing module (6) carries out data buffer storage by calculating output network dynamic characteristic information (10) in neuroid information storage SDRAM (35), be transferred in ethernet communication module (5) again, be transferred in host computer (2) by parameter transmission bus (23), thus carry out display and the analysis operation of neuroid dynamic perfromance.
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