CN111061662A - Compiling system and method for expanding FPGA (field programmable Gate array) interconnected IO (input/output) based on connector - Google Patents
Compiling system and method for expanding FPGA (field programmable Gate array) interconnected IO (input/output) based on connector Download PDFInfo
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- CN111061662A CN111061662A CN201911239475.5A CN201911239475A CN111061662A CN 111061662 A CN111061662 A CN 111061662A CN 201911239475 A CN201911239475 A CN 201911239475A CN 111061662 A CN111061662 A CN 111061662A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention discloses a compiling system and a method for expanding FPGA interconnection IO based on a connector, wherein the system comprises the following steps: the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards for the user; the TDM module transmits different signals in different time periods of the same physical connection; the time division multiplexing TDM insertion module is used for a user to insert the time division multiplexing TDM module, and aiming at user design, the time division multiplexing TDM insertion module automatically generates an interconnection module in a TDM transmission mode of all interconnection signals according to the number of interconnection lines set by the user; the interface distribution module is used for providing a function of automatically matching the interface of the connector for a user according to the result of the connector setting management module, and the number of interconnection IO between the FPGAs is expanded by using the connectors belonging to each FPGA, so that the limitation that in-board interconnection lines are required to be used between the FPGAs is broken through, and the problem in the background technology can be effectively solved.
Description
Technical Field
The invention relates to the technical field of connectors, in particular to a compiling system and method for expanding FPGA interconnection IO based on a connector.
Background
The development board is a circuit board for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. The development board is generally customized by an embedded system developer according to development requirements, and can also be researched and designed by a user. The development board is hardware and software for a beginner to learn and learn the system, and simultaneously part of the development board also provides basic integrated development environment, software source codes, hardware schematic diagrams and the like, and common development boards comprise 51, ARM, FPGA and DSP development boards
The user needs to use connectors belonging to each FPGA for the design needing to be deployed to a plurality of FPGAs during the compiling process, if the user cannot run the compiling process well, the use of the connectors and the expansion of the FPGAs are affected, so that the FPGA development boards can only use respective connectors, the number of interconnection IO between the FPGAs cannot be expanded, the limitation of interconnection lines between the FPGA development boards cannot be broken through, and the rapid development of the development boards is not facilitated.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides the compiling system and method for expanding the FPGA interconnection IO based on the connector, and a user can conveniently expand the number of the FPGA interconnection IO, so that the capacity of chip design is improved, the chip design development process is accelerated, and the problems provided by the background technology can be effectively solved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a compiler system based on connector extension FPGA interconnection IO comprises:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards for the user;
the TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module is used for a user to insert the time division multiplexing TDM module, and aiming at user design, the time division multiplexing TDM insertion module automatically generates an interconnection module in a TDM transmission mode of all interconnection signals according to the number of interconnection lines set by the user;
and the interface distribution module is used for providing the function of automatically matching the connector interface for the user.
Further, the connector setting management module estimates the number of interconnection signals of a possible time division multiplexing proportion for an engineering design using time division multiplexing, and for an engineering design not using time division multiplexing transmission, the connector setting management module obtains the number of interconnection signals to be transmitted among the FPGAs and the number of Cable connecting lines set between the FPGAs by a current user, and indicates how many interconnection lines each Cable connecting line corresponds to.
Further, the time division multiplexing TDM is inserted into the module, and a user can select to transmit a part of signals through time division multiplexing according to design requirements, and a part of signals are not transmitted through time division multiplexing.
Further, for engineering designs that do not use time division multiplexing TDM, the assignment of interconnect signals to interconnect lines is done in the interface assignment module.
Further, the time division multiplexing TDM insertion module adds the number of interconnection signals of the corresponding number into the corresponding FPGA engineering according to the number of interconnection signals of the time division multiplexing ratio estimated by the connector setting management module.
A compiling method for expanding FPGA interconnection IO based on a connector comprises the following steps:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards;
the TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module inserts the time division multiplexing TDM module for a user, and aiming at user design, according to the number of interconnection lines set by the user, an interconnection module is automatically generated in a mode that all interconnection signals are transmitted by TDM;
the interface assignment module is used to provide the user with the functionality to automatically match the connector interface.
Further, the connector setting management module estimates the number of interconnection signals of a time division multiplexing proportion which may be used for an engineering design using time division multiplexing, and the time division multiplexing TDM insertion module adds the number of interconnection signals of a corresponding number into a corresponding FPGA engineering according to the number of interconnection signals of the time division multiplexing proportion estimated by the connector setting management module.
Further, for engineering designs that do not use time division multiplexing TDM, the assignment of interconnect signals to interconnect lines is done in the interface assignment module.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, for the design needing to be deployed to a plurality of FPGAs, when the compiling flow is operated, the number of interconnected IO between the FPGAs is expanded by using the connectors belonging to each FPGA, so that the limitation that in-board interconnection lines are required to be used between the FPGAs is broken through, a user can design a large-capacity and complex development board, and the development flow of SoC products is accelerated.
Drawings
FIG. 1 is a schematic diagram of the overall work flow of the compiling method of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a compiler system for expanding FPGA interconnection IO based on a connector, which comprises:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards for the user;
it should be noted that, for an engineering design using time division multiplexing, the connector configuration management module estimates the number of interconnection signals that may be used in a time division multiplexing ratio.
For the engineering design without using time division multiplexing, the connector setting management module can acquire the number of interconnection signals needing to be transmitted among the FPGAs and the number of the cables set between the FPGAs by the current user, and can indicate how many interconnection lines each Cable corresponds to.
The TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module is used for a user to insert the time division multiplexing TDM module, and aiming at user design, the time division multiplexing TDM insertion module automatically generates an interconnection module in a TDM transmission mode of all interconnection signals according to the number of interconnection lines set by the user;
and the time division multiplexing TDM insertion module adds the interconnection signal quantity of the corresponding quantity into the corresponding FPGA engineering according to the interconnection signal quantity of the time division multiplexing proportion estimated by the connector setting management module.
And the interface distribution module is used for providing a function of automatically matching the interface of the connector for a user, and distributing the connecting lines and the interfaces according to the result of the connector setting management module for the user to select until the test process is finished.
In the time division multiplexing TDM insertion module, a user can select to transmit part of signals through time division multiplexing according to design requirements, and part of signals are not transmitted through time division multiplexing, so that the selection is more flexible during specific use.
For engineering designs that do not use time division multiplexing TDM, the assignment of interconnect signals to interconnect lines is done in an interface assignment module.
According to the invention, for the design needing to be deployed to a plurality of FPGAs, when the compiling flow is operated, the number of interconnected IO between the FPGAs is expanded by using the connectors belonging to each FPGA, so that the limitation that in-board interconnection lines are required to be used between the FPGAs is broken through, a user can design a large-capacity and complex development board, and the development flow of SoC products is accelerated.
As shown in fig. 1, the present invention further provides a connector extension FPGA interconnection IO-based compiling method, including:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards;
the TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module inserts the time division multiplexing TDM module for a user, and aiming at user design, according to the number of interconnection lines set by the user, an interconnection module is automatically generated in a mode that all interconnection signals are transmitted by TDM;
the interface assignment module is used to provide the user with the functionality to automatically match the connector interface.
The time division multiplexing TDM insertion module adds the number of the interconnection signals with the corresponding number into the corresponding FPGA engineering according to the number of the interconnection signals with the time division multiplexing proportion estimated by the connector setting management module.
For engineering designs that do not use time division multiplexing TDM, the assignment of interconnect signals to interconnect lines is done in an interface assignment module.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (8)
1. The utility model provides a compiling system based on connector extension FPGA interconnection IO which characterized in that includes:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards for the user;
the TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module is used for a user to insert the time division multiplexing TDM module, and aiming at user design, the time division multiplexing TDM insertion module automatically generates an interconnection module in a TDM transmission mode of all interconnection signals according to the number of interconnection lines set by the user;
and the interface distribution module is used for providing a function of automatically matching the interface of the connector for a user according to the result of the connector setting management module and expanding the number of interconnected IO between the FPGA.
2. The compiling system based on connector extension FPGA interconnection IO of claim 1, characterized in that, for an engineering design using time division multiplexing, the connector setting management module estimates the number of interconnection signals of a possible time division multiplexing proportion, and for an engineering design not using time division multiplexing transmission, the connector setting management module obtains the number of interconnection signals to be transmitted between FPGAs and the number of Cable connecting lines set between FPGAs by a current user, and indicates how many interconnection lines each Cable connecting line corresponds to.
3. The compiling system based on the connector extension FPGA interconnection IO of claim 1 is characterized in that in the time division multiplexing TDM insertion module, a user can select to transmit part of signals through time division multiplexing according to design requirements, and part of signals are not transmitted through time division multiplexing.
4. The connector extension FPGA interconnection IO-based compiling system according to claim 1, characterized in that: for engineering designs that do not use time division multiplexing TDM, the assignment of interconnect signals to interconnect lines is done in an interface assignment module.
5. The connector extension FPGA interconnection IO-based compiling system according to claim 2, characterized in that: and the time division multiplexing TDM insertion module adds the interconnection signal quantity of the corresponding quantity into the corresponding FPGA engineering according to the interconnection signal quantity of the time division multiplexing proportion estimated by the connector setting management module.
6. A compiling method for expanding FPGA interconnection IO based on a connector is characterized by comprising the following steps:
the connector setting management module is used for providing a setting interface for a user and setting a connection setting management function between a single FPGA development board or a plurality of FPGA development boards;
the TDM module adopts different periods of the same physical connection to transmit different signals, divides the time for transmitting information to the whole channel into a plurality of time slots, and distributes the time slots to each signal source for use;
the time division multiplexing TDM insertion module inserts the time division multiplexing TDM module for a user, and aiming at user design, according to the number of interconnection lines set by the user, an interconnection module is automatically generated in a mode that all interconnection signals are transmitted by TDM;
the interface distribution module is used for providing a function of automatically matching the interface of the connector for a user, and the number of interconnected IO between the FPGAs is expanded.
7. The connector extension FPGA interconnection IO compiling method of claim 6, wherein the connector setting management module estimates the number of interconnection signals with a possible time division multiplexing ratio for an engineering design using time division multiplexing, and the time division multiplexing TDM insertion module adds the number of interconnection signals with a corresponding number to the corresponding FPGA engineering according to the number of interconnection signals with the time division multiplexing ratio estimated by the connector setting management module.
8. The connector extension FPGA interconnection IO-based compiling system of claim 6, characterized in that for engineering designs not using Time Division Multiplexing (TDM), the allocation of interconnection signals with respect to interconnection lines is done in an interface allocation module.
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Citations (4)
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| CN1492642A (en) * | 2002-10-21 | 2004-04-28 | 华为技术有限公司 | Method and device for establishing time-division multiplexing mode interconnection of multiple modules |
| CN103902501A (en) * | 2014-04-02 | 2014-07-02 | 浙江大学 | FPGA (field programmable gate array) development board based detection method for optical interconnection network topology structural performance among boards |
| CN104615909A (en) * | 2015-02-02 | 2015-05-13 | 天津大学 | Izhikevich neural network synchronous discharging simulation platform based on FPGA |
| CN109491854A (en) * | 2017-09-12 | 2019-03-19 | 北京遥感设备研究所 | A kind of SoC prototype verification method based on FPGA |
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- 2019-12-06 CN CN201911239475.5A patent/CN111061662B/en active Active
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| CN1492642A (en) * | 2002-10-21 | 2004-04-28 | 华为技术有限公司 | Method and device for establishing time-division multiplexing mode interconnection of multiple modules |
| CN103902501A (en) * | 2014-04-02 | 2014-07-02 | 浙江大学 | FPGA (field programmable gate array) development board based detection method for optical interconnection network topology structural performance among boards |
| CN104615909A (en) * | 2015-02-02 | 2015-05-13 | 天津大学 | Izhikevich neural network synchronous discharging simulation platform based on FPGA |
| CN109491854A (en) * | 2017-09-12 | 2019-03-19 | 北京遥感设备研究所 | A kind of SoC prototype verification method based on FPGA |
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| 张潇筱: "基于多FPGA的高性能嵌入式计算硬件平台设计与应用", 《中国优秀硕士学位沦为全文数据库(电子期刊)》 * |
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