CN110245389A - Spiking feedforward network hippocampus function emulation system based on FPGA - Google Patents
Spiking feedforward network hippocampus function emulation system based on FPGA Download PDFInfo
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Abstract
The present invention provides a kind of Spiking feedforward network hippocampus function emulation system based on FPGA, it is characterized in that: the analogue system includes FPGA development board, host computer, FPGA development board includes feed forward neural metanetwork, the soft nuclear control device of NiosII and usb interface module, it further include three layers of feedforward network of the simulation hippocampal neural meta function for being compiled by VHDL language program downloads and being run in FPGA development board, initial value signal issues module, the first layer of network experiences layer, second layer hippocampus functional layer, third layer acts output layer, LIF stream of neuron waterline model, judge control module, STDP, that is, cynapse control updates matrix；LIF stream of neuron waterline model in each layer feedforward network judges that control module and STDP synapse turnover matrix are all made of VHDL language programming and realize；Judge that control module is responsible for the control exported to every layer signal, the control signal issued passes through to experience layer signal transmission channel, hippocampus functional layer signal transmission pathway and act output layer signal transmission pathway respectively passes to every layer of neuron.
Description
Technical field
The present invention relates to biomedical engineering technology, especially a kind of Spiking feedforward network hippocampus function based on FPGA
It can analogue system.
Background technique
It is present in all mammals and the hippocampus that can retain long-term memory is the most important structure of brain
One of, it is mainly responsible for episodic memory and tasking learning.The study found that when solving a behavior task instantly, hippocampus mind
It can be influenced by the environment of surrounding through member, rat is tested done in a T-type labyrinth according to researcher and is shown when big
Mouse turns left in labyrinth or the hippocampal neuron of right-hand rotation Shi Yousan/bis- is discharged in different ways；Many equal tables of research
Bright hippocampal neuron is forward-looking to the coding of memory with backtracking property and before discharge to specific event in the brain
With selectivity.But while the research to hippocampal neuron is numerous, up to the present also only phenomenon is analyzed, to sea
The discharge mechanism of horse neuron is still not clear, therefore by building feed forward neural metanetwork, simulating the function of hippocampal neuron simultaneously
Check analysis is carried out with experimental data, will be of great significance to the discharge mechanism for deeply probing into hippocampal neuron.
Since the development of Bioexperiment needs to pay high cost, simultaneously because the baseline of ethics and with
Certain limitation；Appliance computer carries out software emulation, and not only calculating speed is slow but also complex steps do not have real-time, together
When do not have the scalability and flexibility of experiment to the analog circuit that specific neuron is built, greatly reduce simulation work
Efficiency.Therefore the hardware realization of hippocampal neuron functional network is a completely new research direction.
Field programmable gate array (Field Programmable Gate Array, FPGA) is that the number of a new generation is patrolled
Device is collected, it is suitable for extensive timing, and the occasion of the logic circuit applications such as combination is that researcher can using most instantly
One of programmed process device, there is driven by program, and a similar microprocessor, its control program stores in memory, and is powering on
It is loaded into chip automatically later.Its speed of service is fast, and stability is strong, can be re-defined by user to it, meets not
Same experiment demand.Under normal circumstances, the structure of FPGA is by programmable I/O unit, basic programmable logic cells, rich
Rich interconnection resource, embedded RAM, embedded functional circuit unit and embed dedicated six part of stone composition.Based on FPGA's
System design, can be implemented on software the description of hardware capability, can also be adjusted repeatedly during entire design
The characteristics of trying, having stronger adaptability, its parallel computation can satisfy the neuroid synchronous movement under true scale
Emulation and specificity analysis, improve operation efficiency, therefore real for the emulation of large-scale nervous system nerves network and programming
Existing, FPGA is highly effective platform.
Existing technology has the disadvantage in that also in foundation phase and there is no the special of the perfect in shape and function based on FPGA
For probing into the analogue system of hippocampal neural meta function；The simulation hardware neuron models structure realized with FPGA is simple and smart
It spends lower；Man-machine interface is not perfect, it has not been convenient to carry out real-time control and data are analyzed, therefore to hippocampal neuronal network dynamic
The FPGA simulation analysis of characteristic is relatively difficult.
Summary of the invention
Deficiency present in view of the above technology, the Spiking feedforward based on FPGA that the object of the present invention is to provide a kind of
Network hippocampus function emulation system completes researcher flexibly easily under heterogeneous networks scale to hippocampal neural elementary work
Can emulation, can intuitively read data using man machine operation interface, change network parameter network can also be carried out into
The theory analysis of one step provides important theoretical foundation for research hippocampal neuron discharge mechanism and function.Technical solution is such as
Under:
A kind of Spiking feedforward network hippocampus function emulation system based on FPGA, it is characterized in that: the analogue system includes
FPGA development board (1), host computer (2), the FPGA development board (1) include feed forward neural metanetwork (3), the soft core control of NiosII
Device (34) processed and usb interface module (36), feed forward neural metanetwork (3) therein include being compiled by VHDL language program downloads
The three layers of feedforward network (4) for simulating hippocampal neural meta function translated and run in FPGA development board (1), initial value signal issue mould
Block (5), network first layer experience layer (6), second layer hippocampus functional layer (7), third layer movement output layer (8), LIF i.e.
Leaky-integrate and Fire stream of neuron waterline model (9) judges control module (21), STDP i.e. Spiking-
Timing Dependent Plasticity cynapse control updates matrix (23)；LIF neuron flowing water in each layer feedforward network
Line model (9) judges that control module (21) and STDP synapse turnover matrix (23) are all made of VHDL language programming and realize；Judgement control
Molding block (21) is responsible for the control exported to every layer signal, and the control signal issued passes through respectively experiences layer signal transmission channel
(18), hippocampus functional layer signal transmission pathway (19) and movement output layer signal transmission pathway (20) pass to every layer of nerve
Member；With the progress of emulation, judges that control module (21) obtain the synaptic weight of each layer and pass it to cynapse control and update
Matrix (23), cynapse control update matrix (23) and are advised according to the variation of the signal behavior weight issued by judgement control module (21)
Then, corresponding matrix value can become larger if LTP, that is, Long-term Potentiation is selected, if LTD, that is, Long-term
Depression is selected, and corresponding matrix value can reduce, by each neuron of this new mechanism to another nerve
The weight of member, the weight of the update by signal transmission pathway (22) and can judge that control module (21) is returned to every layer of nerve
Member；It acts output layer (8) and the output result of network is transmitted to by NiosII soft-core processor (34) by signal transmission pathway (30),
The processor, which is also received, simultaneously obtains the real-time weight variation of network from alternative data selector (32) selected signal
Information；Host computer (2) is programmed by C++ and realizes man machine operation interface (38), and usb interface module (36) and fpga chip are passed through
(1) it is communicated, the data by communicating network model obtained are further processed in host computer (2)；Imitative
The true incipient stage generates stimulus signal by initial value signal module (5) and passes it to the impression layer (6) of network, then by feeling
Data are transmitted to by layer signal transmission channel (18) and judge control module (21), are by judging control module (21) according to victor
King's rule calculates, i.e., experiences row vector and synaptic weight of the film potential of layer (6) with resting potential work after poor by certain
Matrix does multiplying row vector obtained and its next layer, i.e. the film potential of hippocampus functional layer (7) and resting potential is made poor
Row vector and synaptic weight matrix later does multiplying and makees difference and maximizing to row vector obtained, then in hippocampus function
In ergosphere (7), neuron corresponding to the maximum value obtains stimulus signal, while other neurons of this layer do not obtain stimulation letter
Number, the rule is shown as the following formula, wherein VrestIt is constant, V for neuron resting potentialiFor every layer of i-th of neuron
Film potential, IkFor stimulated current signal,Excitatory synapse weight between i-th and jth layer,For i-th with jth layer it
Between inhibitory synapse weight, l indicates different layers, and respectively information experiences layer, hippocampus functional layer and movement output layer, j table
Show l layers some neuron, acquires the value of j corresponding to the maximum value inside braces according to the following formula, it then will thorn
Swash current signal IkIt is assigned to the neuron, regular according to the victor is a king, other neurons of this layer mustn't go to stimulated current to believe
Number:
It is calculated according to above formula and corresponding stimulation is generated to some neuron of the second layer hippocampus functional layer (7) of network,
Result is passed by signal transmission pathway (19) after being calculated in hippocampus functional layer (7) according to LIF stream of neuron waterline model (9)
To control module (21) are judged, then again by judging that the calculating of control module (21) is generated to some mind of movement output layer (8)
Then stimulation through member is calculated and is passed through also according to LIF stream of neuron waterline model (9) in movement output layer (8)
Signal transmission pathway (20), which is transmitted to, judges control module (21), experiences layer signal transmission channel (18), hippocampus function layer signal passes
Data are transmitted to after judging control module (21) by defeated access (19), movement output layer signal transmission pathway (20) every time, judgement
Control module (21) all can update matrix (23) to the cynapse control of different layers according to STDP rule and carry out right value update appropriate
And value information is returned to host computer (2) by data selector (32), while the Neural spike train information of network passes through USB
Interface module (36) returns to host computer (2), and in simulation process later, initial value signal is provided by movement output layer (8), makes
Network is able to continuous operation.
The judgement control module (21) obtains each layer membrane potential of neurons value and carries out corresponding judgement and calculate, and will sentence
Break signal, which exports to control to cynapse, updates matrix (23), while obtaining the updated neuron that cynapse control updates matrix (23)
Foundation of weight during emulation together with the output signal of feed forward neural metanetwork (3) each layer as judgement control, should
Module realizes the communication of information, by updating matrix (23) two-way interconnection with feed forward neural metanetwork (3) and cynapse control with energy
The function of enough more preferable simulation hippocampal neurons.
Cynapse control update matrix (23) by receive from judge the control signal of control module (21) according to
STDP rule carries out calculating update to the connection weight of neuron, and calculated result is returned to and judges control module (21), together
When be transmitted to data selector (31) by data transmission path (29) and analyzed and judged and in human-machine operation for host computer (2)
The corresponding weight of display in interface (38).
The NiosII soft-core processor (34) is realized entire analogue system by FPGA development board (1) and is controlled；
NiosII soft-core processor (34) on the one hand receives the signal of the movement output layer (8) in feed forward neural metanetwork (3), separately
On the one hand it is connected again with alternative data selector (32), data selector (32) is controlled and is obtained by data selector
(32) synaptic weight exported.Corresponding information obtained is transmitted to host computer (2) by usb interface module (36), passes through number
The input to FPGA development board (1) may be implemented according to the information that transmission channel (37) man machine operation interface (38) exports.
The alternative data selector (32) receives the two-way weight signal point that matrix (23) are updated from cynapse control
Three layers of synaptic weight between any two is not represented；The command selection transmitted according to NiosII soft-core processor (34) signal all the way
And it is exported by usb interface module (36) into host computer (2) and is shown in man machine operation interface (38).
The host computer (2) is communicated by usb interface module (36) with fpga chip (1), and host computer (2) is passed through
Processing and data operation realize setting network parameter and model parameter in man machine operation interface (38) and pass through USB interface mould
Block (36) passes to the facilities in man machine operation interface (38) fpga chip (1) by each data transmission path, real
Existing human-computer interaction.
The modeling of the Spiking feedforward network hippocampus function based on FPGA may be implemented in analogue system provided by the invention,
Devise have both visualization and can operationalization man machine operation interface, make system flexibility with higher and exploitativeness, energy
The enough emulation completed in appropriate time scale to the mathematical model of biological neuron；In addition, the analogue system passes through building
Three layers of feedforward network realize the research to hippocampal neural meta function, visual platform are provided, to the research hippocampus of deeper
Neuron, research hippocampal neuron control mechanical arm and control unmanned vehicle etc. have important practical value.The present invention is based on
The FPGA that parallel high-speed calculates realizes Spiking feedforward network hippocampus function, is a kind of test method of no animal, proposes base
In the Spiking feedforward network hippocampus function emulation system of FPGA, with following advantage: 1, designed simulation hardware
The mathematical model of model application biological neuron can be kept in time scale and the consistency of true biological neuron, wherein
The maximum operation frequency of fpga chip is 200MHz, and concurrent operation can guarantee that the frequency for exporting film potential within 1 millisecond, expires
Requirement of the neuron to time scale under sufficient truth, for study hippocampal neuron function provide it is more convenient, quick
Simulating experimental system；2, in this analogue system, the scale of network and the parameter of network model can pass through man-machine behaviour
It modifies and configures as interface, the characteristic for meeting computer user's operation interface and experimental facilities being configured；3, people
The cynapse power for observing the discharge scenario of every layer of neuron, the accuracy of network simulation and interlayer in real time may be implemented in machine operation interface
Value information can obtain amplitude and the discharge time of Neural spike train, and the same of its electric discharge can also be analyzed between every layer of neuron
Step property, while the stability of network can also be observed by replacement noise model, this analogue system can also store data just
In the progress of subsequent data analysis work, better visualized experiment research platform is provided for research hippocampal neural meta function.
Detailed description of the invention
Fig. 1 is experimental platform system structural schematic diagram of the invention；
Fig. 2 is LIF stream of neuron waterline model；
Fig. 3 is that synaptic weight calculates pipeline model；
Fig. 4 is man machine operation interface I schematic diagram of the invention；
Fig. 5 is man machine operation interface II schematic diagram of the invention；
Fig. 6 is man machine operation interface III schematic diagram of the invention.
In figure:
2. host computer of 1.FPGA development board, 3. feed forward neural metanetwork, 4. 3 layers of 5. initial value signal of feedforward network issue module
6. the movement output layer 9.LIF neuron flowing water of 8. feedforward network of hippocampus functional layer for experiencing 7. feedforward network of layer of feedforward network
The mathematical model 12.LIF neuron models spike potential constant 13.LIF of 10. initial value stimulus signal 11.LIF neuron of line model
15. multichannel data comparator of neuron models threshold potential constant 14.LIF neuron models resting potential constant, 16. noise letter
Number 17. time delay processes 18. experience 19. hippocampus functional layer signal transmission pathway 20. of layer signal transmission channel movement output layer signal
Transmission channel 21. judges that control module 22. judges that 23. cynapse of control module output signal control updates matrix (synaptic weight meter
Calculate pipeline model) 24.LIF discharge time neuron models postsynaptic discharge time 25.LIF in neuron models presynaptic 26.
29. signal of the constant transmission that 27. synaptic weight mathematical model 28. of multichannel data comparator characterizes neuron models learning efficiency is logical
30. network output signal transmission channel of road, 31. network film potential signal transmission pathway has 32. alternative data selectors 33. letter
Number soft 35. signal transmission pathway 36.USB interface module of nuclear control device, 37. signal transmission pathway 38. of transmission channel 34.NiosII
41. curve display interface of human-computer interaction interface 39. man machine operation interface I, 40. tabs, 42. neuron selection operation frame 43. ginseng
General 44. interface basic operation frame of setting frame, the 45. man machine operation interface II 46. of number emulates 47. people of accuracy curve display interface
48. interface rolling motion item of machine operation interface III, 49. synaptic weight display interface
Specific embodiment
The Spiking feedforward network hippocampus function emulation system to of the invention based on FPGA is said with reference to the accompanying drawing
It is bright
The design philosophy of Spiking feedforward network hippocampus function emulation system based on FPGA of the invention is to exist first
LIF (leaky integrate-and-fire) single neuron model is built on fpga chip, and then builds three layers of feedforward net
Then network model is realized and judges control module, and connect feed-forward network model and cynapse control update matrix as bridge, with
On module be all made of Verilog HDL language realize correlation function, judge control module can complete to Neural spike train believe
Number and the transmitting of synaptic weight also can control the update of synaptic weight simultaneously and be achieved in complete Spiking feedforward network
Model；It then, can according to the corresponding operating of man machine operation interface using NiosII soft-core processor as the core of hardware controls
To realize that the extraction to data is transmitted, while NiosII soft-core processor is also used as host computer to exchange with what slave computer data were transmitted
Center；Upper computer software interface is finally designed, upper computer software interface is by setting network parameter and model parameter and is transmitted to
Fpga chip is realized to the key parameter of network model and the configuration of noise signal, can replace feedforward net by option window
The number of plies of network and the accuracy for observing network simulation, while cynapse can also be controlled on the data value updated in matrix module
It reaches in host computer, discharge waveform and the different moments of each neuron can be shown in the man machine operation interface of host computer
Film potential, the synaptic weight of passback can also be observed and check the accuracy rate of network simulation by waveform.Party's needle system
It is made of a piece of fpga chip and host computer, wherein FPGA portion is for realizing three layers of feed-forward network model (including neuron mould
Type and synaptic weight more new model based on STDP rule), epigynous computer section is for designing man machine operation interface and passing through USB
Interface module realizes the communication with FPGA development board.
The LIF neuron models and synaptic weight transformation model are all made of Euler method in FPGA and carry out discretization,
Then it is built using pipelining, parallel computation is carried out to model equation, the essence of assembly line thought is to utilize delay deposit
Device makes mathematical model be divided into several sub- calculating processes, and within each clock cycle, every sub- calculating process can carry out mind simultaneously
Operation through meta-model in different moments, model data upload in host computer interface in time, and transmit with clock.In the network
In model, the parameter setting of LIF neuron models and synaptic weight variation model can be modified by man machine operation interface.
The man machine operation interface is programmed using C Plus Plus and is realized, develops window interfaces by MFC, software platform is
Micro Visual Studio2010, man machine operation interface are able to achieve real time data extraction, analysis and waveform display function.
Spiking feedforward network hippocampus function emulation system based on FPGA of the invention is by fpga chip interconnected
1 and host computer 2 form.Wherein FPGA is used to realize the feedforward network with hippocampal neural meta function, and host computer 2 is for designing
Man machine operation interface 38 simultaneously realizes the data communication with fpga chip 1 by usb interface module 36, is illustrated below:
As shown in Figure 1, being designed to hardware platform, fpga chip used is using altera corp's production
StratixIIIEP3SE260F1152C2 chip, according to the mathematical model of neuron and synaptic weight model, using Euler method into
Row discretization simultaneously builds LIF stream of neuron waterline model 9 and synaptic weight pipeline model 23, in a network each neuron mould
Type is all identical, the difference is that the presence or absence of noise signal and input stimulus signal, are that rule judges signal according to the victor is a king here
Whether it is applied on neuron models, and the regular second layer and only one each mind of third layer neuron according to the victor is a king
It is discharging through member, by the way that membrane potential of neurons compared with several constants, to be constructed to the network mould with hippocampal neural meta function
Type.Data transmission path 37 receives the setting of man machine operation interface 38, and data information is passed in hardware system, synaptic weight
The film potential signal 30 and 31 of signal 29 and neuron by data transmission path 37 reach in host computer 2 for operator into
Row data and waveform analysis.LIF stream of neuron waterline model 9 and all data paths of synaptic weight pipeline model 23 are being united
With stepping row under one clock, and the conversion that QuartusII software realization hardware description language is passed through according to the structure of FPGA.
LIF stream of neuron waterline model 9 as shown in Figure 2 is mainly made of multiplier, comparator and adder, described
The mathematical model of LIF stream of neuron waterline model 9 are as follows:
If V >=Vpeak, then V=Vrest
If V >=Vth, then V=Vpeak
Wherein in model expression, I indicates that input current, V represent the membrane potential of neurons fast variable driven by I, Gl
The conductance in leakage channel is represented, C indicates membrane capacitance value, and η represents noise inputs, VrestThe resting potential for representing neuron is constant,
VthIt is the threshold potential constant of neuron, VpeakIt is the spike potential constant of neuron.The model includes the assembly line of variable V,
Neuron computation delay link 17 is used to increase the handling capacity of system.LIF stream of neuron waterline model 9, which receives, comes from human-machine operation
The parameter that interface 38 is arranged meets the requirement under different experiments to LIF neuron models by changing parameter；Noise signal 16
The type of its signal can be changed by man machine operation interface 38；Every layer of neuron is used with lower layer's neuron and is connect entirely, i.e.,
The output signal for experiencing layer neuron can be transmitted to each neuron of hippocampus layer, and hippocampus layer output signal can also be transmitted to movement layer
Each neuron.LIF stream of neuron waterline model 9 shown in Fig. 2 by the mathematical model of LIF neuron by Euler method carry out from
Dispersion, what following formula indicated is the process of discretization, consistent with LIF stream of neuron waterline model 9 represented by Fig. 2.
It is illustrated in figure 3 the synaptic weight based on STDP rule and calculates pipeline model 23 mainly by multiplier, comparator
It is constituted with adder, the synaptic weight calculates the mathematical model of pipeline model 23 are as follows:
Wherein in model expression, τ+Indicate that discharge time in presynaptic is ahead of postsynaptic discharge time constant, τ-It indicates
Discharge time in presynaptic lags behind postsynaptic discharge time constant, A+It is normal to indicate that presynaptic electric discharge is ahead of postsynaptic electric discharge amplitude
Amount, A-Indicate presynaptic discharge lag in postsynaptic electric discharge amplitude constant, wminIndicate synaptic weight minimal stimulation constant, wmaxTable
Show synaptic weight maximal stimulation constant, τwIt is the constant for indicating learning rate, Δ indicates that discharge time in presynaptic 24 puts with the postsynaptic
The difference of electric time 25, cynapse control update matrix 23 under the coordination for judging control module 21, obtain network of relation parameter value
And the change to synaptic weight is realized according to above formula, the weight after change is output to host computer by alternative data selector 32
In 2；The model parameter can also be modified and be arranged by man machine operation interface 38 simultaneously.Time delay process in the model
It is the handling capacity for increasing system.Equally, it makes explanations to the pipeline model of Fig. 3: i.e. by the change to its mathematical model
Shape is shown below, and carries out sliding-model control using Euler method.
The instruction that the control work of system is mainly inputted by NiosII soft-core processor 34 according to man machine operation interface 38 is complete
At, the initial value signal of system generates stimulus signal by initial value signal module 5 in first time simulation process and is transmitted to feedforward network 4,
Stimulation is provided by the signal 10 of network output passback in subsequent emulation.Judge that control module 21 receives the film electricity from every layer
Position output and discharge time export and pass through signal transmission pathway 31 and discharge information is transmitted to NiosII soft-core processor 34, lead to
It crosses corresponding calculation processing and signal is transmitted to the cynapse control update update connection weight of matrix 23, cynapse control updates matrix 23 will
Signal is transmitted to alternative data selector 32 and data information is back to host computer 2, and information above is in man machine operation interface 38
Middle display.
Man machine operation interface 38 mainly includes six tabss, man machine operation interface I 39,45 He of man machine operation interface II
Man machine operation interface III 47 designs man machine operation interface 38 in host computer 2 with C++ programming forms, and fpga chip passes through
1 is worked by the realization of usb interface module 36 and the data communication of host computer 2, and man machine operation interface 38 passes through usb interface module 36
Receive the data transmitted from fpga chip 1；Man machine operation interface 38 is by setting network parameter and model parameter via USB interface
Data are transmitted to fpga chip 1 and realize man-machine interaction by module 36.C++ is visual, object-oriented, by event driven
High-level programming language, uses Mutli-thread Programming Technology when programming using Labview, which has had both graph curve and shown
With the function of data processing, guarantee that data can carry out continuous acquisition.
Man machine operation interface I 39 is as shown in Figure 4: it includes tabs 40, curve display interface 41, neuron selection behaviour
Make the general setting frame 43 of frame 42, parameter and interface basic operation frame 44: tabs 40 includes to each layer of Neural spike train waveform
Display, the waveform of emulation accuracy is shown and is shown to the data of synaptic weight between different layers, totally six tabss.It is bent
Line display interface 41 is mainly used for showing the waveform of membrane potential of neurons variation, by neuron choice box 42 to neuron label
The situation of change of each Neural spike train waveform can be observed by carrying out selection.The general setting frame 43 of parameter is used to show the master of network
Parameter is wanted, and parameter can be modified, fpga chip 1 is returned to by usb interface module 36.Interface basic operation frame 44 includes
The basic control instructions such as beginning, stopping, refreshing, analysis, realize the control to network start and stop.
People and operation interface II 45 are as shown in Figure 5: switching to emulation accuracy assay surface by tabs 40, pass through
The analysis to network simulation authenticity may be implemented in observation emulation accuracy curve display interface 46, and then mentions by adjusting parameter
The accuracy of high network simulation.
Man machine operation interface III47 is as shown in Figure 6: synaptic weight display interface is switched to by tabs 40, wherein dashing forward
The synaptic weight experienced between layer neuron and hippocampus layer neuron is shown in touching 1 tabs of weight, and similarly synaptic weight 2 selects
Synaptic weight between item card display hippocampus layer and movement layer, can be observed between neuron by synaptic weight display interface 49
Synaptic weight variation, while more weight datas can be observed by the horizontal and vertical scroll bar 48 at interface.
FPGA emulation platform
Neural network model based on discrete, fixed step size fixed-point number operation is write by Verilog HDL language
With the synaptic weight model based on STDP rule, go forward side by side through QuartusII software programming complete operation logic and program structure
Row compiling, analysis integrated, placement-and-routing are downloaded in FPGA development board and run.The data that operation generates in FPGA development board
The Spiking feedforward network hippocampus function system based on FPGA is divided in the man machine operation interface write by C Plus Plus
Analysis and research.
Claims (6)
1. a kind of Spiking feedforward network hippocampus function emulation system based on FPGA, it is characterized in that: the analogue system includes
FPGA development board (1), host computer (2), the FPGA development board (1) include feed forward neural metanetwork (3), the soft core control of NiosII
Device (34) processed and usb interface module (36), feed forward neural metanetwork (3) therein include being compiled by VHDL language program downloads
The three layers of feedforward network (4) for simulating hippocampal neural meta function translated and run in FPGA development board (1), initial value signal issue mould
Block (5), network first layer experience layer (6), second layer hippocampus functional layer (7), third layer movement output layer (8), LIF i.e.
Leaky-integrate and Fire stream of neuron waterline model (9) judges control module (21), STDP i.e. Spiking-
Timing Dependent Plasticity cynapse control updates matrix (23)；LIF neuron flowing water in each layer feedforward network
Line model (9) judges that control module (21) and STDP synapse turnover matrix (23) are all made of VHDL language programming and realize；Judgement control
Molding block (21) is responsible for the control exported to every layer signal, and the control signal issued passes through respectively experiences layer signal transmission channel
(18), hippocampus functional layer signal transmission pathway (19) and movement output layer signal transmission pathway (20) pass to every layer of nerve
Member；With the progress of emulation, judges that control module (21) obtain the synaptic weight of each layer and pass it to cynapse control and update
Matrix (23), cynapse control update matrix (23) and are advised according to the variation of the signal behavior weight issued by judgement control module (21)
Then, corresponding matrix value can become larger if LTP, that is, Long-term Potentiation is selected, if LTD, that is, Long-term
Depression is selected, and corresponding matrix value can reduce, by each neuron of this new mechanism to another nerve
The weight of member, the weight of the update by signal transmission pathway (22) and can judge that control module (21) is returned to every layer of nerve
Member；It acts output layer (8) and the output result of network is transmitted to by NiosII soft-core processor (34) by signal transmission pathway (30),
The processor, which is also received, simultaneously obtains the real-time weight variation of network from alternative data selector (32) selected signal
Information；Host computer (2) is programmed by C++ and realizes man machine operation interface (38), and usb interface module (36) and fpga chip are passed through
(1) it is communicated, the data by communicating network model obtained are further processed in host computer (2)；Imitative
The true incipient stage generates stimulus signal by initial value signal module (5) and passes it to the impression layer (6) of network, then by feeling
Data are transmitted to by layer signal transmission channel (18) and judge control module (21), are by judging control module (21) according to victor
King's rule calculates, i.e., experiences row vector and synaptic weight of the film potential of layer (6) with resting potential work after poor by certain
Matrix does multiplying row vector obtained and its next layer, i.e. the film potential of hippocampus functional layer (7) and resting potential is made poor
Row vector and synaptic weight matrix later does multiplying and makees difference and maximizing to row vector obtained, then in hippocampus function
In ergosphere (7), neuron corresponding to the maximum value obtains stimulus signal, while other neurons of this layer do not obtain stimulation letter
Number, the rule is shown as the following formula, wherein VrestIt is constant, V for neuron resting potentialiFor every layer of i-th of neuron
Film potential, IkFor stimulated current signal,Excitatory synapse weight between i-th and jth layer,For i-th with jth layer it
Between inhibitory synapse weight, l indicates different layers, and respectively information experiences layer, hippocampus functional layer and movement output layer, j table
Show l layers some neuron, acquires the value of j corresponding to the maximum value inside braces according to the following formula, it then will thorn
Swash current signal IkIt is assigned to the neuron, regular according to the victor is a king, other neurons of this layer mustn't go to stimulated current to believe
Number:
It is calculated according to above formula and corresponding stimulation is generated to some neuron of the second layer hippocampus functional layer (7) of network, in hippocampus
Result is transmitted to by signal transmission pathway (19) after being calculated in functional layer (7) according to LIF stream of neuron waterline model (9) and is sentenced
Disconnected control module (21), then again by judging that the calculating of control module (21) is generated to movement output layer (8) some neuron
Stimulation, then calculated also according to LIF stream of neuron waterline model (9) in movement output layer (8) and pass through signal
Transmission channel (20), which is transmitted to, judges control module (21), experiences layer signal transmission channel (18), the transmission of hippocampus function layer signal is led to
Data are transmitted to after judging control module (21) by road (19), movement output layer signal transmission pathway (20) every time, judge to control
Module (21) all can update matrix (23) progress right value update appropriate to the cynapse control of different layers according to STDP rule and lead to
It crosses data selector (32) to return to value information host computer (2), while the Neural spike train information of network passes through USB interface
Module (36) returns to host computer (2), and in simulation process later, initial value signal is provided by movement output layer (8), makes network
It is able to continuous operation.
2. the Spiking feedforward network hippocampus function emulation system based on FPGA according to claim 1, it is characterized in that: institute
It states and judges that control module (21) obtain each layer membrane potential of neurons value and carry out corresponding judgement and calculate, will judge that signal exports
It is controlled to cynapse and updates matrix (23), while the updated neuron weight for obtaining cynapse control update matrix (23) is emulating
During together with the output signal of feed forward neural metanetwork (3) each layer as judgement control foundation, the module by with
Feed forward neural metanetwork (3) and cynapse control update matrix (23) two-way interconnection, realize the communication of information, with being capable of preferably mould
The function of quasi- hippocampal neuron.
3. the Spiking feedforward network hippocampus function emulation system based on FPGA according to claim 1, it is characterized in that: institute
It states cynapse control update matrix (23) and comes from the control signal for judging control module (21) according to STDP rule to mind by receiving
Connection weight through member carries out calculating update, and calculated result is returned to and is judged control module (21), while being passed by data
Defeated access (29) is transmitted to data selector (31) and is analyzed for host computer (2) and judged and shown in man machine operation interface (38)
Show corresponding weight.
4. the Spiking feedforward network hippocampus function emulation system based on FPGA according to claim 1, it is characterized in that: institute
It states NiosII soft-core processor (34) and control is realized to entire analogue system by FPGA development board (1)；The soft core processing of NiosII
Device (34) one side receives the signal of the movement output layer (8) in feed forward neural metanetwork (3), on the other hand selects again with two
One data selector (32) is connected, and is controlled data selector (32) and obtains the cynapse exported by data selector (32)
Weight.Corresponding information obtained is transmitted to host computer (2) by usb interface module (36), passes through data transmission path (37)
The input to FPGA development board (1) may be implemented in the information of man machine operation interface (38) output.
5. the Spiking feedforward network hippocampus function emulation system based on FPGA according to claim 1, it is characterized in that: institute
It states alternative data selector (32) reception and respectively represents three layers from the two-way weight signal that cynapse control updates matrix (23)
Synaptic weight between any two；The command selection transmitted according to NiosII soft-core processor (34) signal and is passed through all the way
Usb interface module (36) output display into host computer (2) and in man machine operation interface (38).
6. the Spiking feedforward network hippocampus function emulation system based on FPGA according to claim 1, it is characterized in that: institute
It states host computer (2) to be communicated by usb interface module (36) with fpga chip (1), passes through the processing and data of host computer (2)
Operation realizes setting network parameter and model parameter in man machine operation interface (38) and passes through usb interface module (36) for people
Facilities in machine operation interface (38) are passed to fpga chip (1) by each data transmission path, realize human-computer interaction.
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