KR20170080473A - Neuromorphic device - Google Patents

Abstract

A nyomorphic device is provided. According to an aspect of the present invention, there is provided a neuromodule apparatus comprising: a plurality of row lines extending in a first direction; A plurality of additional row wirings extending in the first direction; A plurality of column lines extending in a second direction intersecting the first direction; And a synapse located at an intersection area of the row wiring, the additional row wiring, and the column wiring, wherein the synapse has a floating gate, the control gate insulated from the floating gate is connected to the row wiring, 1 junction is connected to the additional row wiring, and a second junction is connected to the column wiring.

Description

NEUROMORPHIC DEVICE}

This patent document relates to a neuromotor apparatus for simulating a human nervous system and their applications.

BACKGROUND ART In recent years, there has been a demand for a technology capable of efficiently processing a large amount of information in accordance with miniaturization, low power consumption, high performance, and diversification of electronic devices. In particular, there is growing interest in neuromorphic technology, which simulates the human nervous system. There are hundreds of billions of neurons in the human nervous system and synapses that are the junctions between neurons. In the neuromotor technology, we try to implement a neuromotor device by designing neuron circuits and synapse circuits corresponding to these neurons and synapses, respectively. The NyomopliK device can be used in various fields such as data classification and pattern recognition.

A problem to be solved by the embodiments of the present invention is to provide a novel Lomographic device capable of improving the accuracy of learning and recognition.

According to an aspect of the present invention, there is provided a neuromodule apparatus including: a plurality of row lines extending in a first direction; A plurality of additional row wirings extending in the first direction; A plurality of column lines extending in a second direction intersecting the first direction; And a synapse located at an intersection area of the row wiring, the additional row wiring, and the column wiring, wherein the synapse has a floating gate, the control gate insulated from the floating gate is connected to the row wiring, 1 junction is connected to the additional row wiring, and a second junction is connected to the column wiring.

In the up-neuromotor apparatus, a voltage pulse corresponding to specific data may be applied to the plurality of row wirings. The transistor may have a decreasing threshold voltage when a predetermined charge is trapped in the floating gate. The amount of charge trapped in the floating gate may increase as the number of voltage pulses increases. The threshold voltage of the transistor may decrease as the number of voltage pulses increases. The current flow between the first junction and the second junction may increase as the number of voltage pulses increases. A voltage having the same polarity as the voltage pulse may be applied to the plurality of additional row wirings. The voltage applied to the plurality of additional row wirings may have the same magnitude as the voltage pulse. Different data can be learned in each of the plurality of column wirings. In the process of learning the specific data to the first column wiring among the plurality of column wirings, the second column wiring that has been learned may be in a floating state.

According to another aspect of the present invention, there is provided a neurometric device comprising: a substrate; A lower wiring located on the substrate and extending in a first direction; An upper wiring located on the lower wiring and extending in a second direction intersecting with the first direction; A semiconductor column located between the lower wiring and the upper wiring at a crossing region of the lower wiring and the upper wiring; A tunnel insulating film, a floating gate, and a charge blocking film sequentially surrounding side surfaces of the semiconductor pillars; And a control gate extending in the first direction or the second direction while surrounding the side surface of the charge blocking film, wherein the semiconductor column, the tunnel insulating film, the floating gate, the charge blocking film, .

In the up-neuromotor apparatus, a voltage pulse corresponding to specific data may be applied to the control gate. The synapse may have a decreasing threshold voltage when a predetermined charge is trapped in the floating gate. The amount of charge trapped in the floating gate may increase as the number of voltage pulses increases. The threshold voltage of the synapse may decrease as the number of voltage pulses increases. Current flow through the semiconductor pillars may increase as the number of voltage pulses increases. A voltage having the same polarity as the voltage pulse may be applied to either the lower wiring or the upper wiring. The voltage applied to any one of the lower wiring and the upper wiring may have the same magnitude as the voltage pulse. Specific data may be stored in another one of the lower wiring and the upper wiring. And a first junction region located between the lower wiring and the semiconductor column and overlapping the lower wiring. And a second junction region formed on the semiconductor column and connected to the upper wiring.

According to the embodiments of the present invention described above, it is possible to improve the accuracy of learning and recognition of the neuromotor device.

FIG. 1A is a diagram showing a neuromotor apparatus of a comparative example, and FIGS. 1B and 1C are views for explaining an example of a method of operating the neuromotor apparatus of FIG. 1A.
FIG. 2A is a diagram illustrating a neuromotor apparatus according to an embodiment of the present invention, and FIGS. 2B and 2C are views for explaining an example of a method of operating the neuromotor apparatus of FIG. 2A.
FIG. 3 is a view for explaining a threshold voltage reduction mechanism of the transistors of FIGS. 2A to 2C. Referring to FIG.
4A to 4D are views for explaining an example of a learning process of the neuromorphic device according to an embodiment of the present invention in more detail.
FIG. 5 is a perspective view for explaining an example of a synapse of a nyombol pick apparatus according to an embodiment of the present invention.
6A to 9B are views for explaining a method of manufacturing a nyombol picking apparatus according to an embodiment of the present invention.
10 is an example of a pattern recognition system according to an embodiment of the present invention.

In the following, various embodiments are described in detail with reference to the accompanying drawings.

The drawings are not necessarily drawn to scale, and in some instances, proportions of at least some of the structures shown in the figures may be exaggerated to clearly show features of the embodiments. When a multi-layer structure having two or more layers is disclosed in the drawings or the detailed description, the relative positional relationship or arrangement order of the layers as shown is only a specific example and the present invention is not limited thereto. The order of relationships and arrangements may vary. In addition, a drawing or a detailed description of a multi-layer structure may not reflect all layers present in a particular multi-layer structure (e.g., there may be more than one additional layer between the two layers shown). For example, if the first layer is on the substrate or in the multilayer structure of the drawings or the detailed description, the first layer may be formed directly on the second layer or may be formed directly on the substrate As well as the case where more than one other layer is present between the first layer and the second layer or between the first layer and the substrate.

Prior to the description of this embodiment, a description will be given of the neurometer apparatus of the comparative example, its operation method, and its problems.

FIG. 1A is a diagram showing a neuromotor apparatus of a comparative example, and FIGS. 1B and 1C are views for explaining an example of a method of operating the neuromotor apparatus of FIG. 1A.

1A, a neuromotry device according to one embodiment of the present invention includes a plurality of presynaptic neurons 10, a plurality of postsynaptic neurons 20, and a plurality of presynaptic neurons 10) and a plurality of post-synaptic neurons 20, respectively.

The neuromotry apparatus of the present embodiment includes four pre-synaptic neurons 10, four post-synaptic neurons 20, and sixteen synapses 30, but these numbers can be variously modified. Wherein the number of presynaptic neurons 10 is N (where N is a natural number of 2 or more), the number of post-synaptic neurons 20 is M (where M is a natural number of 2 or more, ), The N * M synapses 30 may be arranged in a matrix form. To this end, a wiring 12 connected to each of the plurality of pre-synaptic neurons 10 and extending in a first direction, for example, in the transverse direction, and a plurality of post-synaptic neurons 20 connected to each of the plurality of post- A wiring 22 extending in two directions, for example, a longitudinal direction, may be provided. Hereinafter, for convenience of explanation, the wiring 12 extending in the first direction is referred to as a row line, and the wiring 22 extending in the second direction is referred to as a column line. A plurality of synapses 30 may be arranged at each intersection of the row wiring 12 and the column wiring 22 to connect the corresponding row wiring 12 and the corresponding column wiring 22 to each other.

The pre-synaptic neuron 10 generates a signal corresponding to a specific data, for example, and sends it to the row wiring 12. The post-synaptic neuron 20 transmits a synaptic signal through the synapse element 30 to the column wiring 12. [ And receive and process the data through the network 22. The row wiring 12 corresponds to the axon of the presynaptic neuron 10 and the column wiring 22 corresponds to the dendrite of the post synaptic neuron 20. However, whether it is a pre-synaptic neuron or a post-synaptic neuron can be determined by its relative relationship with other neurons. For example, a presynaptic neuron 10 may function as a post-synaptic neuron if it receives a synaptic signal in relation to another neuron. Similarly, post-synaptic neurons 20 can function as presynaptic neurons when they send signals in relation to other neurons. The pre-synaptic neuron 10 and the post-synaptic neuron 20 may be implemented with various circuits such as CMOS.

The connection between the presynaptic neuron 10 and the post-synaptic neuron 20 may be via the synapse 30. Here, the synapse 30 is an element whose electrical conductance or weight changes in accordance with an electric pulse applied to both ends, for example, a voltage or a current.

The synapse 30 may comprise, for example, a variable resistive element. The variable resistive element is an element that can switch between different resistance states depending on the voltage or current applied to both ends. The variable resistive element includes various materials capable of having a plurality of resistance states, such as a transition metal oxide, a perovskite system And may have a single-layer structure or a multi-layer structure including a phase-change material such as a metal oxide such as a material, a chalcogenide-based material, a ferroelectric material, a ferromagnetic material and the like. The operation in which the variable resistance element and / or the synapse 30 changes from the high resistance state to the low resistance state is referred to as a set operation and the operation in which the resistance state changes from the low resistance state to the high resistance state is referred to as a reset operation .

However, unlike the variable resistive element used in the memory device such as the RRAM, the PRAM, the FRAM and the MRAM, the synapse 30 of the neuromodule device has no abrupt resistance change in the set operation and the reset operation, It can be implemented to have various characteristics that distinguish it from the variable resistance element in the memory, such as showing analog behavior in which the conductivity gradually changes according to the number of electric pulses. This is because the characteristics required for the variable resistive element in the memory and the characteristics required for the synapse 30 in the neuromotor device are different from each other. For reference, it is preferable that the variable resistive element used in the memory maintains its conductivity before the set operation or the reset operation is performed even if the electric pulse is repeatedly applied. That is, the variable resistance element in the low resistance state can maintain its low resistance value even if the electric pulse is repeatedly applied, and the variable element in the high resistance state can maintain its high resistance value even if the electric pulse is repeatedly applied . To distinguish between the low-resistance state and the high-resistance state, thereby storing different data. On the other hand, the synapse 30 suitable for a neuromotor device can be gradually increased when an electrical pulse having a magnitude equal to or greater than a set voltage and repeatedly applied to the synapse 30 is set to a low resistance state by a set operation, When the electric pulse having a magnitude equal to or greater than the reset voltage and having the same polarity is repeatedly applied after being in the high resistance state, the conductivity may gradually decrease. Even in this case, the conductivity of the synapse 30 may not be varied if an electrical pulse having a magnitude less than the set voltage and / or the reset voltage is applied.

The learning operation of the neurometer apparatus will be described below with reference to FIGS. 1B and 1C. The row wiring 12 may be referred to as a first row wiring 12A, a second row wiring 12B, a third row wiring 12C and a fourth row wiring 12D from the top in order And the column wiring 22 may be referred to as a first column wiring 22A, a second column wiring 22B, a third column wiring 22C and a fourth column wiring 22D in this order from the left.

First, referring to FIG. 1B, in the initial state, all of the synapses 30 may be in a state in which the conductivity is relatively low, that is, in a high resistance state. If at least some of the plurality of synapses 30 are in a low resistance state, an initialization operation may be further required to bring them into a high resistance state. Each of the plurality of synapses 30 may have a predetermined threshold value required for resistance and / or conductivity variation. More specifically, when a voltage or current of a magnitude smaller than a predetermined threshold value is applied to both ends of each synapse 30, the conductivity of the synapse 30 does not change and a voltage or current larger than a predetermined threshold value is applied to the synapse 30 The conductivity of the synapse 30 may change.

In this state, in order to perform the operation of learning the specific data to the specific column wiring 22, an input signal corresponding to the specific data corresponding to the output of the pre-synaptic circuit 10 may enter the row wiring 12 . At this time, the input signal may appear as an application of an electrical pulse to each of the row wirings 12. For example, when an input signal corresponding to data of '0011' is input to the row wiring 12, an electric pulse is applied to the row wiring 12 corresponding to '0', such as the first and second row wirings 12A and 12B Electric pulses may be applied only to the row wiring 12 corresponding to '1', for example, the third and fourth row wirings 12C and 12D. At this time, the column wiring 22 may be driven with appropriate voltage or current for learning.

For example, when the column wiring 22 to learn specific data is already determined, the column wiring 22 has a synapse 30 positioned at the intersection with the row wiring 12 corresponding to '1' The remaining column wirings 22 can be driven so that the remaining synapses 30 are supplied with a voltage smaller than the set voltage. For example, when the set voltage level is Vset and the column wiring 22 to learn the data of '0011' is defined as the third column wiring 22C, the third column wiring 22C and the third and fourth rows The magnitudes of the electric pulses applied to the third and fourth row wirings 12C and 12D are set such that the first and second synapses 30A and 30B located at the intersections with the wirings 12C and 12D receive a voltage equal to or greater than Vset. May be equal to or greater than Vset, and the voltage applied to the third column wiring 22C may be 0V. Accordingly, the first and second synapses 30A and 30B can be in a low resistance state. The conductivity of the first and second synapses 30A and 30B in the low resistance state can be gradually increased as the number of electrical pulses increases. The magnitude and width of the applied electrical pulse may be substantially constant. The remaining synapses 30 except for the first and second synapses 30A and 30B are connected to the remaining column wirings, that is, the first, second and fourth column wirings 22A, 22B and 22D, The applied voltage may have a value between 0 V and Vset, for example, 1/2 Vset. Accordingly, the resistance state of the remaining synapses 30 except for the first and second synapses 30A and 30B may not change. The flow of current or electrons in this case is indicated by the dotted arrow.

As another example, the column wiring 22 to learn specific data may not be defined. In this case, the electric current corresponding to the specific data is applied to the row interconnection 12 while measuring the electric current flowing through each of the column interconnection 22, and the column interconnection 22, for example, the third column interconnection 22, The column wiring 22C can learn the specific data.

According to the above-described method, different data can be learned in different column wirings 22, respectively.

In any case, when the learning is terminated, the previously learned column wiring 22, for example, the third column wiring 22C, can be floated. And to allow the other column wiring 22 to learn other data. 1C shows a case where other data is learned in the other column wiring 22 in a state in which the third column wiring 22C is floated. For example, when data of '0110' is learned in the fourth column wiring 22D .

Referring to FIG. 1C, the row wiring 12 and the column wiring 22 are driven in a manner similar to that described above, so that data of '0110' can be learned in the fourth column wiring 22D.

In other words, as an example, the third and fourth synapses 30C and 30D located at the intersections of the fourth column wiring 22D and the second and third row wiring 12B and 12C are supplied with a voltage equal to or greater than Vset, An electrical pulse having a magnitude of Vset or more may be applied to the second and third row wirings 12B and 12C and 0V may be applied to the fourth column wiring 22D. Accordingly, the third and fourth synapses 30C and 30D can be in a low resistance state. The conductivity of the third and fourth synapses 30A and 30B in the low resistance state can be gradually increased as the number of electrical pulses increases. Electricpulses are not applied to the first and fourth row wirings 12A and 12D so that voltages lower than Vset are applied to the remaining synapses 30 except for the third and fourth synapses 30C and 30D, A voltage of 1/2 Vset may be applied to the second column wirings 22A and 22B. As described above, the third column wiring 22C may be in a floating state. The flow of current or electrons in this case is indicated by the dotted arrow.

However, since the third column wiring 22C thus learned is in a floating state, it has a potential larger than 0 V and lower than Vset. As a result, in the process of learning the fourth column wiring 22D due to the potential of the third column wiring 22C, a leakage current or an electron flow as indicated by a solid line arrow may occur. Particularly, since the first and second synapses 30A and 30B have changed to the low resistance state during the learning process of the third column wiring 22C, a leakage current or an electron flow can be generated through them.

Since this leakage current increases the current flowing through the fourth column wiring 22D, it can be judged that the current flowing through the fourth column wiring 22D reaches a predetermined threshold current before the fourth column wiring 22D is learned . In other words, an error may occur that the current flowing in the fourth column wiring 22D is over-estimated and the untrained fourth column wiring 22D is recognized as being learned. This error can occur more as the number of the column wirings 22 to be learned and floated increases, and as the size of the array including the row wirings 12 and the column wirings 22 increases.

In order to solve the above learning error, it may be considered to use a transistor for controlling connection to a variable resistance element together with a variable resistance element as a synapse. That is, each synapse may include a variable resistance element and a transistor connected thereto. However, since the transistor is not only fabricated using a semiconductor substrate but also occupies a large area, it may interfere with an increase in integration of a neuromodule device. At present, no other access elements other than transistors have been developed.

In this embodiment, it is intended to provide a new novel Lomographic apparatus and an operation method thereof that can increase the degree of integration of a neuromorphic apparatus while preventing learning errors caused by leakage currents.

FIG. 2A is a diagram illustrating a neuromotor apparatus according to an embodiment of the present invention, and FIGS. 2B and 2C are views for explaining an example of a method of operating the neuromotor apparatus of FIG. 2A.

Referring to FIG. 2A, the ny Lomopol apparatus of the present embodiment includes a plurality of row wirings 120 and a plurality of additional row wirings 420 extending in a first direction, for example, a lateral direction, A plurality of column wirings 220 extending in a direction such as a longitudinal direction and synapses arranged at the intersections of the row wirings 120 and the additional row wirings 420 and the column wirings 220. [

Here, each of the synapses may include a transistor 300 having a floating gate and a control gate electrically separated from the floating gate. That is, each of the synapses may have a one-transistor structure. Here, the control gate of the transistor 300 may be connected to the row wiring 120, and the two junctions of the transistor 300 may be connected to the additional row wiring 420 and the column wiring 220, respectively. As an example, the drain of the transistor 300 may be connected to the additional row wiring 420 and the source of the transistor 300 may be connected to the column wiring 220, and vice versa.

A circuit for appropriately driving these wirings may be connected to one end of each of the row wiring 120, the additional row wiring 420, and the column wiring 220. As an example, the plurality of row wirings 120 may be connected to the control gate of the transistor 300, respectively, and connected to the pre-synaptic neuron 100 for transferring signals corresponding to specific data thereto, The wiring 420 may be connected to a drain voltage application circuit 400 for supplying a predetermined voltage by being connected to a junction of the transistor 300. The plurality of column wirings 220 may be connected to the drain of the transistor 300, For example, to a post-synaptic neuron 200 that receives and processes a signal via a transistor 300 connected to a source.

In this way, each of the synapses includes a transistor 300 having a floating gate and a junction with the gate of the transistor 300 is connected along the first direction, while the other junction of the transistor 300 is connected along the second direction The errors of the above-described learning and recognizing process can be improved. This will be described in more detail with reference to FIGS. 2B and 2C below. The row wiring 120 can be referred to as a first row wiring 120A, a second row wiring 120B, a third row wiring 120C and a fourth row wiring 120D from the top in order And the additional row wiring 420 may be referred to as a first additional row wiring 420A, a second additional row wiring 420B, a third additional row wiring 420C and a fourth additional row wiring 420D in this order from the top And the column wirings 220 may be referred to as a first column wirings 220A, a second column wirings 220B, a third column wirings 220C and a fourth column wirings 220D in order from the left.

First, referring to FIG. 2B, in the initial state, the transistor 300 may be in a state having a relatively high threshold voltage.

In this state, an input signal corresponding to specific data may be input to the row wiring 120 in response to the output of the pre-synaptic circuit 100, in order to perform an operation of learning specific data to the specific column wiring 220. At this time, the input signal may appear as an application of a voltage pulse to each of the row wirings 120. For example, when an input signal corresponding to data of '0011' is input to the row wiring 120, a voltage pulse (not shown) is applied to the row wiring 120 (e.g., the first and second row wirings 120A and 120B) A voltage pulse of a predetermined magnitude and a width may be applied only to the row wiring 120 corresponding to '1', for example, the third and fourth row wirings 120C and 120D, .

At this time, the column wiring 220 and the additional row wiring 420 can be driven with appropriate voltage or current for learning.

Specifically, as an example, when the column wiring 220 to learn specific data is already determined, the column wiring 220 is connected to the transistor 300 located at the intersection with the row wiring 120 corresponding to '1' And the remaining column wirings 220 may be driven so that the threshold voltage of the remaining transistor 300 is not varied. For example, when the column wiring 220 to learn the data of '0011' is defined as the third column wiring 220C, the potential difference between the third column wiring 220C and the third and fourth row wiring 120C and 120D The third column wiring 220C and the third and fourth row wirings 120C and 120D can be driven so that the threshold voltages of the first and second transistors 300A and 300B located at the intersections decrease. As an example, when a voltage having a minimum magnitude necessary for a threshold voltage variation of the first and second transistors 300A and 300B is Vset, the voltage pulse applied to the third and fourth row wirings 120C and 120D The size may be equal to or greater than Vset, and the voltage applied to the third column wiring 220C may be 0V. In this case, since the threshold voltages of the first and second transistors 300A and 300B are lowered, the third and fourth additional row wirings 420C and 420D are connected to the third and fourth transistors 300A and 300B through the third and fourth transistors 300A and 300B. A current or electron flow toward the column wiring 220C may occur (see the dotted arrow). As the number of voltage pulses applied to the third and fourth row wirings 120C and 120D increases, the threshold voltages of the first and second transistors 300A and 300B gradually decrease. That is, the conductivity of the synapse gradually increases, The current or electron flow through the first and second transistors 300A and 300B may gradually increase. The magnitude and width of the applied voltage pulse may be substantially constant.

The remaining transistors 300 except for the first and second transistors 300A and 300B are connected to the remaining column wirings 220, that is, the first, second and fourth column wirings 220A, 220B, 220D may have a value between 0V and Vset, for example, 1/2 Vset. Accordingly, the threshold voltage of the transistor 300 excluding the first and second transistors 300A and 300B may not change.

Meanwhile, the specific applied voltage and mechanism for gradually reducing the threshold voltage of the transistor 300 will be described in detail with reference to FIG. 3, which will be described later.

The additional row wiring 420 is formed to have a predetermined size and polarity voltage for causing current or electron flow to be generated in the column wiring 220 to be learned through the transistor 300 when the threshold voltage of the transistor 300 decreases . As an example, the additional row wiring 420 may receive a voltage having the same magnitude and polarity as the voltage pulse applied to the row wiring 120. [ That is, no voltage is applied to the first and second additional wirings 420A and 420B corresponding to the first and second row wirings 120A and 120B, a voltage of 0V is applied to the first and second additional wirings 420A and 420B, A voltage equal to or higher than Vset may be applied to the third and fourth additional wirings 420C and 420D corresponding to the wirings 120C and 120D, respectively. In this case, one voltage generating circuit can commonly drive the additional low-wirings 420 and the low-wirings 120, so that it can have various advantages such as increased integration of the novelrometer device and cost reduction. However, in another embodiment, a voltage different from at least one of polarity and magnitude may be applied to the voltage pulse applied to the row wiring 120 to the additional row wiring 420. [

As another example, the column wiring 220 to learn specific data may not be defined. In this case, a voltage pulse corresponding to specific data is applied to the row wiring 120, and a voltage of the same magnitude and polarity as the predetermined voltage, for example, the above voltage pulse is applied to the additional row wiring 420, The column wiring 220, for example, the third column wiring 220C that first reaches a predetermined threshold current by measuring the current flowing through the column wiring 220 may be referred to as a column wiring 220 that has learned the specific data.

According to the above-described method, different data can be learned in different column wirings 220, respectively.

In any case, when the learning ends, the previously learned column wiring 220, for example, the third column wiring 220C, can be floated. And to allow other data to be learned in the other column wiring 220. 2C shows a case in which data is read in another column wiring 220 in a state where the previously learned third column wiring 220C is floated and data of '0110' is written in the fourth column wiring 220D .

Referring to FIG. 2C, the row wiring 120, the column wiring 220, and the additional row wiring 420 are driven in a manner similar to the above-described method for learning data of '0110' to the fourth column wiring 220D .

More specifically, as an example, the third and fourth transistors 300C and 300D located at the intersections of the fourth column wiring 220D to be learned and the second and third row wiring 120B and 120C corresponding to '1' Applies a voltage pulse having a voltage equal to or greater than Vset to the second and third row wirings 120B and 120C and applies a voltage of 0V to the fourth column wiring 220D so as to decrease the threshold voltage, . On the other hand, the transistor 300 except for the third and fourth transistors 300C and 300D is supplied with a voltage pulse (not shown) to the first and fourth row wirings 120A and 120D corresponding to '0' And a voltage of 0 V may be applied to the first and second column wirings 220 and 220. The remaining column wirings 220 excluding the learned third column wirings 220C and the fourth column wirings 220D to be learned, A voltage having a value between 0 V and V set, for example, a value of 1/2 V set, may be applied to the electrodes 220A and 220B. No voltage is applied to the first and fourth additional row wirings 420A and 420D or a voltage of 0V is applied to the first and fourth additional row wirings 420A and 420D and a voltage having a magnitude equal to or greater than Vset is applied to the second and third additional row wirings 420B and 420C have. In this case, since the threshold voltages of the third and fourth transistors 300C and 300D are lowered, the fourth and fifth transistors 300C and 300D are turned off from the second and third additional row wirings 420B and 420C through the third and fourth transistors 300C and 300D. A current or electron flow toward the column wiring 220D may occur (see the dotted arrow). As the number of voltage pulses applied to the second and third row wirings 120B and 120C increases, the threshold voltages of the third and fourth transistors 300C and 300D gradually decrease. Therefore, the third and fourth transistors 300C, 300D can be gradually increased. The magnitude and width of the applied voltage pulse may be substantially constant.

At this time, since the previously learned third column wiring 220C is in a floating state and has a potential higher than 0 V and lower than Vset, a leakage current or an electron flow as indicated by a solid line arrow may occur. Looking at the solid line arrows, it can be seen that the leakage current or the flow of electrons is blocked before reaching the fourth column wiring 220D. In the case of the transistor 300 in which the threshold voltage is not lowered during the learning process, it is possible to cut off the leakage current or the flow of electrons. In addition, even if the first and second transistors 300A and 300B, which have lower threshold voltages in the learning process, allow the leakage current or electron flow, the flow of current or electrons is controlled by the control of the transistor 300 It is assumed that a predetermined voltage is input to the gate so that the transistor 300 is turned on. Therefore, since the voltage pulse is not applied to the fourth row wiring 120D to which the control gate of the second transistor 300B is connected, the second transistor 300B may be turned off, The flow of electrons can be blocked without passing through the second transistor 300B.

In summary, in the present embodiment, the potential of the column wiring 220 that has been learned is relatively low, so that a leakage current or an electron flow can be generated. However, in the low wiring 120 where a voltage pulse is not applied corresponding to specific data, The transistor 300 connected to the transistor 300 may turn off the leakage current or the flow of electrons. As a result, since the leakage current or the flow of electrons reaching the learning target column wiring 220 can be reduced or blocked, the phenomenon that the current flowing in the learning target column wiring 220 is excessively measured is prevented, Can be improved.

As another example, the column wiring 220 to learn specific data may not be defined. In this case, a voltage pulse corresponding to the specific data is applied to the row wiring 120 and a voltage of the same magnitude and polarity as the predetermined voltage, for example, the above voltage pulse, is applied to the additional row wiring 420, The column wiring 220, for example, the fourth column wiring 220D, which firstly reaches a predetermined threshold current, is measured by measuring the current flowing through each of the column wirings 220 except for the wiring 220C, 220). In this case as well, it is a matter of course that the transistor 300 connected to the row wiring 120 to which the voltage pulse is not applied corresponding to the specific data can turn off the leakage current or the flow of electrons as a turn off state.

According to the neuromodule device described above, in the column-by-column learning process, the leakage current due to the potential of the column wiring that has been learned by turning off the transistor connected to the specific row wiring can be cut off in the row direction. As a result, learning and recognition errors can be improved.

On the other hand, how the threshold voltage gradually decreases in the transistor 300 of the above embodiment will be described with reference to FIG.

FIG. 3 is a view for explaining a threshold voltage reduction mechanism of the transistors of FIGS. 2A to 2C. Referring to FIG.

Referring to FIG. 3, the transistor 300 may include a floating gate and a control gate electrically insulated from the floating gate. The control gate of the transistor 300 may be connected to the row wiring 120 and the two junctions of the transistor 300, for example, the drain and the source, may be connected to the additional row wiring 420 and the column wiring 220, respectively . The voltages applied to the row wiring 120, the additional row wiring 420 and the column wiring 220 may be referred to as a first voltage V1, a second voltage V2 and a third voltage V3, respectively. In particular, a first voltage (V1) in the form of a pulse may be applied to the row wiring 120.

As an example, when a hole is trapped in the floating gate of the transistor 300, that is, when electrons are emitted from the floating gate, the threshold voltage of the transistor 300 decreases, The threshold voltage of the transistor 300 may increase when electrons are trapped in the floating gate.

In this case, in order to trap holes in the floating gate of the transistor 300, the first voltage V1 may be a relatively negative voltage having a predetermined threshold value or more in comparison with the third voltage V3. Conversely, in order to discharge holes from the floating gate of the transistor 300, the first voltage V1 may be a relatively positive voltage having a predetermined threshold magnitude or greater relative to the third voltage V3. For example, assuming that the required magnitude of the voltage difference between the control gate and the source of the transistor 300 is | V ^{+ -} V ^- | for trapping / discharging the holes, the first voltage V1 during trapping of the holes is V ^- corresponding negative voltage and the third voltage (V3) is a positive voltage and the third voltage (V3) corresponding to the amount can be a voltage, and holes emitted when a first voltage (V1) is V ⁺ corresponding to the V ^+, which is V ^- May be a negative voltage corresponding to the negative voltage. On the other hand, if the voltage difference between the control gate and the source of the transistor 300 has a value less than | V ^{+ -} V ^- |, the trap / emission of holes may not occur. For example, the first voltage (V1) is V ^- even if the amount of voltage corresponding to the negative voltage V ⁺ or corresponding to, in the case where the third voltage (V3) is 0V, the hole trap / discharge may not be generated. Similarly, the third voltage (V3) is V ^- even if the amount of voltage corresponding to a negative voltage, or V ⁺ corresponding to the first voltage (V1) is 0V, the hole trap / discharge may not be generated.

The second voltage V2 may be a voltage having the same polarity as the first voltage V1. Furthermore, the second voltage V2 may have the same polarity and magnitude as the first voltage V1.

In the learning operations of FIGS. 2B and 2C, in order to perform the operation of lowering the threshold voltage of the transistor 300, a negative voltage of V ^- is applied as the first voltage V1 to the row wiring 120, A negative voltage of V ^- may be applied as the second voltage V2 to the wiring 420 and a positive voltage of V ⁺ may be applied to the column wiring 220 as the third voltage V3. At this time, since the first voltage V1 is applied in the form of a pulse, the amount of holes trapped in the floating gate of the transistor 300 may increase as the number of voltage pulses applied to the row wiring 120 increases. In other words, the threshold voltage of the transistor 300 may gradually decrease as the number of voltage pulses applied to the row wiring 120 increases. Accordingly, as the number of voltage pulses applied to the row wiring 120 increases, the current flowing through the transistor 300 or the flow of electrons may increase.

As a result, the transistor 300, which has a floating gate and a control gate and is applied with a plurality of voltage pulses to the control gate as in the present embodiment, changes gradually in accordance with the number of input voltage pulses, such that the threshold voltage and / Can be seen. Accordingly, it may be appropriate to use it as a synapse.

4A to 4D are diagrams for explaining an example of a learning process of a neuromotor apparatus according to an embodiment of the present invention. Six row wirings, two additional row wirings, three column wirings, and six transistors located at their intersections. Further, where transistors are to be used, it is possible to, the threshold voltage is reduced by a hole trap, as described in Figure 3, the voltage difference between the control gate and the source required to reduce the threshold voltage | V ⁺ -V ^- | days .

First, referring to FIG. 4A, a voltage pulse of V ^- may be applied to the first row wiring in order to learn specific data, for example, data of '10'. A voltage pulse may not be applied to the second row wiring or a voltage of 0 V may be applied. And voltages of the same polarity and magnitude as those of the row wiring can be respectively applied to the additional row wiring. That is, a voltage of V ^- may be applied to the first additional row wiring, and a voltage of 0 V may be applied to the second additional row wiring. At this point, | V ⁺ -V ^- | to secure the voltage difference, the column wiring may be applied with a voltage of V ^+.

In particular, this figure shows a case where a voltage of V ⁺ is applied to all the circuit wiring. This can explain the case where the column wiring to be learned is not defined. In this case, the threshold voltage of the three transistors connected to the first row wiring begins to decrease by the hole trap, so that the flow of electrons from the first additional row wiring to the three column wiring can begin to occur. That is, current can flow through the three column wirings. As the number of voltage pulses applied to the first row wiring increases, the current flow in the three column wirings may increase. By measuring this current, the column wiring that first reaches the predetermined threshold current can be the column wiring that has learned this specific data. As an example, the first column wiring is referred to as a column wiring in which the specific data, that is, data of '10', is learned.

On the other hand, when the column wiring to be learned is determined, a voltage of V ⁺ is applied only to the subject column wiring and a voltage of 0 V is applied to the remaining column wiring, as shown in Fig. That is, when the column wiring to be learned is determined, the step of FIG. 4A is omitted, and the step of FIG. 4B may be performed immediately.

4B, in order to strengthen the learning of '10' data in the first column wiring, the voltage applied to the row wiring and the additional row wiring and the voltage applied to the first column wiring are the same as those in the step of FIG. 4A The voltage of 0 V can be applied to the remaining column wirings. In this case, the threshold voltages of the transistors located at the intersections of the transistors other than the dashed line, that is, the first row wiring, the first additional row wiring, and the first column wiring can be lowered, and the current flow through the first column wiring Can be increased further.

Next, referring to FIG. 4C, it is possible to perform an operation of initializing the remaining transistors except the transistors (see the dotted line portion) connected to the first learned column wiring, that is, increasing the threshold voltage of the remaining transistors again . This is because, in the learning process of FIGS. 4A and / or 4B described above, voltage pulses or the like are also applied to the transistors connected to the second and third column wirings which are not to be studied, and undesired threshold voltage reduction of these transistors may occur .

To this end, voltages for hole discharge from the transistors connected to the second and third column wirings can be applied to the row wirings and the column wirings. For example, a voltage of V ^- may be applied to the second and third column wirings, and a voltage of V ⁺ may be applied to the first and second row wirings. In this case, holes may be emitted from the floating gate to the source of the transistors connected to the second and third column wirings so that the threshold voltage of these transistors may increase again. On the other hand, by applying a voltage of 0 V to the first column wiring, the threshold voltage fluctuation of the transistors connected to the first column wiring can be prevented. And voltages of the same polarity and magnitude as those of the row wiring can be respectively applied to the additional row wiring.

Referring to FIG. 4D, after the above-described learning and initializing operation, it is possible to perform an operation of verifying and / or recognizing that data of '10' is learned in the first column wiring.

To this end, a read voltage of Vrd may be applied to the first row wiring so as to correspond to data of '10', and a voltage of 0 V may be applied to the second row wiring. Vrd may be a predetermined positive voltage having a size equal to or smaller than V ⁺ . A voltage having the same polarity and magnitude as the row wiring can be applied to the additional row wiring, or a voltage having a larger size can be applied while having the same polarity. For example, when a voltage of Vrd smaller than V ⁺ is applied to the first row wiring, a voltage of Vrd or a voltage of V ⁺ may be applied to the first additional row wiring. The voltage applied to the second additional row wiring may not be applied or a voltage of 0 V may be applied. A voltage of 0 V may be applied to the column wiring. In this case, it is possible to verify and / or recognize that the data of '10' is learned in the first column wiring by checking whether the current flowing through all the column wirings is the largest and the current flowing through the first column wiring is the largest. As described above, the threshold voltage of the transistors connected to the first column wiring, in particular, the threshold voltage of the transistor located at the intersection of the first row wiring and the first column wiring is lower, while the threshold voltage of the transistor connected to the second column wiring and the third column wiring is It is predicted that the current flowing through the first column wiring is the largest.

4A to 4D described above can be repeatedly performed until different data are learned in all the column wirings.

FIG. 5 is a perspective view for explaining an example of a synapse of a nyombol pick apparatus according to an embodiment of the present invention. As described above, the synapse may include a transistor having a floating gate and a control gate.

5, the synapse according to an embodiment of the present invention includes a semiconductor column 320 extending in a vertical direction from a substrate (not shown), and a tunnel 320 sequentially surrounding the semiconductor column 320, An insulating film 330, a floating gate 340, a charge blocking film 350, and a control gate 310.

Semiconductor pillars 320 are for providing channel and junction regions of transistors, and may include various semiconductor materials such as polysilicon. Further, in order to function as a channel and a junction region, it is possible to include impurity regions of various conductivity types by impurity doping. In the semiconductor column 320, the channel region may be located at a portion overlapping the control gate 310, and the junction region may be located at both sides of the channel region, that is, the semiconductor column 320 may be located at the top and bottom.

The tunnel insulating film 330 may enable tunneling of charges according to a voltage applied to the control gate 310 between the semiconductor pillars 320 and the floating gate 330. The tunnel insulating film 330 may include various insulating materials such as silicon oxide, silicon nitride, or combinations thereof.

The floating gate 340 may trap and / or store charge transferred from the semiconductor pillars 320 or emit traps and / or stored charges to the semiconductor pillars 320 according to the voltage applied to the control gate 310 have. The floating gate 340 is a material capable of trapping and / or storing charge, and may include an insulating material such as silicon nitride or the like or a semiconductor material such as polysilicon.

The charge blocking layer 350 may include various insulating materials such as silicon oxide, silicon nitride, or a combination thereof, as a film that can block the movement of charge between the floating gate 340 and the control gate 310.

 When the floating gate 340 includes an insulating material, it may include an insulating material different from the tunnel insulating film 330 and the charge blocking film 350. For example, when the floating gate 340 includes silicon nitride, the tunnel insulating film 330 and the charge blocking film 350 may include silicon oxide different therefrom. That is, the tunnel insulating film 330, the floating gate 340, and the charge blocking film 350 may form an ONO (Oxide-Nitride-Oxide) structure. Although the tunnel insulating film 330, the floating gate 340 and the charge blocking film 350 are shown to surround all the side walls of the semiconductor pillars 320 in the present embodiment, the tunnel insulating film 330, the floating gate 340, And the charge blocking layer 350 are interposed between the semiconductor pillars 320 and the control gate 310, the position and the shape of the charge blocking layer 350 may be variously changed.

The control gate 310 functions as a gate of the transistor and receives a voltage to control charge input / output of the floating gate 340. The control gate 310 may include a conductive material such as a metal, a metal nitride, or a combination thereof. Although not shown, the control gate 310 may have a line shape extending in one horizontal direction while surrounding the outer wall of the charge blocking film 350.

The transistor described above may be a vertical-type transistor whose channel extends in a direction perpendicular to the substrate. When a vertical transistor is used as a synapse, the semiconductor substrate is not fabricated using a semiconductor substrate, so that the semiconductor substrate can be used for manufacturing other elements. This can be efficient in terms of the integration degree of the semiconductor device. However, in another embodiment, a planar-type transistor may be used in which the channel extends horizontally with respect to the substrate at the synapse. The planar type transistor may include a tunnel insulating film, a floating gate, a charge blocking film, and a control gate sequentially stacked on a semiconductor substrate.

FIGS. 6A and 9B are views for explaining a method of manufacturing a nyomotelophone apparatus according to an embodiment of the present invention. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along the line A-A 'in FIG. The neurometric device of this embodiment may include a synapse having the vertical transistor of FIG.

6A and 6B, a substrate 305 on which a predetermined substructure (not shown) is formed may be provided.

Subsequently, a lower wiring 307 extending in the first direction, e.g., the longitudinal direction, may be formed on the substrate 305. [ This lower wiring 307 is for supplying a voltage to a single junction region of the transistor and may correspond to any one of the additional row wiring 420 and the column wiring 220 in FIGS. 2A to 3 described above. In this embodiment, the lower wiring 307 is connected to the source region of the transistor, and can correspond to the column wiring 220 of FIGS. 2A to 3 described above. The lower wiring 307 may include various conductive materials such as a metal such as W, Cu, a metal nitride, or a combination thereof. In this embodiment, although two lower wirings 307 are shown spaced apart from the second direction intersecting the first direction, the number of the lower wirings 307 may be variously modified.

A source region 308 overlapping the lower wiring 307 may be formed on the lower wiring 307. The source region 308 may comprise a semiconductor material of the first conductivity type, such as N-type polysilicon. However, if the lower wiring 307 corresponds to an additional column wiring (see 420 in FIG. 2A to FIG. 3) for supplying a voltage to the drain region of the transistor, a drain region instead of the source region 308 is formed on the lower wiring 307 . The drain region may also include a semiconductor material of the same conductivity type as the source region 308.

A first interlayer insulating film 306 may be buried between the stacked structure of the lower wiring 307 and the source region 308. The first interlayer insulating film 306 may include an insulating material such as silicon oxide.

The lower wiring 307, the source region 308 and the first interlayer insulating film 306 may be formed by the following method.

As an example, a metal containing material for forming the lower wiring 307 and a first conductive type semiconductor material for forming the source region 308 are sequentially deposited on the substrate 305, and then selectively etched to form the lower wiring 307, and a source region 308. [0064] Subsequently, an insulating material covering the bottom wiring 307 and the source region 308 is deposited. Then, a planarization process such as a CMP (Chemical Mechanical Polishing) process is performed until the top surface of the source region 308 is exposed can do.

As another example, an insulating material may be deposited on the substrate 305, and then the insulating material may be selectively etched to form a first interlayer insulating film 306 (not shown) to provide space for forming the lower wiring 307 and the source region 308 ) Can be formed. Subsequently, the lower wiring 307 and the source region 308 can be formed by sequentially forming the metal-containing material and the semiconductor material in this space.

7A and 7B, an etch stop layer 311, a second interlayer insulating layer 312, a control gate layer 313, and a third interlayer insulating layer 314 are stacked on the resultant process of FIGS. 6A and 6B Thereby forming a laminated structure.

6A and 6B, an insulating material such as silicon nitride for forming the etch stop film 311, an insulating material such as silicon oxide for forming the second interlayer insulating film 312, A conductive material such as a metal for forming the film 313 and an insulating material such as silicon oxide for forming the third interlayer insulating film 314 sequentially and then selectively etching these deposited materials. The stacked structure of the etching stopper film 311, the second interlayer insulating film 312, the control gate film 313 and the third interlayer insulating film 314 is formed in the lower wiring 307 and the source region 308 And extend in a second direction so as to traverse the laminated structure. However, in another embodiment, if the lower wiring 307 corresponds to an additional column wiring (see 420 in FIGS. 2A-3) for supplying voltage to the drain region of the transistor, the upper stacked structure overlaps the lower wiring 307 And extend in the same direction as the lower wiring 307. The plurality of stacked structures may be spaced apart from each other in the first direction. Although not shown, the plurality of stacked structures may be filled with an insulating material. The control gate film 313 extending in the second direction can correspond to the row wiring 120 of Figs. 2A to 3 described above.

The laminated structure of the etching stopper film 311, the second interlayer insulating film 312, the control gate film 313 and the third interlayer insulating film 314 is selectively etched to expose the source region 308 H) can be formed. The holes H are formed in the stacked structure of the lower wiring 307 and the source region 308 and the stacked structure of the etching stopper film 311, the second interlayer insulating film 312, the control gate film 313 and the third interlayer insulating film 314 May be formed so as to overlap the intersecting region of the laminated structure. In order to prevent an attack to the source region 308 in the formation of the holes H, after stopping the etching at the time when the etching stopper film 311 is exposed, the exposed etching stopper film 311 is removed, (308) can be exposed.

8A and 8B, a charge blocking film 352, a floating gate film 342 and a tunnel insulating film 332 are sequentially formed on the sidewall of the hole H, The semiconductor pillars 322 to be buried can be formed.

The formation of the charge blocking film 352, the floating gate film 342 and the tunnel insulating film 332 can be performed by forming the charge blocking material, the material for the floating gate And a tunnel insulating material are sequentially deposited, and then these materials are front-etched. Alternatively, the formation of the charge blocking film 352, the floating gate film 342 and the tunnel insulating film 332 can be performed by depositing a charge blocking material and its front side etching, the material for the floating gate and its front side etching, It may be performed by its front side etching.

The semiconductor pillar 322 is formed to have a thickness sufficient to fill the remaining space of the hole H formed with the charge blocking film 352, the floating gate film 342 and the tunnel insulating film 332, The planarization process may be performed until the upper surface of the first substrate 314 is exposed.

Thereby, a vertical transistor including the semiconductor column 322 and the tunnel insulating film 332 surrounding it, the floating gate film 342, the charge blocking film 352, and the control gate film 313 can be formed.

Although not shown, after forming the hole H in FIGS. 7A and 7B and / or forming the charge blocking film 352, the floating gate film 342, and the tunnel insulating film 332 in FIGS. 8A and 8B, An additional impurity implantation process may be performed on the exposed source region 308 to compensate for the impurity loss in the source region 308. This impurity may be an N-type impurity.

Further, although not shown, after the step of forming the semiconductor pillars 322 in FIGS. 8A and 8B, an additional impurity implantation process may be performed to the top of the semiconductor pillars 322 to form other junction regions, for example, drain regions of the transistors . This impurity may be an N-type impurity.

Referring to FIGS. 9A and 9B, an upper wiring 362 may be formed on the process result of FIGS. 8A and 8B. This upper wiring 362 is for supplying a voltage to another junction region of the transistor and may correspond to the other one of the additional row wiring 420 and the column wiring 220 in FIGS. 2A to 3 described above. In this embodiment, since the lower wiring 307 corresponds to the column wiring 220 of FIGS. 2A to 3, the upper wiring 362 can correspond to the additional column wiring 420 of FIGS. 2A to 3. In this case, the upper wiring 362 can extend in the same direction as the control gate 313 while overlapping the control gate 313. The upper wiring 362 may include various conductive materials such as a metal such as W, Cu, a metal nitride, or a combination thereof. The upper wiring 362 can be connected to a drain region (not shown) formed at the upper end of the semiconductor column 322 to supply a required voltage.

Thereby, a neurometric device as shown in Figs. 9A and 9B can be provided. This neuromodule device may correspond to an example in which the neuromodule device of Fig. 2A is implemented.

The neurometric device of the above-described embodiments may be used in various devices or systems. This will be described by way of example with reference to FIG.

10 is an example of a pattern recognition system according to an embodiment of the present invention. The pattern recognition system of the present embodiment may be a system for recognizing various kinds of patterns such as a speech recognition system and an imaging recognition system. The pattern recognition system of this embodiment can be implemented with the neurometric apparatus of the above-described embodiments.

10, the pattern recognition system 1000 of the present embodiment includes a central processing unit (CPU) 1010, a memory device 1020, a communication control device 1030, a network 1040, a pattern output device 1050, A pattern input device 1060, an analog-to-digital converter (ADC) 1070, a nebulizer device 1080, a bus line 1090, and the like.

The central processing unit 1010 generates and transmits various signals for the learning of the neuromorphic device 1080 and performs various processes for recognizing patterns such as voice, And functions. The central processing unit 1010 includes a bus line 1090 to the memory device 1020, the communication control device 1030, the pattern output device 1050, the analog-to-digital converter 1070, Lt; / RTI >

The memory device 1020 may store various information required to be stored in the pattern recognition system 1000 and may include different kinds of memories for this purpose. For example, the memory device 1020 may include a ROM (ROM) 1022, a RAM (RAM) 1024, and the like. The ROM 1022 may store various programs or data used in the central processing unit 1010 to process and control learning, pattern recognition, and the like of the neuromorphic apparatus 1080. [ The ROM 1024 may download and store the program or data of the ROM 1022 or may store data such as voice and image converted and analyzed by the analog-to-digital converter 1070.

The communication control device 1030 can exchange the recognized voice and video data with another communication control device through the network 1040. [

The pattern output device 1050 can output the recognized voice, video, and other data in various ways. For example, the pattern recognition apparatus 1050 can include a printer, a display unit, and the like, and can display a voice as a waveform or an image.

The pattern input device 1060 receives a voice, an image, and the like in an analog form, and may include a microphone, a camera, and the like.

The analog-to-digital converter 1070 can convert the analog data input from the pattern input device 1060 into digital data and perform analysis of the digital data.

The neuromotor apparatus 1080 can perform learning, recognition, and the like using data output from the analog-digital converter 1070, and can output data corresponding to the recognized pattern. The neurometer device 1080 may include one or more of the neurometric devices of the embodiments described above. For example, the neurometer device 1080 may include first to Nth row wires (where N is a natural number of 2 or more) and first to Mth column wires (where M is a natural number of 2 or more) A synapse located at an intersection, the synapse including a variable resistor element and a first transistor connected in series; And a tenth gate wiring to which the gates of the first transistors connected to the tth column wiring (where t is a natural number equal to or greater than 1 and equal to or less than M) are commonly connected. This improves the accuracy of learning and perception of the neurometer device 1080. In this way, the operating characteristics of the pattern recognition system 1000 and the accuracy of pattern recognition can be improved.

In addition, the pattern recognition system 1000 may further include other components necessary for properly performing its function. For example, the input unit may further include a keyboard, a mouse, and the like as an input unit for inputting various parameters and setting conditions for driving the pattern recognition system 1000.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, .

100: Presynaptic neuron 120: Low wiring
200: Post Synaptic Neuron 220: Column Wiring
300: Synapse
400: drain voltage application circuit 420: additional row wiring

Claims (19)

A plurality of row lines extending in a first direction;
A plurality of additional row wirings extending in the first direction;
A plurality of column lines extending in a second direction intersecting the first direction; And
And a synapse located in an intersection area of the row wiring, the additional row wiring, and the column wiring,
The synapse,
And a transistor having a floating gate, a control gate insulated from the floating gate, the transistor being connected to the row wiring, the first junction being connected to the additional row wiring, and the second junction being connected to the column wiring
New LomoPick device.
The method according to claim 1,
A voltage pulse corresponding to specific data is applied to the plurality of row wirings
New LomoPick device.
3. The method of claim 2,
The transistor comprising:
Having a threshold voltage that is reduced when a predetermined charge is trapped in the floating gate
New LomoPick device.
The method of claim 3,
The amount of charge trapped in the floating gate increases as the number of voltage pulses increases
New LomoPick device.
The method of claim 3,
The threshold voltage of the transistor decreases as the number of the voltage pulses increases
New LomoPick device.
The method of claim 3,
The current flow between the first junction and the second junction increases as the number of voltage pulses increases
New LomoPick device.
3. The method of claim 2,
A voltage having the same polarity as the voltage pulse is applied to the plurality of additional row wirings
New LomoPick device.
8. The method of claim 7,
Wherein the voltage applied to the plurality of additional row wirings has the same magnitude as the voltage pulse
New LomoPick device.
3. The method of claim 2,
Different data are learned in each of the plurality of column wirings
New LomoPick device.
10. The method of claim 9,
In the process of learning the specific data to the first column wiring among the plurality of column wirings,
New LomoPick device.
Board;
A lower wiring located on the substrate and extending in a first direction;
An upper wiring located on the lower wiring and extending in a second direction intersecting with the first direction;
A semiconductor column located between the lower wiring and the upper wiring at a crossing region of the lower wiring and the upper wiring;
A tunnel insulating film, a floating gate, and a charge blocking film sequentially surrounding side surfaces of the semiconductor pillars; And
And a control gate surrounding the side surface of the charge blocking film and extending in the first direction or the second direction,
Wherein the semiconductor column, the tunnel insulating film, the floating gate, the charge blocking film, and the control gate form a synapse
New LomoPick device. 12. The method of claim 11,
A voltage pulse corresponding to specific data is applied to the control gate
New LomoPick device.
13. The method of claim 12,
The synapse,
Having a conductivity decreasing when a predetermined charge is trapped in the floating gate
New LomoPick device.
14. The method of claim 13,
The amount of charge trapped in the floating gate increases as the number of voltage pulses increases
New LomoPick device.
14. The method of claim 13,
The conductivity of the synapse decreases as the number of voltage pulses increases
New LomoPick device.
14. The method of claim 13,
The current flow through the semiconductor column increases as the number of voltage pulses increases
New LomoPick device.
13. The method of claim 12,
A voltage having the same polarity as the voltage pulse is applied to either the lower wiring or the upper wiring
New LomoPick device.
18. The method of claim 17,
Wherein the voltage applied to any one of the lower wiring and the upper wiring has the same magnitude as the voltage pulse
New LomoPick device.
18. The method of claim 17,
Specific data is stored in the other of the lower wiring and the upper wiring
New LomoPick device.

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