KR102296316B1 - Nonvolatile memory device and operating method of the same - Google Patents

Abstract

A nonvolatile memory device includes a resistance switching layer, a gate positioned above or below the resistance change layer, a gate oxide layer formed between the resistance change layer and the gate, and a resistance change layer. It is formed on the layer and may include a source (Source) and a drain (Drain) spaced apart from each other.
The resistance value of the resistance change layer may be changed based on illumination of light irradiated through the upper portion of the resistance change layer, and may be maintained at the changed resistance value.

Description

Non-volatile memory device and operating method thereof

The present disclosure relates to a non-volatile memory device and a method of operating the same.

As a semiconductor memory device, a nonvolatile memory device retains information even when power is cut off, so that the stored information can be used again when power is supplied. Non-volatile memory devices may be used in cell phones, digital cameras, portable digital assistants (PDAs), mobile computer devices, stationary computer devices, and other devices.

Recently, research using a nonvolatile memory device in a next-generation neuromorphic computing platform or a chip forming a neural network is in progress.

In particular, research on a nonvolatile memory device having photoconductivity (PC) is required.

To provide a non-volatile memory device and a method of operating the same. Another object of the present invention is to provide a computer-readable recording medium in which a program for executing the method in a computer is recorded. The technical problem to be solved is not limited to the technical problems as described above, and other technical problems may exist.

As a technical means for achieving the above technical problem, a first aspect of the present disclosure is a nonvolatile memory device, comprising: a resistance switching layer; a gate positioned above or below the resistance change layer; a gate oxide layer formed between the resistance change layer and the gate; and a source and a drain that are formed on the resistance change layer and are spaced apart from each other, wherein the resistance value of the resistance change layer is the illuminance ( illumination) and maintained at the changed resistance value.

In addition, the gate may be a transparent conductive electrode (TCE) gate positioned on the resistance change layer and through which the irradiated light may pass, a nonvolatile memory device may be provided.

In addition, the resistance change layer is formed of a 2D material, and the 2D material includes at least one selected from the group consisting of Transition Metal Dichalcogenide (TMD), Phosphorene (Black Phosphorus), and Graphene. can provide

Also, the resistance change layer may be formed of a single layer or a multilayer, and a nonvolatile memory device may be provided.

In addition, the resistance change layer may be formed of a 3D material, and the 3D material may include at least one selected from the group consisting of Germanane, Silicene, III-V, and IGZO.

In addition, the nonvolatile memory device may be provided in which the gate oxide layer is formed in multiple layers, and the multilayer includes a charge trapping layer.

In addition, in a state in which an off-voltage is applied to the gate, as the illuminance of light irradiated through the upper portion of the resistance change layer increases, the resistance value of the resistance change layer decreases. devices can be provided.

In addition, it is possible to provide a nonvolatile memory device in which the resistance value of the resistance change layer is reset when an on-voltage is applied to the voltage of the gate.

A second aspect of the present disclosure provides a method of performing a predetermined operation using a crossbar array including a plurality of non-volatile memory devices, wherein the gate of each of the plurality of non-volatile memory devices is turned off- applying a voltage; irradiating light of an illuminance corresponding to each of the plurality of elements to each of the plurality of non-volatile memory elements to change the resistance value of the resistance change layer of each of the plurality of non-volatile memory elements; and performing the predetermined operation by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array. can provide

The irradiating may include irradiating light of an illuminance corresponding to each of the plurality of pixels included in the image to each of the plurality of non-volatile memory devices, and performing the predetermined operation. may provide a method, including: acquiring the image by applying a gate-off voltage to each row of the crossbar array and acquiring a source current for each column of the crossbar array.

In addition, the irradiating may include sequentially disposing a plurality of color filters on the non-volatile memory devices, and applying light of an illuminance corresponding to each of a plurality of pixels included in an image to each of the plurality of non-volatile memory devices. and irradiating to; and performing the predetermined operation includes applying a gate-off voltage to each row of the crossbar array and acquiring a source current for each column of the crossbar array, so that the plurality of color filters obtaining intermediate images corresponding to each of the ; and obtaining a color image by synthesizing the intermediate images.

In addition, the irradiating includes irradiating light of an illuminance corresponding to each of a plurality of weights included in a specific layer of a neural network to each of the plurality of non-volatile memory devices; The performing step includes: performing a convolution operation of the specific layer by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array; can provide

Also, in the irradiating step, a window is shifted by a predetermined stride interval on the image, and light having an illuminance corresponding to a plurality of elements included in the window for each column of the crossbar array. It can provide a method, including the step of irradiating;

A third aspect of the present disclosure provides a method of recognizing an image using a crossbar array including a plurality of non-volatile memory devices, the method comprising: applying an off-voltage to gates of each of the plurality of non-volatile memory devices; shifting a window by a predetermined stride interval on an image and irradiating light of an illuminance corresponding to each of a plurality of pixels of the image included in the window for each column of the crossbar array; performing a pooling operation by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a first source current for each column of the crossbar array; resetting the crossbar array by applying an on-voltage to the gates of each of the plurality of nonvolatile memory devices, and then applying an off-voltage; irradiating light of an illuminance corresponding to each of a plurality of weights included in a specific layer of a neural network to each of the plurality of non-volatile memory devices; Fully-connected convolution operation by applying a voltage corresponding to the first source current as a drain voltage to at least one row of the crossbar array and obtaining a second source current for each column of the crossbar array performing the steps; and recognizing the image based on the second source current.

In addition, a fourth aspect of the present disclosure may provide a computer-readable recording medium in which a program for executing the method of the second aspect is recorded on a computer.

According to the above-described problem solving means of the present disclosure, a crossbar array including a plurality of non-volatile memory elements may have a photoconductive characteristic, and the crossbar array according to the present disclosure is used in an image storage/acquisition process by using this characteristic. can be utilized

In addition, according to the above-described problem solving means of the present disclosure, the crossbar array can perform vector matrix operation, and the crossbar array according to the present disclosure can be utilized for learning and reasoning of a neural network by using this characteristic.

In addition, according to the above-described problem solving means of the present disclosure, the crossbar array utilized in the imaging mode (image storage/acquisition) may be utilized in the recognition mode (neural network learning/inference) after being reset. Accordingly, the imaging mode and the recognition mode can be performed using one crossbar array.

1A to 1B are diagrams for explaining a method of operating a crossbar array including a plurality of nonvolatile memory devices according to an exemplary embodiment.
2 is a diagram for explaining an architecture of a neural network according to an embodiment.
3 is a diagram for describing a relationship between an input feature map and an output feature map in a neural network according to an embodiment.
4A to 4B are diagrams for comparing vector-matrix multiplication and an operation performed in a crossbar array according to an exemplary embodiment.
5 is a diagram for explaining an example in which a convolution operation is performed in a crossbar array according to an embodiment.
6 is a diagram for explaining an example in which a sub-feature map and a crossbar array are matched according to an embodiment.
7A to 7B are side views illustrating a phototransistor and a nonvolatile memory device having memory characteristics according to an exemplary embodiment.
8 is a diagram for explaining a phenomenon in which a resistance value of a nonvolatile memory device varies according to before and after light is irradiated, according to an exemplary embodiment.
9A to 9B are exemplary diagrams for explaining a process of storing an image and acquiring the stored image using a crossbar array including a plurality of non-volatile memory devices, according to an exemplary embodiment.
10 is an exemplary diagram for explaining a process of performing a pulling operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to an embodiment.
11 is an exemplary diagram for explaining a process of performing a convolution operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to an embodiment.
12 is a flowchart illustrating a method of performing a predetermined operation using a crossbar array according to an exemplary embodiment.
13 is a block diagram illustrating a memory system according to an exemplary embodiment.

The appearances of the phrases "in some embodiments" or "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

Some embodiments of the present disclosure may be represented by functional block configurations and various processing steps. Some or all of these functional blocks may be implemented in various numbers of hardware and/or software configurations that perform specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors, or by circuit configurations for a given function. Also, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages. The functional blocks may be implemented as an algorithm running on one or more processors. Also, the present disclosure may employ prior art for electronic configuration, signal processing, and/or data processing, and the like. Terms such as “mechanism”, “element”, “means” and “configuration” may be used broadly and are not limited to mechanical and physical components.

In addition, the connecting lines or connecting members between the components shown in the drawings only exemplify functional connections and/or physical or circuit connections. In an actual device, a connection between components may be represented by various functional connections, physical connections, or circuit connections that are replaceable or added.

Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

1A to 1B are diagrams for explaining a method of operating a crossbar array including a plurality of nonvolatile memory devices according to an exemplary embodiment.

Referring to FIG. 1A , the crossbar array includes a plurality of presynaptic neurons (10), a plurality of postsynaptic neurons (20), and a plurality of presynaptic neurons (10) and a plurality of postsynaptic neurons (20). ) may include a synapse 30 that provides each connection between. The synapse 30 may represent a non-volatile memory device.

In an embodiment, the crossbar array includes four pre-synaptic neurons 10 , four post-synaptic neurons 20 , and 16 synapses 30 , but the number of these may be variously modified. The number of pre-synaptic neurons 10 is N (where N is a natural number greater than or equal to 2), and the number of post-synaptic neurons 20 is M (where M is a natural number greater than or equal to N, and may be equal to or different from N). If there is), N * M synapses 30 may be arranged in a matrix form.

Specifically, a wiring 12 connected to each of the plurality of pre-synaptic neurons 10 and extending in a first direction (eg, a transverse direction) and a plurality of post-synaptic neurons 20 connected to each of the first direction A wiring 22 extending in a second direction (eg, a vertical direction) intersecting with the ? Hereinafter, for convenience of description, the wiring 12 extending in the first direction will be referred to as a row line, and the wiring 22 extending in the second direction will be referred to as a column line. The plurality of synapses 30 may be disposed at each intersection of the row wiring 12 and the column wiring 22 to connect the corresponding row wiring 12 and the corresponding column wiring 22 to each other.

The pre-synaptic neuron 10 generates a signal, for example, a signal corresponding to specific data and sends it to the row wiring 12, and the post-synaptic neuron 20 transmits the synaptic signal that has passed through the synapse 30 to the column wiring ( 22) through which it can receive and process. The pre-synaptic neuron 10 may correspond to an axon, and the post-synaptic neuron 20 may correspond to a neuron. However, whether it is a pre-synaptic neuron or a post-synaptic neuron can be determined by its relative relationship with other neurons. For example, when the pre-synaptic neuron 10 receives a synaptic signal in relation to another neuron, it may function as a post-synaptic neuron. Similarly, the post-synaptic neuron 20 may function as a pre-synaptic neuron if it sends a signal in relation to another neuron. The pre-synaptic neuron 10 and the post-synaptic neuron 20 may be implemented in various circuits such as CMOS.

A connection between the pre-synaptic neuron 10 and the post-synaptic neuron 20 may be made through the synapse 30 . Here, the synapse 30 is an electrical pulse applied to both ends, for example, according to a voltage or a current, electrical conductivity or weight is a device that changes.

The synapse 30 may include, for example, a variable resistance element. A variable resistance element is an element that can switch between different resistance states depending on a voltage or current applied to both ends, and various materials that can have a plurality of resistance states, for example, transition metal oxide, perovskite-based It may have a single-layer structure or a multi-layer structure including a metal oxide such as a material, a phase change material such as a chalcogenide-based material, a ferroelectric material, a ferromagnetic material, and the like. An operation in which the variable resistance element and/or the synapse 30 changes from a high resistance state to a low resistance state is referred to as a set operation, and an operation in which the variable resistance element and/or the synapse 30 changes from a low resistance state to a high resistance state is referred to as a reset operation. .

However, in the synapse 30, unlike variable resistance elements used in memory devices such as RRAM, PRAM, FRAM, and MRAM, there is no abrupt resistance change in the set operation and the reset operation, and the number of input electrical pulses Accordingly, it may be implemented to have various characteristics that are distinguished from the variable resistance element in the memory, such as analog behavior in which the conductivity is gradually changed.

An operation of the above crossbar array will be described with reference to FIG. 1B as follows. For convenience of description, the row wiring 12 may be referred to as a first row wiring 12A, a second row wiring 12B, a third row wiring 12C, and a fourth row wiring 12D in order from the top. , the column wiring 22 may be referred to as a first column wiring 22A, a second column wiring 22B, a third column wiring 22C, and a fourth column wiring 22D in order from the left.

Referring to Figure 1b, in the initial state, all of the synapses 30 may be in a relatively low conductivity state, that is, in a high resistance state. When at least a portion of the plurality of synapses 30 is in a low resistance state, an initialization operation for making them into a high resistance state may be additionally required. Each of the plurality of synapses 30 may have a predetermined threshold value required for resistance and/or conductivity change. More specifically, when a voltage or current having a magnitude smaller than a predetermined threshold is applied to both ends of each synapse 30 , the conductivity of the synapse 30 does not change, and a voltage or current greater than a predetermined threshold is applied to the synapse 30 . When the conductivity of the synapse 30 can be changed.

In this state, in order to perform an operation of outputting specific data as a result of the specific column wiring 22 , an input signal corresponding to the specific data may enter the row wiring 12 . In this case, the input signal may be represented by application of an electrical pulse to each of the row wirings 12 . For example, when an input signal corresponding to data of '0011' is input to the row wiring 12, an electric pulse is applied to the row wiring 12 corresponding to '0', for example, the first and second row wirings 12A and 12B. is not applied, and an electrical pulse may be applied only to the row wiring 12 corresponding to '1', for example, the third and fourth row wirings 12C and 12D. In this case, the column wiring 22 may be driven with an appropriate voltage or current for output.

As an example, when the column wiring 22 for outputting specific data has already been determined, the synapse 30 positioned at the intersection with the row wiring 12 corresponding to '1' is set in the column wiring 22 . It may be driven to receive a voltage having a magnitude greater than or equal to a required voltage (hereinafter, referred to as a set voltage), and the remaining column wirings 22 may be driven so that the remaining synapses 30 receive a voltage having a smaller magnitude than the set voltage. For example, when the magnitude of the set voltage is Vset and the column wiring 22 for outputting data of '0011' is determined as the third column wiring 22C, the third column wiring 22C and the third and fourth rows The magnitude of the electric pulse applied to the third and fourth row wirings 12C and 12D so that the first and second synapses 30A and 30B located at the intersection with the wirings 12C and 12D receive a voltage of Vset or higher may be greater than or equal to Vset, and the voltage applied to the third column wiring 22C may be 0V. Accordingly, the first and second synapses 30A and 30B may be in a low resistance state. Conductivity of the first and second synapses 30A and 30B in the low resistance state may gradually increase as the number of electrical pulses increases. The magnitude and width of the applied electrical pulse may be substantially constant. The remaining synapses 30 except for the first and second synapses 30A and 30B are applied to the remaining column wirings, that is, the first, second and fourth column wirings 22A, 22B, 22D, so as to receive a voltage smaller than Vset. The applied voltage may have a value between 0V and Vset, for example, 1/2Vset. Accordingly, the resistance state of the remaining synapses 30 except for the first and second synapses 30A and 30B may not change. The flow of current or electrons in this case is indicated by a dotted arrow.

As another example, the column wiring 22 for outputting specific data may not be determined. In this case, the column wiring 22 that first reaches a predetermined threshold current by measuring the current flowing through each of the column wirings 22 while applying an electric pulse corresponding to specific data to the row wiring 12 , for example, the third column wiring 22C may be the column wiring 22 outputting this specific data.

According to the method described above, different data may be respectively output to different column wirings 22 .

2 is a diagram for explaining an architecture of a neural network according to an embodiment.

Referring to FIG. 2 , the neural network 2 may be an architecture of a deep neural network (DNN) or an n-layers neural network. The DNN or n-layer neural network may correspond to convolutional neural networks (CNNs), recurrent neural networks (RNNs), deep belief networks, restricted boltzman machines, and the like. For example, the neural network 2 may be implemented as a convolutional neural network (CNN), but is not limited thereto. Although some convolutional layers are shown in the convolutional neural network corresponding to the example of the neural network 2 in FIG. 2 , the convolutional neural network includes a pooling layer and a fully connected layer in addition to the illustrated convolutional layer. and the like may be further included.

The neural network 2 may be implemented as an architecture having multiple layers including an input image, feature maps and an output. In the neural network 2, a convolution operation is performed on an input image with a filter called a weight, and as a result, feature maps are output. At this time, the generated output feature maps are input feature maps, and a convolution operation with weights is performed again, and new feature maps are output. As a result of repeatedly performing such a convolution operation, a result of recognizing the features of the input image through the neural network 2 may be finally output.

For example, when an image having a size of 24x24 pixels is input to the neural network 2 of FIG. 2 , the input image may be output as feature maps of 4 channels having a size of 20x20 through a convolution operation with a weight. Thereafter, the size of the 20x20 feature maps may be reduced through iterative convolution with weights, and finally, features of 1x1 size may be output. The neural network 2 filters and outputs robust features that can represent the entire image from the input image by repeatedly performing convolutional operations and subsampling (or pooling) operations in several layers, and input through the output final features. Image recognition results can be derived.

3 is a diagram for describing a relationship between an input feature map and an output feature map in a neural network according to an embodiment.

Referring to FIG. 3 , in a certain layer 3 of the neural network, a first feature map FM1 may correspond to an input feature map, and a second feature map FM2 may correspond to an output feature map. The feature map may mean a data set in which various features of input data are expressed. The feature maps FM1 and FM2 may have elements of a two-dimensional matrix or elements of a three-dimensional matrix, and a pixel value may be defined in each element. The feature maps FM1 and FM2 have a width W (or called a column), a height H (or called a row) and a depth D. In this case, the depth D may correspond to the number of channels.

A convolution operation may be performed on the first feature map FM1 and the weight, and as a result, the second feature map FM2 may be generated. The weight filters features of the first feature map FM1 by performing a convolution operation with the first feature map FM1. The weight performs a convolution operation with windows (also referred to as tiles) of the first feature map FM1 while shifting the first feature map FM1 in a sliding window manner. During each shift, the weight may be multiplied and added to each of the pixel values of the overlapped window in the first feature map FM1 . As the first feature map FM1 and the weight are convolved, one channel of the second feature map FM2 may be generated. Although one weight is illustrated in FIG. 2 , in reality, a plurality of weights may be respectively convolved with the first feature map FM1 to generate a second feature map FM2 of a plurality of channels.

Meanwhile, the second feature map FM2 may correspond to an input feature map of a next layer. For example, the second feature map FM2 may be an input feature map of a pooling (or subsampling) layer.

2 and 3 show only the schematic architecture of the neural network 2 for convenience of description. However, it is known in the art that the neural network 2 may be implemented with a larger or smaller number of layers, feature maps, weights, etc. It can be understood by those skilled in the art.

4A to 4B are diagrams for comparing vector-matrix multiplication and an operation performed in a crossbar array according to an exemplary embodiment.

First, referring to FIG. 4A , a convolution operation between an input feature map and a weight may be performed using vector-matrix multiplication. For example, pixel data of the input feature map may be represented by a matrix X 410 , and weight values may be represented by a matrix W 411 . Pixel data of the output feature map may be expressed as a matrix Y 412 that is a result of a multiplication operation between the matrix X 410 and the matrix W 411 .

Referring to FIG. 4B , a vector multiplication operation may be performed using a nonvolatile memory device of a crossbar array. Referring to FIG. 4A , pixel data of the input feature map may be received as an input value of the nonvolatile memory device, and the input value may be a voltage 420 . Also, the weight values may be stored in a synapse of the nonvolatile memory device, that is, a memory cell, and the weight values stored in the memory cell may be a conductance 421 . Accordingly, the output value of the nonvolatile memory device may be expressed as a current 422 that is a result of a multiplication operation between the voltage 420 and the conductance 421 .

5 is a diagram for explaining an example in which a convolution operation is performed in a crossbar array according to an embodiment.

The crossbar array 500 may receive pixel data of the input feature map 510 . The crossbar array 500 may include a plurality of nonvolatile memory devices.

In an embodiment, when the crossbar array 500 is an NxM matrix (N and M are natural numbers greater than or equal to 2), the number of pixel data of the input feature map 510 is the number of columns M of the crossbar array 500 . may be less than or equal to Pixel data of the input feature map 510 may be a parameter in a floating-point format or a fixed-point format. Meanwhile, in another embodiment, the number of pixel data of the input feature map 510 may be greater than the number of columns M of the crossbar array 500 , which will be described in detail with reference to FIG. 6 .

The digital analog converter (DAC) 520 may receive pixel data in the form of a digital signal and convert it into a voltage in the form of an analog signal. Pixel data of the input feature map 510 may have various bit resolution values such as 1-bit, 4-bit, and 8-bit resolution. In an embodiment, the crossbar array 500 may convert pixel data into a voltage using the DAC 520 , and then receive the voltage 501 as an input value of the crossbar array 500 .

In addition, learned weight values may be stored in each of the plurality of nonvolatile memory devices included in the crossbar array 500 . The weight values may be stored in a memory cell of the nonvolatile memory device, and the weight values stored in the memory cell may be a conductance 502 . In this case, the crossbar array 500 may calculate an output value by performing a vector multiplication operation between the voltage 501 and the conductance 502 , and the output value may be expressed as a current 503 . That is, the crossbar array 500 may output the same result value as a result of a convolution operation between the input feature map and the weight using a plurality of nonvolatile memory devices.

Since the current 503 output from the crossbar array 500 is an analog signal, an analog digital converter (ADC) 530 may be used to use the current 503 as input data of another crossbar array 550 . The current 503 output from the crossbar array 500 may be converted into a digital signal by the ADC 530 . By using the ADC 530 in an embodiment, the current 503 may be converted into a digital signal to have the same bit resolution as the pixel data of the input feature map 510 . For example, when pixel data of the input feature map 510 has 1-bit resolution, the current 503 may also be converted into a 1-bit resolution digital signal by the ADC 530 .

The activation unit 540 may apply an activation function to the digital signal converted by the ADC 530 . As the activation function, a sigmoid function, a Tanh function, and a Rectified Linear Unit (ReLU) function may be used, but the activation function applicable to the digital signal is not limited thereto.

The digital signal to which the activation function is applied may be used as an input value of another crossbar array 550 . When the digital signal to which the activation function is applied is used as an input value of another crossbar array 550 , the above-described process may be equally applied to other crossbar arrays 550 .

6 is a diagram for explaining an example in which a sub-feature map and a crossbar array are matched according to an embodiment.

The input feature map 610 used for learning and inference may have various sizes. Since the size of the crossbar array 600 is limited, the number of pixel data of a single input feature map 610 may be received from the crossbar array 600 . It can be more than the number of possible input values.

Referring to FIG. 6 , the size of the input feature map 610 is 8x8, and the size of the crossbar array 600 is 16x16. In this case, since the number of pixel data of the 8x8 input feature map 610 is 64 (=8x8), the number of input values that can be received by the crossbar array 600 is larger than 16.

When the number of pixel data of the input feature map 610 is greater than the number of input values of the crossbar array 600 , that is, the number of rows m, the input feature map 610 may be divided into sub-feature maps 611 . have. Based on the size information of the crossbar array 600 , the input feature map 610 may be divided into sub feature maps 611 .

Specifically, when the size of the input feature map 610 is 8x8 and the size of the crossbar array 600 is 16x16, the input feature map 610 has 4 sub-features so that the number of pixel data of each of the sub-feature maps is 16. It can be divided into maps. Each of the divided sub-feature maps may be matched to the crossbar array 600 .

For example, the crossbar array 600 may receive 'aa' of the sub-feature map 610 as a first input value 'V1', and receive 'ab' of the sub-feature map 610 as a second input value ' V2' may be received, and 'dd' of the sub-feature map 610 may be received as a sixteenth input value 'V16'.

Meanwhile, as described above in FIG. 5 , the pixel data of the sub feature map 610 may be a digital signal (eg, 1 bit, 4 bits, etc.), and the pixel data of the sub feature map 610 is DAC ( _{After being converted into analog voltage signals (V 1} to V ₁₆ ) through a digital-to-analog converter), it may be input to the crossbar array 600 .

_{Also, the currents I 1} to I ₁₆ output from the crossbar array 600 may be analog signals, and the currents I ₁ to I ₁₆ may pass through an analog digital converter (ADC) to be converted into a digital signal.

7A to 7B are side views illustrating a phototransistor and a nonvolatile memory device having memory characteristics according to an exemplary embodiment.

The nonvolatile memory devices 710 and 720 may include resistance change layers 715 and 725 . Gates 713 and 723 may be positioned above or below the resistance change layers 715 and 725 . Gate oxide layers 714 and 724 may be formed between the resistance change layers 715 and 725 and the gates 713 and 723 . In addition, the sources 711 and 721 and the drains 712 and 722 are formed on the resistance change layers 715 and 725 and may be spaced apart from each other.

Hereinafter, when light is irradiated to the resistance change layers 715 and 725, it is assumed that an off-voltage is applied to the gates 713 and 723, and a detailed description thereof will be described later in FIG. 8 . do it with

The resistance values of the resistance change layers 715 and 725 may be changed based on the illumination of the light irradiated to the resistance change layers 715 and 725 and may be maintained at the changed resistance values.

Specifically, as light is irradiated to the resistive layers 715 and 725 , charges (electrons or holes) may be trapped in defects inside the resistive layers 715 and 725 . As electric charges are trapped in the defects inside the resistive layers 715 and 725, the resistance values of the resistive layers 715 and 725 are changed, and thereafter, even if light is no longer irradiated to the resistive layers 715 and 725, the resistance The resistance values of the change layers 715 and 725 may be maintained at the changed values.

As the illuminance of the light irradiated to the resistive layers 715 and 725 increases, the resistance values of the resistive layers 715 and 725 may decrease in width. Specifically, as the illuminance of the light irradiated to the resistive layers 715 and 725 increases, the charge trapped in the defects inside the resistive layers 715 and 725 may increase. When the charge trapped inside the resistive layers 715 and 725 increases, the resistance values of the resistive layers 715 and 725 may decrease.

In an embodiment, the light irradiated to the resistance change layers 715 and 725 may be light in the visible ray region. The resistance change layers 715 and 725 are formed of a material to be described later, so that even when light in the visible region, not high energy light such as UV (ultra violet), is irradiated to the resistance change layers 715 and 725, the resistance change layer The resistance value of (715, 725) can be changed.

In an embodiment, the resistive layers 715 and 725 may be formed of a 2D (2 Dimension) material. The resistance change layers 715 and 725 may be formed of a single-layered 2D material or a multi-layered 2D material. For example, the resistance change layers 715 and 725 may be formed of at least one selected from the group consisting of Transition Metal Dichalcogenide (TMD), Black Phosphorus (Phosphorene), and Grephene. TMD is, for example, MoS ₂ , MoSe ₂ , MoTe ₂ , WS ₂ , WSe ₂ , WTe ₂ , TaS ₂ , TaSe ₂ , TiS ₂ , TiSe ₂ , ZrS ₂ , ZrSe ₂ , HfS ₂ , HfSe ₂ , SnS ₂ , SnSe ₂ , GeS ₂ , GeSe ₂ , _{GaS 2} , GaSe ₂ , GaSe, GaTe, InSe, In ₂ Se ₃ , Bi ₂ S ₃ , Bi ₂ Se ₃ and Bi ₂ Te ₃ at least one selected from the group consisting of may include

In another embodiment, the resistive layers 715 and 725 may be formed of a 3 dimensional (3D) material. For example, the resistance change layers 715 and 725 may include at least one selected from the group consisting of Germanane, Silicene, III-V, and IGZO.

In one embodiment, the gate oxide layers 714 and 724 may be formed as a single layer. For example, the gate oxide layers 714 and 724 may be formed of a single layer of aluminum oxide.

In other embodiments, the gate oxide layers 714 and 724 may be formed in multiple layers. The multi-layered gate oxide layers 714 and 724 may include a charge trapping layer. For example, the multi-layered gate oxide layers 714 and 724 may include a charge trapping layer between two aluminum oxide layers. The charge trapping layer may include, but is not limited to, hafnium oxide or silicon nitride.

Referring to FIG. 7A , an inactive memory device 710 using a back-gate 713 is illustrated. The back-gate 713 may be positioned under the resistance change layer 715 . For example, the back-gate 713 may be implemented in any suitable technology, such as a Silicon On Insulator (SOI) substrate.

The gate oxide layer 714 may be disposed under the resistive layer 715 , and may be positioned between the resistive layer 715 and the back-gate 713 .

Referring to FIG. 7B , an inactive memory device 720 using a transparent conductive electrode (TCE) gate 723 is illustrated. The TCE gate 723 may be positioned on the resistance change layer 725 .

As light is irradiated to the resistive layer 725 through the upper portion of the resistive layer 725 , the light hits the TCE gate 723 before the resistive layer 725 . The inactive memory device 720 uses the TCE gate 723 through which light can pass, so that light can reach the resistive layer 725 through the upper portion of the resistive layer 725 .

The gate oxide layer 724 may be disposed on the resistive layer 725 , and may be positioned between the resistive layer 725 and the TCE gate 723 .

FIG. 8 is a diagram for explaining a phenomenon in which a resistance value of a nonvolatile memory device varies depending on before and after light is irradiated, according to an exemplary embodiment.

The nonvolatile memory device may include a resistance change layer. A gate may be positioned above or below the resistance change layer. A gate oxide layer may be formed between the resistance change layer and the gate. In addition, the source and the drain may be formed on the resistance change layer and spaced apart from each other.

When an off-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may operate as a phototransistor and a device having memory characteristics. Hereinafter, it is assumed that the nonvolatile memory device is nmos, but it is apparent to those skilled in the art that the nonvolatile memory device can be implemented with various types of field effect transistors (FETs).

Claim a graph showing a first graph 810, the current (I _S) which is detected from the source of the nonvolatile memory element according to the non-volatile memory before the light is irradiated to the device, the gate voltage (V _G).

Claim a graph showing a current (I _S) which is detected from the source of non-volatile memory device according to the second graph 820, the gate voltage (V _G) after the light irradiation to the non-volatile memory device.

In the first graph 810 and the second graph 820 , it is assumed that a predetermined voltage V _D is applied to the drain of the nonvolatile memory device.

By trapping a charge in a defect inside the resistance change layer of the nonvolatile memory device, _{a current (IS} ) of a constant value is detected from the source even when _{the gate voltage (V G ) of the nonvolatile memory device is off-voltage.} can be

As light is irradiated to the resistive layer of the nonvolatile memory device, more charges are trapped in the defect, thereby reducing the resistance value of the resistive layer. After that, even if light is no longer irradiated to the resistance change layer, the resistance value of the resistance change layer may be maintained at a reduced value.

Referring to the first graph 810 , when an off-voltage is applied to the gate of the nonvolatile memory device, the current detected from the source is I ₁ .

Referring to the second graph 820 showing after light is irradiated to the nonvolatile memory device, when an off-voltage is applied to the gate of the nonvolatile memory device, the current detected from the source increases from I _{1 to I 2 .} can As light is irradiated to the resistive layer of the nonvolatile memory device, the resistance value of the resistive layer is decreased, and accordingly, a current detected from the source of the nonvolatile memory device may increase. Thereafter, even if light is no longer irradiated to the resistance change layer of the nonvolatile memory device, the resistance value of the resistance change layer may be maintained at the changed value, and when an off-voltage is applied to the gate of the nonvolatile memory device, the The detected current may also be maintained as _{I 2 .}

In an embodiment, as the illuminance of light irradiated to the resistance change layer of the nonvolatile memory device increases, charges trapped inside the resistance change layer increase, and thus the resistance value of the resistance change layer may decrease. As a result, the current detected from the source of the nonvolatile memory device may increase more than _{I 2 .}

Meanwhile, when an on-voltage greater than or equal to a threshold value is applied to the gate of the nonvolatile memory device, the resistance value of the resistance change layer of the nonvolatile memory device may be reset. For example, a voltage of 7V may be applied to the gate for 10 seconds to reset the resistance value of the resistance change layer.

Specifically, when the source current increases from I _{1 to I 2} under the off-voltage of the gate as light is irradiated to the resistance change layer of the nonvolatile memory device, an on-voltage greater than or equal to the threshold value is applied to the gate of the nonvolatile memory device. , the source current can decrease back _{from I 2} to I _{1 .}

9A to 9B are exemplary views for explaining a process of storing an image using a crossbar array including a plurality of non-volatile memory devices and acquiring the stored image, according to an exemplary embodiment.

9A to 9B, it is assumed that the image 910 has a size of 4x4 and the crossbar array 900 has a size of 4x4, but the sizes of the image 910 and the crossbar array 900 are variously modified. It can be understood by those of ordinary skill in the art.

The crossbar array 900 may include a plurality of nonvolatile memory devices. In FIGS. 9A to 9B , the nonvolatile memory device is represented by positions (a, b) of synapses where rows and columns of the crossbar array 900 intersect.

Referring to FIG. 9A , an image may be stored using a crossbar array 900 including a plurality of nonvolatile memory devices.

In order to store an image using the crossbar array 900 , an off-voltage may be applied to the gates of the plurality of nonvolatile memory devices, and a drain voltage V _D may be applied to the drains.

In order to change the resistance value of the resistance change layer of each of the plurality of non-volatile memory devices, light of an illuminance corresponding to the image 910 may be irradiated to each of the plurality of non-volatile memory devices.

Specifically, light of an illuminance corresponding to each of the plurality of pixels P ₁₁ to P ₁₄ , P ₂₁ to P _{24 ,} P ₃₁ to P _{34 , and} P ₄₁ to P _{44 included in the image 910 emits a plurality of ratios.} Each of the volatile memory devices may be irradiated. For example, _{light having an illuminance corresponding to P 11} of the image 910 is irradiated to the non-volatile memory device 1,1, and _{light having an illuminance corresponding to P 21} of the image 910 is applied to the non-volatile memory device ( 2,1), the light of illuminance corresponding to _{P 32} of the image 910 is irradiated to the nonvolatile memory device 3,2, and the light of illuminance corresponding to _{P 44 of the image 910 is not} It can be irradiated to the volatile memory element (4,4).

The brightness of each of the plurality of pixels included in the image 910 may be different from each other, and accordingly, the illuminance of light irradiated to each of the plurality of nonvolatile memory devices may also be different from each other. As a result, the degree to which the resistance value of the resistance change layer of each of the plurality of nonvolatile memory devices changes may be different from each other. Even when light is no longer irradiated to the plurality of nonvolatile memory devices, the resistance value of the resistance change layer may be maintained as a changed value.

That is, the resistance value of each of the plurality of non-volatile memory devices is changed according to the brightness of each of the plurality of pixels included in the image 910 , and even when light is no longer irradiated, the resistance values of the plurality of non-volatile memory devices are Since the changed value is maintained, the image 910 may be stored in the crossbar array 900 .

_{Meanwhile, R 11} to R ₁₄ , R ₂₁ to R _{24 ,} R ₃₁ to R _{34 , and} R ₄₁ to R ₄₄ displayed on the crossbar array 900 represent resistance values of each of the plurality of nonvolatile memory devices.

Referring to FIG. 9B , a stored image may be acquired using a crossbar array 900 including a plurality of nonvolatile memory devices.

In order to obtain an image stored in the crossbar array 900 , a gate-off voltage may be applied to each row of the crossbar array 900 . In the crossbar array 900 of FIG. 9B , the nonvolatile memory device to which the gate off-voltage is applied is indicated by a circle.

_{Specifically, to obtain pixels P 11} to P ₁₄ included in the first row of the image 910 , a gate-off voltage may be applied to the first row 901a of the crossbar array 900 . In this case, a gate-on-voltage may be applied to the second to fourth rows 901b to 901d.

_{Each of the source currents I S11} to I _S14 obtained for each column of the crossbar array 900 may be determined according _{to the resistance values R 11} to R ₁₄ of the nonvolatile memory devices (1,1) to (1,4). Meanwhile, the resistance values R ₁₁ to R ₁₄ of the nonvolatile memory device are values determined according to the illuminance of light corresponding _{to the pixels P 11} to P ₁₄ included in the first row of the image 910 . _{Accordingly, the pixels P 11} to P ₁₄ included in the first row of the image 910 may be obtained _{using the source currents I S11} to I _S14 obtained for each column of the crossbar array 900 .

In a similar manner, by applying a gate off-voltage to each of the second to fourth rows 901b to 901d of the crossbar array 900 and a gate on-voltage to the remaining rows, the second row of the image 910 The pixels included in the to fourth rows may be sequentially obtained.

In an embodiment, a color image may be obtained from the crossbar array 900 by sequentially disposing color filters on the crossbar array 900 .

For example, a color image may be obtained from the crossbar array 900 using three color filters of red, green, and blue.

Specifically, first, after disposing a red color filter on the crossbar array 900 , light having an illuminance corresponding to each of a plurality of pixels included in a color image may be irradiated to each of the plurality of nonvolatile memory devices. A red image may be acquired by applying a gate-off voltage to each row of the crossbar array 900 and acquiring a source current for each column of the crossbar array 900 .

After resetting by applying a gate-on voltage to the crossbar array 900 , a green image and a blue image may be obtained by repeating the above-described operation using the green color filter and the blue color filter. After the red image, the green image, and the blue image are obtained, a color image may be finally obtained by synthesizing the three images.

The crossbar array 900 including a plurality of non-volatile memory elements according to the present disclosure may have a photoconductivity (PC) characteristic, and may be utilized in an imaging mode (storing/acquiring an image) due to this characteristic. have.

10 is an exemplary diagram for explaining a process of performing a pulling operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to an embodiment.

In FIG. 10 , it is assumed that the image 1010 has a size of 8x8 and the crossbar array 1000 has a size of 16x16. It can be understood by those of ordinary skill in the art. For example, the image 1010 may be an image representing any one of the numbers '1' to '9', but is not limited thereto.

In one embodiment, the window 1011 may be shifted by a predetermined stride interval on the image 1010 . The size of the window 1011 may be determined based on the size of the crossbar array 1000 . In an embodiment, the size of the window 1011 may be determined based on the number of rows of the crossbar array 1000 . For example, when the number of rows of the crossbar array 1000 is 16, the size of the window 1011 may be 4x4.

Hereinafter, it is assumed that the window 1011 is shifted by an interval of '1 stride', and the size of the window 1011 is 4x4.

A plurality of pixels may be included in the window 1011 at each position on the image 1010 . For example, the window 1011 may include pixels of _{P 11} to P ₁₄ , P ₂₁ to P ₂₄ , P ₃₁ to P _{34 ,} and P ₄₁ to P _{44 at the first position.} Further, the window 1011 may include pixels of _{P 12} through P ₁₅ , P ₂₂ through P ₂₅ , P ₃₂ through P ₃₅ and P ₄₂ through P ₄₅ in the second position shifted right by one from the first position. can

For each column of the crossbar array 1000 , light having an illuminance corresponding to a plurality of pixels included in the window 1011 may be irradiated. For example, light of illuminance corresponding _{to the plurality of pixels P 11} to P ₁₄ , P ₂₁ to P ₂₄ , P ₃₁ to P ₃₄ and P ₄₁ to P ₄₄ included in the window 1011 at the first position The first column 1002a of the crossbar array 1000 may be irradiated. That is, light having an illuminance corresponding to each of the 16 pixels included in the window 1011 at the first position may be irradiated to each of the 16 nonvolatile memory devices included in the first column 1002a.

In the same manner, light having an illuminance corresponding to the plurality of pixels included in the window 1011 at the n-th position may be irradiated to the n-th column of the crossbar array 1000 .

A gate-off voltage may be applied to the first to sixteenth rows 1001a to 1001p of the crossbar array 1000 . _{Also, drain voltages V 0} to V ₁₅ may be applied to the first to sixteenth rows 1001a to 1001p of the crossbar array 1000 . The drain voltages V ₀ to V ₁₅ may be a mask used for a pooling operation.

By acquiring a source current for each column of the crossbar array 1000 , a pooling operation may be performed. Specifically, the first-first source current I _{S11 obtained from the first column 1002a is a plurality of pixels P 11} to P ₁₄ , P ₂₁ to P ₂₄ included in the window 1011 at the first position. , P ₃₁ to P ₃₄ and P ₄₁ to P ₄₄ ).

In the same manner, the 1-2th source currents to the 1-5th source currents I _S12 to I _S15 obtained from the second column to the fifth column 1002b to 1002e are the windows ( 1011 ) may be a pooling result for a plurality of pixels included in FIG.

Meanwhile, since the window 1011 may be located in a total of 25 places on the image 1010 , a pooling result for a plurality of pixels included in the window 1011 at the first to 25th positions is obtained through the above-described method. By doing so, the pooling operation of the neural network can be completed.

The crossbar array 1000 including a plurality of non-volatile memory devices according to the present disclosure may perform a vector matrix operation (eg, a pooling operation), and using this characteristic, the crossbar array 1000 is an in-memory It can be utilized for (in-memory) computing.

11 is an exemplary diagram for explaining a process of performing a convolution operation of a neural network using a crossbar array including a plurality of nonvolatile memory devices according to an embodiment.

A plurality of weights included in a specific layer of a neural network may be stored in the crossbar array 1000 . The plurality of weights may be stored in the crossbar array 1000 by irradiating each of the plurality of nonvolatile memory devices of the crossbar array 1000 with light having an illuminance corresponding to each of the plurality of weights included in a specific layer. Since the specific method overlaps with that of FIG. 9A, it will be omitted here.

In an embodiment, a fully-connected convolution operation may be performed using the crossbar array 1000 . In FIG. 11 , a fully-connected convolution operation for recognizing the image 1010 of FIG. 10 is performed. For example, using the crossbar array 1000 , a fully-connected convolution operation for determining which of the numbers 1 to 9 corresponds to the image 1010 may be performed.

First, in order to perform a fully-connected convolution operation, the crossbar array 1000 may be reset.

A drain voltage of the crossbar array 1000 may correspond to an input value of the pulley-connected layer. _{The first to fifth source currents I S11} to I _S15 corresponding to the windows 1011 at the first to fifth positions obtained from the crossbar array 1000 are the pulley-connected layers. may correspond to an input value of .

Specifically, the 1-1th source currents to the 1-5th source currents I _S11 to I _S15 may be converted into the first drain voltages to the fifth drain voltages V _D11 to V _{D15 .} Also, each of the first to fifth drain voltages V _D11 to V _D15 may be applied to the first to fifth rows 1001a to 1001e.

By acquiring the source current for each column of the crossbar array 1000 , the image 1010 may be recognized. Specifically, the second-first source current I ₁₁ obtained from the first column 1002a represents the probability that the image 1010 corresponds to the number '1'. In addition, in each of the 2-2nd source current to 2-9th source current I ₁₂ to I ₁₉ obtained from the second column to the ninth column 1002b to 1002i, the image 1010 is a number '2' to It represents the probability of '9'.

On the other hand, the window 1011 on the image 1010 may be located in a total of 25 places, the 2-1 source current to the 2-9 source current (I ₁₁ to I ₁₉ ) obtained from the crossbar array 1000, The pulley-connected operation result for the window 1011 at the first to fifth positions is nothing but a result. That is, the image 1010 may be finally recognized by obtaining a fully-connected operation result for the window 1011 at the remaining positions on the image 1010 .

By repeating the above-described process, the first to ninth columns 1002a to 1002i from the crossbar array 1000 based on 25 source currents corresponding to the windows 1011 at the first to 25th positions. Second-first to second-ninth source currents I ₁₁ to I ₁₉ may be obtained.

_{The 2-1 source currents to the 2-9th source currents I 11} to I ₁₉ obtained from the first to ninth columns 1002a to 1002i of the crossbar array 1000 indicate that the image 1010 is a number '1'. It may represent a probability corresponding to ' to '9'. The image 1010 may be finally recognized as a number having the highest probability value among numbers '1' to '9'. For example, when the value of the 2-1 th source current I ₁₁ is the largest, the image 1010 may be finally recognized as the number '1'.

Meanwhile, a plurality of weights included in a specific layer of the neural network may be updated as learning of the neural network progresses. When the weights are updated, after resetting the crossbar array 1000 , by irradiating light of an illuminance corresponding to each of the updated weights to each of the plurality of nonvolatile memory elements, the updated weights in the crossbar array 1000 are can be saved. The crossbar array 1000 may be widely used in learning and reasoning of a neural network.

The crossbar array 1000 including a plurality of non-volatile memory devices according to the present disclosure may perform vector matrix operation, and the crossbar array 1000 uses this characteristic to learn and reason for image recognition. can be used in the process.

In one embodiment, a crossbar array utilized in imaging mode (image storage/acquisition) may be utilized in recognition mode (neural network learning/inference) after being reset, whereby one crossbar array is used in both imaging mode and recognition mode can be utilized.

12 is a flowchart illustrating a method of performing a predetermined operation using a crossbar array according to an exemplary embodiment. 12, the method of performing a predetermined operation, as it relates to the embodiments described in the above-described drawings, even if omitted below, the contents described in the drawings are also in the method of FIG. can be applied.

A crossbar array to be described below may include a plurality of nonvolatile memory devices. The nonvolatile memory device may include a resistance change layer. A gate may be positioned above or below the resistance change layer. A gate oxide layer may be formed between the resistance change layer and the gate. In addition, the source and the drain may be formed on the resistance change layer and spaced apart from each other.

Referring to FIG. 12 , in operation 1210 , the processor may apply an off-voltage to the gates of each of the plurality of nonvolatile memory devices.

When an off-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may operate as a phototransistor and a device having memory characteristics. The gate off-voltage may be -6V, but is not limited thereto.

Meanwhile, when an on-voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device may be reset.

In operation 1220 , the processor may irradiate light of an illuminance corresponding to each of the plurality of elements to each of the plurality of non-volatile memory elements in order to change the resistance value of the resistance change layer of each of the plurality of non-volatile memory elements. .

The resistance value of the resistance change layer may be changed based on the illuminance of light irradiated to the resistance change layer, and may be maintained at the changed resistance value. Specifically, as light is irradiated to the resistance change layer, the resistance value of the resistance change layer is changed by trapping electric charges on defects inside the resistance change layer, and then the resistance change even if the light is no longer irradiated to the resistance change layer. The resistance value of the layer may be maintained at a changed value.

As the illuminance of the light irradiated to the resistance change layer increases, the decrease in the resistance value of the resistance change layer may increase. Specifically, as the illuminance of light irradiated to the resistance change layer increases, the charge trapped in the defect inside the resistance change layer may increase. If the charge trapped inside the resistive layer increases, the resistance value of the resistive layer may decrease.

In one embodiment, the resistive layer may be formed of a 2D material. For example, the resistance change layer may be formed of at least one selected from the group consisting of Transition Metal Dichalcogenide (TMD), Phosphorene (Black Phosphorus), and Grephene.

Also, the resistive layer may be formed of a 3D material. For example, the resistance change layer may include at least one selected from the group consisting of Germanane, Silicene, III-V, and IGZO.

In operation 1230, the processor may perform a predetermined operation by applying a gate-off voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array.

In one embodiment, the processor may acquire the image using the crossbar array. In this case, the plurality of elements may be a plurality of pixels included in the image.

Light having an illuminance corresponding to each of the plurality of pixels included in the image may be irradiated to each of the plurality of nonvolatile memory devices. The processor may acquire an image by applying a gate-off voltage for each row of the crossbar array and acquiring a source current for each column of the crossbar array.

Also, by sequentially arranging color filters on the crossbar array, a color image can be obtained from the crossbar array.

In an embodiment, the processor may perform an operation of the neural network using the crossbar array. In this case, the plurality of elements may be a plurality of weights included in a specific layer of the neural network.

Light having an illuminance corresponding to each of a plurality of weights included in a specific layer of the neural network may be irradiated to each of the plurality of nonvolatile memory devices. The processor may perform a neural network operation by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array. For example, the operation of the neural network may include, but is not limited to, a pooling operation, a convolution operation, and a fully-connected convolution operation.

In the present disclosure, an image may be stored using a crossbar array or a stored image may be acquired from the crossbar array. In addition, in the present disclosure, an image may be recognized by performing a neural network operation using a crossbar array.

13 is a block diagram illustrating a memory system according to an exemplary embodiment.

Referring to FIG. 13 , the memory system 1300 may include a processor 1310 and at least one crossbar array 1320 . The processor 1310 performs a control operation on the crossbar array 1320 , and as an example, the processor 1310 provides an address ADD and a command CMD to the crossbar array 1320 , thereby providing the crossbar array 1320 . It is possible to perform data storage, reading, and erasing operations for the . Also, data for storage and reading may be transmitted/received between the processor 1310 and the crossbar array 1320 .

The crossbar array 1321 may include a plurality of nonvolatile memory devices disposed in regions where a plurality of rows and a plurality of columns intersect. In an embodiment, the non-volatile memory device may include a resistance change layer. A gate may be positioned above or below the resistance change layer. A gate oxide layer may be formed between the resistance change layer and the gate. In addition, the source and the drain may be formed on the resistance change layer and spaced apart from each other.

The processor 1310 may include a storage/read control unit 1311 , a voltage control unit 1312 , and a data determination unit 1313 . However, it is apparent to those skilled in the art that the configuration included in the processor 1310 is merely an example, and some configurations may be excluded or other configurations may be further added.

The store/read controller 1311 may generate an address ADD and a command CMD for performing data storage, reading, and erasing operations on the crossbar array 1321 . Also, the voltage controller 1312 may generate a voltage control signal to control at least one voltage level used in the crossbar array 1320 . As an example, the voltage controller 1312 controls a voltage level applied to a row of the crossbar array 1321 to read data from the crossbar array 1321 or store data in the crossbar array 1321 . can create

Meanwhile, the data determining unit 1313 may perform a determination operation on data read from the crossbar array 1320 . For example, the data determining unit 1313 determines data read from the crossbar array 1321 to determine whether each of the plurality of nonvolatile memory elements included in the crossbar array 1321 is in an on state or an off state. can As an example of operation, when data is stored in the crossbar array 1321 , the data determining unit 1313 determines the data state of the plurality of nonvolatile memory devices included in the crossbar array 1321 using a predetermined read voltage. By doing so, it may be determined whether data storage is normally completed for the nonvolatile memory devices.

The present embodiments may also be implemented in the form of a recording medium including instructions executable by a computer, such as a program module executed by a computer. Computer-readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, computer-readable media may include both computer storage media and communication media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Communication media typically includes computer readable instructions, data structures, other data in modulated data signals, such as program modules, or other transport mechanisms, and includes any information delivery media.

Also, in this specification, "unit" may be a hardware component such as a processor or circuit, and/or a software component executed by a hardware component such as a processor.

The description of the present specification described above is for illustration, and those of ordinary skill in the art to which the content of this specification belongs will understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be able Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a dispersed form, and likewise components described as distributed may be implemented in a combined form.

The scope of the present embodiment is indicated by the following claims rather than the detailed description, and it should be construed as including all changes or modifications derived from the meaning and scope of the claims and their equivalents.

Claims (15)

A non-volatile memory device comprising:
a resistance switching layer;
a gate positioned above or below the resistance change layer;
a gate oxide layer formed between the resistance change layer and the gate; and
a source and a drain formed on the resistance change layer and spaced apart from each other; and
a plurality of color filters sequentially disposed on top;
including,
The resistance value of the resistance change layer is changed based on illumination of light irradiated through an upper portion of the resistance change layer and is maintained at the changed resistance value. The method of claim 1,
The gate is
A non-volatile memory device that is positioned on the resistance change layer and is a transparent conducting electrode (TCE) gate through which the irradiated light can pass. The method of claim 1,
The resistance change layer,
It is formed of a 2D material, wherein the 2D material includes at least one selected from the group consisting of transition metal dichalcogenide (TMD), phosphorene (black phosphorus), and graphene. 4. The method of claim 3,
The resistance change layer is a non-volatile memory device that is formed of a single layer or a multi-layer. The method of claim 1,
The resistance change layer,
It is formed of a 3D material, wherein the 3D material includes at least one selected from the group consisting of Germanane, Silicene, III-V and IGZO. The method of claim 1,
The nonvolatile memory device of claim 1 , wherein the gate oxide layer is formed in multiple layers, and the multiple layers include a charge trapping layer. The method of claim 1,
In a state in which an off-voltage is applied to the gate, the resistance value of the resistance change layer decreases as the illuminance of light irradiated through the upper portion of the resistance change layer increases. The method of claim 1,
and a resistance value of the resistance change layer is reset when an on-voltage is applied to the voltage of the gate. A method of performing a predetermined operation using a crossbar array including a plurality of non-volatile memory devices, the method comprising:
applying an off-voltage to the gates of each of the plurality of nonvolatile memory devices;
irradiating light of an illuminance corresponding to each of the plurality of elements to each of the plurality of non-volatile memory elements to change the resistance value of the resistance change layer of each of the plurality of non-volatile memory elements; and
performing the predetermined operation by applying a gate-off voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array;
including,
The investigation step is
shifting a window by a predetermined stride interval on an image, and irradiating light of an illuminance corresponding to a plurality of elements included in the window for each column of the crossbar array;
A method comprising 10. The method of claim 9,
The investigation step is
irradiating light of an illuminance corresponding to each of a plurality of pixels included in an image to each of the plurality of non-volatile memory devices;
including,
The step of performing the predetermined operation comprises:
acquiring the image by applying a gate-off voltage to each row of the crossbar array and acquiring a source current for each column of the crossbar array;
A method comprising 10. The method of claim 9,
The investigation step is
sequentially arranging a plurality of color filters on the non-volatile memory devices, and irradiating light of an illuminance corresponding to each of a plurality of pixels included in an image to each of the plurality of non-volatile memory devices;
including,
The step of performing the predetermined operation comprises:
acquiring intermediate images corresponding to each of the plurality of color filters by applying a gate-off voltage to each row of the crossbar array and acquiring a source current for each column of the crossbar array; and
obtaining a color image by synthesizing the intermediate images;
A method comprising 10. The method of claim 9,
The investigation step is
irradiating light of an illuminance corresponding to each of a plurality of weights included in a specific layer of a neural network to each of the plurality of non-volatile memory devices;
including,
The step of performing the predetermined operation comprises:
performing a vector matrix operation of the specific layer by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array;
A method comprising delete A method of recognizing an image using a crossbar array including a plurality of non-volatile memory devices, the method comprising:
applying an off-voltage to the gates of each of the plurality of nonvolatile memory devices;
shifting a window by a predetermined stride interval on an image and irradiating light of an illuminance corresponding to each of a plurality of pixels of the image included in the window for each column of the crossbar array;
performing a pooling operation by applying a gate-off-voltage to at least one row of the crossbar array and acquiring a first source current for each column of the crossbar array;
resetting the crossbar array by applying an on-voltage to the gates of each of the plurality of nonvolatile memory devices, and then applying an off-voltage;
irradiating light of an illuminance corresponding to each of a plurality of weights included in a specific layer of a neural network to each of the plurality of non-volatile memory devices;
Fully-connected convolution operation by applying a voltage corresponding to the first source current as a drain voltage to at least one row of the crossbar array and obtaining a second source current for each column of the crossbar array performing the steps; and
recognizing the image based on the second source current;
A non-volatile memory device comprising: A computer-readable recording medium recording a program for executing the method of claim 9 on a computer.

Images