JPWO2020085148A1 - Ceramic substrate - Google Patents

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JPWO2020085148A1
JPWO2020085148A1 JP2020553197A JP2020553197A JPWO2020085148A1 JP WO2020085148 A1 JPWO2020085148 A1 JP WO2020085148A1 JP 2020553197 A JP2020553197 A JP 2020553197A JP 2020553197 A JP2020553197 A JP 2020553197A JP WO2020085148 A1 JPWO2020085148 A1 JP WO2020085148A1
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浩 河野
河野  浩
孝友 緒方
孝友 緒方
間瀬 淳
淳 間瀬
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NGK Electronics Devices Inc
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Abstract

セラミック素地は、Al2O3、SiO2及びMnOを必須成分として含み、Mo及びCr2O3の少なくとも一方を任意成分として含む。セラミック素地において、Al2O3の含有量が、82.0質量%以上95.0質量%以下であり、SiO2の含有量が、3.0質量%以上8.0質量%以下であり、MnOの含有量が、2.0質量%以上6.0質量%以下であり、MoO3換算でのMoの含有量とCr2O3の含有量との合計が、4.0質量%以下であり、残部の含有量が、0.1質量%未満である。The ceramic substrate contains Al2O3, SiO2 and MnO as essential components, and at least one of Mo and Cr2O3 as an optional component. In the ceramic base, the content of Al2O3 is 82.0% by mass or more and 95.0% by mass or less, the content of SiO2 is 3.0% by mass or more and 8.0% by mass or less, and the content of MnO. However, the total content of Mo and Cr2O3 in terms of MoO3 is 4.0% by mass or less, and the remaining content is 4.0% by mass or less. It is less than 0.1% by mass.

Description

本発明は、セラミック素地に関する。 The present invention relates to a ceramic substrate.

特許文献1には、セラミック素地の一例として、90質量%以上のAlと、1〜6質量%のSiOと、Mn換算で2〜8質量%のMnAlと、2質量%以下のMoとを含む絶縁基板が開示されている。特許文献1に記載の絶縁基板では、強度の安定性改善のために、Mgを酸化物換算で0.1〜3質量%の割合で含むことが好ましいとされている。In Patent Document 1, as an example of the ceramic base material, 90% by mass or more of Al 2 O 3 , 1 to 6% by mass of SiO 2, and 2 to 8% by mass of Mn Al 2 O 4 in terms of Mn 2 O 3 An insulating substrate containing 2% by mass or less of Mo is disclosed. It is said that the insulating substrate described in Patent Document 1 preferably contains Mg in a proportion of 0.1 to 3% by mass in terms of oxide in order to improve the stability of strength.

特許文献2には、セラミック素地の一例として、主成分としてのAlと、3〜7.5質量%のSiOと、Mn換算で2〜5質量%のMnと、MgO換算で0.3〜0.7質量%のMgと、MoO換算で0.3〜0.7質量%のMoとを含む絶縁基板が開示されている。In Patent Document 2, as an example of the ceramic base material, Al 2 O 3 as a main component, SiO 2 of 3 to 7.5% by mass, Mn of 2 to 5% by mass in terms of Mn 2 O 3, and MgO An insulating substrate containing 0.3 to 0.7% by mass of Mg in terms of conversion and 0.3 to 0.7% by mass of Mo in terms of MoO is disclosed.

特許文献3には、AlをAl換算で89.0〜92.0質量%、SiをSiO換算で2.0〜5.0質量%、MnをMnO換算で2.0〜5.0質量%、MgをMgO換算で0〜2.0質量%、ZrをZrO換算で0.05〜2.0質量%含むセラミック素地が開示されている。In Patent Document 3, Al is 89.0 to 92.0% by mass in terms of Al 2 O 3 , Si is 2.0 to 5.0% by mass in terms of SiO 2 , and Mn is 2.0 to 5 in terms of MnO. .0 wt%, 0 to 2.0 wt% of Mg in terms of MgO, ceramic green body containing 0.05 to 2.0 wt% of Zr in terms of ZrO 2 is disclosed.

特許第4413224号公報Japanese Patent No. 4413224 特許第5784153号公報Japanese Patent No. 5784153 国際公開第2015/141099号International Publication No. 2015/141099

特許文献1〜3に記載のセラミック素地では、寸法ばらつきが生じやすいという問題がある。本発明者等は、鋭意検討した結果、主成分であるAlと、焼結助剤としてのSiO及びMnOと、着色剤としてのMo又は/及びCrとを除いた残部の含有量が寸法ばらつきに影響を与えているという新たな知見を得た。The ceramic substrates described in Patent Documents 1 to 3 have a problem that dimensional variation is likely to occur. As a result of diligent studies, the present inventors have made a balance excluding Al 2 O 3 which is the main component, SiO 2 and Mn O as sintering aids, and Mo or / and Cr 2 O 3 as colorants. We obtained a new finding that the content of is affecting the dimensional variation.

本発明は、寸法ばらつきを抑制可能なセラミック素地の提供を目的とする。 An object of the present invention is to provide a ceramic substrate capable of suppressing dimensional variation.

本発明に係るセラミック素地は、Al、SiO及びMnOを必須成分として含み、Mo及びCrの少なくとも一方を任意成分として含む。セラミック素地において、Alの含有量が、82.0質量%以上95.0質量%以下であり、SiOの含有量が、3.0質量%以上8.0質量%以下であり、MnOの含有量が、2.0質量%以上6.0質量%以下であり、MoO換算でのMoの含有量とCrの含有量との合計が、4.0質量%以下であり、残部の含有量が、0.1質量%未満である。The ceramic substrate according to the present invention contains Al 2 O 3 , SiO 2 and Mn O as essential components, and contains at least one of Mo and Cr 2 O 3 as optional components. In the ceramic substrate, the content of Al 2 O 3 is 82.0% by mass or more and 95.0% by mass or less, and the content of SiO 2 is 3.0% by mass or more and 8.0% by mass or less. the content of MnO is not more than 2.0 mass% to 6.0 mass%, the sum of the content of content and Cr 2 O 3 of Mo calculated as MoO 3 is 4.0 wt% or less Yes, the content of the balance is less than 0.1% by mass.

本発明によれば、寸法ばらつきを抑制可能なセラミック素地を提供することができる。 According to the present invention, it is possible to provide a ceramic substrate capable of suppressing dimensional variation.

実施形態に係る第1セラミックパッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the 1st ceramic package which concerns on embodiment. 実施形態に係る第2セラミックパッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the 2nd ceramic package which concerns on embodiment. 実施形態に係る第2セラミックパッケージのうち多層回路基板の構成を示す断面図である。It is sectional drawing which shows the structure of the multilayer circuit board in the 2nd ceramic package which concerns on embodiment.

(セラミック素地)
セラミック素地とは、セラミックス材料粉末をテープ状に成形したグリーンシートやセラミックス材料粉末を圧粉成形した成形体を焼結することによって得られる組成物である。本実施形態に係るセラミック素地は、水晶振動子などの振動子を封止するセラミックパッケージ、CMOSイメージセンサなどの半導体素子を封止するセラミックパッケージ、或いは、光半導体素子を封止するセラミックパッケージなどの各種セラミックパッケージに好適に用いられる。
(Ceramic base)
The ceramic base is a composition obtained by sintering a green sheet obtained by molding ceramic material powder into a tape or a compact formed by compacting ceramic material powder. The ceramic substrate according to the present embodiment is a ceramic package for sealing an oscillator such as a crystal oscillator, a ceramic package for encapsulating a semiconductor element such as a CMOS image sensor, or a ceramic package for encapsulating an optical semiconductor element. Suitable for various ceramic packages.

本実施形態に係るセラミック素地は、主成分としてのAl(アルミナ)と、焼結助剤としてのSiO(シリカ)及びMnO(酸化マンガン)とを必須成分として含む。The ceramic substrate according to the present embodiment contains Al 2 O 3 (alumina) as a main component and SiO 2 (silica) and MnO (manganese oxide) as sintering aids as essential components.

セラミック素地は、着色剤としてMo(モリブデン)及びCr(酸化クロム)の少なくとも一方を任意成分として含む。セラミック素地は、着色剤として、Moのみを含有していてもよいし、Crのみを含有していてもよいし、Mo及びCrの両方を含有していてもよいし、さらに、Mo及びCrの両方を含有していなくてもよい。セラミック素地が着色剤としてMoを含有する場合、Moの少なくとも一部は金属として存在していてもよいし、Moの少なくとも一部は酸化物の形態(例えば、MoO)で存在していてもよい。The ceramic substrate contains at least one of Mo (molybdenum) and Cr 2 O 3 (chromium oxide) as an optional component as a colorant. Ceramic green body, as a colorant, may contain only Mo, may contain only the Cr 2 O 3, may also contain both of Mo and Cr 2 O 3, Furthermore, it does not have to contain both Mo and Cr 2 O 3. When the ceramic substrate contains Mo as a colorant, at least a part of Mo may be present as a metal, or at least a part of Mo may be present in the form of an oxide (eg, MoO 3 ). good.

セラミック素地を構成する各成分の含有量は、以下の通りである。 The content of each component constituting the ceramic substrate is as follows.

・Al
82.0質量%以上95.0質量%以下
・SiO
3.0質量%以上8.0質量%以下
・MnO:
2.0質量%以上6.0質量%以下
・MoO換算でのMoの含有量とCrの含有量との合計:
4.0質量%以下
・残部:
0.1質量%未満
・ Al 2 O 3 :
82.0% by mass or more and 95.0% by mass or less ・ SiO 2 :
3.0% by mass or more and 8.0% by mass or less ・ MnO:
2.0% by mass or more and 6.0% by mass or less ・ Total of Mo content and Cr 2 O 3 content in terms of MoO 3:
4.0% by mass or less ・ Remaining:
Less than 0.1% by mass

このように、本実施形態に係るセラミック素地では、Al、SiO、MnO及び着色剤(Mo又は/及びCr)以外の残部の含有量が0.1質量%未満に抑えられているため、各成分が偏析することなく分散された状態で均一に焼結されている。そのため、本実施形態に係るセラミック素地では、寸法ばらつきが抑制されている。As described above, in the ceramic substrate according to the present embodiment, the content of the balance other than Al 2 O 3 , SiO 2 , MnO and the colorant (Mo or / and Cr 2 O 3 ) is suppressed to less than 0.1% by mass. Therefore, each component is uniformly sintered in a dispersed state without segregation. Therefore, in the ceramic substrate according to the present embodiment, dimensional variation is suppressed.

また、セラミック素地は、残部の含有量が0.1質量%未満に抑えられることによって、各成分が偏析することなく分散された状態で均一に焼結されるため、ガラス成分のフラックス中に低融点領域が局所的に発生することを抑制できる。そのため、セラミック素地が焼成セッターに貼り付くことを抑制できる。 Further, since the content of the balance of the ceramic base material is suppressed to less than 0.1% by mass, each component is uniformly sintered in a dispersed state without segregation, so that the content is low in the flux of the glass component. It is possible to suppress the local generation of the melting point region. Therefore, it is possible to prevent the ceramic base material from sticking to the firing setter.

さらに、セラミック素地は、残部の含有量が0.1質量%未満に抑えられることによって、各成分が偏析することなく分散された状態で均一に焼結されるため、焼成セッター側の裏側領域でガラス成分が溶融するタイミングを、焼成セッターと反対側の表側領域でガラス成分が溶融するタイミングに合わせることができる。そのため、セラミック素地が厚み方向に反ることを抑制できる。 Further, since the content of the balance of the ceramic base material is suppressed to less than 0.1% by mass, each component is uniformly sintered in a dispersed state without segregation, so that the ceramic base material is uniformly sintered in the back side region on the calcined setter side. The timing at which the glass component melts can be matched with the timing at which the glass component melts in the front region opposite to the firing setter. Therefore, it is possible to prevent the ceramic base material from warping in the thickness direction.

セラミック素地における残部の含有量は、0.05質量%未満がより好ましい。これによって、セラミック素地の寸法ばらつきを更に抑制できる。 The content of the balance in the ceramic substrate is more preferably less than 0.05% by mass. Thereby, the dimensional variation of the ceramic base material can be further suppressed.

セラミック素地における残部の含有量は、0質量%であることが特に好ましい。これによって、セラミック素地の寸法ばらつきを更に抑制できるだけでなく、セラミック素地が焼成セッターに貼り付くことを更に抑制できる。 The content of the balance in the ceramic substrate is particularly preferably 0% by mass. As a result, not only the dimensional variation of the ceramic base material can be further suppressed, but also the sticking of the ceramic base material to the firing setter can be further suppressed.

セラミック素地において、MnOの含有量に対するSiOの含有量の比は特に制限されないが、0.8以上3.5以下が好ましい。この範囲であれば、セラミック素地中にMnAlSi12が析出することを抑制できるため、MnAlSi12の析出に起因する色むらの発生を低減することができる。さらに、セラミック素地が、振動子又は半導体素子を封止するセラミックパッケージに適用される場合、MnOの含有量に対するSiOの含有量の比は、0.8以上2.1以下が特に好ましい。これにより、セラミック素地の曲げ強度を特に向上させることができる。一方、セラミック素地が、光半導体素子を封止するセラミックパッケージに適用される場合、MnOの含有量に対するSiO2の含有量の比は1.9以上3.5以下が特に好ましい。これにより、セラミック素地の曲げ強度は若干低下するものの、セラミック素地の比誘電率を8.0以上9.0以下に調整しやすくなる。In the ceramic substrate, the ratio of the content of SiO 2 to the content of MnO is not particularly limited, but is preferably 0.8 or more and 3.5 or less. Within this range, the precipitation of Mn 3 Al 2 Si 3 O 12 in the ceramic substrate can be suppressed, so that the occurrence of color unevenness due to the precipitation of Mn 3 Al 2 Si 3 O 12 can be reduced. .. Further, when the ceramic substrate is applied to a ceramic package for encapsulating a vibrator or a semiconductor element, the ratio of the content of SiO 2 to the content of MnO is particularly preferably 0.8 or more and 2.1 or less. Thereby, the bending strength of the ceramic base material can be particularly improved. On the other hand, when the ceramic substrate is applied to a ceramic package for encapsulating an optical semiconductor element, the ratio of the content of SiO2 to the content of MnO is particularly preferably 1.9 or more and 3.5 or less. As a result, although the bending strength of the ceramic base is slightly reduced, the relative permittivity of the ceramic base can be easily adjusted to 8.0 or more and 9.0 or less.

セラミック素地は、結晶相とガラス相とを含む。セラミック素地が着色剤としてMoを含有している場合、結晶相は、主結晶相としてのAl結晶相と、副結晶相としてのMo結晶相とを含む。結晶相は、Al結晶相及びMo結晶相以外の結晶相(以下、「残部の結晶相」という。)を含んでいてもよい。一方、セラミック素地が着色剤としてMoを含有しない場合、結晶相は、主結晶相としてのAl結晶相を含む。結晶相は、Al結晶相以外に残部の結晶相を含んでいてもよい。結晶相は、残部の結晶相として、1種の結晶相のみを含んでいてもよいし、複数種の結晶相を含んでいてもよい。The ceramic substrate contains a crystalline phase and a glass phase. When the ceramic substrate contains Mo as a colorant, the crystal phase includes an Al 2 O 3 crystal phase as a main crystal phase and a Mo crystal phase as a sub crystal phase. The crystal phase may include a crystal phase other than the Al 2 O 3 crystal phase and the Mo crystal phase (hereinafter, referred to as “remaining crystal phase”). On the other hand, when the ceramic substrate does not contain Mo as a colorant, the crystal phase contains an Al 2 O 3 crystal phase as a main crystal phase. The crystal phase may contain the remaining crystal phase in addition to the Al 2 O 3 crystal phase. The crystal phase may contain only one kind of crystal phase or a plurality of kinds of crystal phases as the remaining crystal phase.

ここで、セラミック素地を粉砕してX線回折パターンから結晶相を同定した場合、残部の結晶相のX線回折パターンのメインピーク強度は、Al結晶相のX線回折パターンのメインピーク強度に対して、0.5%以下であることが好ましい。これにより、残部の結晶相の存在によりガラス相に歪みが生じることを抑制できるため、セラミック素地の曲げ強度(いわゆる、抗折強度)を向上させることができる。Here, when the crystal phase is identified from the X-ray diffraction pattern by crushing the ceramic substrate, the main peak intensity of the X-ray diffraction pattern of the remaining crystal phase is the main peak of the X-ray diffraction pattern of the Al 2 O 3 crystal phase. It is preferably 0.5% or less with respect to the strength. As a result, it is possible to suppress the occurrence of distortion in the glass phase due to the presence of the remaining crystal phase, so that the bending strength (so-called bending strength) of the ceramic substrate can be improved.

セラミック素地の曲げ強度は、セラミック素地が適用されるセラミックパッケージに求められる特性に応じて設定される。例えば、セラミック素地が、振動子又は半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の曲げ強度は、700MPa以上が好ましい。また、セラミック素地が、光半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の曲げ強度は、390MPa以上が好ましい。本実施形態において、“曲げ強度”とは、3点曲げ強度を意味し、JISR1601(ファインセラミックスの曲げ試験方法)に準拠し室温にて測定した値である。 The bending strength of the ceramic substrate is set according to the properties required for the ceramic package to which the ceramic substrate is applied. For example, when the ceramic base is applied to a ceramic package for encapsulating a vibrator or a semiconductor element, the bending strength of the ceramic base is preferably 700 MPa or more. When the ceramic base is applied to a ceramic package for encapsulating an optical semiconductor element, the bending strength of the ceramic base is preferably 390 MPa or more. In the present embodiment, the "bending strength" means a three-point bending strength, and is a value measured at room temperature in accordance with JIS R1601 (bending test method for fine ceramics).

セラミック素地の比誘電率は、セラミック素地が適用されるセラミックパッケージに求められる特性に応じて設定される。例えば、セラミック素地が、振動子又は半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の比誘電率は特に制限されない。セラミック素地が、光半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の比誘電率は、8.0以上9.0以下が好ましい。 The relative permittivity of the ceramic substrate is set according to the characteristics required for the ceramic package to which the ceramic substrate is applied. For example, when the ceramic substrate is applied to a ceramic package for encapsulating a vibrator or a semiconductor element, the relative permittivity of the ceramic substrate is not particularly limited. When the ceramic base material is applied to a ceramic package for encapsulating an optical semiconductor element, the relative permittivity of the ceramic base material is preferably 8.0 or more and 9.0 or less.

セラミック素地の気孔率は、セラミック素地が適用されるセラミックパッケージに求められる特性に応じて設定される。例えば、セラミック素地が、振動子又は半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の気孔率は、3%以下が好ましい。また、セラミック素地が、光半導体素子を封止するセラミックパッケージに適用される場合、セラミック素地の気孔率は、3%以上8%以下が好ましい。本実施形態において、“気孔率”とは、研磨したセラミック断面を電子顕微鏡で撮影し、画像処理ソフトにより2値化して測定した値である。 The porosity of the ceramic substrate is set according to the properties required for the ceramic package to which the ceramic substrate is applied. For example, when the ceramic base is applied to a ceramic package for encapsulating a vibrator or a semiconductor element, the porosity of the ceramic base is preferably 3% or less. When the ceramic base is applied to a ceramic package for encapsulating an optical semiconductor element, the porosity of the ceramic base is preferably 3% or more and 8% or less. In the present embodiment, the "porosity" is a value measured by photographing a polished ceramic cross section with an electron microscope and binarizing it with image processing software.

(セラミックパッケージ)
ここで、本実施形態に係るセラミック素地を適用したセラミックパッケージの2つの構成例について、図面を参照しながら説明する。
(Ceramic package)
Here, two configuration examples of the ceramic package to which the ceramic substrate according to the present embodiment is applied will be described with reference to the drawings.

(1)第1セラミックパッケージ100
図1は、第1セラミックパッケージ100の断面図である。
(1) First ceramic package 100
FIG. 1 is a cross-sectional view of the first ceramic package 100.

第1セラミックパッケージ100は、絶縁基板1、複数の導体層2、メタライズ層3、水晶振動子4、CMOSイメージセンサ6、メッキ層8、及び蓋体10を備える。第1セラミックパッケージ100は、水晶振動子4及びCMOSイメージセンサ6を封止している。 The first ceramic package 100 includes an insulating substrate 1, a plurality of conductor layers 2, a metallized layer 3, a crystal oscillator 4, a CMOS image sensor 6, a plating layer 8, and a lid 10. The first ceramic package 100 seals the crystal oscillator 4 and the CMOS image sensor 6.

絶縁基板1は、上述したセラミック素地によって構成される。絶縁基板1を構成する各成分の含有量は、以下の通りである。 The insulating substrate 1 is made of the above-mentioned ceramic substrate. The content of each component constituting the insulating substrate 1 is as follows.

・Al
82.0質量%以上95.0質量%以下
・SiO
3.0質量%以上8.0質量%以下
・MnO:
2.0質量%以上6.0質量%以下
・MoO換算でのMoの含有量とCrの含有量との合計:
4.0質量%以下
・残部:
0.1質量%未満
・ Al 2 O 3 :
82.0% by mass or more and 95.0% by mass or less ・ SiO 2 :
3.0% by mass or more and 8.0% by mass or less ・ MnO:
2.0% by mass or more and 6.0% by mass or less ・ Total of Mo content and Cr 2 O 3 content in terms of MoO 3:
4.0% by mass or less ・ Remaining:
Less than 0.1% by mass

このように、本実施形態に係る絶縁基板1では、残部の含有量が0.1質量%未満に抑えられているため、各成分が偏析することなく分散された状態で均一に焼結されることによって、寸法ばらつきが抑制されている。絶縁基板1の曲げ強度は、700MPa以上が好ましい。絶縁基板1の気孔率は、3%以下が好ましい。 As described above, in the insulating substrate 1 according to the present embodiment, since the content of the remaining portion is suppressed to less than 0.1% by mass, each component is uniformly sintered in a dispersed state without segregation. As a result, dimensional variation is suppressed. The bending strength of the insulating substrate 1 is preferably 700 MPa or more. The porosity of the insulating substrate 1 is preferably 3% or less.

絶縁基板1は、底部1aと、側壁部1bとを有する。側壁部1bは、底部1aの外縁上に配置される。底部1aと側壁部1bは、一体的に形成されていてもよい。 The insulating substrate 1 has a bottom portion 1a and a side wall portion 1b. The side wall portion 1b is arranged on the outer edge of the bottom portion 1a. The bottom portion 1a and the side wall portion 1b may be integrally formed.

各導体層2は、底部1aを貫通するように設けられる。メタライズ層3は、側壁部1bの上面に配置される。メタライズ層3は、環状に形成される。メタライズ層3は、導体としてW又はMoを主成分とし、これにセラミック成分を若干添加することによって構成できる。また、本実施形態に係る絶縁基板1と上記メタライズ層3は、水素、窒素、水蒸気を含む還元雰囲気で同時焼成することによって作製される。 Each conductor layer 2 is provided so as to penetrate the bottom portion 1a. The metallized layer 3 is arranged on the upper surface of the side wall portion 1b. The metallized layer 3 is formed in a ring shape. The metallized layer 3 can be formed by using W or Mo as a main component as a conductor and adding a small amount of a ceramic component to the main component. Further, the insulating substrate 1 and the metallized layer 3 according to the present embodiment are produced by simultaneous firing in a reducing atmosphere containing hydrogen, nitrogen, and water vapor.

水晶振動子4は、振動子の一例である。水晶振動子4は、導電性接着剤5を介して導体層2に接続される。CMOSイメージセンサ6は、半導体素子の一例である。CMOSイメージセンサ6は、ワイヤボンディング7を介して導体層2に接続される。 The crystal oscillator 4 is an example of an oscillator. The crystal oscillator 4 is connected to the conductor layer 2 via the conductive adhesive 5. The CMOS image sensor 6 is an example of a semiconductor element. The CMOS image sensor 6 is connected to the conductor layer 2 via wire bonding 7.

メッキ層8は、メタライズ層3の上面に配置される。メッキ層8は、環状に形成される。蓋体10は、共晶Ag−Cuロウ材9を介して、メッキ層8上に配置される。蓋体10は、側壁部1bの開口を塞ぐ。蓋体10は、金属材料によって構成することができる。 The plating layer 8 is arranged on the upper surface of the metallize layer 3. The plating layer 8 is formed in an annular shape. The lid 10 is arranged on the plating layer 8 via the eutectic Ag-Cu brazing material 9. The lid 10 closes the opening of the side wall portion 1b. The lid body 10 can be made of a metal material.

(2)第2セラミックパッケージ200
図2は、第2セラミックパッケージ200の断面図である。
(2) Second ceramic package 200
FIG. 2 is a cross-sectional view of the second ceramic package 200.

第2セラミックパッケージ200は、基台11、電子冷却素子12、光半導体素子13、多層回路基板14、枠体15、シールリング16、蓋17、透光性窓部材18、パイプ19、光ファイバ接続管20a、及び光ファイバ20bを備える。第2セラミックパッケージ200は、光半導体素子13を封止する。第2セラミックパッケージ200は、いわゆる光モジュールである。 The second ceramic package 200 includes a base 11, an electronic cooling element 12, an optical semiconductor element 13, a multilayer circuit board 14, a frame body 15, a seal ring 16, a lid 17, a translucent window member 18, a pipe 19, and an optical fiber connection. A tube 20a and an optical fiber 20b are provided. The second ceramic package 200 seals the optical semiconductor element 13. The second ceramic package 200 is a so-called optical module.

基台11は、板状に形成される。基台11は、銅タングステンなどの熱伝導率の高い材料によって構成される。電子冷却素子12は、基台11上に配置される。光半導体素子13は、電子冷却素子12上に配置される。 The base 11 is formed in a plate shape. The base 11 is made of a material having high thermal conductivity such as copper tungsten. The electronic cooling element 12 is arranged on the base 11. The optical semiconductor element 13 is arranged on the electronic cooling element 12.

多層回路基板14は、基台11の外縁上に配置される。多層回路基板14には、パッケージ外部に露出する入力端子30a,30bと、パッケージ内部に露出する出力端子31a,31bとが設けられている。入力端子30aには、外部から正相信号が入力される。入力端子30bには、正相信号と逆相の逆相信号が入力される。入力端子30aに入力された正相信号は、ボンディングワイヤ13aを介して、出力端子31aから光半導体素子13に出力される。入力端子30bに入力された逆相信号は、ボンディングワイヤ13bを介して、出力端子31bから光半導体素子13に出力される。以下の説明では、正相信号と逆相信号とを合わせて差動信号と略称する。 The multilayer circuit board 14 is arranged on the outer edge of the base 11. The multilayer circuit board 14 is provided with input terminals 30a and 30b exposed to the outside of the package and output terminals 31a and 31b exposed to the inside of the package. A positive phase signal is input to the input terminal 30a from the outside. A positive phase signal and a negative phase negative phase signal are input to the input terminal 30b. The positive phase signal input to the input terminal 30a is output from the output terminal 31a to the optical semiconductor element 13 via the bonding wire 13a. The reverse phase signal input to the input terminal 30b is output from the output terminal 31b to the optical semiconductor element 13 via the bonding wire 13b. In the following description, the positive phase signal and the negative phase signal are collectively referred to as a differential signal.

枠体15は、多層回路基板14上に配置される。シールリング16は、枠体15の上面に配置される。シールリング16は、蓋17を溶接するための部材である。シールリング16及び蓋17のそれぞれは、ニッケル及びコバルトを鉄に配合したコバールなどによって構成することができる。 The frame body 15 is arranged on the multilayer circuit board 14. The seal ring 16 is arranged on the upper surface of the frame body 15. The seal ring 16 is a member for welding the lid 17. Each of the seal ring 16 and the lid 17 can be made of Kovar or the like in which nickel and cobalt are mixed with iron.

多層回路基板14と枠体15との間に形成された孔19aには、パイプ19が嵌め込まれる。パイプ19は、透光性窓部材18を収容する。透光性窓部材18は、サファイア、ガラスなどによって構成される。パイプ19には、光ファイバ接続管20aが接続される。パイプ19及び光ファイバ接続管20aのそれぞれは、コバールなどによって構成することができる。光ファイバ接続管20aには、光ファイバ20bが固定される。 The pipe 19 is fitted into the hole 19a formed between the multilayer circuit board 14 and the frame body 15. The pipe 19 accommodates the translucent window member 18. The translucent window member 18 is made of sapphire, glass, or the like. An optical fiber connecting pipe 20a is connected to the pipe 19. Each of the pipe 19 and the optical fiber connecting tube 20a can be configured by Kovar or the like. The optical fiber 20b is fixed to the optical fiber connecting tube 20a.

ここで、図3は、多層回路基板14の構成を示す分解斜視図である。 Here, FIG. 3 is an exploded perspective view showing the configuration of the multilayer circuit board 14.

多層回路基板14は、6層の回路基板14a〜14f、第1信号線21a,22a,23a、第2信号線21b,22b,23b、グランド層24a,24b,24c、グランドビア25a,25b,25c、及びグランド端子26a,26b,26cを備える。 The multilayer circuit board 14 includes 6-layer circuit boards 14a to 14f, first signal lines 21a, 22a, 23a, second signal lines 21b, 22b, 23b, ground layers 24a, 24b, 24c, ground vias 25a, 25b, 25c. , And ground terminals 26a, 26b, 26c.

各回路基板14a〜14fは、上述したセラミック素地によって構成される。各回路基板14a〜14fを構成する各成分の含有量は、以下の通りである。 Each circuit board 14a to 14f is composed of the above-mentioned ceramic substrate. The content of each component constituting each circuit board 14a to 14f is as follows.

・Al
82.0質量%以上95.0質量%以下
・SiO
3.0質量%以上8.0質量%以下
・MnO:
2.0質量%以上6.0質量%以下
・MoO換算でのMoの含有量とCrの含有量との合計:
4.0質量%以下
・残部:
0.1質量%未満
・ Al 2 O 3 :
82.0% by mass or more and 95.0% by mass or less ・ SiO 2 :
3.0% by mass or more and 8.0% by mass or less ・ MnO:
2.0% by mass or more and 6.0% by mass or less ・ Total of Mo content and Cr 2 O 3 content in terms of MoO 3:
4.0% by mass or less ・ Remaining:
Less than 0.1% by mass

このように、本実施形態に係る各回路基板14a〜14fでは、残部の含有量が0.1質量%未満に抑えられているため、各成分が偏析することなく分散された状態で均一に焼結されることによって、寸法ばらつきが抑制されている。各回路基板14a〜14fの比誘電率は、8.0以上9.0以下が好ましい。各回路基板14a〜14fの曲げ強度は、390MPa以上が好ましい。各回路基板14a〜14fの気孔率は、3%以上8%以下とすることができる。 As described above, in the circuit boards 14a to 14f according to the present embodiment, since the content of the balance is suppressed to less than 0.1% by mass, each component is uniformly baked in a dispersed state without segregation. By being tied, dimensional variation is suppressed. The relative permittivity of each of the circuit boards 14a to 14f is preferably 8.0 or more and 9.0 or less. The bending strength of each of the circuit boards 14a to 14f is preferably 390 MPa or more. The porosity of each of the circuit boards 14a to 14f can be 3% or more and 8% or less.

6層の回路基板14a〜14fは、この順で積層される。6層目の回路基板14fには、上述した入力端子30a,30bと出力端子31a,31bとが設けられる。 The six-layer circuit boards 14a to 14f are laminated in this order. The input terminals 30a and 30b and the output terminals 31a and 31b described above are provided on the sixth layer circuit board 14f.

第1信号線21a,22a,23aのうち入力側ビア接続部21aは、6層目の回路基板14fから3層目の回路基板14cまでを貫通するビア導体として構成され、第1入力端子30aと層間配線部22aの間を接続する。第1信号線21b,22b,23bのうち入力側ビア接続部21bは、6層目の回路基板14fから5層目の回路基板14eまでを貫通するビア導体として構成され、第2入力端子30bと層間配線部22bの間を接続する。 Of the first signal lines 21a, 22a, 23a, the input side via connection portion 21a is configured as a via conductor penetrating from the sixth layer circuit board 14f to the third layer circuit board 14c, and is configured as a via conductor with the first input terminal 30a. The interlayer wiring portion 22a is connected. Of the first signal lines 21b, 22b, 23b, the input side via connection portion 21b is configured as a via conductor penetrating from the sixth layer circuit board 14f to the fifth layer circuit board 14e, and is configured as a via conductor with the second input terminal 30b. Connect between the interlayer wiring portions 22b.

第1の信号線21a,22a,23aのうち出力側ビア接続部23aは、6層目の回路基板14fから3層目の回路基板14cまでを貫通するビア導体として構成され、第1出力端子31aと層間配線部22aの間を接続する。第2信号線21b,22b,23bのうち出力側ビア接続部23bは、6層目の回路基板14fから5層目の回路基板14eまでを貫通するビア導体として構成され、第2出力端子31bと層間配線部22bの間を接続する。 Of the first signal lines 21a, 22a, 23a, the output side via connection portion 23a is configured as a via conductor penetrating from the sixth layer circuit board 14f to the third layer circuit board 14c, and is configured as the first output terminal 31a. And the interlayer wiring portion 22a are connected. Of the second signal lines 21b, 22b, 23b, the output side via connection portion 23b is configured as a via conductor penetrating from the sixth layer circuit board 14f to the fifth layer circuit board 14e, and is configured with the second output terminal 31b. Connect between the interlayer wiring portions 22b.

2本の層間配線部22a,22bの間には、グランド層24bが配置される。層間配線部22aが設けられた1層目の回路基板14aには、グランド層24aが設けられる。層間配線部22bが設けられた5層目の回路基板14eには、グランド層24cが設けられる。 A ground layer 24b is arranged between the two interlayer wiring portions 22a and 22b. A ground layer 24a is provided on the first layer circuit board 14a provided with the interlayer wiring portion 22a. A ground layer 24c is provided on the fifth layer circuit board 14e provided with the interlayer wiring portion 22b.

グランド層24a,24b,24cは、導電性の金属電極を構成する。グランド層24a,24b,24cは、グランドビア25a,25b,25cを介して、6層目の回路基板14f上のグランド端子26a,26b,26cに接続される。 The ground layers 24a, 24b, 24c form a conductive metal electrode. The ground layers 24a, 24b, 24c are connected to the ground terminals 26a, 26b, 26c on the circuit board 14f of the sixth layer via the ground vias 25a, 25b, 25c.

以上の構成を有する多層回路基板14によって、入力端子30aに入力された正相信号は、第1信号線21a,22a,23aを介して出力端子31aに伝送された後、ボンディングワイヤ13aを介して光半導体素子13に出力される。また、入力端子30bに入力された逆相信号は、第2信号線21b,22b,23bを介して第2出力端子31bに伝送された後、ボンディングワイヤ13bを介して光半導体素子13に出力される。光半導体素子13は、出力端子31a,31bから入力される差動信号によって駆動され、レーザ光信号を透光性窓部材18側に出力する。光半導体素子13から出力された光信号は、光ファイバ20bによって伝送される。 The positive phase signal input to the input terminal 30a by the multilayer circuit board 14 having the above configuration is transmitted to the output terminal 31a via the first signal lines 21a, 22a, 23a, and then via the bonding wire 13a. It is output to the optical semiconductor element 13. Further, the reverse phase signal input to the input terminal 30b is transmitted to the second output terminal 31b via the second signal lines 21b, 22b, 23b, and then output to the optical semiconductor element 13 via the bonding wire 13b. NS. The optical semiconductor element 13 is driven by the differential signals input from the output terminals 31a and 31b, and outputs the laser light signal to the translucent window member 18 side. The optical signal output from the optical semiconductor element 13 is transmitted by the optical fiber 20b.

実施例1〜17及び比較例1〜8に係るセラミック素地について、寸法ばらつき、焼成セッターへの貼り付き、反り、色むら、曲げ強度及び比誘電率を確認した。
(サンプルの作製)
各原料粉末を表1に示す割合で混合して混合粉末を得た。
With respect to the ceramic substrates according to Examples 1 to 17 and Comparative Examples 1 to 8, dimensional variation, sticking to a firing setter, warpage, color unevenness, bending strength and relative permittivity were confirmed.
(Preparation of sample)
Each raw material powder was mixed at the ratio shown in Table 1 to obtain a mixed powder.

得られた混合粉末に、有機成分としてポリビニルブチラール及び3級アミン及びフタル酸エステル(フタル酸ジイソノニル:DINP)を混合し、さらに、溶剤としてIPA(イソプロピルアルコール)及びトルエンを混合してスラリーを調製した。 Polyvinyl butyral, a tertiary amine and a phthalate ester (diisononyl phthalate: DINP) were mixed as an organic component with the obtained mixed powder, and IPA (isopropyl alcohol) and toluene were further mixed as a solvent to prepare a slurry. ..

調製したスラリーを用いて、ドクターブレード法にて厚さ50〜400μmのセラミックテープを作製した。得られたセラミックテープを、縦50mm×横50mmにカットし、Mo製の焼成セッター上に並べて、表1に示す焼成温度(最高温度)で焼成(2時間)した。これによって、実施例1〜17及び比較例1〜8それぞれの焼成基板を100枚ずつ作成した。なお、表1に示す焼成温度で焼成した際の炉内の温度ばらつきは±5℃の範囲内であった。 Using the prepared slurry, a ceramic tape having a thickness of 50 to 400 μm was prepared by a doctor blade method. The obtained ceramic tape was cut into a length of 50 mm and a width of 50 mm, arranged on a firing setter made of Mo, and fired (2 hours) at the firing temperature (maximum temperature) shown in Table 1. As a result, 100 fired substrates for each of Examples 1 to 17 and Comparative Examples 1 to 8 were prepared. The temperature variation in the furnace when firing at the firing temperature shown in Table 1 was within the range of ± 5 ° C.

(寸法ばらつき)
実施例1〜17及び比較例1〜8それぞれについて、表1に示す焼成温度で焼成した際の寸法ばらつきを測定した。具体的には、寸法測定装置を用いて焼成基板の外形寸法を測定し、その平均値および標準偏差を算出し、標準偏差を平均値で割った値を寸法ばらつきとした。表1では、寸法ばらつきが0.20未満のものを○と評価し、寸法ばらつきが0.20以上0.50未満のものを△と評価し、寸法ばらつきが0.50以上のものを×と評価した。
(Dimension variation)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the dimensional variation when firing at the firing temperature shown in Table 1 was measured. Specifically, the external dimensions of the fired substrate were measured using a dimensional measuring device, the average value and standard deviation were calculated, and the value obtained by dividing the standard deviation by the average value was defined as the dimensional variation. In Table 1, those having a dimensional variation of less than 0.20 are evaluated as ◯, those having a dimensional variation of 0.20 or more and less than 0.50 are evaluated as Δ, and those having a dimensional variation of 0.50 or more are evaluated as ×. evaluated.

(焼成セッターへの貼り付き)
実施例1〜17及び比較例1〜8それぞれについて、焼成セッターに貼り付いてセラミック素地に欠損が生じた焼成基板の枚数を数えた。表1では、1枚も欠損が生じなかったものを○と評価し、1〜4枚に欠損が生じたものを△と評価し、5枚以上に欠損が生じたものを×と評価した。
(Attachment to the firing setter)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the number of fired substrates that were attached to the fired setter and had defects in the ceramic substrate was counted. In Table 1, those with no defects were evaluated as ◯, those with defects on 1 to 4 sheets were evaluated as Δ, and those with defects on 5 or more sheets were evaluated as ×.

(反り)
実施例1〜17及び比較例1〜8それぞれについて、三次元形状測定器を用いて、焼成基板の反り量の平均値を測定した。表1では、反り量が100μm未満のものを○と評価し、反り量が100μm以上200μm未満のものを△と評価し、反り量が200μm以上のものを×と評価した。
(warp)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the average value of the amount of warpage of the fired substrate was measured using a three-dimensional shape measuring device. In Table 1, those having a warp amount of less than 100 μm were evaluated as ◯, those having a warp amount of 100 μm or more and less than 200 μm were evaluated as Δ, and those having a warp amount of 200 μm or more were evaluated as ×.

(色むら)
実施例1〜17及び比較例1〜8それぞれについて、実体顕微鏡を用いて、焼成基板の色むらを観察した。表1では、色むらが無かったものを○と評価し、色むらが有ったものを×と評価した。
(Color unevenness)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the color unevenness of the fired substrate was observed using a stereomicroscope. In Table 1, those having no color unevenness were evaluated as ◯, and those having color unevenness were evaluated as ×.

(強度)
実施例1〜17及び比較例1〜8それぞれについて、焼成基板の曲げ強度を、JISR1601の3点曲げ強度試験に従って室温で測定した。
(Strength)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the bending strength of the fired substrate was measured at room temperature according to the 3-point bending strength test of JIS R1601.

(比誘電率)
実施例1〜17及び比較例1〜8それぞれについて、焼成基板の比誘電率を、JISR1641の空洞共振法に従って室温、周波数10GHzで測定した。
(Relative permittivity)
For each of Examples 1 to 17 and Comparative Examples 1 to 8, the relative permittivity of the fired substrate was measured at room temperature and a frequency of 10 GHz according to the cavity resonance method of JISR1641.

Figure 2020085148
Figure 2020085148

実施例1〜17では、比較例1〜8に比べて、寸法ばらつき、セッターへの貼り付き、及び反りを抑制することができた。これは、セラミック素地が含有するAl、SiO、MnO及び着色剤(Mo又は/及びCr)以外の残部の含有量を0.1質量%未満に抑えたため、各成分が偏析することなく分散された状態で均一に焼結させることができたためである。なお、MgO、ZrO、CaO及びBaO以外の添加物を添加した場合においても、同様の結果を得られることが実験的に確認されている。In Examples 1 to 17, dimensional variation, sticking to the setter, and warpage could be suppressed as compared with Comparative Examples 1 to 8. This is because the content of the balance other than Al 2 O 3 , SiO 2 , MnO and the colorant (Mo or / and Cr 2 O 3 ) contained in the ceramic substrate was suppressed to less than 0.1% by mass, so that each component contained This is because it was possible to uniformly sinter in a dispersed state without segregation. It has been experimentally confirmed that the same result can be obtained even when additives other than MgO, ZrO 2, CaO and BaO are added.

また、残部の含有量を0.07質量%以下とした実施例1〜9及び12〜17では、反りを更に抑制することができた。 Further, in Examples 1 to 9 and 12 to 17 in which the content of the balance was 0.07% by mass or less, the warp could be further suppressed.

また、残部の含有量を0.05質量%未満とした実施例1〜8及び12〜17では、寸法ばらつきを更に抑制することができた。 Further, in Examples 1 to 8 and 12 to 17 in which the content of the balance was less than 0.05% by mass, the dimensional variation could be further suppressed.

また、残部の含有量を0質量%未満とした実施例1〜5及び12〜17では、寸法ばらつきだけでなくセッターへの貼り付きも更に抑制することができた。 Further, in Examples 1 to 5 and 12 to 17 in which the content of the balance was less than 0% by mass, not only the dimensional variation but also the sticking to the setter could be further suppressed.

また、MnOの含有量に対するSiOの含有量の比を0.8以上2.1以下とした実施例1〜15では、曲げ強度を700MPa以上とすることができた。従って1〜15は、強度を要するセラミックパッケージ(例えば、振動子又は半導体素子を封止するもの)に好適であることが分かった。Further, in Examples 1 to 15 in which the ratio of the content of SiO 2 to the content of MnO was 0.8 or more and 2.1 or less, the bending strength could be 700 MPa or more. Therefore, it was found that 1 to 15 are suitable for ceramic packages requiring strength (for example, those for encapsulating a vibrator or a semiconductor element).

また、MnOの含有量に対するSiOの含有量の比を1.9以上3.5以下とした実施例15〜17では、8.0以上9.0以下の比誘電率と390MPa以上の抗折強度とを両立することができた。従って、実施例15〜17は、比較的低い比誘電率を要するセラミックパッケージ(例えば、光半導体素子を封止するもの)に好適であることが分かった。Further, in Examples 15 to 17 in which the ratio of the content of SiO 2 to the content of MnO was 1.9 or more and 3.5 or less, the relative permittivity of 8.0 or more and 9.0 or less and the bending resistance of 390 MPa or more were obtained. It was possible to achieve both strength and strength. Therefore, it was found that Examples 15 to 17 are suitable for ceramic packages (for example, those for encapsulating an optical semiconductor element) that require a relatively low relative permittivity.

100 第1セラミックパッケージ
1 絶縁基板
200 第2セラミックパッケージ
6 多層回路基板
14a〜14f 回路基板
100 1st ceramic package 1 Insulated substrate 200 2nd ceramic package 6 Multilayer circuit board 14a to 14f Circuit board

Claims (5)

Al、SiO及びMnOを必須成分として含み、Mo及びCrの少なくとも一方を任意成分として含み、
Alの含有量が、82.0質量%以上95.0質量%以下であり、
SiOの含有量が、3.0質量%以上8.0質量%以下であり、
MnOの含有量が、2.0質量%以上6.0質量%以下であり、
MoO換算でのMoの含有量とCrの含有量との合計が、4.0質量%以下であり、
残部の含有量が、0.1質量%未満である、
セラミック素地。
Al 2 O 3 , SiO 2 and MnO are contained as essential components, and at least one of Mo and Cr 2 O 3 is contained as an optional component.
The content of Al 2 O 3 is 82.0% by mass or more and 95.0% by mass or less.
The content of SiO 2 is 3.0% by mass or more and 8.0% by mass or less.
The MnO content is 2.0% by mass or more and 6.0% by mass or less.
The total of the Mo content and the Cr 2 O 3 content in terms of MoO 3 is 4.0% by mass or less.
The content of the balance is less than 0.1% by mass,
Ceramic substrate.
残部の含有量が、0.05質量%未満である、
請求項1に記載のセラミック素地。
The content of the balance is less than 0.05% by mass,
The ceramic substrate according to claim 1.
MnOの含有量に対するSiOの含有量の比が、0.8以上3.5以下である、
請求項1又は2に記載のセラミック素地。
The ratio of the content of SiO 2 to the content of MnO is 0.8 or more and 3.5 or less.
The ceramic substrate according to claim 1 or 2.
抗折強度が、700MPa以上である、
請求項1乃至3のいずれかに記載のセラミック素地。
The bending strength is 700 MPa or more.
The ceramic substrate according to any one of claims 1 to 3.
10GHzでの比誘電率が、8.0以上9.0以下であり、
抗折強度が、390MPa以上である、
請求項1乃至3のいずれかに記載のセラミック素地。
The relative permittivity at 10 GHz is 8.0 or more and 9.0 or less.
The bending strength is 390 MPa or more.
The ceramic substrate according to any one of claims 1 to 3.
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