JPWO2020049641A1 - How to build communication devices and logic circuits - Google Patents

Abstract

Provide a method for constructing a communication device and a logic circuit capable of appropriately transmitting and receiving position information between the changed detection device and the programmable logic device even when the detection device to be connected is changed. The communication device includes a connection unit connected to a detection device that detects and outputs position information, a first config information that constructs a logic circuit that can communicate with the detection device, and a detection device that can communicate with the first config information. Is a storage unit that can store the second config information that constructs a logic circuit that can communicate with different types of detection devices, and a selection signal output that outputs a selection signal for selecting the first config information or the second config information. A logic circuit is constructed by reading the first config information or the second config information based on the selection signal output from the selection signal output unit, and the detection device connected to the connection unit by the constructed logic circuit. It includes a programmable logic device that executes location information communication between the devices.

Description

The present disclosure relates to a technique for constructing a logic circuit of a programmable logic device that communicates with a detection device that detects and outputs position information such as a motor.

Conventionally, there is a technique for changing the input / output characteristics of a programmable logic device such as an FPGA (Field Programmable Gate Array) (for example, Patent Document 1). The PROM of the FPGA device described in Patent Document 1 stores two types of config information having different input / output characteristics. The FPGA device selects config information according to the magnitude of the power supply voltage and constructs a logic circuit based on the selected config information.

JP-A-11-95994

By the way, when constructing a circuit that communicates with an encoder or the like that detects the position information of a motor with a logic circuit of a programmable logic device, for example, it is possible to construct a logic circuit using config information provided by an encoder manufacturer. it can. However, when an encoder or the like of another manufacturer is connected to the constructed logic circuit, there is a possibility that position information cannot be appropriately transmitted and received between the logic circuit and the encoder due to a difference in communication protocol or the like.

The present application has been made in view of the above problems, and even if the detection device to be connected is changed, communication capable of appropriately transmitting and receiving position information between the changed detection device and the programmable logic device. It is an object of the present invention to provide a method of constructing a device and a logic circuit.

In order to solve the above problems, the present specification includes a connection unit connected to a detection device that detects and outputs position information, first config information for constructing a logic circuit capable of communicating with the detection device, and the above. A storage unit capable of storing the first config information and the second config information for constructing the logic circuit capable of communicating with the detection device, which is different from the detection device capable of communicating with the first config information, and the first config information or Based on the selection signal output unit that outputs the selection signal for selecting the second config information and the selection signal output from the selection signal output unit, the first config information or the second config information is read and described. Disclosed is a communication device including a programmable logic device that constructs a logic circuit and executes communication of the position information between the connection unit and the detection device connected by the constructed logic circuit.

Further, the content of the present disclosure is not limited to the implementation as a communication device, but can also be implemented as a method for constructing a logic circuit in a communication device.

According to the communication device and the like of the present disclosure, the programmable logic device can construct a logic circuit according to the type of the detection device based on the selection signal, and the constructed logic circuit enables communication with the detection device. Therefore, even if the detection device connected to the connection unit is changed, the position information can be appropriately transmitted and received between the changed detection device and the programmable logic device.

It is a schematic block diagram of the work transfer system of this embodiment. It is a schematic block diagram of the work transfer apparatus. It is a block diagram which shows the structure which concerns on the drive part of the work transfer device among the structure of the work transfer system. It is a block diagram which shows the connection structure of the FPGA board and the 1st drive part. It is a flowchart for demonstrating the process at the time of startup.

Hereinafter, one embodiment of the present disclosure will be described with reference to the drawings. First, a component mounting system including an FPGA board 81 (see FIG. 3), which is an embodiment of the communication device of the present disclosure, will be described. FIG. 1 is a perspective view showing a schematic configuration of the work transfer system 10. As shown in FIG. 1, the work transfer system 10 includes a work transfer device 11, a work supply device 13, a work accommodating member 15, and the like on the base 10A.

The work transfer system 10 uses the work 21 housed in the work accommodating member 15 as a pallet 17 used for the subsequent work under the control of the system control unit 19 (see FIG. 3) provided in the base 10A. Move to and place. In the work transfer system 10, for example, the work 21 mounted on the collection mounting table 15A of the work accommodating member 15 in an indefinite posture can be easily worked by a work robot (not shown) or a worker in a subsequent process. , Placed on the pallet 17 in a state of being aligned in a predetermined posture. The "indefinite posture" here means a state in which the position, direction, etc. of the work 21 are not unified. In the following description, as shown in FIG. 1, the direction in which the pallet 17 is conveyed in the work transfer system 10 is the left-right direction (X-axis), the direction orthogonal to the left-right direction and parallel to the plane of the pallet 17 to be conveyed. Is referred to as a front-back direction (Y-axis), and a direction orthogonal to the left-right direction and the front-back direction is referred to as a vertical direction (Z-axis).

The work 21 to be worked on is, for example, a bolt. The work 21 is not limited to bolts, and may be, for example, other mechanical parts (nuts, washers, etc.), and is not limited to mechanical parts, but may be electrical parts, electronic parts, chemical parts, or the like. At least a part of the work 21, for example, the adsorption portion 23 shown in the enlarged view of FIG. 1 is formed of a magnetic material. The work 21 is attracted by the electromagnets of the work transfer device 11 and the work supply device 13, which will be described later, to move the suction portion 23 formed of the magnetic material in a sucked state.

The work accommodating member 15 is a member for storing the work 21, and is provided with a plurality of boxes having a bottomed box shape with an open upper portion. Each of the work accommodating members 15 is provided with a collection stand 15A at a predetermined height from the bottom. The work 21 stored at the bottom of the work accommodating member 15 is transferred to the collection stand 15A by the work supply device 13. A part of the bottom of the work accommodating member 15 is inclined, and the work 21 dropped from the collection platform 15A is stored in one place.

Further, a moving portion 16 for moving the work accommodating member 15 is provided on the base 10A. The moving unit 16 is located between the accommodating table 16A on which the work accommodating member 15 is placed, the retracting position of the accommodating table 16A (the position shown by the dotted line in FIG. It has a rail 16B to be moved. The system control unit 19 (see FIG. 3) drives a drive source (not shown) based on an operation or the like from an operator, and moves the accommodating table 16A to a retracted position or a mounting processing position. As a result, the operator can appropriately replenish the work 21 with the work accommodating member 15.

The pallet 17 is a member on which the work 21 is arranged and placed, and has a magnetic force, and the work 21 is fixed by the magnetic force. The work transfer device 11 is arranged on the pallet 17 at predetermined intervals, for example, with the heads of the bolts, which are the work 21, facing downward. The work transfer device 11 arranges the work 21 at a predetermined position on the pallet 17 determined according to the type of the work 21.

Further, the work transfer system 10 includes a transport unit 25 for transporting the pallet 17. The transport unit 25 is a unit that carries in and transports the pallet 17, fixes the work 21 at the transfer position, and carries it out. The conveyor 25 is arranged with a predetermined interval in the front-rear direction, and has a pair of conveyor belts extending in the left-right direction. The pallet 17 is conveyed by this conveyor belt. The system control unit 19 (see FIG. 3) controls the transport unit 25 to, for example, carry out the pallet 17 to a subsequent device. The device in the subsequent stage identifies the position of the work 21 on the pallet 17 based on, for example, predetermined position information according to the type of the work 21 and performs the work.

Next, the detailed configuration of the work transfer device 11 will be described. FIG. 2 shows a schematic configuration of the work transfer device 11. The work transfer device 11 collects the work 21 from each of the work accommodating members 15, and places the collected work 21 on the pallet 17. As shown in FIG. 2, the work transfer device 11 includes a base portion 31, an arm portion 33, an end effector 39, and the like.

The base portion 31 is fixed on the base portion 10A (see FIG. 1) of the work transfer system 10 and has a support shaft portion 41 for supporting the arm portion 33. The support shaft portion 41 has a cylindrical portion 41A and a holding portion 41B. The columnar portion 41A has a cylindrical shape extending in the vertical direction, and has a holding portion 41B at the upper end portion. The holding portion 41B supports the base end portion of the arm portion 33. Further, the base portion 31 has a built-in first drive unit 32, and drives the first drive unit 32 under the control of the FPGA substrate 81 (see FIG. 3) to rotate the columnar portion 41A. The holding portion 41B is rotationally driven with an axis along the vertical direction as a central axis as the cylindrical portion 41A rotates.

The arm portion 33 is a so-called articulated robot in which the first arm 45 and the second arm 46 are connected from the base end portion toward the tip end portion. The first arm 45 is a longitudinal member extending in one direction, and the base end portion is supported by the holding portion 41B of the support shaft portion 41. The holding portion 41B of the support shaft portion 41 is connected to the first arm 45 via the second driving portion 35. The second drive unit 35 rotates the first arm 45 with respect to the holding unit 41B about a direction orthogonal to the vertical direction as a central axis based on the control of the FPGA board 81 (see FIG. 3).

The second arm 46 is connected to the tip end portion of the first arm 45 via a third drive unit 37. The second arm 46 is a longitudinal member extending in one direction from the tip end portion of the first arm 45. Based on the control of the FPGA substrate 81 (see FIG. 3), the third drive unit 37 is the third with respect to the tip end portion of the first arm 45 with the direction orthogonal to the extension direction of the first arm 45 as the central axis. 2 Rotate the arm 46.

The end effector 39 is provided at the tip of the second arm 46, and is configured to be detachable from the second arm 46. The work transfer device 11 can change the type of end effector 39 according to its use. The end effector 39 mounted in FIG. 2 is an example, and has a fourth drive unit 51, a sampling unit 53, an imaging unit 55, and a pedestal unit 57. The fourth drive unit 51 rotates the pedestal portion 57 of the end effector 39 about a direction orthogonal to the extension direction of the second arm 46 based on the control of the FPGA substrate 81 (see FIG. 3).

As shown in FIG. 2, the pedestal portion 57 is an L-shaped plate member, and the sampling portion 53 is attached to the tip portion. The collecting unit 53 is a member that attracts and collects the suction portion 23 (see the enlarged view of FIG. 1) of the work 21, and has an attracting portion 61, a pair of holding portions 63, a fixing member 67, and the like. The attracting portion 61, the holding portion 63, and the fixing member 67 are arranged between the two plates 65. The fixing member 67 is a rod-shaped member, and is configured to be vertically movable by an air cylinder 71. The air cylinder 71 moves the fixing member 67 up and down according to the amount of air supplied from the air supply unit (not shown) provided on the base 10A.

The fixing member 67 is initially arranged above the plate 65 and moves downward when the work 21 is sandwiched. The pair of holding portions 63 are rotatably supported at both ends of the rod-shaped fixing member 67. The pair of holding portions 63 are housed inside the plate 65 when the fixing member 67 is in the initial position (see the enlarged view on the left side of FIG. 2). The attraction portion 61 is configured by connecting a shaft member to an electromagnet, and attracts and collects a magnetic work 21 to the tip of the shaft member. The attraction portion 61 is fixed below the plate 65. The attraction unit 61 is configured to generate, for example, three stages of magnetic force (attraction force) according to the electric power supplied from the power supply unit 77 (see FIG. 3) provided on the base 10A.

The pair of holding portions 63 sandwich and support the work 21 (see FIG. 1) after being attracted by the attracting portion 61. The pair of holding portions 63 are provided with holding pins 69. The sandwiching pin 69 is fixed to the surface of each of the sandwiching portions 63 facing the plate 65. A guide groove 65A for guiding the holding pin 69 is formed in each of the plates 65. When the fixing member 67 moves downward, the pair of sandwiching portions 63 are guided to a predetermined track by the guide groove 65A, and sandwich the work 21 at the tip thereof (see the enlarged view on the right side of FIG. 2). Further, the image pickup unit 55 is a unit for capturing an image, and is fixed to a surface on the tip end side of the plate 65. The image pickup unit 55 transmits the captured image data to the system control unit 19 (see FIG. 3).

Similar to the work transfer device 11, the work supply device 13 shown in FIG. 1 is configured such that the end effector 73 can be replaced according to its use. Further, the work supply device 13 has the same configuration as the work transfer device 11 except for the type of the end effector 73, and its operation is controlled by the system control unit 19 and the FPGA board 81. Therefore, the detailed description of the work supply device 13 will be omitted.

Next, the configurations of the first drive unit 32 to the fourth drive unit 51 will be described. The configuration of the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 is the same as that of the first drive unit 32. Therefore, in the following description, the first drive unit 32 will be mainly described, and the description of the other drive units will be omitted as appropriate.

FIG. 3 shows the configuration of the work transfer system 10 related to the drive portion of the work transfer device 11. As shown in FIG. 3, the first drive unit 32 includes a servomotor 83 as a drive source and an encoder 85 that detects and outputs position information ED such as a rotational position of the servomotor 83. The encoder 85 is connected to the FPGA board 81 provided on the base 10A via the encoder cable 87. Similarly, the second drive unit 35 and the like other than the first drive unit 32 are also connected to the FPGA board 81 via the encoder cable 87.

FIG. 4 shows a connection configuration between the FPGA board 81 and the first drive unit 32. In addition, in order to avoid complicating the drawings, the drawings of the drive units (second drive unit 35, etc.) other than the first drive unit 32 are omitted in FIG. As shown in FIG. 4, the FPGA board 81 includes an amplifier circuit 91 (FPGA92), a connection unit 93, an upper connection unit 95, a power supply connection unit 97, a memory 99, a memory controller 110, a CPU 111, and a DIP switch. It is equipped with a switch 115. The amplifier circuit 91, the connection unit 93, the upper connection unit 95, and the like can communicate with each other by a communication bus or the like.

Further, the FPGA board 81 has, for example, an FPGA (Field Programmable Gate Array) 92 as a programmable logic device capable of constructing a logic circuit based on config information. The FPGA 92 reads the config information and constructs the amplifier circuit 91 with a logic circuit. The programmable logic device of the present disclosure is not limited to FPGA, and may be a programmable logic device (PLD), a composite programmable logic device (CPLD), or the like.

The amplifier circuit 91 of the FPGA 92 is connected to the connection unit 93. The connection portion 93 is a connector mounted on the FPGA board 81, and is connected to the encoder cable 87 of the encoder 85. The connection unit 93 is not limited to the configuration mounted on the board of the FPGA board 81, and may be connected to the FPGA board 81 by a cable or the like.

The connection unit 93 of the present embodiment is composed of a common interface that can be connected to a plurality of types of encoders 85. For example, the connector 89 provided at the tip of the encoder cable 87 has the same shape. The connector 89 may be a connector provided at the tip of the encoder cable 87 directly connected to the encoder 85, or may be a connector after the encoder cable 87 is once converted. Therefore, in the encoder 85 of the present embodiment, the shape of the connector 89 is standardized even if the manufacturer, model number, model, and the like are different.

The connecting portion 93 has a shape that can be connected to the common connector 89. Therefore, the connection unit 93 can be connected even if the encoder 85 is of a different type. The encoder 85 transmits the position information ED corresponding to the rotational drive of the servomotor 83 to the FPGA board 81 via the encoder cable 87, the connector 89, and the connection portion 93.

Further, the upper connection unit 95 of the FPGA board 81 is connected to the system control unit 19 which is the upper control unit. Further, the FPGA board 81 is connected to the power supply unit 77 provided on the base 10A via the power supply connection unit 97. The amplifier circuit 91 can control the power supply unit 77 via the power supply connection unit 97. The amplifier circuit 91 controls the power supply unit 77 based on the position information ED input via the connection unit 93 and the command value input from the system control unit 19 via the upper connection unit 95. The servomotor 83 of the first drive unit 32 is, for example, a motor driven by three-phase alternating current having coils of U-phase, V-phase, and W-phase, and the coils of each phase are used as a power source via the power supply line 90. It is connected to unit 77. The servomotor 83 is driven according to the three-phase alternating current W supplied from the power supply unit 77 through the power supply line 90. The amplifier circuit 91 changes the size, period, and the like of the three-phase AC W based on the position information ED and the like. As a result, the FPGA board 81 executes feedback control on the servomotor 83 of the first drive unit 32. The FPGA board 81 may not only control the rotation position and rotation speed of the servomotor 83, but also control the torque of the servomotor 83.

In addition, in FIG. 3, in order to avoid complicating the drawing, one power supply line 90 connected to each servomotor 83 of the plurality of drive units (first drive unit 32 and second drive unit 35) is provided. Illustrated with cable. Further, as described above, the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 other than the first drive unit 32 have the same configuration as the first drive unit 32, and the amplifier circuit 91. Feedback is controlled by.

Further, the memory 99 of the FPGA board 81 stores the first config information 101, the second config information 102, and the start program 103. The first and second config information 101 and 102 are config information for constructing a logic circuit that functions as an amplifier circuit 91. The first config information 101 is, for example, information for constructing an amplifier circuit 91 capable of communicating with the position information ED using a communication protocol different from that of the second config information 102. The communication protocol referred to here is, for example, an agreement on the transmitting / receiving side for normal communication such as the data format, bit order, communication speed, and communication command used for the communication of the position information ED. The communication protocol may include one specified by a communication standard such as HDLC (High level Data Link Control procedure) or one independently specified by a manufacturer of the encoder 85 or the like. Specifically, the first config information 101 corresponds to, for example, the encoder 85 manufactured by A company, and constructs an amplifier circuit 91 capable of communicating the position information ED with the communication protocol used by the encoder 85 manufactured by A company. Information to do. Further, the second config information 102 corresponds to, for example, the encoder 85 manufactured by B company, and is information for constructing an amplifier circuit 91 capable of communicating the position information ED with the communication protocol used by the encoder 85 manufactured by B company. is there. The first config information 101 may be any information corresponding to the encoder 85 of a different type from the second config information 102. For example, the first config information 101 and the second config information 102 may be encoders 85 of the same manufacturer or information corresponding to encoders 85 having different model numbers (such as different data formats of position information ED). That is, the first config information 101 may be any information corresponding to the encoder 85, which cannot execute communication in the amplifier circuit 91 constructed by the second config information 102.

Therefore, the detection device of this embodiment is an encoder 85 that detects the position information ED of the servomotor 83 (an example of the motor). Then, the FPGA 92 (an example of a programmable logic device) constructs an amplifier circuit 91 that feedback-controls the servomotor 83 as a logic circuit based on the position information ED acquired from the encoder 85. According to this, the config information (first and second config information 101, 102) can be selected according to the type of the encoder 85, and the amplifier circuit 91 according to the type of the encoder 85 can be constructed by the logic circuit. Then, the constructed amplifier circuit 91 can appropriately perform feedback control on the servomotor 83 based on the position information ED of the encoder 85.

Further, the first config information 101 of the present embodiment is, for example, an amplifier circuit 91 (an example of a logic circuit) capable of communicating position information ED with an encoder 85 (an example of a first detection device) manufactured by A company. Is the information to build. The second config information 102 includes, for example, an amplifier circuit 91 capable of communicating position information ED with an encoder 85 manufactured by B company (an example of a second detection device) which is different from the encoder 85 manufactured by A company. Information to build. The encoder 85 manufactured by A company and the encoder 85 manufactured by B company communicate the position information ED using different communication protocols. According to this, as will be described later, an amplifier circuit 91 capable of executing communication with the encoder 85 can be constructed regardless of which of the encoders 85 having different communication protocols for transmitting and receiving the position information ED is connected.

Further, the start program 103 of the memory 99 is a program executed by the CPU 111 when the FPGA board 81 is started. The memory 99 includes, for example, a non-volatile memory such as a flash memory and a volatile memory such as a RAM. The storage unit for storing the config information is not limited to the memory, and may be another storage device such as a hard disk.

The memory controller 110 controls a write process for the memory 99 and a read process from the memory 99. For example, when the power of the work transfer system 10 is turned on and the power is supplied to the FPGA board 81, the CPU 111 reads the start program 103 from the memory 99 and executes it via the memory controller 110. By executing the start-up program 103, the CPU 111 selects the config information (first and second config information 101, 102) to be loaded into the FPGA 92 of the FPGA board 81, and constructs the amplifier circuit 91 based on the config information. In the following description, the CPU 111 that executes the startup program 103 may be simply described by the device name. For example, the description "CPU 111 determines the signal level and notifies an error according to the determination result" states that "CPU 111 determines the signal level by reading and executing the startup program 103, and the determination result is used. It may mean "notify an error accordingly".

The connection unit 93 of the present embodiment is provided with a connection terminal 113 for determining the type of encoder 85 connected to the connection unit 93. For example, when the connector 89 of the encoder 85 manufactured by A company is connected to the connection terminal 113, a specific connection pin is short-circuited and a high-level first selection signal CS1 is output to the CPU 111. Further, for example, when the connector 89 of the encoder 85 manufactured by Company B is connected to the connection terminal 113, a specific connection pin is connected to the ground, and a low-level first selection signal CS1 is output to the CPU 111. That is, the connection terminal 113 outputs the first selection signal CS1 having a different signal level when different types of encoders 85 are connected. The connection terminal 113 outputs not only a configuration corresponding to two types of encoders 85 such as company A and company B, but also a first selection signal CS1 having a different signal level corresponding to three or more types of encoders 85. It may be configured to be used. For example, the connection terminal 113 receives the first selection signal CS1 of the first signal level when the connector 89 of the company A is connected, and the first selection signal CS1 of the second signal level when the connector 89 of the company B is connected. , The first selection signal CS1 of the third signal level may be output when the connector 89 of the company C is connected.

Therefore, the connection unit 93 of the present embodiment is a common interface that can be connected to a plurality of types of encoders 85. The connection terminal 113 (an example of a selection signal output unit) is a first selection signal CS1 (an example of a selection signal) provided in the connection unit 93 and different depending on the connection structure of the connector 89 of the encoder 85 connected to the connection unit 93. Is output. According to this, the connection terminal 113 can output a different first selection signal CS1 depending on the connection structure of the connector 89 of the encoder 85 connected to the connection portion 93, for example, the position of the connection pin, the position of the GND, and the like. As a result, the config information to be read by the FPGA 92 by changing the signal level of the first selection signal CS1 and the like while reducing the number of connection units 93 by standardizing the interface (first config information 101 or second config information 102). Can be appropriately instructed to the CPU 111.

Further, the DIP switch 115 is a small switch mounted on the substrate of the FPGA substrate 81, and for example, a slide switch capable of slide operation is provided. The DIP switch 115 outputs, for example, a second selection signal CS2 having a different signal level depending on the position of the slide switch to the CPU 111. For example, when the DIP switch 115 moves the slide switch to the first position, it outputs a high-level second selection signal CS2 and moves the slide switch to a second position different from the first position. In this case, the low-level second selection signal CS2 is output. The CPU 111 determines whether to use the first config information 101 or the second config information 102 based on the first selection signal CS1 of the connection terminal 113 and the second selection signal CS2 of the DIP switch 115. As a result, the user can select the config information to be used by operating the DIP switch 115. The DIP switch 115 is not limited to the slide switch, and may be a push-lock type switch or the like.

Therefore, the DIP switch 115 (an example of the selection signal output unit) of the present embodiment is a switch that outputs a different second selection signal CS2 (an example of the selection signal) according to an operation from the outside. According to this, for example, the user can change the type of the second selection signal CS2 by changing the setting of the DIP switch 115 provided on the FPGA board 81, and the config information to be read by the FPGA 92 (first config information). 101 or the second config information 102) can be appropriately instructed to the CPU 111.

Next, the process at startup by the CPU 111 will be described with reference to FIG.
First, in step 11 of FIG. 5 (hereinafter, simply referred to as “S”) 11, the power of the work transfer system 10 is turned on, and power is supplied to the FPGA board 81. The CPU 111 reads the start program 103 from the memory 99 and executes it (S13). Further, the connection terminal 113 outputs a high-level or low-level first selection signal CS1 to the CPU 111 according to the connection structure (arrangement of connection pins, etc.) of the connector 89 connected to the connection portion 93. Further, when the power is supplied, the DIP switch 115 outputs a high level or low level second selection signal CS2 to the CPU 111 according to the position of the slide switch, that is, the setting by the user (S13).

When the first selection signal CS1 and the second selection signal CS2 are input in S13, the CPU 111 determines whether or not the signal levels of the two selection signals match (S15). For example, when the CPU 111 inputs the high-level first selection signal CS1, it means that the encoder 85 manufactured by Company A is connected. Further, for example, when the CPU 111 inputs the high-level second selection signal CS2, the user has set the DIP switch 115 to connect the encoder 85 manufactured by Company A. Therefore, the CPU 111 determines whether or not the signal levels of the first selection signal CS1 and the second selection signal CS2 match, so that the encoder 85 actually connected to the connector 89 and the setting of the DIP switch 115 can be set. You can judge whether or not they match. As a result, it is possible to detect an error in the setting of the DIP switch 115 by the user and an error in the first selection signal CS1 due to damage to the connector 89.

When the CPU 111 determines that the signal levels of the first selection signal CS1 and the second selection signal CS2 match (S15: YES), it executes S17, and when it determines that they do not match (S15: NO), it executes S19. The CPU 111 notifies an error in S19 and ends the process shown in FIG. In this case, the CPU 111 displays an error such as "The setting of the DIP switch 115 and the type of the encoder 85 (connector 89) do not match" on the screen of the management PC connected to the work transfer system 10, for example. Alternatively, the CPU 111 notifies the error by turning on the error lamp provided in the work transfer device 11 or sounding the buzzer. As a result, the user can recognize that the type of the connected encoder 85 and the type of the encoder 85 set by the DIP switch 115 do not match. The user can take appropriate measures such as confirming the model name of the encoder 85 and the setting of the DIP switch 115. The CPU 111 similarly determines that the first selection signal CS1 and the second selection signal CS2 match each of the second drive unit 35, the third drive unit 37, and the fourth drive unit 51 other than the first drive unit 32. And so on.

Further, in S17, the CPU 111 causes the FPGA 92 to read the config information corresponding to the signal levels of the first selection signal CS1 and the second selection signal CS2, and constructs the amplifier circuit 91. For example, when the first and second selection signals CS1 and CS2 are both high-level signals, the CPU 111 causes the FPGA 92 to read the first config information 101 to construct the amplifier circuit 91. Further, for example, when the first and second selection signals CS1 and CS2 are both low-level signals, the CPU 111 causes the FPGA 92 to read the second config information 102 to construct the amplifier circuit 91. As a result, the amplifier circuit 91 according to the manufacturer and the communication protocol is automatically constructed.

When the amplifier circuit 91 is constructed, it starts communication with the encoder 85 of the first drive unit 32, and when the initial value setting and the like are completed, it starts transmission and reception of the position information ED (S21). Similarly, the amplifier circuit 91 corresponding to other drive units (second drive unit 35, etc.) other than the first drive unit 32 is also constructed in the same manner, and starts communication of the position information ED with the encoder 85 ( S21). As a result, the amplifier circuit 91 corresponding to the type of the connected encoder 85 can be constructed, and the transmission / reception of the position information ED can be appropriately executed between the amplifier circuit 91 and the encoder 85.

Incidentally, the FPGA board 81 is an example of a communication device. The encoder 85 is an example of a detection device. The amplifier circuit 91 is an example of a logic circuit. The memory 99 is an example of a storage unit. The connection terminal 113 and the DIP switch 115 are examples of the selection signal output unit. The first selection signal CS1 and the second selection signal CS2 are examples of selection signals. The FPGA 92 is an example of a programmable logic device.

As described above, according to the present embodiment described above, the following effects are obtained.
In one aspect of this embodiment, the FPGA board 81 has a connection unit 93 connected to the encoder 85, a memory 99 capable of storing the first config information 101 and the second config information 102, and the first config information 101 or An amplifier circuit based on a connection terminal 113 and a DIP switch 115 that output selection signals (first selection signal CS1 and second selection signal CS2) for selecting the second config information 102, and first and second selection signals CS1 and CS2. The amplifier circuit 91 is provided with an FPGA 92 for constructing the 91 and executing the communication of the position information ED by the constructed amplifier circuit 91.

According to this, the FPGA 92 reads the first config information 101 or the second config information 102 based on the first and second selection signals CS1 and CS2 to construct the amplifier circuit 91, and positions the amplifier circuit 91 with the encoder 85. Information ED communication is executed. The FPGA 92 can construct an amplifier circuit 91 according to the type of the encoder 85 based on the first and second selection signals CS1 and CS2, and the constructed amplifier circuit 91 enables communication with the encoder 85. Therefore, even if the encoder 85 connected to the connection unit 93 is changed, the position information ED can be appropriately transmitted and received between the changed encoder 85 and the amplifier circuit 91.

It goes without saying that the present application is not limited to the above-described embodiment, and various improvements and changes can be made within a range that does not deviate from the gist of the present application.
For example, in the above embodiment, the two config information (first and second config information 101 and 102) are stored in the memory 99. That is, the configuration was compatible with two types of encoders 85. However, the FPGA substrate 81 may have a configuration capable of supporting a plurality of types of three or more. For example, the memory 99 has a configuration capable of communicating with a plurality of types of encoders 85, such as the first config information 101 for company A, the second config information 102 for company B, and the third config information for company C. Information may be stored. In this case, the connection terminal 113 and the DIP switch 115 are configured to be capable of outputting the first selection signal CS1 and the second selection signal CS2 having different signal levels (three or more types of signal levels) according to the number of config information. ..

Further, the selection signal may be changed without changing the signal level (high level or low level) of the first selection signal CS1 or the second selection signal CS2. For example, the connection terminal 113 may turn on signals of different signal lines among a plurality of signal lines connected to the CPU 111 according to the connection structure (type of encoder 85) of the connector 89 to be connected. As a result, the CPU 111 can determine which config information should be selected according to the signal line of the ON signal. Further, for example, the DIP switch 115 may be configured to output a second selection signal CS2 having a different bit value depending on the position of the slide switch. As a result, the CPU 111 can determine which config information should be selected based on the bit value input from the DIP switch 115.

Further, the FPGA board 81 may be configured to include only one of the connection terminal 113 and the DIP switch 115. In this case, the CPU 111 may select the config information based only on the input first selection signal CS1 or second selection signal CS2 without executing the determination process of S15 of FIG.
Further, the process of selecting the first config information 101 or the second config information 102 does not have to be realized by executing the start program 103 in the CPU 111, that is, by processing on the software. For example, the memory 99 that stores the first config information 101 and the memory 99 that stores the second config information 102 are different memories. Further, a switch circuit for changing the connection circuit is connected to both of the two memories according to the signal level of the input first selection signal CS1. Then, by changing the connection circuit of the switch circuit according to the signal level of the first selection signal CS1, the memory 99 for reading the config information may be changed, and the amplifier circuit 91 may be changed.

Further, the detection device in the present disclosure is not limited to the encoder 85 that detects the rotational position of the servomotor 83, and may be, for example, a linear scale that detects the position information ED of linear movement. In this case, the FPGA board 81 may select config information according to the type of linear scale to be connected, and change the amplifier circuit 91 that controls the linear motor. Thereby, for example, the amplifier circuit 91 can be changed according to the type of the linear scale for the linear motor that moves based on the position information ED of the linear scale, and the linear motor can be appropriately feedback-controlled by the amplifier circuit 91.
Further, the FPGA board 81 may control the drive source of the moving unit 16 and the drive source of the transport unit 25.

81 FPGA board (example of communication device), 83 servo motor (motor), 85 encoder (detector), 89 connector, 91 amplifier circuit (logic circuit), 92 FPGA (programmable logic device), 93 connection part, 113 connection terminal (Selection signal output unit), CS1 first selection signal (selection signal), CS2 second selection signal (selection signal), ED position information.

Claims (6)

The connection part connected to the detection device that detects and outputs the position information,
A first config information for constructing a logic circuit capable of communicating with the detection device and a second logic circuit capable of communicating with the detection device having a different type from the detection device capable of communicating with the first config information. A storage unit that can store config information and
A selection signal output unit that outputs a selection signal for selecting the first config information or the second config information,
Based on the selection signal output from the selection signal output unit, the first config information or the second config information is read to construct the logic circuit, and the logic circuit constructed is connected to the connection unit. A programmable logic device that executes communication of the position information with the detection device, and
A communication device. The connection part
It is a common interface that can be connected to a plurality of types of the detection devices.
The selection signal output unit
The communication device according to claim 1, wherein the communication device provided in the connection portion and outputs the selection signal different depending on the connection structure of the connector of the detection device connected to the connection portion. The selection signal output unit
The communication device according to claim 1 or 2, which is a switch that outputs different selection signals according to an operation from the outside. The detection device
It is an encoder that detects the position information of the motor.
The programmable logic device is
The communication device according to any one of claims 1 to 3, wherein an amplifier circuit that feedback-controls the motor is constructed as the logic circuit based on the position information acquired from the detection device. The first config information is
This is information for constructing the logic circuit capable of communicating the position information with the first detection device.
The second config information is
This is information for constructing the logic circuit capable of communicating the position information with the second detection device of a type different from that of the first detection device.
The first detection device and the second detection device are
The communication device according to any one of claims 1 to 4, wherein the location information is communicated using communication protocols different from each other. The connection unit connected to the detection device that detects and outputs the position information, the first config information that constructs the logic circuit that can communicate with the detection device, and the detection device that can communicate with the first config information. A logic circuit in a communication device including a storage unit capable of storing a second config information for constructing the logic circuit capable of communicating with the detection device of a different type, and a programmable logic device for constructing the logic circuit. It ’s a construction method,
A step of outputting a selection signal for selecting the first config information or the second config information, and
A step of causing the programmable logic device to read the first config information or the second config information to construct the logic circuit based on the selection signal.
A step of executing communication of the position information between the detection device connected to the connection portion by the constructed logic circuit, and
How to build a logic circuit, including.

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