JPWO2020046645A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2020046645A5 JPWO2020046645A5 JP2021537028A JP2021537028A JPWO2020046645A5 JP WO2020046645 A5 JPWO2020046645 A5 JP WO2020046645A5 JP 2021537028 A JP2021537028 A JP 2021537028A JP 2021537028 A JP2021537028 A JP 2021537028A JP WO2020046645 A5 JPWO2020046645 A5 JP WO2020046645A5
- Authority
- JP
- Japan
- Prior art keywords
- primitive
- subset
- dsp block
- variants
- partial reconfiguration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 12
- 238000005192 partition Methods 0.000 claims 11
- 238000005259 measurement Methods 0.000 claims 2
- 238000012544 monitoring process Methods 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023218099A JP2024038092A (ja) | 2018-08-27 | 2023-12-25 | 部分的リコンフィギュレーションを使用したフィールドプログラマブルゲートアレイのプログラミングプロセスの改善 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/113,490 US10642630B1 (en) | 2018-08-27 | 2018-08-27 | Process of programming field programmable gate arrays using partial reconfiguration |
| US16/113,490 | 2018-08-27 | ||
| PCT/US2019/047251 WO2020046645A1 (en) | 2018-08-27 | 2019-08-20 | Improved process of programming field programmable gate arrays using partial reconfiguration |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023218099A Division JP2024038092A (ja) | 2018-08-27 | 2023-12-25 | 部分的リコンフィギュレーションを使用したフィールドプログラマブルゲートアレイのプログラミングプロセスの改善 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021536650A JP2021536650A (ja) | 2021-12-27 |
| JPWO2020046645A5 true JPWO2020046645A5 (de) | 2022-07-29 |
| JP7411663B2 JP7411663B2 (ja) | 2024-01-11 |
Family
ID=69643748
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021537028A Active JP7411663B2 (ja) | 2018-08-27 | 2019-08-20 | 部分的リコンフィギュレーションを使用したフィールドプログラマブルゲートアレイのプログラミングプロセスの改善 |
| JP2023218099A Pending JP2024038092A (ja) | 2018-08-27 | 2023-12-25 | 部分的リコンフィギュレーションを使用したフィールドプログラマブルゲートアレイのプログラミングプロセスの改善 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023218099A Pending JP2024038092A (ja) | 2018-08-27 | 2023-12-25 | 部分的リコンフィギュレーションを使用したフィールドプログラマブルゲートアレイのプログラミングプロセスの改善 |
Country Status (12)
| Country | Link |
|---|---|
| US (2) | US10642630B1 (de) |
| EP (1) | EP3844662A4 (de) |
| JP (2) | JP7411663B2 (de) |
| KR (2) | KR102521275B1 (de) |
| CN (1) | CN112997145A (de) |
| AU (1) | AU2019327360B2 (de) |
| CA (1) | CA3114313C (de) |
| CH (1) | CH716706B1 (de) |
| DE (1) | DE112019004301T5 (de) |
| GB (2) | GB2590859B (de) |
| SG (1) | SG11202101816YA (de) |
| WO (1) | WO2020046645A1 (de) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018228693A1 (en) * | 2017-06-15 | 2018-12-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Hardware platform based on fpga partial reconfiguration for wireless communication device |
| US11188497B2 (en) | 2018-11-21 | 2021-11-30 | SambaNova Systems, Inc. | Configuration unload of a reconfigurable data processor |
| US10831507B2 (en) | 2018-11-21 | 2020-11-10 | SambaNova Systems, Inc. | Configuration load of a reconfigurable data processor |
| US11907828B2 (en) * | 2019-09-03 | 2024-02-20 | International Business Machines Corporation | Deep neural network on field-programmable gate array |
| CN112199320B (zh) * | 2020-09-28 | 2023-06-02 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | 多通道可重构信号处理装置 |
| US20220131915A1 (en) * | 2020-10-27 | 2022-04-28 | Nokia Solutions And Networks Oy | Management and implementation of applications in cloud-based fpgas |
| WO2022131397A1 (ko) * | 2020-12-16 | 2022-06-23 | 주식회사 모빌린트 | Cnn-rnn 아키텍처 전환형 연산 가속장치 설계 방법 |
| CN112560370A (zh) * | 2020-12-21 | 2021-03-26 | 上海逸集晟网络科技有限公司 | 芯片设计代码的生成方法、终端以及存储介质 |
| CN113203935B (zh) * | 2021-03-11 | 2024-06-28 | 江西创成微电子有限公司 | 芯片测试方法、系统及可读存储介质 |
| CN117203534A (zh) * | 2021-03-15 | 2023-12-08 | 领汇仪器有限公司 | 基于部分重配置fpga的多仪器设备 |
| US20220321403A1 (en) * | 2021-04-02 | 2022-10-06 | Nokia Solutions And Networks Oy | Programmable network segmentation for multi-tenant fpgas in cloud infrastructures |
| US11409540B1 (en) | 2021-07-16 | 2022-08-09 | SambaNova Systems, Inc. | Routing circuits for defect repair for a reconfigurable data processor |
| US11556494B1 (en) * | 2021-07-16 | 2023-01-17 | SambaNova Systems, Inc. | Defect repair for a reconfigurable data processor for homogeneous subarrays |
| US11327771B1 (en) | 2021-07-16 | 2022-05-10 | SambaNova Systems, Inc. | Defect repair circuits for a reconfigurable data processor |
| CN116737618B (zh) * | 2023-08-14 | 2023-11-14 | 浪潮电子信息产业股份有限公司 | Fpga架构、器件、数据处理方法、系统及存储介质 |
| CN117077599B (zh) * | 2023-09-18 | 2024-04-19 | 苏州异格技术有限公司 | 一种现场可编程逻辑门阵列视图生成方法及装置 |
| CN117807938B (zh) * | 2023-12-29 | 2024-07-12 | 苏州异格技术有限公司 | 一种从逻辑原语参数产生fpga芯片配置比特的方法 |
| CN118118444B (zh) * | 2024-04-28 | 2024-07-12 | 之江实验室 | 一种基于可编程交换机的计算功能抽象方法及装置 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7698118B2 (en) * | 2004-04-15 | 2010-04-13 | Mentor Graphics Corporation | Logic design modeling and interconnection |
| US7679401B1 (en) * | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
| US7739092B1 (en) | 2006-01-31 | 2010-06-15 | Xilinx, Inc. | Fast hardware co-simulation reset using partial bitstreams |
| US7823117B1 (en) | 2007-12-21 | 2010-10-26 | Xilinx, Inc. | Separating a high-level programming language program into hardware and software components |
| US8797061B2 (en) * | 2011-12-21 | 2014-08-05 | Altera Corporation | Partial reconfiguration circuitry |
| US20130212366A1 (en) * | 2012-02-09 | 2013-08-15 | Altera Corporation | Configuring a programmable device using high-level language |
| US9134981B2 (en) * | 2012-06-22 | 2015-09-15 | Altera Corporation | OpenCL compilation |
| US8997033B1 (en) * | 2014-03-05 | 2015-03-31 | Altera Corporation | Techniques for generating a single configuration file for multiple partial reconfiguration regions |
| US9584129B1 (en) * | 2014-06-20 | 2017-02-28 | Altera Corporation | Integrated circuit applications using partial reconfiguration |
| US9542244B2 (en) * | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| US9449134B1 (en) * | 2015-06-25 | 2016-09-20 | International Business Machines Corporation | Dynamically reconfigurable logic circuits using native field-programmable gate array primitives |
| US9929734B2 (en) * | 2015-09-08 | 2018-03-27 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method for changing the configuration of a programmable logic module |
| US9824173B1 (en) | 2015-09-11 | 2017-11-21 | Xilinx, Inc. | Software development-based compilation flow for hardware implementation |
| US9584130B1 (en) * | 2016-01-11 | 2017-02-28 | Altera Corporation | Partial reconfiguration control interface for integrated circuits |
| US10218359B2 (en) | 2017-06-29 | 2019-02-26 | Intel Corporation | Regional partial reconfiguration of a programmable device |
| US10761951B2 (en) * | 2017-12-28 | 2020-09-01 | Intel Corporation | FPGA based functional safety control logic (FFSCL) |
-
2018
- 2018-08-27 US US16/113,490 patent/US10642630B1/en active Active
-
2019
- 2019-08-20 DE DE112019004301.3T patent/DE112019004301T5/de active Pending
- 2019-08-20 CA CA3114313A patent/CA3114313C/en active Active
- 2019-08-20 JP JP2021537028A patent/JP7411663B2/ja active Active
- 2019-08-20 US US17/272,277 patent/US11675604B2/en active Active
- 2019-08-20 CH CH00210/21A patent/CH716706B1/de not_active IP Right Cessation
- 2019-08-20 CN CN201980070251.8A patent/CN112997145A/zh active Pending
- 2019-08-20 GB GB2103251.1A patent/GB2590859B/en active Active
- 2019-08-20 WO PCT/US2019/047251 patent/WO2020046645A1/en active Application Filing
- 2019-08-20 KR KR1020217008145A patent/KR102521275B1/ko active IP Right Grant
- 2019-08-20 GB GB2117992.4A patent/GB2599051B/en active Active
- 2019-08-20 EP EP19854260.7A patent/EP3844662A4/de active Pending
- 2019-08-20 KR KR1020237011909A patent/KR20230052994A/ko active Application Filing
- 2019-08-20 SG SG11202101816YA patent/SG11202101816YA/en unknown
- 2019-08-20 AU AU2019327360A patent/AU2019327360B2/en active Active
-
2023
- 2023-12-25 JP JP2023218099A patent/JP2024038092A/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2590859A (en) | Improved process of programming field programmable gate arrays using partial reconfiguration | |
| JPWO2020046645A5 (de) | ||
| CN109657782B (zh) | 运算方法、装置及相关产品 | |
| TWI816475B (zh) | 低延遲矩陣乘法單元中之胞元、相關之方法及非暫時性電腦程式產品 | |
| TWI515669B (zh) | 用於狀態機中資料分析之系統與方法 | |
| US9977758B1 (en) | Device profiling for tuning OpenCL applications on programmable integrated circuits | |
| CN109740747A (zh) | 运算方法、装置及相关产品 | |
| EP3149577B1 (de) | Extraktion einer systemarchitektur in der hochebenen-synthese | |
| US9298865B1 (en) | Debugging an optimized design implemented in a device with a pre-optimized design simulation | |
| WO2017157267A1 (en) | Reconfigurable data interface unit for compute systems | |
| Hung et al. | Towards simulator-like observability for FPGAs: A virtual overlay network for trace-buffers | |
| JPS58169663A (ja) | アレイプロセツサ装置 | |
| KR102596637B1 (ko) | 상호작용형 다단계 물리적 합성 | |
| US8949576B2 (en) | Arithmetic node including general digital signal processing functions for an adaptive computing machine | |
| US20220156293A1 (en) | Demand Based Dynamic Creation Of Data Analytics Query Accelerators | |
| TW201428521A (zh) | 設計及模擬系統、裝置及方法 | |
| JP2009003765A (ja) | データ処理装置およびその制御方法 | |
| US11580055B2 (en) | Devices for time division multiplexing of state machine engine signals | |
| WO2017148221A1 (zh) | 串行外设接口的传输控制方法、装置及系统 | |
| US10476492B2 (en) | Structures and operations of integrated circuits having network of configurable switches | |
| US11204889B1 (en) | Tensor partitioning and partition access order | |
| JP2007293871A (ja) | プロセッサの異種クラスターを有するハードウエアエミュレーションシステム | |
| GB2424503A (en) | Active memory device including a processor array | |
| JP6616420B2 (ja) | 情報処理装置 | |
| US7730438B2 (en) | Methods and apparatuses for designing multiplexers |