SG11202101816YA - Improved process of programming field programmable gate arrays using partial reconfiguration - Google Patents

Improved process of programming field programmable gate arrays using partial reconfiguration

Info

Publication number
SG11202101816YA
SG11202101816YA SG11202101816YA SG11202101816YA SG11202101816YA SG 11202101816Y A SG11202101816Y A SG 11202101816YA SG 11202101816Y A SG11202101816Y A SG 11202101816YA SG 11202101816Y A SG11202101816Y A SG 11202101816YA SG 11202101816Y A SG11202101816Y A SG 11202101816YA
Authority
SG
Singapore
Prior art keywords
programmable gate
field programmable
gate arrays
improved process
partial reconfiguration
Prior art date
Application number
SG11202101816YA
Inventor
Daniel Shaddock
Max Schwenke
Wuchenich Danielle Rawles
Benjamin Coughlan
Timothy Lam
Paul Altin
Original Assignee
Liquid Instr Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liquid Instr Pty Ltd filed Critical Liquid Instr Pty Ltd
Publication of SG11202101816YA publication Critical patent/SG11202101816YA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Stored Programmes (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Information Transfer Between Computers (AREA)
SG11202101816YA 2018-08-27 2019-08-20 Improved process of programming field programmable gate arrays using partial reconfiguration SG11202101816YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/113,490 US10642630B1 (en) 2018-08-27 2018-08-27 Process of programming field programmable gate arrays using partial reconfiguration
PCT/US2019/047251 WO2020046645A1 (en) 2018-08-27 2019-08-20 Improved process of programming field programmable gate arrays using partial reconfiguration

Publications (1)

Publication Number Publication Date
SG11202101816YA true SG11202101816YA (en) 2021-03-30

Family

ID=69643748

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202101816YA SG11202101816YA (en) 2018-08-27 2019-08-20 Improved process of programming field programmable gate arrays using partial reconfiguration

Country Status (12)

Country Link
US (2) US10642630B1 (en)
EP (1) EP3844662A4 (en)
JP (2) JP7411663B2 (en)
KR (2) KR20230052994A (en)
CN (1) CN112997145A (en)
AU (1) AU2019327360B2 (en)
CA (1) CA3114313C (en)
CH (1) CH716706B1 (en)
DE (1) DE112019004301T5 (en)
GB (2) GB2599051B (en)
SG (1) SG11202101816YA (en)
WO (1) WO2020046645A1 (en)

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WO2018228693A1 (en) * 2017-06-15 2018-12-20 Telefonaktiebolaget Lm Ericsson (Publ) Hardware platform based on fpga partial reconfiguration for wireless communication device
US11188497B2 (en) 2018-11-21 2021-11-30 SambaNova Systems, Inc. Configuration unload of a reconfigurable data processor
US10831507B2 (en) 2018-11-21 2020-11-10 SambaNova Systems, Inc. Configuration load of a reconfigurable data processor
US11907828B2 (en) * 2019-09-03 2024-02-20 International Business Machines Corporation Deep neural network on field-programmable gate array
CN112199320B (en) * 2020-09-28 2023-06-02 西南电子技术研究所（中国电子科技集团公司第十研究所） Multi-channel reconfigurable signal processing device
US20220131915A1 (en) * 2020-10-27 2022-04-28 Nokia Solutions And Networks Oy Management and implementation of applications in cloud-based fpgas
WO2022131397A1 (en) * 2020-12-16 2022-06-23 주식회사 모빌린트 Cnn-rnn architecture conversion type computational acceleration device design method
CN112560370A (en) * 2020-12-21 2021-03-26 上海逸集晟网络科技有限公司 Chip design code generation method, terminal and storage medium
CN113203935B (en) * 2021-03-11 2024-06-28 江西创成微电子有限公司 Chip testing method, system and readable storage medium
DE112022001503T5 (en) * 2021-03-15 2024-01-25 Liquid Instruments Pty Ltd. MULTIMETER BASED ON AN FPGA WITH PARTIAL RECONFIGURATION
US20220321403A1 (en) * 2021-04-02 2022-10-06 Nokia Solutions And Networks Oy Programmable network segmentation for multi-tenant fpgas in cloud infrastructures
US11409540B1 (en) 2021-07-16 2022-08-09 SambaNova Systems, Inc. Routing circuits for defect repair for a reconfigurable data processor
US11327771B1 (en) 2021-07-16 2022-05-10 SambaNova Systems, Inc. Defect repair circuits for a reconfigurable data processor
US11556494B1 (en) * 2021-07-16 2023-01-17 SambaNova Systems, Inc. Defect repair for a reconfigurable data processor for homogeneous subarrays
CN116737618B (en) * 2023-08-14 2023-11-14 浪潮电子信息产业股份有限公司 FPGA architecture, device, data processing method, system and storage medium
CN117077599B (en) * 2023-09-18 2024-04-19 苏州异格技术有限公司 Method and device for generating field programmable gate array view
CN117807938B (en) * 2023-12-29 2024-07-12 苏州异格技术有限公司 Method for generating FPGA chip configuration bits from logic primitive parameters
CN118118444B (en) * 2024-04-28 2024-07-12 之江实验室 Computing function abstraction method and device based on programmable switch

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US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7679401B1 (en) * 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US7739092B1 (en) 2006-01-31 2010-06-15 Xilinx, Inc. Fast hardware co-simulation reset using partial bitstreams
US7823117B1 (en) 2007-12-21 2010-10-26 Xilinx, Inc. Separating a high-level programming language program into hardware and software components
US8797061B2 (en) * 2011-12-21 2014-08-05 Altera Corporation Partial reconfiguration circuitry
US20130212366A1 (en) * 2012-02-09 2013-08-15 Altera Corporation Configuring a programmable device using high-level language
US9134981B2 (en) * 2012-06-22 2015-09-15 Altera Corporation OpenCL compilation
US8997033B1 (en) * 2014-03-05 2015-03-31 Altera Corporation Techniques for generating a single configuration file for multiple partial reconfiguration regions
US9584129B1 (en) * 2014-06-20 2017-02-28 Altera Corporation Integrated circuit applications using partial reconfiguration
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US9449134B1 (en) * 2015-06-25 2016-09-20 International Business Machines Corporation Dynamically reconfigurable logic circuits using native field-programmable gate array primitives
US9929734B2 (en) 2015-09-08 2018-03-27 Dspace Digital Signal Processing And Control Engineering Gmbh Method for changing the configuration of a programmable logic module
US9824173B1 (en) 2015-09-11 2017-11-21 Xilinx, Inc. Software development-based compilation flow for hardware implementation
US9584130B1 (en) * 2016-01-11 2017-02-28 Altera Corporation Partial reconfiguration control interface for integrated circuits
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Also Published As

Publication number Publication date
EP3844662A4 (en) 2021-11-03
CA3114313C (en) 2024-02-27
CH716706B1 (en) 2023-02-15
GB202117992D0 (en) 2022-01-26
US20210255879A1 (en) 2021-08-19
KR20210078475A (en) 2021-06-28
GB2599051B (en) 2022-10-26
JP7411663B2 (en) 2024-01-11
KR20230052994A (en) 2023-04-20
GB2590859B (en) 2022-02-09
JP2021536650A (en) 2021-12-27
US11675604B2 (en) 2023-06-13
GB2590859A (en) 2021-07-07
EP3844662A1 (en) 2021-07-07
JP2024038092A (en) 2024-03-19
GB2590859A8 (en) 2021-07-21
CN112997145A (en) 2021-06-18
AU2019327360B2 (en) 2023-07-20
AU2019327360A1 (en) 2021-03-18
WO2020046645A1 (en) 2020-03-05
GB2599051A (en) 2022-03-23
DE112019004301T5 (en) 2021-06-17
KR102521275B1 (en) 2023-04-12
GB202103251D0 (en) 2021-04-21
US10642630B1 (en) 2020-05-05
CA3114313A1 (en) 2020-03-05

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