JPWO2019140113A5 - - Google Patents
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- JPWO2019140113A5 JPWO2019140113A5 JP2020538647A JP2020538647A JPWO2019140113A5 JP WO2019140113 A5 JPWO2019140113 A5 JP WO2019140113A5 JP 2020538647 A JP2020538647 A JP 2020538647A JP 2020538647 A JP2020538647 A JP 2020538647A JP WO2019140113 A5 JPWO2019140113 A5 JP WO2019140113A5
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- Prior art keywords
- gate
- driver
- voltage
- load switch
- switch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000003990 capacitor Substances 0.000 claims 4
- 229910044991 metal oxide Inorganic materials 0.000 claims 3
- 150000004706 metal oxides Chemical class 0.000 claims 3
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000004913 activation Effects 0.000 claims 2
- 230000003213 activating Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000000875 corresponding Effects 0.000 claims 1
Claims (19)
ゲートとソースとドレインとを含むトランジスタと、
前記トランジスタのゲートに接続されるトランスコンダクタと、
前記トランジスタのゲートに接続される第1の端子と、チャージポンプ又は接地の少なくとも一方に接続される第2の端子とを含む抵抗器と、
前記トランスコンダクタの入力に結合されるコンパレータであって、前記トランジスタのゲートの電圧が前記チャージポンプのチャージポンプ電圧に達すると前記トランスコンダクタをディセーブルするように構成される、前記コンパレータと、
を含む、負荷スイッチ回路。 It is a load switch circuit,
Transistors , including gates , sources and drains ,
The transconductor connected to the gate of the transistor and
A resistor comprising a first terminal connected to the gate of the transistor and a second terminal connected to at least one of the charge pump or ground.
A comparator coupled to the input of the transistor, wherein the comparator is configured to disable the transformer when the voltage at the gate of the transistor reaches the charge pump voltage of the charge pump.
Including load switch circuit.
前記トランスコンダクタが電圧を前記トランジスタのゲートのための電流入力に変換するためのものであり、前記トランジスタのゲートへの前記電流入力が電源から負荷に電力を搬送するよう前記トランジスタゲートを制御するためのものであり、
前記抵抗器が、前記トランスコンダクタによって制御される前記トランジスタのゲートに前記チャージポンプから電力を提供するためのものである、負荷スイッチ回路。 The load switch circuit according to claim 1.
The transformer is intended to convert a voltage into a current input for the gate of the transistor, and to control the transistor gate so that the current input to the gate of the transistor carries power from a power source to a load. And
A load switch circuit in which the resistor is for supplying power from the charge pump to the gate of the transistor controlled by the transformer.
前記コンパレータに接続されるラッチを更に含む、負荷スイッチ回路。 The load switch circuit according to claim 1.
A load switch circuit further comprising a latch connected to the comparator.
前記ラッチが、前記トランスコンダクタをディセーブルするための信号を記憶して提供する、負荷スイッチ回路。 The load switch circuit according to claim 3 .
A load switch circuit in which the latch stores and provides a signal for disabling the transconductor.
前記トランスコンダクタに接続されるコンデンサを更に含む、負荷スイッチ回路。 The load switch circuit according to claim 1.
A load switch circuit further comprising a capacitor connected to the conductor.
前記コンデンサが、前記トランスコンダクタに前記電圧を提供するためである、負荷スイッチ回路。 The load switch circuit according to claim 5 .
A load switch circuit in which the capacitor provides the voltage to the transformer.
前記トランスコンダクタと前記コンパレータとが、N型金属酸化物半導体論理構成要素を用いて実装される、負荷スイッチ回路。 The load switch circuit according to claim 1.
A load switch circuit in which the transducer and the comparator are mounted using an N-type metal oxide semiconductor logic component.
負荷に電力を供給するためにチャージポンプと抵抗器とを含み、トランジスのゲートを制御するドライバであって、前記ゲートが活性化されると前記ゲートが前記トランジスタに電源から電力を前記負荷に搬送させる、前記ドライバと、
前記ゲートを活性化するように前記ゲートに関連する電圧の経時的変化率を制御し、前記ゲートが活性化されるときに前記ドライバをディセーブルするためのゲート傾斜制御回路と、
を含む、装置。 It ’s a device,
A driver that includes a charge pump and a resistor to power the load and controls the gate of the transistor, which, when activated, transfers power from the power source to the transistor to the load. With the above driver
A gate tilt control circuit for controlling the rate of change of the voltage associated with the gate over time to activate the gate and disabling the driver when the gate is activated.
Including equipment.
前記ドライバが、電圧を前記ゲートに入力される電流に変換するためのトランスコンダクタを更に含む、装置。 The device according to claim 8 .
A device in which the driver further comprises a transformer for converting a voltage into a current input to the gate.
前記ドライバが、前記トランスコンダクタに前記電圧を提供するためのコンデンサを更に含む、装置。 The device according to claim 9 .
A device in which the driver further comprises a capacitor for providing the voltage to the transformer.
前記ゲート傾斜制御回路が前記ドライバをディセーブルするときに、前記ゲート傾斜制御回路が前記電圧を入力電圧にプルアップするためものである、装置。 The device according to claim 9 .
A device for the gate tilt control circuit to pull up the voltage to an input voltage when the gate tilt control circuit disables the driver.
前記ゲート傾斜制御回路が、前記電圧が閾値を満足する時点を検出し、前記電圧が前記敷値を満足するときに前記ドライバをディセーブルするためのコンパレータを含む、装置。 The device according to claim 9 .
A device comprising a comparator for detecting a time point at which the voltage satisfies a threshold value and disabling the driver when the voltage satisfies the threshold value.
前記ゲート傾斜制御回路が、前記ドライバをディセーブルするための信号を記憶して提供するためのラッチを含む、装置。 The device according to claim 8 .
A device comprising a latch for the gate tilt control circuit to store and provide a signal for disabling the driver.
前記ドライバと前記ゲート傾斜制御回路とが、N型金属酸化物半導体論理構成要素を用いて実装される、装置。 The device according to claim 8 .
A device in which the driver and the gate inclination control circuit are mounted by using an N-type metal oxide semiconductor logic component.
電圧を提供するための電源と、
前記電圧を受け取り、トランジスタのゲートを活性化して前記電源から電力を提供するように前記電圧を電流に変換するためのゲート傾斜制御及びドライバ回路であって、前記ゲートに電力を提供するためにチャージポンプと抵抗器とを含む、前記ゲート傾斜制御及びドライバ回路と、
前記ゲート傾斜制御が及びドライバ回路が前記ゲートを活性化するときに、前記電源から前記電力を受け取るためのデバイスと、
を含み、
前記ゲート傾斜制御及びドライバ回路が、前記ゲートが活性化されるまで前記ゲートの活性化を前記電流の経時的変化率に対応する経時的変化率で制御し、前記ゲートが活性化されるときに前記ゲート傾斜制御及びドライバ回路をディセーブルするためのものである、システム。 It ’s a system,
With a power supply to provide the voltage,
A gate tilt control and driver circuit for receiving the voltage, activating the gate of the transistor and converting the voltage into a current to provide power from the power source , charging to provide power to the gate. The gate tilt control and driver circuit, including the pump and resistor ,
A device for receiving the power from the power source when the gate tilt control and the driver circuit activates the gate.
Including
When the gate tilt control and driver circuit controls the activation of the gate at a rate of change over time corresponding to the rate of change of the current over time until the gate is activated and the gate is activated . A system for disabling the gate tilt control and driver circuits.
前記ゲート傾斜制御及びドライバ回路が、
前記電圧を前記ゲートに入力される電流に変換するためのトランスコンダクタを含むドライバと、
前記ゲートの活性化を制御し、制御傾斜がアクティブにされるときに前記ドライバをディセーブルするためのコンパレータと、
を更に含む、システム。 The system according to claim 15 .
The gate tilt control and driver circuit
A driver including a transformer for converting the voltage into a current input to the gate, and a driver.
A comparator that controls the activation of the gate and disables the driver when the control tilt is activated .
Further includes the system.
前記ゲート傾斜制御及びドライバ回路が、前記コンパレータが前記ドライバをディセーブルするときに前記電圧を入力電圧にプルアップするためものである、システム。 The system according to claim 16 .
A system in which the gate tilt control and driver circuit is for pulling up the voltage to an input voltage when the comparator disables the driver.
前記電源が、前記ゲート傾斜制御及びドライバ回路に前記電圧を提供するためコンデンサを含む、システム。 The system according to claim 15 .
A system in which the power supply comprises a capacitor to provide the voltage to the gate tilt control and driver circuit.
前記ゲート傾斜制御及びドライバ回路が、N型金属酸化物半導体論理構成要素を用いて実装される、システム。 The system according to claim 15 .
A system in which the gate tilt control and driver circuit are implemented using N-type metal oxide semiconductor logic components.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862615728P | 2018-01-10 | 2018-01-10 | |
US62/615,728 | 2018-01-10 | ||
US16/119,457 US10432175B2 (en) | 2018-01-10 | 2018-08-31 | Low quiescent current load switch |
US16/119,457 | 2018-08-31 | ||
PCT/US2019/013085 WO2019140113A1 (en) | 2018-01-10 | 2019-01-10 | Low quiescent current load switch |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2021518061A JP2021518061A (en) | 2021-07-29 |
JPWO2019140113A5 true JPWO2019140113A5 (en) | 2022-01-19 |
Family
ID=67141066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020538647A Pending JP2021518061A (en) | 2018-01-10 | 2019-01-10 | Low quiescent current load switch |
Country Status (5)
Country | Link |
---|---|
US (2) | US10432175B2 (en) |
EP (1) | EP3738207B1 (en) |
JP (1) | JP2021518061A (en) |
CN (1) | CN111801893B (en) |
WO (1) | WO2019140113A1 (en) |
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2018
- 2018-08-31 US US16/119,457 patent/US10432175B2/en active Active
-
2019
- 2019-01-10 JP JP2020538647A patent/JP2021518061A/en active Pending
- 2019-01-10 EP EP19738707.9A patent/EP3738207B1/en active Active
- 2019-01-10 CN CN201980016691.5A patent/CN111801893B/en active Active
- 2019-01-10 WO PCT/US2019/013085 patent/WO2019140113A1/en unknown
- 2019-08-16 US US16/543,110 patent/US10868521B2/en active Active
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