JPWO2019065656A1 - Through silicon via substrate and semiconductor device using through silicon via substrate - Google Patents

Abstract

The through electrode substrate is a substrate made of an inorganic material, a first wiring provided on the substrate, a through hole provided in the substrate at a position separated from the first wiring, and a through hole of the through hole. It has a through electrode provided on the inner wall, the first wiring, and a second wiring for connecting the through electrode. According to the present disclosure, in a through electrode substrate having a high aspect ratio using a glass substrate, a through electrode substrate in which continuity between the through electrode and the wiring on the substrate is ensured and electrical reliability is improved, and a manufacturing method thereof are provided. can do.

Description

The present disclosure relates to a through silicon via substrate. In particular, the present invention relates to a through electrode substrate having a crosslinked wiring that bridges the through electrode and the wiring on the substrate.

In recent years, with the miniaturization and speeding up of electronic devices such as smartphones and laptop computers, the density and speed of semiconductor components constituting electronic devices and wiring boards on which semiconductor components are mounted have been increased. ..

In a multilayer wiring board on which a plurality of wiring boards are laminated, a through electrode substrate on which a through electrode penetrating the wiring board is formed is used to connect the upper and lower wirings. As a method for forming such a through electrode, when the base material is an organic substrate, it is formed on the substrate by forming wiring in the through hole and performing electroless copper plating to obtain continuity. It is possible to obtain continuity between the formed wiring and the through electrode formed in the through hole.

Patent Document 1 discloses a printed wiring board having a bottomed hole formed in a substrate whose base material is glass epoxy and a via hole in which a conductive layer is formed in the bottomed hole.

Japanese Unexamined Patent Publication No. 2008-205070

However, when the base material is a substrate made of an inorganic material such as glass, silicon, or ceramic, it is difficult to uniformly roughen the inner wall of the through hole, and in order to form electroless copper plating, an adhesive layer is previously formed. Need to be formed. Further, when the adhesion layer is formed and electroless copper plating is performed, the copper plating is formed only on the portion where the adhesion layer is formed. In this case, if the wiring on the substrate and the through electrode in the through hole are connected by electroless copper plating, the wiring and the through electrode are connected via an insulating adhesive layer, which causes a problem in electrical reliability. ..

In view of the above problems, in the present disclosure, in a through electrode substrate having a high aspect ratio using a substrate made of an inorganic material such as glass, continuity between the through electrode and the wiring on the substrate is ensured, and electrical reliability is improved. One of the purposes is to provide a through electrode substrate and a method for manufacturing the same.

The through silicon via substrate according to the embodiment of the present disclosure is provided on the substrate at a position separated from the substrate made of an inorganic material, the first wiring provided on the substrate, and the first wiring. It has a through hole, a through electrode provided on the inner wall of the through hole, and a first wiring and a second wiring connecting the through electrode.

The through electrode substrate according to the embodiment of the present disclosure may further have an adhesion layer provided between the substrate and the through electrode.

In the through silicon via substrate according to the embodiment of the present disclosure, the second wiring may be further in contact with the adhesion layer.

In the through silicon via substrate according to the embodiment of the present disclosure, the adhesion layer may include an organic resin material.

The through electrode substrate according to the embodiment of the present disclosure includes the first wiring, the second wiring, an insulating layer provided on the through electrode, and a third wiring provided on the insulating layer. It may further have the insulating layer, the third wiring, and the fourth wiring in contact with the through electrode.

In the through electrode substrate according to the embodiment of the present disclosure, the insulating layer is made of an organic resin material, and the through electrode is provided inside the inner wall of the through hole and the opening provided in the insulating layer. You may.

In the through electrode substrate according to the embodiment of the present disclosure, the through electrodes are provided inside the first through electrode provided on the inner wall of the through hole and the opening provided in the insulating layer. It may include two through electrodes.

The through electrode substrate according to the embodiment of the present disclosure may have an aspect ratio of the through holes of 3 or more.

According to the present disclosure, in a through electrode substrate having a high aspect ratio using a glass substrate, a through electrode substrate in which continuity between the through electrode and the wiring on the substrate is ensured and electrical reliability is improved, and a manufacturing method thereof are provided. can do.

It is sectional drawing of the semiconductor device which uses the through electrode substrate which concerns on one Embodiment of this disclosure. FIG. 2A is a top view of the through silicon via substrate according to the embodiment of the present disclosure. FIG. 2B is a cross-sectional view taken along the cutting line shown in FIG. 2A. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing of the through silicon via substrate which concerns on another Embodiment of this disclosure. It is a top view of the through silicon via substrate shown in FIG. 7. FIG. 9A is a top view of the through silicon via substrate according to the embodiment of the present disclosure. 9 (B) is a cross-sectional view taken along the cutting line shown in FIG. 9 (A). It is sectional drawing of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view of the through silicon via substrate which concerns on one Embodiment of this disclosure.

Hereinafter, each embodiment of the present disclosure will be described with reference to drawings and the like. However, the present disclosure can be carried out in various aspects without departing from the gist thereof, and is not construed as being limited to the contents of the embodiments illustrated below.

In order to clarify the explanation, the drawings may schematically show the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example and the interpretation of the present disclosure is limited. It's not something to do. In the present specification and each drawing, elements having the same functions as those described with respect to the above-described drawings may be designated by the same reference numerals to omit duplicate explanations.

In the present specification and claims, when expressing the mode of arranging another structure on one structure, when it is simply described as "above", it comes into contact with a certain structure unless otherwise specified. It is assumed to include both the case where another structure is arranged directly above the structure and the case where another structure is arranged above the one structure via another structure. Further, in the present specification and claims, "U" and its arrow represent up or up in a cross section, and "D" and its arrow represent down or down in a cross section.

In the present specification and claims, the expression "overlapping" of one structure and another means that at least a part of these structures overlap in a plan view. In other words, it means that one of these structures is located above or below the other, and that at least some of these structures overlap each other when viewed from above or below. ..

The configuration of the through silicon via substrate 100 and the method of manufacturing the through silicon via substrate 100 according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 6.

[Structure of semiconductor device]
FIG. 1 shows a top view showing an example of a semiconductor device 1000 having a through electrode substrate 100, which is one of the embodiments of the present disclosure. The semiconductor device 1000 includes a printed circuit board 200, a through electrode substrate 100, an integrated circuit 300, bumps 122, and a wiring layer 120.

A plurality of integrated circuits 300 may be provided on the wiring layer 120, and the plurality of integrated circuits 300 may be electrically connected to each other via the wiring layer 120. Further, each integrated circuit 300 is electrically connected to the through silicon via substrate 100 via a conductor such as a wiring layer 120 and a bump 122. The through electrode substrate 100 is electrically connected to the printed circuit board 200 via a through electrode 108 described later.

FIG. 1 shows an example in which one integrated circuit 300 electrically connected to the wiring layer 120 is mounted on the through silicon via substrate 100, but the example is not limited to the example shown here. The number of terminals of the integrated circuit 300 may be four, five or more, or less than four. Further, the number of integrated circuits 300 mounted on the through electrode substrate 100 may be a plurality or one. Further, in the integrated circuit 300 mounted on the through electrode substrate 100, a plurality of integrated circuits having different numbers of terminals may be mounted. It can be appropriately selected depending on the application of the semiconductor device 1000. Note that FIG. 1 shows an example in which the through electrode substrate 100 is mounted on the printed circuit board 200, but the present invention is not limited to this example. The through silicon via substrate 100 may be mounted on, for example, a glass substrate or a flexible material such as FPC. It can be appropriately selected depending on the application of the semiconductor device.

[Structure of wiring board 1]
FIG. 2 shows an example of the through silicon via substrate according to the embodiment of the present disclosure. FIG. 2A is a top view of the through silicon via substrate according to the embodiment of the present disclosure. FIG. 2B is a cross-sectional view taken along the cutting line shown in FIG. 2A.

FIG. 2 shows a partial top view and a partial cross-sectional view of the through silicon via substrate 100 shown in FIG. The through electrode substrate 100 includes a glass substrate 102 having a through hole 10 penetrating the first surface 102a, the second surface 102b, the first surface 102a and the second surface 102b, and a through electrode provided on the inner wall of the through hole 10. Has 108. Further, although partly omitted in FIG. 2, a multilayer wiring layer such as the wiring layer 120 shown in FIG. 1 may be provided on the first surface 102a. The first wiring 104 shown in FIG. 2 constitutes a part of the wiring layer 120 shown in FIG.

The wiring layer 120 and the bump 122 are electrically connected to the through electrode 108. The through silicon via 108 is electrically connected to the bump 122. The integrated circuit 300 is electrically connected to the wiring layer 120 via the bump 122. The through silicon via substrate 100 is electrically connected to the printed circuit board 200 via the bump 122. The first surface 102a and the second surface 102b have a relationship of upper and lower or front and back with respect to the through electrode substrate 100.

As shown in FIG. 2, the through electrode substrate 100 is formed on the glass substrate 102, the through hole 10 penetrating the first surface 102a to the second surface 102b of the glass substrate 102, and the first surface 102a of the glass substrate 102. The first wiring 104 is provided, and the contact layer 106 provided on the inner wall of the through hole 10 and the through electrode 108 formed on the contact layer 106 are provided, and the through electrode 108 is formed on the first surface 102a of the glass substrate 102. It has a second wiring 110 that electrically connects the electrode 108 and the first wiring 104.

In this embodiment, an example in which a glass substrate 102 made of a glass material is used as a substrate is shown, but the present disclosure is not limited to this, and a silicon substrate made of a material containing silicon and a material containing alumina are shown. A ceramic substrate composed of may be used.

The glass substrate 102 has a first surface 102a and a second surface 102b as two main surfaces, and a first wiring 104 is formed on at least the first surface 102a. The first wiring 104 may constitute, for example, a TFT (thin film transistor).

In the present embodiment, the first wiring 104 is formed only on the first surface 102a, but the present disclosure is not limited to this, and both sides of the first surface 102a and the second surface 102b of the glass substrate 102 are both sides. Wiring may be formed in. The material of the first wiring 104 may be, for example, copper.

The thickness of the glass substrate 102 may be, for example, about 200 μm to 900 μm.

A through electrode 108 formed on the close contact layer 106 and the close contact layer 106 is formed on the side wall of the glass substrate 102 in the through hole 10. The adhesion layer 106 functions as a base for forming the material of the through electrode 108 on the glass substrate 102 by electroless plating. The adhesion layer 106 may be formed of a material containing an organic resin. The material containing the organic resin constituting the adhesion layer 106 may be, for example, an epoxy resin, an acrylic resin, a polyimide resin, a urethane resin, or the like. By forming the adhesion layer 106, a functional group having better catalytic adsorption than the glass surface can be introduced, and an electroless plating such as copper or nickel having good adhesion can be formed.

The through electrode 108 is formed on the surface of the glass substrate 102 on which the adhesion layer 106 is formed. Since the through electrode 108 is formed to obtain vertical conduction of the glass substrate 102, it is formed so as to cover all the side walls in the through hole 10 of the glass substrate 102, and is a hollow circle along the inner wall of the through hole 10. It is formed in a columnar shape. The hollow portion of the through electrode 108 may be referred to as a through hole 130. Further, since the through electrode 108 is electrically connected to the upper and lower wirings, the land 108-1 (from the through hole diameter) is formed on the peripheral edge of the through hole 130 on the first surface 102a to the second surface 102b of the glass substrate 102. May also have a large "land" portion). The material of the through electrode 108 may be, for example, copper or nickel.

As shown in FIG. 2, the through hole 10 and the through hole 130 may be concentric circles having the same central axis. The hole diameter of the through hole 10 may be, for example, about 40 μm to 140 μm, and the hole diameter of the through hole 130 may be, for example, about 30 μm to 135 μm. In the wiring board shown in FIG. 2, the hole diameter of the through hole 10 is larger than the hole diameter of the through hole 130.

Although the hollow through hole 130 is shown in FIG. 2, the inside of the through hole 130 may be filled with the same plating as the through electrode 108, or may be filled with an organic resin or a metal different from the through electrode 108. May be good.

A second wiring 110 in contact with the glass substrate 102, the first wiring 104, and the through electrode 108 is formed on the first surface 102a of the glass substrate 102. The second wiring 110 has a function as a cross-linking wiring that electrically connects the first wiring 104 and the land 108-1 on the first surface 102a of the through electrode 108. The material of the second wiring 110 may be any material as long as it is a conductive material such as copper, nickel, or tin.

The second wiring 110 may be a single layer as shown in FIG. 2, but the present disclosure is not limited thereto. For example, when the material of the second wiring 110 is copper, in order to improve the adhesion between the copper and the glass substrate 102, an adhesion layer made of a low resistance metal film such as Ti is provided between the copper and the glass substrate 102. It may have a multi-layer structure including one or more layers.

FIG. 10 is a cross-sectional view of the through silicon via substrate according to the embodiment of the present disclosure. The second wiring 110'shown in FIG. 10 has a contact layer 110-1 made of a low resistance metal film such as Ti formed on the glass substrate 102 and a conductive layer 110-1 such as copper formed on the contact layer 110-1. It has a two-layer structure in which a second wiring portion 110-2 made of a material having a property is laminated. According to the configuration shown in FIG. 10, the adhesion between the second wiring portion 110-2 of the second wiring 110'and the glass substrate 102 can be improved. Further, although not shown, the close contact layer 110-1 of the second wiring 110'shown in FIG. 10 may have a multilayer structure composed of two or more low resistance metal films.

Further, any wiring can be used as long as the second wiring 110 can be electrically connected by bridging the first wiring 104 formed on one main surface of the glass substrate 102 and the through electrode 108. It may be anything. For example, the second wiring 110 may be wire bonding that electrically connects the first wiring 104 and the through electrode 108, or may be solder that electrically connects the first wiring 104 and the through electrode 108. There may be. The material of the second wiring 110 may be, for example, a metal oxide such as nickel, gold, tin, copper, aluminum, titanium, chromium, or ITO.

As shown in FIG. 2, a plurality of second wirings 110 may be connected to one through electrode 108 so as to be pulled out in different directions. However, the present disclosure is not limited to this. FIG. 11 is a top view of the through silicon via substrate according to the embodiment of the present disclosure. As shown in FIG. 11, only one second wiring 110 may be connected to one through electrode 108 and electrically connected to the first wiring 104.

The first wiring 104, the second wiring 110, and the through electrode 108 are made of a conductive material. For example, gold, silver, copper, platinum, nickel, rhodium, ruthenium, iridium and the like can be used. The same material may be used for the first wiring 104, the second wiring 110, and the through electrode 108, or different materials may be used in combination. By forming the first wiring 104, the second wiring 110, and the through electrode 108 with the same material, the characteristic impedance matching can be improved.

In the present embodiment, since the through electrode 108 and the first wiring 104 are electrically connected by the second wiring 110, the continuity between the through electrode 108 and the first wiring 104 on the glass substrate 102 is ensured. Improves electrical reliability.

[Modification example of structure 1 of wiring board]
In the example shown in FIG. 2, the second wiring 110 is directly connected to the land 108-1 on the first surface 102a of the through electrode 108, but the present disclosure is not limited thereto. FIG. 9 is a diagram showing a modified example of the through silicon via substrate according to the embodiment of the present disclosure shown in FIG. FIG. 9A is a top view of the through silicon via substrate according to the embodiment of the present disclosure. 9 (B) is a cross-sectional view taken along the cutting line shown in FIG. 9 (A).

As shown in FIG. 9, the through electrode 108 may have a wiring portion 108-2 extending from the land 108-1 formed on the first surface 102a. In this case, the second wiring 110 may be directly connected to the wiring portion 108-2 extending from the land 108-1 formed on the first surface 102a of the through electrode 108.

[Manufacturing method of wiring board 1]
The manufacturing method of the through silicon via substrate 100 according to the first embodiment of the present disclosure shown in FIG. 2 will be described with reference to FIGS. 2 to 6. Note that, in FIGS. 3 to 6, the same configurations as those in FIGS. 1 to 2 will be described with the same reference numerals.

First, the first wiring 104 is formed on the glass substrate 102 (see FIG. 3). The first wiring 104 may constitute an element such as a TFT. In FIG. 3, the first wiring 104 is formed on the first surface 102a of the glass substrate 102, but the present invention is not limited to this, and the first wiring is formed not only on the first surface 102a but also on the second surface 102b. 104 may be formed.

Next, a through hole 10 penetrating the first surface 102a and the second surface 102b is formed in the glass substrate 102 on which the first wiring 104 is formed on one side or both sides (see FIG. 4). The position where the through hole 10 is formed in the glass substrate 102 is a portion where the first wiring 104 is not formed. The through hole 10 is formed at a position separated from the first wiring 104. The shape of the through hole 10 may be a cylindrical shape in which the upper and lower hole diameters are substantially constant.

The method of forming the through hole 10 in the glass substrate 102 may be any method.

Next, the adhesion layer 106 is formed on the inner wall of the through hole 10 formed in the glass substrate 102 and the peripheral edge of the through hole on the first surface 102a and the second surface 102b (see FIG. 5). The adhesion layer 106 may be formed by a method such as spin coating, dip coating, or spray coating. The close contact layer 106 functions as a close contact layer for subsequently forming a through electrode material. The adhesion layer 106 may be formed of a material containing an organic resin.

Next, the through electrode 108 is formed on the portion of the surface of the glass substrate 102 on which the adhesion layer 106 is formed (see FIG. 6). The through electrode 108 is formed on the adhesion layer 106 formed on the surface of the glass substrate 102. The through silicon via 108 is formed by coating copper, nickel, or the like using an electroless plating method.

Here, when a modified example of the structure 1 of the wiring board shown in FIG. 9 is manufactured, the wiring portion 108-2 extending from the land 108-1 formed on the first surface 102a of the through electrode 108 also penetrates. It may be formed in the above step at the same time as the electrode 108. Specifically, a through electrode 108 including a land 108-1 and a wiring portion 108-2 extending from the land 108-1 is formed on a portion of the surface of the glass substrate 102 on which the adhesion layer 106 is formed (FIG. 9). See). The through electrode 108 is formed on the adhesion layer 106 formed on the surface of the glass substrate 102. The through silicon via 108 is formed by coating copper, nickel, or the like using an electroless plating method.

In the present disclosure, by using the adhesion layer 106 as an adhesion layer or a reducing agent, a through electrode material can be formed in the through holes 10 formed on the glass substrate 102 by an electroless plating method or the like.

Unlike the present disclosure, there is also a method in which a through electrode material such as copper is formed by a sputtering method in the through holes 10 formed on the glass substrate 102 without forming the adhesion layer 106.

If the aspect ratio of the through hole of the glass substrate is low (for example, if the plate thickness is small or the hole diameter is large), even if the method of forming an electrode material such as copper in the through hole by the sputtering method is used. , It is possible to form a through electrode.

The aspect ratio is a value of plate thickness / hole diameter, and the relationship between the plate thickness of the glass substrate 102 and the hole diameter of the through hole of the glass substrate 102 is expressed by the aspect ratio of the through hole of the glass substrate. For example, when the plate thickness is large or the hole diameter is small, the aspect ratio is high, and when the plate thickness is small or the hole diameter is large, the aspect ratio is small.

However, when the aspect ratio of the through hole of the glass substrate is high (for example, when the plate thickness is large or the hole diameter is small), the electrode material is sufficiently applied to the inside of the through hole far from the main surface of the glass substrate by the sputtering method. Since the film cannot be formed, blank portions (voids and voids) in which the electrode material is not formed are likely to occur inside the through holes, which causes a problem in electrical reliability. For example, when the aspect ratio of the through hole of the glass substrate is 3 or more, voids and voids are likely to be generated in the through hole in the sputtering method, which causes a problem in electrical reliability.

In the present disclosure, by using the adhesion layer 106 as an adhesion layer or a reducing agent, even when the aspect ratio of the through hole 10 formed in the glass substrate 102 is high, it penetrates into the through hole 10 by an electroless plating method or the like. The electrode material can be sufficiently formed. Therefore, the present disclosure is particularly useful in that the electrical reliability can be further improved in a wiring board having a high density arrangement in which the aspect ratio of the through holes 10 formed in the glass substrate 102 is 3 or more.

Next, in order to electrically connect the first wiring 104 formed on the glass substrate 102 and the through electrode 108 formed at a position separated from the first wiring 104, the first wiring 104 and the glass substrate 102 are connected. A second wiring 110 in contact with the through electrode 108 is formed (see FIG. 2). In FIG. 2, the second wiring 110 is a wiring formed so as to be in contact with the first surface 102a of the glass substrate by a sputtering method or the like, but the present disclosure is not limited thereto.

As described above, in order to form the through electrode 108 by electroless copper plating on the glass substrate 102, it is necessary to form the adhesion layer 106 on the glass substrate 102 as an adhesion layer. Further, it is not possible to obtain continuity between the through electrode 108 and the wiring layer such as the first wiring 104 formed in advance on the glass substrate 102 only by forming the through electrode 108 via the close contact layer 106. Therefore, in the present disclosure, in order to obtain continuity between the wiring layer such as the first wiring 104 formed in advance on the glass substrate 102 and the through electrode 108 formed via the close contact layer 106, the first wiring is used as a crosslinked wiring. Two wirings 110 are provided.

In the present disclosure, since the second wiring 110 electrically connects the first wiring 104 and the through electrode 108 formed on one main surface of the glass substrate 102 as a bridge wiring, the through electrode 108 and the through electrode 108 are the first. It is possible to provide a through silicon via substrate in which continuity with one wiring 104 is ensured and electrical reliability is improved.

Further, as shown in FIG. 2, the second wiring 110 may be a wiring formed so as to be in contact with the first surface 102a of the glass substrate by a sputtering method or the like. In this case, the second wiring 110 is arranged so as to be in direct contact with one main surface of the glass substrate 102 (not insulated and separated), and the first wiring 104 and the through electrode 108 (however, the through electrode 108) are in direct contact with the same surface. A close contact layer 106 is interposed between the glass substrate 102 and the glass substrate 102). Specifically, in FIG. 2, the first wiring 104 that is in direct contact with the first surface 102a of the glass substrate and the land 108-1 on the first surface 102a of the through electrode 108 are formed on the first surface 102a of the glass substrate. It is electrically connected by a second wire 110 that is in direct contact with it.

According to the structure of the second wiring 110 shown in FIG. 2, the first wiring 104 directly in contact with the first surface 102a of the glass substrate and the land 108-1 of the through electrode 108 are in direct contact with the first surface 102a of the glass substrate. Since it is electrically connected by the second wiring 110, the wiring density in the layer directly in contact with the first surface 102a of the glass substrate on which the first wiring 104 and the land 108-1 of the through electrode 108 are formed can be determined. Can be enhanced. If the wiring density in the layer that is in direct contact with the first surface 102a of the glass substrate is increased in this way, it becomes easier to form wiring to other layers, and the degree of freedom in wiring design is increased.

Further, since the first wiring 104 and the land 108-1 of the through electrode 108 are connected in the same layer that is in direct contact with the first surface 102a of the glass substrate, the wiring length of the second wiring 110 can be shortened. Therefore, the resistance is low and the current can flow stably. Further, since the second wiring 110 is in direct contact with the same surface as the first wiring 104 and the land 108-1 of the through electrode 108, the height of the wiring layer can be reduced. Further, when another wiring is laminated on the wiring layer via an insulating layer, the flatness of the lower wiring layer can be ensured.

Further, since the first wiring 104, the land 108-1 of the through electrode 108, and the second wiring 110 are formed on the first surface 102a of the same glass substrate as a base, the first surface 102a of the glass substrate is thermally expanded. Since the stress due to the above is uniformly applied to each of the first wiring 104, the through electrode 108, and the second wiring 110, distortion and disconnection of the wiring are less likely to occur, and the connection reliability is improved.

[Structure of wiring board 2]
As the configuration 2 of the wiring board, the through silicon via substrate according to another embodiment of the present disclosure will be described with reference to FIGS. 7 and 8. The same configurations as those in FIGS. 1 and 2 will be described with the same reference numerals.

The through electrode substrate 100'shown in FIG. 7 includes a glass substrate 102, a first through electrode 108a, a first wiring 104, and a second wiring 110 constituting the through electrode substrate 100 shown in FIG. The through silicon via substrate 100'shown in FIG. 7 further has an insulating layer 112, and on the insulating layer 112, a third wiring 114 constituting an upper wiring layer of the first wiring 104 is provided. The insulating layer 112 has an opening 20 on the first through electrode 108a, and a second through electrode 108b is formed on the inner wall of the opening 20. The second through electrode 108b and the third wiring 114 have a configuration in which they are crosslinked by the fourth wiring 116 on the insulating layer 112.

The insulating layer 112 is provided so as to cover the first wiring 104, the second wiring 110, and the first through electrode 108 on the first surface 102a of the glass substrate 102. The insulating layer 112 is an insulating layer made of an organic resin material, and is an interlayer insulation for laminating another wiring layer composed of the third wiring layer 114 on the wiring layer composed of the first wiring 104. Functions as a film.

The insulating layer 112 has an opening 20 at a position where it overlaps with the through hole 10 in which the first through electrode 108a is formed, and the second through electrode 108b is formed on the inner wall of the opening 20 of the insulating layer 112. There is.

Since the second through electrode 108b is formed in the opening 20 of the insulating layer 112 made of an organic resin material, unlike the first through electrode 108a, it is not necessary to interpose a close contact layer. Therefore, the second through electrode 108b can be directly formed on the surface of the insulating layer 112 by a method such as electroless copper plating.

The second through electrode 108b electrically connects the third wiring 114 formed in the upper layer and the first through electrode 108a, and the third wiring 114 and the second wiring 114 formed on the first surface 102a of the glass substrate 102. It functions to obtain vertical continuity with other wiring or the like formed on the surface 102b.

The second through electrode 108b and the third wiring are formed at a position separated from each other on the insulating layer 112, and the fourth wiring 116 bridges the second through electrode 108b and the third wiring on the insulating layer 112. And electrically connect in the same layer.

In the through electrode substrate 100'shown in FIG. 7, a wiring layer including the first wiring 104 and a wiring layer including the third wiring are laminated on the first surface 102a of the glass substrate 102, and the first wiring 104 is formed. In the including wiring layer, the first through electrode 108a and the first wiring 104 that are in direct contact with the first surface 102a of the glass substrate 102 are bridged in the same layer by the second wiring 110 that is in direct contact with the first surface 102a of the glass substrate 102. Has a configuration that Further, in the wiring layer including the third wiring 114, the second through electrode 108b and the third wiring 114 that are in direct contact with the upper surface of the insulating layer 112 are crosslinked in the same layer by the fourth wiring 116 that is directly in contact with the upper surface of the insulating layer 112. Has a configuration to be Other configurations are the same as those of the through silicon via substrate 100 shown in FIGS. 1 and 2.

In FIG. 7, two layers, a wiring layer including the first wiring 104 and a wiring layer including the third wiring, are laminated on the first surface 102a of the glass substrate 102, but the present disclosure is limited to this. Instead, three or more wiring layers may be laminated.

Further, as shown in FIG. 7, the through electrode substrate 100 ′ has a third through electrode 108c that vertically conducts the third wiring 114 and other wiring or the like formed on the second surface 102b of the glass substrate 102. Further preparations may be made. As shown in FIG. 7, an insulating layer 112 may be formed between the third through electrode 108c and the glass substrate 102. As a method for manufacturing the insulating layer 112, for example, the insulating layer 112 may be formed by applying an insulating liquid resist film on the surface of the glass substrate 102 using a roller coater. In addition, the insulating layer 112 may be formed by using a dip coater or a spray coater.

FIG. 8 is a top view of the through silicon via substrate shown in FIG. 7. In FIG. 8, the wiring and through electrodes on the uppermost surface are shown by solid lines, and the wiring and through electrodes located in the lower layer are shown by broken lines as a transmission diagram. As shown in FIGS. 7 and 8, the plurality of first through electrodes 108a are connected to each other by a wiring layer including the first wiring 104, and the second through electrode 108b is the third wiring which is the upper layer of the first wiring 104. A wiring layer including 114 is connected to a third through electrode 108c, which is another through electrode.

In the present disclosure, since the fourth wiring 116 bridges and connects the third wiring 114 and the second through electrode 108b formed separately on the insulating layer 112 with the same layer, the second through electrode 108b and the second through electrode 108b are connected. It is possible to provide a through electrode substrate 100'in which continuity with the three wirings 114 is ensured and electrical reliability is improved.

As shown in FIGS. 7 and 8, the second through electrode 108b forms a land 108b-1 on the peripheral edge of the through hole 130b, which is a hollow portion, and this land electrically connects other wiring and the through electrode. It functions as a connection part to connect to. Further, the first through electrode 108a and the third through electrode 108c may also have lands on the peripheral edge of the through hole as in the case of the second through electrode 108b.

According to the through silicon via substrate 100'having a plurality of wiring layers shown in FIGS. 7 and 8, the wiring density can be further improved by stacking the wiring layers while ensuring electrical reliability.

Each of the above-described embodiments as the embodiments of the present disclosure can be appropriately combined and implemented as long as they do not contradict each other. In addition, those skilled in the art who appropriately add, delete, or change the design of components based on each embodiment are also included in the scope of the present disclosure as long as the gist of the present disclosure is provided.

In addition, even if the effects are different from the effects brought about by each of the above-described embodiments, those that are clear from the description of the present specification or those that can be easily predicted by those skilled in the art are of course. It is understood to be brought about by this disclosure.

100, 100': Through electrode substrate, 102: glass substrate, 102a: first surface, 102b: second surface, 104: first wiring, 10: through hole, 108, 108a, 108b: through electrode, 110: second Wiring, 106: Adhesion layer, 112: Insulation layer, 114: Third wiring, 116: Fourth wiring, 20: Opening

Claims (9)

A substrate made of an inorganic material and
The first wiring provided on the substrate and
A through hole provided in the substrate at a position separated from the first wiring,
Through electrodes provided on the inner wall of the through hole and
The first wiring and the second wiring connecting the through electrodes,
A through silicon via substrate. The through electrode substrate according to claim 1, further comprising an adhesion layer provided between the substrate and the through electrode. The through silicon via substrate according to claim 2, wherein the second wiring is in contact with the close contact layer. The through silicon via substrate according to claim 2, wherein the adhesion layer contains an organic resin material. An insulating layer provided on the first wiring, the second wiring, and the through electrode,
The third wiring provided on the insulating layer and
The through electrode substrate according to any one of claims 1 to 4, further comprising the insulating layer, the third wiring, and the fourth wiring in contact with the through electrode. The insulating layer is made of an organic resin material.
The through electrode substrate according to claim 5, wherein the through electrode is provided inside the inner wall of the through hole and the opening provided in the insulating layer. The through silicon via according to claim 6, wherein the through electrode includes a first through electrode provided on the inner wall of the through hole and a second through electrode provided inside the opening provided in the insulating layer. Through electrode substrate. The through electrode substrate according to any one of claims 1 to 4, wherein the through hole has an aspect ratio of 3 or more. A semiconductor device using the through silicon via substrate according to any one of claims 1 to 4.

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