JPWO2017159029A1 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JPWO2017159029A1 JPWO2017159029A1 JP2017523934A JP2017523934A JPWO2017159029A1 JP WO2017159029 A1 JPWO2017159029 A1 JP WO2017159029A1 JP 2017523934 A JP2017523934 A JP 2017523934A JP 2017523934 A JP2017523934 A JP 2017523934A JP WO2017159029 A1 JPWO2017159029 A1 JP WO2017159029A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
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- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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Abstract
Description
最初に、本開示の技術の実施形態の内容を列記して説明する。
本開示の技術の実施形態の具体例を、以下に図面を参照しつつ説明する。本発明はこれらの例示に限定されるものではなく、請求の範囲によって示され、請求の範囲内と均等の範囲内とでのすべての変更が含まれることが意図される。図面の説明においては同一要素には同一符号を付し、重複する説明を省略する。
図4は、第1の変形例に係る半導体モジュール1Aの模式図である。図5は、図4に示した半導体モジュール1Aが有する絶縁基板10上の構成を模試的に示す図面である。図5では、導線W1〜W8の図示を省略している。半導体モジュール1Aは、Nパッド23が第3領域233を有する点で、半導体モジュール1の構成と主に相違する。この相違点を中心にして、半導体モジュール1Aについて説明する。
図6は、第2の変形例に係る半導体モジュール1Bの模式図である。半導体モジュール1Bは、Nパッド23が第4領域(コンデンサ接続領域)234を更に有する点で、第1の変形例の半導体モジュール1Aの構成と主に相違する。この相違点を中心にして、半導体モジュール1Bについて説明する。複数の第1トランジスタTr1及び複数の第2トランジスタTr2などの配線構造は、第1の変形例と同様であるため、図6において、導線W1〜W8の図示は、省略している。
図7は、第3の変形例に係る半導体モジュール1Cの模式図である。図8は、図7に示した半導体モジュール1Cが有する絶縁基板10上の構成を模式的に示す図面である。図8では、導線W1〜W8の図示を省略している。半導体モジュール1Cの構成は、第3補助パッド28を有する点及び吸収素子30Aを有する点で、第1の変形例の半導体モジュール1Aと主に相違する。この相違点を中心にして、半導体モジュール1Cについて説明する。
Claims (6)
- 電力変換回路を含む半導体モジュールであって、
絶縁基板と、
前記電力変換回路における上アームを構成する第1トランジスタと、
前記電力変換回路における下アームを構成しており前記第1トランジスタに電気的に直列接続される第2トランジスタと、
前記絶縁基板上に設けられており、前記電力変換回路に正電力を供給する正側入力端子が接続される第1入力用配線パターンと、
前記絶縁基板上に設けられており、前記電力変換回路に負電力を供給する負側入力端子が接続される第2入力用配線パターンと、
前記絶縁基板上に設けられており、前記電力変換回路からの出力電力を取り出す出力端子が接続される出力用配線パターンと、
前記電力変換回路におけるサージ電圧を吸収する吸収素子と、
を備え、
前記第1入力用配線パターンは、前記第1トランジスタが搭載される第1トランジスタ搭載領域を有し、
前記出力用配線パターンは、前記第2トランジスタが搭載される第2トランジスタ搭載領域を有し、
前記第2入力用配線パターンは、前記第1トランジスタ搭載領域と前記第2トランジスタ搭載領域との間に配置される吸収素子接続領域を有し、
前記吸収素子接続領域と前記第1トランジスタ搭載領域とが前記吸収素子を介して電気的に接続されている、
半導体モジュール。 - 前記第2入力用配線パターンは、前記吸収素子接続領域の一端に連続的に繋がったコンデンサ接続領域を有し、
前記吸収素子接続領域及び前記コンデンサ接続領域は、前記第1トランジスタ搭載領域を囲むように前記絶縁基板上に設けられており、
前記コンデンサ接続領域と前記第1トランジスタ搭載領域とは、コンデンサを介して電気的に接続されている、
請求項1に記載の半導体モジュール。 - 前記絶縁基板上において、前記吸収素子接続領域と、前記第1トランジスタ搭載領域との間に設けられる補助配線パターンを更に備え、
前記吸収素子は、第1回路素子と第2回路素子を含み、
前記第1回路素子は、前記補助配線パターンと前記第1トランジスタ搭載領域とを電気的に接続しており、
前記第2回路素子は、前記補助配線パターンと前記吸収素子接続領域とを電気的に接続している、
請求項1又は2に記載の半導体モジュール。 - 前記第1トランジスタを複数有し、
複数の前記第1トランジスタは、前記第1トランジスタ搭載領域に搭載されると共に、電気的に並列接続されており、
前記第2トランジスタを複数有し、
複数の前記第2トランジスタは、前記第2トランジスタ搭載領域に搭載されると共に、電気的に並列接続されている、
請求項1〜3の何れか一項に記載の半導体モジュール。 - 前記吸収素子を複数有し、
複数の前記吸収素子は、互いに離間して配置されている、
請求項1〜4の何れか一項に記載の半導体モジュール。 - 絶縁基板と、
電力変換回路の上アームを構成する第1トランジスタと、
前記電力変換回路の下アームを構成する第2トランジスタと、
前記絶縁基板上に設けられる平板状導体であって、前記第1トランジスタが搭載され、前記第1トランジスタの第1端が電気的に接続される第1入力用配線パターンと、
前記絶縁基板上に設けられる平板状導体であって、前記第2トランジスタが搭載され、前記第2トランジスタの第1端が電気的に接続される出力用配線パターンと、
前記絶縁基板上に設けられ、前記第1入力用配線パターンと前記出力用配線パターンとの間の位置に配置される第2入力用配線パターンと、
前記第1トランジスタの第2端と前記出力用配線パターンとを互いに電気的に接続する配線と、
前記第2トランジスタの第2端と前記第2入力用配線パターンとを互いに電気的に接続する配線と、
前記第1入力用配線パターンと前記第2入力用配線パターンとの間に接続される容量性素子と
を含む半導体モジュール。
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