JPWO2017033082A1 - Semiconductor device and electronic device having the semiconductor device - Google Patents

Abstract

A light-emitting device that has an oxide semiconductor film and emits near-infrared light is provided. A semiconductor device including a transistor. The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film having a region overlapping with the first gate electrode with the first insulating film interposed therebetween, A second insulating film over the oxide semiconductor film, a second gate electrode having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween, and over the oxide semiconductor film and the second gate electrode A third insulating film. The oxide semiconductor film includes a channel region in contact with the second insulating film, the channel region includes a region that emits light, and light emission includes near-infrared light.

Description

  One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and an electronic device including the semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a driving method thereof, or As an example, their production methods can be mentioned.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  A technique for forming a transistor (also referred to as a thin film transistor (TFT) or a field effect transistor (FET)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image device (display device). As a semiconductor thin film applicable to a transistor, a semiconductor material typified by silicon is widely known, but an oxide semiconductor has attracted attention as another material.

  For example, a technique for manufacturing a transistor using an In—Ga—Zn-based oxide as an oxide semiconductor is disclosed (see Patent Document 1). In addition, a technique for manufacturing an oxide thin film transistor having a self-aligned top gate structure is disclosed (see Patent Document 2).

  In recent years, technical development of a display device having a function of inputting information has been advanced, and Patent Document 3 discloses an optical touch panel that reads input data by detecting infrared rays.

  Further, electronic devices having a function of detecting biological information such as a pulse, a vein, and a pupil are attracting attention, and a biological sensor using infrared rays has been developed (Patent Document 4).

JP 2007-96055 A JP 2009-278115 A JP 2012-22675 A JP-A-5-329116

  In an optical touch panel having a light emitting diode (LED) that exhibits infrared light, a sensor that detects infrared light is provided on the display surface side of the display device, and the LED that exhibits infrared light is used as a backlight. The position of the sensor for detecting is separated. Therefore, the light in the detection environment and the light in the display device become noise, and the infrared detection accuracy is lowered.

  In addition, when an LED is used as a light emitting element that emits infrared light in an electronic device that reads biological information or the like, the LED can irradiate infrared light over a wide range, but it is difficult to irradiate a minute region with infrared light. . Therefore, it is difficult to increase the detection accuracy and the detection definition only by increasing the definition of a sensor that detects infrared rays in order to detect minute information.

  In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device including a transistor that emits infrared light. Another object of one embodiment of the present invention is to provide a semiconductor device that emits infrared light with high definition. Another object of one embodiment of the present invention is to provide a semiconductor device capable of detecting infrared light with high accuracy. Another object of one embodiment of the present invention is to provide a display device capable of detecting infrared rays with high accuracy. Another object of one embodiment of the present invention is to provide an electronic device that can detect infrared light with high accuracy. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

  Note that the description of the above problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than those described above are naturally apparent from the description of the specification and the like, and it is possible to extract problems other than the above from the description of the specification and the like.

  One embodiment of the present invention is a semiconductor device including an oxide semiconductor film that can efficiently exhibit infrared rays. Alternatively, the semiconductor device has an oxide semiconductor film and can exhibit infrared rays with high definition.

  Accordingly, one embodiment of the present invention is a semiconductor device including a transistor, the transistor including the first gate electrode, the first insulating film over the first gate electrode, and the first insulating film. An oxide semiconductor film having a region overlapping with the first gate electrode, a second insulating film over the oxide semiconductor film, and a second region having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween And a third insulating film over the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region in contact with the second insulating film, and a third insulating film. The semiconductor device includes a source region in contact with the film and a drain region in contact with the third insulating film, the channel region includes a region that emits light, and the light emission includes near infrared light.

  Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first gate electrode, a first insulating film over the first gate electrode, and a first insulating film. An oxide semiconductor film having a region overlapping with the first gate electrode, a second insulating film over the oxide semiconductor film, and a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween A second gate electrode, and a third insulating film over the oxide semiconductor film and the second gate electrode, the oxide semiconductor film including a channel region in contact with the second insulating film, 3 has a source region in contact with the third insulating film and a drain region in contact with the third insulating film, the channel region has a function of emitting light, and the light emission is in a wavelength region of 900 nm to 1550 nm. Including a semiconductor device.

  In each of the above structures, the transistor further includes a source electrode electrically connected to the oxide semiconductor film in the source region through the first opening provided in the third insulating film; A drain electrode electrically connected to the oxide semiconductor film in the drain region through a second opening provided in the insulating film is a semiconductor device.

  In each of the above structures, the oxide semiconductor film preferably includes In, Zn, and M (M is Al, Ga, Y, or Sn). The oxide semiconductor film preferably includes a region where the In content is greater than or equal to the M content. The oxide semiconductor film preferably includes a crystal part, and the crystal part preferably has c-axis alignment.

  In each of the above structures, the second gate electrode preferably includes In, Zn, and M (M is Al, Ga, Y, or Sn). The second gate electrode preferably includes a region where the In content is equal to or higher than the M content. The second gate electrode preferably has a higher carrier density than the oxide semiconductor film.

  In each of the above structures, the third insulating film preferably includes at least one of nitrogen and hydrogen.

  Another embodiment of the present invention is a display device including the semiconductor device of any of the above embodiments and a display element. Another embodiment of the present invention is an electronic device including the semiconductor device of the above embodiment and a sensor.

  According to one embodiment of the present invention, a semiconductor device including a transistor exhibiting infrared light can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device exhibiting infrared rays with high definition can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of detecting infrared light with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of detecting infrared light with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, an electronic device that can detect infrared light with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

3A and 3B illustrate a top surface and a cross section of a semiconductor device. 3A and 3B illustrate a top surface and a cross section of a semiconductor device. 3A and 3B illustrate a top surface and a cross section of a semiconductor device. 6A and 6B illustrate a cross section of a semiconductor device. 6A and 6B illustrate a cross section of a semiconductor device. 6A and 6B illustrate a cross section of a semiconductor device. 6A and 6B illustrate a cross section of a semiconductor device. 6A and 6B illustrate a cross section of a semiconductor device. The figure explaining a band structure. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. Sectional drawing which shows the structural example of a display apparatus. FIG. 14 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 10A and 10B each illustrate a circuit configuration of a semiconductor device. 3A and 3B illustrate a structure of a pixel circuit and a timing chart illustrating an operation of the pixel circuit. 10A and 10B are a block diagram and a circuit diagram illustrating a display device. The figure explaining a display module. 10A and 10B each illustrate an electronic device. The figure explaining arrangement | positioning of a light emitting element and a light receiving element. 4A and 4B illustrate an arrangement of a display portion, a light emitting element, and a light receiving element. 3A and 3B illustrate a top surface and a cross section of a transistor in an example. 8A and 8B illustrate an Id-Vg characteristic of a transistor in an example. 8A and 8B illustrate a light-emitting state of a transistor in an example. 8A and 8B illustrate a light-emitting state of a transistor in an example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and various changes can be made in form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

  In the present specification and the like, the ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  Further, in this specification, terms indicating arrangements such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

  Further, in this specification and the like, in describing the structure of the invention with reference to the drawings, the same reference numerals are used in different drawings.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. Further, the boundary between “semiconductor” and “insulator” is ambiguous, and there is a case where it cannot be strictly distinguished. Therefore, the “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. Alternatively, the “insulator” in this specification and the like can be referred to as a “semi-insulator” in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. Further, the boundary between the “semiconductor” and the “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification and the like can be called a “conductor” in some cases. Similarly, a “conductor” in this specification and the like can be called a “semiconductor” in some cases.

  In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification and the like, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification and the like, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

  In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Therefore, a voltage can be rephrased as a potential.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

(Embodiment 1)
In this embodiment, an example of a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described below with reference to FIGS.

<1-1. Configuration Example 1 of Semiconductor Device>
FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG. 1A, and FIG. 1C illustrates the dashed-dotted line Y1- in FIG. This corresponds to a cross-sectional view of the cut surface between Y2. Note that in FIG. 1A, some components of the transistor 100 (a substrate 102, an insulating film, and the like) are omitted for clarity.

  In addition, the dashed-dotted line X1-X2 direction in FIG. 1A may be referred to as a channel length (L) direction of the transistor 100, and the dashed-dotted line Y1-Y2 direction may be referred to as a channel width (W) direction of the transistor 100.

  The transistor 100 includes a conductive film 106 functioning as a first gate electrode (also referred to as a bottom gate electrode) over a substrate 102, an insulating film 104 over the substrate 102 and the conductive film 106, and an oxide semiconductor film over the insulating film 104. 108, an insulating film 110 over the oxide semiconductor film 108, a conductive film 112 functioning as a second gate electrode (also referred to as a top gate electrode) over the insulating film 110, an insulating film 104, an oxide semiconductor film 108, And the insulating film 116 over the conductive film 112. The oxide semiconductor film 108 includes a channel region 108 i in contact with the insulating film 110, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.

  In addition, the transistor 100 is electrically connected to the oxide semiconductor film 108 in the source region 108s through the insulating film 118 over the insulating film 116 and the opening 141s provided in the insulating film 116 and the insulating film 118. The conductive film 120s is electrically connected to the oxide semiconductor film 108 in the drain region 108d through the opening 141d provided in the insulating film 116 and the insulating film 118.

  Note that in this specification and the like, the insulating film 104 is a first insulating film, the insulating film 110 is a second insulating film, the insulating film 116 is a third insulating film, and the insulating film 118 is a fourth insulating film. And may be called respectively. In the transistor 100, the insulating film 104 functions as a first gate insulating film, and the insulating film 110 functions as a second gate insulating film. Therefore, in this specification and the like, the insulating film 104 may be referred to as a first gate insulating film, and the insulating film 110 may be referred to as a second gate insulating film. In addition, the conductive film 120s functions as a source electrode, and the conductive film 120d functions as a drain electrode.

  In the transistor 100, it is preferable that a side end portion of the insulating film 110 and a side end portion of the conductive film 112 have a region where they are aligned. In other words, the transistor 100 has a structure in which the upper end portion of the insulating film 110 and the lower end portion of the conductive film 112 are roughly aligned. For example, the above structure can be obtained by processing the insulating film 110 using the conductive film 112 as a mask.

  In the transistor 100, the conductive film 106 and the conductive film 112 are electrically connected to each other through the insulating film 104 and the opening 143 provided in the insulating film 110. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112.

  As described above, the transistor 100 includes a conductive film functioning as a gate electrode above and below the oxide semiconductor film 108.

≪s-channel structure≫
The oxide semiconductor film 108 is sandwiched between the conductive film 106 and the conductive film 112 with the first gate insulating film and the second gate insulating film interposed therebetween. The length of the conductive film 106 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. In addition, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. Further, since the conductive film 106 and the conductive film 112 are electrically connected to each other in the opening portion 143 provided in the insulating film 104 and the insulating film 110, at least one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is , Opposite to the conductive film 112 with the insulating film 110 interposed therebetween. That is, the entire oxide semiconductor film 108 in the channel width direction is covered with the conductive film 106 and the conductive film 112 with the first gate insulating film and the second gate insulating film interposed therebetween.

  In other words, the conductive film 106 and the conductive film 112 surround the oxide semiconductor film 108 with the first gate insulating film and the second gate insulating film interposed therebetween in the channel width direction of the transistor 100.

  With such a structure, the oxide semiconductor film 108 included in the transistor 100 is electrically surrounded by an electric field of the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. be able to. As in the transistor 100, a device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is referred to as a surround channel (s-channel) structure. Can be called.

  Since the transistor 100 has an s-channel structure, an electric field for inducing a channel by the conductive films 106 and 112 can be effectively applied to the oxide semiconductor film 108. Therefore, the current driving capability of the transistor 100 is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100 can be miniaturized. In addition, since the transistor 100 has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100 can be increased.

With the above structure, the carrier flow region in the oxide semiconductor film 108 includes the oxide semiconductor film 108 on the insulating film 104 side, the oxide semiconductor film 108 on the insulating film 110 side, and the oxide semiconductor film 108. Since the film 108 has a wide range in the film, the amount of carrier movement in the transistor 100 increases. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is increased. Specifically, the field effect mobility is 10 cm ² / V · s or more. Note that the field-effect mobility here is not an approximate value of mobility as a physical property value of the oxide semiconductor film but an index of current driving force in a saturation region of the transistor and is an apparent field-effect mobility.

  Note that in FIG. 1C (in the channel width direction of the transistor 100), an opening which is different from the opening 143 is formed on the opposite side of the oxide semiconductor film 108 from the portion where the opening 143 is formed. Also good.

  Alternatively, different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. That is, the signal A may be applied to one gate electrode, and the fixed potential Vb may be applied to the other gate electrode. Further, the signal A may be given to one gate electrode, and the signal B may be given to the other gate electrode. One gate electrode may be given a fixed potential Va, and the other gate electrode may be given a fixed potential Vb.

  In addition, when a fixed potential is applied to both gate electrodes of a transistor, the transistor may function as an element equivalent to a resistance element. For example, in the case where the transistor is an n-channel transistor, the effective resistance of the transistor can be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

  Thus, since the transistor 100 has an s-channel structure, high on-state current characteristics can be obtained. However, when current is supplied to the channel region 108 i in the oxide semiconductor film 108, one of the electric energy is supplied. The part may be converted to heat as Joule heat. The transistor 100 further includes an insulating film 116 and an insulating film 118 over the conductive film 112 functioning as the second gate electrode. Accordingly, the channel region 108 i in the oxide semiconductor film 108 has a structure sandwiched between the conductive film 106, the insulating film 104, the insulating film 110, the conductive film 112, the insulating film 116, and the insulating film 118. Therefore, the heat retaining effect is excellent, and the heat generated when a current is passed through the transistor 100 is difficult to dissipate. In other words, the transistor 100 has a structure that is likely to become a high temperature when an electric current is passed and easily emits infrared rays generated by heat. In particular, infrared rays having a short wavelength can be strongly emitted at high temperatures, and it is easy to emit near infrared rays having a wavelength region of 780 nm to 2500 nm among infrared rays, particularly emitting near infrared rays having a wavelength region of 900 nm to 1550 nm. Cheap.

  Note that in order to obtain higher on-state current characteristics, the channel width of the transistor 100 is preferably larger. Specifically, the channel width is preferably 50 μm or more, more preferably 100 μm or more.

In addition, the size (d _iw ) of the oxide semiconductor film 108 in the channel width direction overlaps with the oxide semiconductor film 108 so that heat does not easily propagate from the oxide semiconductor film 108 to the conductive films 120 s and 120 d. It is preferable that the region have a size that is approximately the same as the size (d _sw ) of the conductive film 120s in the channel width direction and the size (d _dw ) of the conductive film 120d in the channel width direction. Alternatively, it is preferable that d _iw has a region larger than d _sw and d _dw . In other words, the transistor 100 preferably has regions where d _iw ≧ d _sw and d _iw ≧ d _dw .

In addition, the conductive film 120s has a channel width direction size (d _sw ′) in a region not overlapping with the oxide semiconductor film 108, and a channel width direction size (d _sw ) in a region overlapping with the oxide semiconductor film 108. More preferably, it has a small (d _sw > d _sw ′) region. The conductive film 120d has a channel width direction size (d _dw ′) in a region not overlapping with the oxide semiconductor film 108 and a channel width direction size (d _dw ) in a region overlapping with the oxide semiconductor film 108. More preferably, it has a small (d _dw > d _dw ′) region.

In addition, the distance (d _si ) between the channel region 108i in the oxide semiconductor film 108 and the region where the oxide semiconductor film 108 is connected to the conductive film 120s in the opening 141s, and the oxide in the channel region 108i and the opening 141d. By increasing the distance (d _di ) between the semiconductor film 108 and the region where the semiconductor film 108 is connected to the conductive film 120d, it is possible to make it difficult for heat generated in the channel region 108i to propagate to the conductive film 120s and the conductive film 120d. Therefore, specifically, it is preferably 5 μm or more, more preferably 10 μm or more.

  In addition, it is preferable to reduce the size of the opening 141s and the opening 141d because heat generated in the channel region 108i can be hardly transmitted to the conductive films 120s and 120d.

  The conductive films 120 s and 120 d that are conductive films connected to the oxide semiconductor film 108 are preferably materials having low thermal conductivity.

  With the above structure, the transistor 100 can be a transistor that easily emits near-infrared light.

<1-2. Components of Semiconductor Device>
Hereinafter, components included in the semiconductor device of the present embodiment will be described in detail.

≪Oxide semiconductor film≫
The oxide semiconductor film 108 in the transistor 100 which is one embodiment of the present invention preferably includes a metal oxide, and the metal oxide preferably includes at least indium (In) or zinc (Zn).

  When the oxide semiconductor film contains In, for example, carrier mobility (electron mobility) increases. In addition, when the oxide semiconductor film contains Zn, the oxide semiconductor film is likely to be crystallized.

  In addition, when the oxide semiconductor film includes the element M having a function as a stabilizer, for example, the energy gap (Eg) of the oxide semiconductor film is increased. An oxide semiconductor film suitable for one embodiment of the present invention has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, the off-state current of the transistor 100 can be reduced by using a metal oxide with a wide energy gap for the oxide semiconductor film 108. Note that the element M is an element having a high binding energy with oxygen, and the binding energy with oxygen is higher than that of In.

  As an oxide semiconductor film suitable for the semiconductor device of one embodiment of the present invention, typically, an In—Zn oxide, an In—M oxide, or an In—M—Zn oxide can be used. Among these, an In-M-Zn oxide (M represents aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)) is preferably used. In particular, an In—Ga—Zn oxide (hereinafter sometimes referred to as IGZO) in which M is Ga is preferably used.

  Note that in the case where the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic ratio of In and M is higher than 25 atomic% and M is less than 75 atomic% when the sum of In and M is 100 atomic%. Or In is higher than 34 atomic% and M is lower than 66 atomic%. In particular, the oxide semiconductor film 108 preferably includes a region where the atomic ratio of In is greater than or equal to the atomic ratio of M.

The oxide semiconductor film 108 includes a region in which the atomic ratio of In is greater than or equal to the atomic ratio of M, so that the field-effect mobility of the transistor 100 (sometimes referred to simply as mobility or μFE) is increased. Can do. Specifically, the field effect mobility of the transistor 100 can be greater than 10 cm ² / V · s, and more preferably, the field force mobility of the transistor 100 can be greater than 30 cm ² / V · s.

  For example, since the above-described transistor with high field-effect mobility can have a small channel width, the transistor has a shift included in a scan line driver circuit (also referred to as a gate driver) that generates a gate signal or a scan line driver circuit. By using the demultiplexer connected to the output terminal of the register, the size of the scan line driver circuit can be reduced, and a semiconductor device or a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Alternatively, since the gate voltage of a transistor used in the circuit can be reduced, power consumption of the display device can be reduced. Note that details of the scanning line driving circuit will be described later.

  In addition, the display device can have high definition by increasing the field-effect mobility of the transistor. For example, a pixel of a high-definition display device typified by 4K × 2K (the number of horizontal pixels = 3840, the number of vertical pixels = 2160) or 8K × 4K (the number of horizontal pixels = 7680, the number of vertical pixels = 4320) The transistor is suitable as a transistor of a circuit or a driver circuit.

  The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.

In the case where the oxide semiconductor film 108 is formed using In-M-Zn oxide, the atomic ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is such that In is M or more, Zn Preferably satisfies M or more. Alternatively, in the sputtering target, if the atomic ratio of the metal element is In: M: Zn = x _b : y _b : z _b [atomic ratio], x _b / y _b is 1/3 or more and 6 or less, Is 1 or more and 6 or less, and z _b / y _b is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that by setting z _b / y _b to 1 to 6, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film described later can be easily formed as the oxide semiconductor film 108. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, and the like are preferable.

  Note that the atomic ratio of the oxide semiconductor film 108 includes a variation of plus or minus 40% of the above atomic ratio as an error. For example, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 4: 2. : It may be in the vicinity of 3. Alternatively, in the case where an atomic ratio of In: Ga: Zn = 1: 1: 1.2 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 1: 1. : 1 in some cases. Alternatively, in the case where an atomic ratio of In: Ga: Zn = 5: 1: 7 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 5: 1: 6. May be near.

  Further, an impurity such as hydrogen or moisture mixed in the channel region 108 i in the oxide semiconductor film 108 is problematic because it affects transistor characteristics. Therefore, the channel region 108 i in the oxide semiconductor film 108 is preferably as few as possible as impurities such as hydrogen or moisture.

  Hydrogen contained in the oxide semiconductor film 108 reacts with oxygen bonded to metal atoms to become water, and oxygen vacancies are formed in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In some cases, a part of hydrogen is bonded to oxygen bonded to a metal atom, so that an electron serving as a carrier is generated. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to have electrical characteristics (also referred to as normally-on characteristics) in which the threshold voltage is negative.

Therefore, the channel region 108i of the oxide semiconductor film 108 is preferably reduced as much as possible. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms. / Cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, preferably less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm 3. ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In the case where the oxide semiconductor film 108 contains silicon or carbon which is one of Group 14 elements, oxygen vacancies increase and the oxide semiconductor film 108 may be n-type. Therefore, in the oxide semiconductor film 108, particularly in the channel region 108i, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁷ atoms. / Cm ³ or less. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁶ atoms / cm ³ or less. Can do. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In addition, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density is increased, and the n-type may be obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen is preferably reduced as much as possible in the channel region 108i. For example, the nitrogen concentration obtained by secondary ion mass spectrometry may be 5 × 10 ¹⁸ atoms / cm ³ or less.

In addition, the carrier density of the oxide semiconductor film 108 can be reduced by reducing the impurity element in the channel region 108i. Therefore, in the channel region 108i, the carrier density is 1 × 10 ¹⁷ / cm ³ or less, or 1 × 10 ¹⁵ / cm ³ or less, or 1 × 10 ¹³ / cm ³ or less, or 1 × 10 ¹¹ / cm ³ or less. It can be.

  When the oxide semiconductor film 108 with a low impurity concentration and a low density of defect states is used for the channel region 108i, a transistor having more excellent electrical characteristics can be manufactured. Here, the low impurity concentration and the low density of defect states (there are few oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film easily has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have characteristics with extremely low off-state current. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a small variation in electrical characteristics and may be a highly reliable transistor.

  Note that a semiconductor impurity refers to a component other than the main component included in the semiconductor film. For example, an element having a concentration of less than 0.1 atomic% is an impurity. By including impurities, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. In the case where the semiconductor includes an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor includes silicon, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements other than oxygen and hydrogen.

  In addition, a transistor in which a channel region is formed in a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film tends to have electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.

In addition, a transistor including a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film is a semiconductor element with extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length L of 10 μm. However, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off current can be obtained to be less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less. . Therefore, a transistor in which a channel region is formed in an oxide semiconductor film has little change in electrical characteristics and has high reliability.

  In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

  The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, the threshold voltage Vth is 0.5V, Vgs is the drain current is 1 × ^{10 -9} A in 0.5V, the drain current Vgs is at 0.1V is located at 1 × ^{10- 13} A Assume that an n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

  The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed, or the transistor includes In some cases, there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature (for example, any one temperature of 5 ° C. to 35 ° C.) at which the semiconductor device or the like is used.

  The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V Vds for which the reliability of the semiconductor device including the transistor is guaranteed, or there is a value of Vgs at which the off-state current of the transistor at Vds used in the semiconductor device including the transistor is I or less. May be pointed to.

  In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

  In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

  Note that the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap state density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.

  Further, oxygen vacancies formed in the channel region 108 i in the oxide semiconductor film 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region 108i of the oxide semiconductor film 108, hydrogen is bonded to the oxygen vacancies to serve as a carrier supply source. When a carrier supply source is generated in the channel region 108 i of the oxide semiconductor film 108, a change in electrical characteristics of the transistor 100 including the oxide semiconductor film 108, typically, a threshold voltage shift occurs. Therefore, it is preferable that the number of oxygen vacancies be smaller in the channel region 108 i of the oxide semiconductor film 108.

  Therefore, in one embodiment of the present invention, the insulating film in contact with the oxide semiconductor film, specifically, the insulating film 104 formed below the oxide semiconductor film 108 and the oxide semiconductor film 108 is formed. The insulating film 110 is configured to contain excess oxygen. By transferring oxygen or excess oxygen from the insulating film 104 and the insulating film 110 to the oxide semiconductor film 108, oxygen vacancies in the oxide semiconductor film 108 can be reduced. Thus, variation in electrical characteristics of the transistor 100, in particular, variation in electrical characteristics of the transistor 100 due to light irradiation can be suppressed.

  In one embodiment of the present invention, a manufacturing method in which there is no increase in manufacturing steps or in which the number of manufacturing steps is extremely small is used in order to contain excess oxygen in the insulating film 104 and the insulating film 110. Thus, the yield of the transistor 100 can be increased.

  Specifically, in the step of forming the oxide semiconductor film 108, the formation surface of the oxide semiconductor film 108 is formed by forming the oxide semiconductor film 108 in an atmosphere containing oxygen gas by a sputtering method. Oxygen or excess oxygen is added to the insulating film 104.

  In the transistor 100 having such a structure, defects in the channel region 108 i in the oxide semiconductor film 108 are extremely small, so that electric characteristics are improved. Typically, the on-state current and the field-effect mobility of the transistor 100 can be increased. In addition, the transistor 100 has a small amount of variation in threshold voltage in a BT stress test and an optical BT stress test, which are examples of a stress test, and has high reliability. Note that the BT stress test is a kind of accelerated test, and a change in characteristics (that is, a secular change) of a transistor caused by long-term use can be evaluated in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is an important index for examining reliability. Before and after the BT stress test, the smaller the variation amount of the threshold voltage, the higher the reliability of the transistor.

  On the other hand, the source region 108 s and the drain region 108 d are in contact with the insulating film 116. When the source region 108s and the drain region 108d are in contact with the insulating film 116, one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density is increased. .

  Note that the oxide semiconductor film 108 is not limited to the above structure, and a film having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of a transistor. Good. In addition, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. of the oxide semiconductor film should be appropriate. Is preferred.

  The oxide semiconductor film 108 may have a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C Axis Crystallized Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  Note that the oxide semiconductor film 108 includes a single-layer film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Or the structure where this film | membrane was laminated | stacked may be sufficient.

  Note that in the oxide semiconductor film 108, the channel region 108i may differ in crystallinity from the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when the impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged, and crystallinity is lowered.

  The source region 108s and the drain region 108d included in the oxide semiconductor film 108 may each include an element that forms oxygen vacancies. Examples of the element that forms oxygen vacancies (also referred to as an impurity element) typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

  When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut, so that an oxygen vacancy is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

<< Board >>
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a specific substrate. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, a plastic substrate, a metal substrate, a stainless steel substrate, and a stainless steel foil. A substrate including a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a bonded film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, and the base film include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Another example is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. As an example, there are polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

  When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. By using a large area substrate such as a generation (2950 mm × 3400 mm), a large display device can be manufactured.

  Alternatively, a flexible substrate may be used as the substrate 102, and the transistor may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is stacked, or a structure in which an organic resin film such as polyimide is formed over a substrate can be used for the above-described release layer.

  Examples of a substrate on which a transistor is transferred include a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) in addition to the above-described substrate capable of forming a transistor. (Silk, cotton, hemp), synthetic fibers (including nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

<< Insulating film functioning as first gate insulating film >>
The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. The insulating film 104 can be formed by a single layer or a stacked layer of an oxide insulating film and a nitride insulating film, for example. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.

  The thickness of the insulating film 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 It is possible to reduce oxygen vacancies contained in 108i.

  The insulating film 104 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and may be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104. In this manner, oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

  Note that in this specification and the like, silicon oxynitride refers to a composition having a higher oxygen content than nitrogen, preferably oxygen is 55 atomic% or more and 65 atomic% or less, and nitrogen is 1 atomic% or more. The term includes 20 atomic% or less, silicon in a range of 25 atomic% to 35 atomic%, and hydrogen in a range of 0.1 atomic% to 10 atomic%. Silicon nitride oxide refers to a composition having a nitrogen content higher than that of oxygen. Preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, and silicon is 25 This means that the concentration is in the range of atomic% to 35 atomic% and hydrogen in the concentration range of 0.1 atomic% to 10 atomic%.

  Note that at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably an oxide insulating film, and has a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region). More preferred. In other words, the insulating film 104 is an insulating film capable of releasing oxygen. In order to provide the oxygen-excess region in the insulating film 104, for example, the insulating film 104 may be formed in an oxygen atmosphere. Alternatively, oxygen may be added to the insulating film 104 after deposition. A method for adding oxygen to the insulating film 104 after film formation will be described later.

As the insulating film 104, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide, A high-k material such as yttrium oxide can be preferably used. The material containing hafnium or yttrium has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, by using the high-k material for the insulating film 104, the film thickness can be increased as compared with the case where a silicon oxide film is used, so that a leakage current due to a tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

  Note that in this embodiment, the insulating film 104 is formed by stacking a silicon nitride film on the conductive film 106 side and a silicon oxide film on the oxide semiconductor film 108 side. The silicon nitride film has a relative dielectric constant higher than that of the silicon oxide film, and has a large film thickness necessary for obtaining a capacitance equivalent to that of the silicon oxide film. Therefore, by including a silicon nitride film as the first gate insulating film of the transistor 100, the first gate insulating film can be physically thickened. Accordingly, a decrease in the withstand voltage of the transistor 100 can be suppressed, and further, the withstand voltage can be improved, so that electrostatic breakdown of the transistor 100 can be suppressed.

<< Insulating film functioning as second gate insulating film >>
The insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 110 is preferably formed using an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 110 can be provided as a single layer or a stacked layer.

  Further, by providing an insulating film having a blocking effect of oxygen, hydrogen, water, or the like as the insulating film 110, diffusion of oxygen from the oxide semiconductor film 108 to the outside and hydrogen from the outside to the oxide semiconductor film 108 are performed. Invasion of water, etc. can be prevented. Examples of the insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

Further, as the insulating film 110, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide, By using a high-k material such as yttrium oxide, gate leakage of the transistor can be reduced.

  In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 110, oxygen contained in the insulating film 110 can be transferred to the oxide semiconductor film 108 by heat treatment.

  For that purpose, the insulating film 110 preferably includes at least an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. Note that the second gate insulating film can have one layer or two or more layers as appropriate. Note that in these cases, it is preferable to include an oxide insulating film containing at least more oxygen than that in the stoichiometric composition.

  The thickness of the insulating film 110 can be 5 nm to 400 nm, 50 nm to 300 nm, or 10 nm to 250 nm.

«First gate electrode and conductive film functioning as a pair of electrodes»
The conductive film 106 and the conductive films 120s and 120d can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. In addition, as the conductive films 120s and 120d, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, It can be formed using an alloy or the like in which the above metal elements are combined. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. In addition, the conductive films 120s and 120d may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding Two-layer structure in which tungsten film is laminated on titanium film, two-layer structure in which tungsten film is laminated on tantalum nitride film or tungsten nitride film, two-layer structure in which copper film is laminated on copper film containing manganese, on titanium film A two-layer structure in which a copper film is laminated, a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure in which a titanium film is formed thereon, and a copper film is laminated on a copper film containing manganese Further, there is a three-layer structure on which a copper film containing manganese is formed. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

  The conductive films 120s and 120d include indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. A light-transmitting conductive material such as indium tin oxide, indium zinc oxide, or indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO) can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

  The thickness of the conductive films 120s and 120d can be 30 nm to 500 nm, or 100 nm to 400 nm.

<< Conductive film 112 functioning as second gate electrode >>
The conductive film 112 functioning as the second gate electrode is formed using a material and a manufacturing method similar to those of the conductive film 106 functioning as the first gate electrode and the conductive films 120 s and 120 d functioning as the pair of electrodes described above. Can be formed. Or these laminated structures may be sufficient.

  The conductive film 112 can be formed using a material and a manufacturing method similar to those of the oxide semiconductor film 108 described above. For example, as the conductive film 112, an In oxide, an In—Sn oxide, an In—Zn oxide, an In—Ga oxide, a Zn oxide, an Al—Zn oxide, an In—Ga—Zn oxide, or the like is used. Can be used. In particular, an In—Sn oxide or an In—Ga—Zn oxide is preferably used. For the conductive film 112, a material such as indium tin oxide (ITO) or indium tin oxide to which silicon oxide is added (ITSO) can be used. Further, when the conductive film 112 and the oxide semiconductor film 108 have the same metal element, manufacturing cost can be reduced.

  For example, in the case where an In-M-Zn oxide is used as the conductive film 112, the atomic ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is a region where In is M or more. It is preferable to have. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4. 1, In: M: Zn = 5: 1: 7 and the like. Note that the conductive film 112 is not limited to the composition of the above sputtering target. The conductive film 112 can have a single-layer structure or a stacked structure including two or more layers.

  The conductive film 112 has a function of supplying oxygen to the insulating film 110. Since the conductive film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen can be contained in the insulating film 110. When the insulating film 110 includes the excess oxygen region, the excess oxygen can be supplied into the oxide semiconductor film 108, more specifically, the channel region 108i. Therefore, a highly reliable semiconductor device can be provided.

  Note that in order to supply excess oxygen into the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. Note that in this case, oxygen contained in the insulating film 104 can be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance in the source region 108s and the drain region 108d may increase.

  On the other hand, when the insulating film 110 formed above the oxide semiconductor film 108 has excess oxygen, excess oxygen can be selectively supplied only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density in the source region 108s and the drain region 108d may be selectively increased.

  In addition, after supplying oxygen to the insulating film 110, the conductive film 112 is supplied with one or both of nitrogen and hydrogen from the insulating film 116, whereby donor levels are formed in the vicinity of the conduction band, and the carrier density Becomes higher. In other words, the conductive film 112 also has a function as an oxide conductor (OC: Oxide Conductor). Therefore, the conductive film 112 has a higher carrier density than the oxide semiconductor film 108.

  In general, an oxide semiconductor has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the oxide conductor is less influenced by absorption due to the donor level, and has a light-transmitting property similar to that of an oxide semiconductor with respect to visible light. Therefore, by using an oxide conductor for the conductive film 112, infrared rays emitted from the channel region 108i can be extracted efficiently.

≪Third insulating film≫
The insulating film 116 includes one or both of nitrogen and hydrogen. With the structure in which the insulating film 116 includes one or both of nitrogen and hydrogen, one or both of nitrogen and hydrogen can be supplied to the oxide semiconductor film 108 and the conductive film 112. An example of the insulating film 116 is a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The concentration of hydrogen contained in the insulating film 116 is preferably 1 × 10 ²² atoms / cm ³ or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. In addition, the insulating film 116 is in contact with the conductive film 112. Accordingly, the hydrogen concentration in the source region 108s, the drain region 108d, and the conductive film 112 in contact with the insulating film 116 is increased, so that the carrier density of the source region 108s, the drain region 108d, and the conductive film 112 can be increased. Note that the source region 108 s, the drain region 108 d, and the conductive film 112 may have regions where the hydrogen concentration in the film is the same by being in contact with the insulating film 116.

≪Fourth insulating film≫
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 118 can be provided as a single layer or a stacked layer.

  The insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, and the like from the outside.

  The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

<1-3. Configuration Examples 2 to 6 of Semiconductor Device>
Next, a structure different from the semiconductor device illustrated in FIGS. 1A to 1C is described with reference to FIGS.

<< Configuration Example 2 of Semiconductor Device >>
2A is a top view of the transistor 100A, FIG. 2B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 2A, and FIG. 2C is FIG. 2A. It is sectional drawing between dashed-dotted lines Y1-Y2.

  2A, 2B, and 2C includes an insulating film 104 formed over a substrate 102, an oxide semiconductor film 108 over the insulating film 104, and an insulating film over the oxide semiconductor film 108. 110, the conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112. The oxide semiconductor film 108 includes a channel region 108 i in contact with the insulating film 110, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.

  The transistor 100A is different from the structure of the transistor 100 described above in that the conductive film 106 and the opening 143 are not provided.

  As described above, the transistor 100A illustrated in FIGS. 2A, 2B, and 2C has a structure in which a conductive film functioning as a gate electrode is formed only over the oxide semiconductor film 108, unlike the transistor 100 described above. is there. As shown in the transistor 100A, when one gate electrode is used, manufacturing is facilitated, so that it can be manufactured at low cost.

<< Configuration Example 3 of Semiconductor Device >>
Next, a different structure from the semiconductor device illustrated in FIGS. 1A to 1C is described with reference to FIGS.

  3A is a top view of the transistor 100B, FIG. 3B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 3A, and FIG. 3C is FIG. 3A. It is sectional drawing between dashed-dotted lines Y1-Y2.

  3A, 3B, and 3C are different in the shape of the conductive film 112 from the transistor 100 described above. Specifically, the lower end portion of the conductive film 112 included in the transistor 100B is formed inside the upper end portion of the insulating film 110. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the conductive film 112.

  For example, the conductive film 112 and the insulating film 110 are processed with the same mask, the conductive film 112 is processed with a wet etching method, and the insulating film 110 is processed with a dry etching method, whereby the above structure can be obtained. .

  Further, when the conductive film 112 has the above structure, the region 108 f may be formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

  The region 108f functions as either a high resistance region or a low resistance region. The high resistance region is a region which has a resistance equivalent to that of the channel region 108 i and does not overlap with the conductive film 112 functioning as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100B.

  The low resistance region is a region having a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, electric field relaxation in the drain region is possible, so that variation in threshold voltage of the transistor due to the electric field in the drain region can be reduced.

  Note that in the case where the region 108f is a low-resistance region, for example, one or both of hydrogen and nitrogen is supplied from the insulating film 116 to the region 108f, or the region 108f is conductive using the insulating film 110 and the conductive film 112 as a mask. By adding an impurity element from above the film 112, the impurity is added to the oxide semiconductor film 108 through the insulating film 110.

<< Configuration Example 4 of Semiconductor Device >>
Next, a modification of the semiconductor device illustrated in FIGS. 3A, 3B, and 3C is described with reference to FIGS.

  4A and 4B are cross-sectional views of the transistor 100C. A top view of the transistor 100C is similar to the transistor 100B illustrated in FIG. 3A, and thus will be described with reference to FIG. 4A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 3A, and FIG. 4B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

  The transistor 100C is different from the transistor 100B described above in that an insulating film 122 functioning as a planarization insulating film is provided. Other configurations are similar to those of the transistor 100B described above, and have the same effects.

  The insulating film 122 has a function of planarizing unevenness caused by a transistor or the like. The insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, and aluminum nitride. As this organic material, photosensitive resin materials, such as an acrylic resin or a polyimide resin, are mentioned, for example.

  4A and 4B, the shape of the opening included in the insulating film 122 is smaller than the openings 141s and 141d. However, the shape is not limited to this, and for example, the openings 141s and 141d are used. The shape may be the same as or larger than the openings 141s and 141d.

  4A and 4B illustrate the structure in which the conductive films 120s and 120d are provided over the insulating film 122, but the present invention is not limited thereto. For example, the conductive films 120s and 120d are provided over the insulating film 118. Alternatively, the insulating film 122 may be provided over the conductive films 120s and 120d.

<< Configuration Example 5 of Semiconductor Device >>
Next, a modification of the semiconductor device illustrated in FIGS. 2A, 2B, and 2C is described with reference to FIGS.

  5A and 5B are cross-sectional views of the transistor 100D. A top view of the transistor 100D is similar to the transistor 100 illustrated in FIG. 2A, and thus will be described with reference to FIG. 5A is a cross-sectional view taken along the alternate long and short dash line X1-X2 in FIG. 2A, and FIG. 5B is a cross-sectional view taken along the alternate long and short dash line Y1-Y2 in FIG.

  The transistor 100D is different from the transistor 100A described above in the shape of the insulating film 110. Other configurations are similar to those of the transistor 100A described above, and have the same effects.

  The insulating film 110 included in the transistor 100D is located on the inner side than the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end portion of the conductive film 112. For example, after the conductive film 112 is processed, the insulating film 110 is side-etched using an etchant or the like, whereby the structure illustrated in FIGS. 5A and 5B can be obtained. Note that with the insulating film 110 having the above structure, a hollow region 147 is formed below the conductive film 112.

  The hollow region 147 has air and functions as a part of the gate insulating film. Note that the relative dielectric constant of the hollow region 147 is approximately 1 as in the case of air. Therefore, with the structure of the transistor 100D, when voltage is applied to the conductive film 112 functioning as a gate electrode, the voltage applied to the channel region 108i below the hollow region 147 is reduced to the channel region below the insulating film 110. It becomes lower than the voltage given to 108i. Therefore, the channel region 108 i below the hollow region 147 effectively functions as an overlap region (also referred to as a Lov region). Note that the Lov region is a region that overlaps with the conductive film 112 functioning as a gate electrode and has a lower resistance than the channel region 108i.

  6A and 6B are cross-sectional views of the transistor 100E. The top view of the transistor 100E is similar to the transistor 100 illustrated in FIG. 2A, and thus will be described with reference to FIG. 9A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 2A, and FIG. 9B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

  The transistor 100E is different from the transistor 100A, the insulating film 110, and the insulating film 116 described above. Other configurations are similar to those of the transistor 100A described above, and have the same effects.

  The insulating film 110 included in the transistor 100E is located on the inner side than the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end portion of the conductive film 112. For example, after the conductive film 112 is processed, the insulating film 110 is side-etched using an etchant or the like, whereby the structure illustrated in FIGS. 6A and 6B can be obtained. In addition, after the insulating film 110 has the above structure, the insulating film 116 is formed so that the insulating film 116 also enters the lower side of the conductive film 112, and the insulating film 116 is positioned below the conductive film 112. In contact with the physical semiconductor film 108.

  With the above structure, the source region 108 s and the drain region 108 d are located inside the lower end portion of the conductive film 112. Thus, the transistor 100E has a Lov region.

  With the structure having the Lov region like the transistor 100D and the transistor 100E, a high-resistance region is not formed between the channel region 108i and the source region 108s and the drain region 108d, so that the on-state current of the transistor is increased. Is possible.

<< Configuration Example 6 of Semiconductor Device >>
Next, modified examples of the semiconductor device illustrated in FIGS. 1A, 1B, and 1C are described with reference to FIGS.

  7A and 7B are cross-sectional views of the transistor 100F. A top view of the transistor 100F is similar to the transistor 100 illustrated in FIG. 1A, and thus will be described with reference to FIG. 7A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 1A, and FIG. 7B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

  The transistor 100F is different from the above-described transistor 100 in the structure of the oxide semiconductor film 108. Other configurations are similar to those of the transistor 100 described above, and have the same effects.

  The oxide semiconductor film 108 included in the transistor 100F includes an oxide semiconductor film 108_1 over the insulating film 116, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. Have.

  The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.

  8A and 8B are cross-sectional views of the transistor 100G. A top view of the transistor 100G is similar to the transistor 100 illustrated in FIG. 1A, and thus will be described with reference to FIG. 8A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 1A, and FIG. 8B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

  The transistor 100G is different from the above-described transistor 100 in structure of the oxide semiconductor film 108. Other configurations are similar to those of the transistor 100 described above, and have the same effects.

  The oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 over the insulating film 116 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.

  The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.

  The transistor 100G has a stacked structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 in the channel region 108i.

≪Band structure≫
Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, and the band structure of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110 are described with reference to FIGS. Will be described.

  FIG. 9A illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 9B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.

  FIG. 9A illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110, and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 2 as an oxide semiconductor film 108_3 is used. It is a band diagram.

  FIG. 9B illustrates a case where a silicon oxide film is used as the insulating films 104 and 110 and a metal oxide atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the oxide semiconductor film 108_2. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 108_3 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 1: 3: 2. FIG. 10 is a band diagram of a structure using an oxide semiconductor film.

  As shown in FIG. 9A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 9B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.

  In order to form a continuous bond with the oxide semiconductor films 108_1, 108_2, and 108_3, each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.

  With the structure illustrated in FIGS. 9A and 9B, the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. Recognize.

  Note that by providing the oxide semiconductor films 108_1 and 108_3, trap levels that can be formed in the oxide semiconductor film 108_2 can be separated from the oxide semiconductor film 108_2.

  In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the trap level. . Accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, a structure in which the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 is preferable. By doing so, electrons are unlikely to accumulate in the trap level, the on-state current of the transistor can be increased, and field effect mobility can be increased.

  The oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.

  With such a structure, the oxide semiconductor film 108_2 serves as a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed. With such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

  The oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is lower than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to apply a material closer to the vacuum level than 0.2 eV than the energy level at the lower end of the band, preferably a material closer to the vacuum level of 0.5 eV or more.

  In addition, the oxide semiconductor films 108_1 and 108_3 preferably do not include a spinel crystal structure. In the case where the oxide semiconductor films 108_1 and 108_3 include a spinel crystal structure, the constituent elements of the conductive films 120s and 120d enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse. Note that it is preferable that the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS because blocking elements of the constituent elements of the conductive films 120s and 120d, for example, a copper element are increased.

  In this embodiment, the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2. Although the configuration using the film is exemplified, the configuration is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 1: 1.2 [atomic ratio], In: Ga : Zn = 1: 3: 4 [atomic ratio], or In: Ga: Zn = 1: 3: 6 [atomic ratio], and an oxide semiconductor formed using a metal oxide target in the vicinity thereof A membrane may be used.

  Note that in the case where a metal oxide target with In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). In the case where a metal oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target with In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.

<1-4. Manufacturing Method 1 of Semiconductor Device>
Next, an example of a method for manufacturing the transistor 100 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 10A to 12B are cross-sectional views in the channel length (L) direction and the channel width (W) direction for describing a method for manufacturing the transistor 100.

  First, a conductive film to be the conductive film 106 is formed over the substrate 102, and then the conductive film is processed into an island shape, whereby the conductive film 106 is formed. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the oxide semiconductor film 107 is formed (see FIG. 10A).

  The conductive film 106 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a tungsten film with a thickness of 100 nm is formed as the conductive film 106 by a sputtering method.

  The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed as the insulating film 104 using a PECVD apparatus.

  Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions. Examples of the addition method include an ion doping method, an ion implantation method, and a plasma treatment method. Alternatively, after a film for suppressing desorption of oxygen is formed over the insulating film, oxygen may be added to the insulating film 104 through the film.

  As a film that suppresses the desorption of oxygen described above, a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, and the above-described metal element are components. Conductive materials such as alloys described above, alloys combining the above metal elements, metal nitrides including the above metal elements, metal oxides including the above metal elements, and metal nitride oxides including the above metal elements Can be used.

  In addition, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

  The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that the oxide semiconductor film 107 can be processed by forming a mask over the oxide semiconductor film by a lithography process and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-separated oxide semiconductor film 107 may be directly formed by a printing method.

  In the case of forming an oxide semiconductor film by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

  Note that when the oxide semiconductor film is formed, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. to 750 ° C., 150 ° C. to 450 ° C., or 200 ° C. to 350 ° C. Forming a film is preferable because crystallinity can be improved.

  Note that in this embodiment, a sputtering apparatus is used as the oxide semiconductor film 107, and an In—Ga—Zn metal oxide (In: Ga: Zn = 1: 1: 1.2 [atomic ratio] is used as a sputtering target. ]) Is used to form an oxide semiconductor film having a thickness of 40 nm.

  Alternatively, after the oxide semiconductor film 107 is formed, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

  The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, heat treatment is performed, so that the hydrogen concentration obtained by secondary ion mass spectrometry in the oxide semiconductor film is 5 × 10 ¹⁹ atoms / cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, Alternatively, it can be set to 1 × 10 ¹⁶ atoms / cm ³ or less.

  Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 10B).

  As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method. In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, as the insulating film 110_0, a PECVD method in which an oxidizing gas with respect to a deposition gas is greater than 20 times and less than 100 times, or greater than or equal to 40 times and less than or equal to 80 times and a pressure in the treatment chamber is less than 100 Pa or less than 50 Pa is used. Thus, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, as the insulating film 110_0, the substrate placed in the processing chamber evacuated in the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110_0 under conditions where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to an electrode provided in the treatment chamber.

  Alternatively, the insulating film 110_0 may be formed by a plasma CVD method using a microwave. Microwave refers to the frequency range from 300 MHz to 300 GHz. In the microwave, the electron temperature is low and the electron energy is small. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110_0 with little plasma damage to the deposition surface and deposits and few defects can be formed.

The insulating film 110_0 can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. Use of silicon-containing compounds such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) it can. By using a CVD method using an organosilane gas, the insulating film 110_0 with high coverage can be formed.

  In this embodiment, as the insulating film 110_0, a silicon oxynitride film with a thickness of 100 nm is formed using a PECVD apparatus.

  Next, after a mask is formed by lithography at a desired position over the insulating film 110_0, the insulating film 110_0 and part of the insulating film 104 are etched, so that an opening 143 reaching the conductive film 106 is formed.

  As a method for forming the opening 143, a wet etching method and / or a dry etching method can be used as appropriate. In this embodiment, the opening 143 is formed using a dry etching method.

  Next, a conductive film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that when the conductive film 112_0 is formed, oxygen is added from the conductive film 112_0 to the insulating film 110_0 (see FIG. 10C).

  As a method for forming the conductive film 112_0, a sputtering method is preferably used in an atmosphere containing oxygen gas at the time of formation. By forming the conductive film 112_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be preferably added to the insulating film 110_0.

  Note that in FIG. 10C, oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, the conductive film 112_0 is formed so as to cover the opening 143, whereby the conductive film 106 and the conductive film 112_0 are electrically connected to each other. Note that the conductive film 112_0 can be formed using a material similar to that of the oxide semiconductor film 107 described above.

  In this embodiment, a sputtering apparatus is used as the conductive film 112_0, and an In—Ga—Zn metal oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) is used as the sputtering target. Thus, an oxide semiconductor film with a thickness of 100 nm is formed.

  Next, a mask 140 is formed at a desired position over the conductive film 112_0 by a lithography process (see FIG. 10D).

  Next, etching is performed on the mask 140 to process the conductive film 112_0 and the insulating film 110_0, and then the mask 140 is removed so that the island-shaped conductive film 112 and the island-shaped insulating film are removed. 110 (see FIG. 11A).

  In this embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by a dry etching method.

  Note that when the conductive film 112 and the insulating film 110 are processed, the oxide semiconductor film 107 in a region where the conductive film 112 is not overlapped may be thin. Alternatively, when the conductive film 112 and the insulating film 110 are processed, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap may be reduced.

  Next, the impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 11B).

  As an addition method of the impurity element 145, an ion doping method, an ion implantation method, a plasma treatment method, or the like can be given. In the case of the plasma treatment method, the impurity element can be added by performing plasma treatment by generating plasma in a gas atmosphere containing the impurity element to be added. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

Note that as source gases for the impurity element 145, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H ₂ and rare One or more of the gases can be used. Alternatively, one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. One or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas is used to convert the impurity element 145 into the oxide semiconductor film 107 and When added to the conductive film 112, one or more of a rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 107 and the conductive film 112.

Alternatively, after adding a rare gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ The above may be added to the oxide semiconductor film 107 and the conductive film 112.

Or, after adding one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ , rare A gas may be added to the oxide semiconductor film 107 and the conductive film 112.

The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose. For example, when argon is added by an ion implantation method, the acceleration voltage may be 10 kV to 100 kV and the dose may be 1 × 10 ¹³ ions / cm ^{2 to} 1 × 10 ¹⁶ ions / cm ² , for example, 1 × It may be 10 ¹⁴ ions / cm ² . In addition, when phosphorus ions are added by an ion implantation method, an acceleration voltage of 30 kV and a dose amount of 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less may be used, for example, 1 × 10 ¹⁵ ions. / Cm ² is sufficient.

  Further, in this embodiment mode, the structure in which the impurity element 145 is added after the mask 140 is removed is illustrated; however, the present invention is not limited to this. For example, the impurity element 145 is left in a state where the mask 140 remains. Addition may be performed.

  In this embodiment, argon is added to the oxide semiconductor film 107 and the conductive film 112 as the impurity element 145 using a doping apparatus. Note that although the structure in which argon is added as the impurity element 145 is described in this embodiment, the present invention is not limited thereto, and for example, the step of adding the impurity element 145 may not be performed.

  Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 11C).

  The insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. In this embodiment, a 100-nm-thick silicon nitride film is formed as the insulating film 116 using a PECVD apparatus.

  By using a silicon nitride film as the insulating film 116, hydrogen in the silicon nitride film enters the conductive film 112, the source region 108s, and the drain region 108d in contact with the insulating film 116, and the conductive film 112, the source region 108s, and the drain The carrier density in the region 108d can be increased.

  Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 11D).

  The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. In this embodiment, a 300-nm-thick silicon oxynitride film is formed as the insulating film 118 using a PECVD apparatus.

  Next, after a mask is formed by lithography at a desired position of the insulating film 118, the insulating film 118 and a part of the insulating film 116 are etched, whereby the opening 141s reaching the source region 108s and the drain region 108d are formed. And an opening 141d to be reached (see FIG. 12A).

  As a method for etching the insulating film 118 and the insulating film 116, a wet etching method and / or a dry etching method can be used as appropriate. In this embodiment, the insulating film 118 and the insulating film 116 are processed using a dry etching method.

  Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 141s and 141d (see FIG. 12B).

  The conductive film 120 can be formed by selecting a material that can be used for the conductive films 120s and 120d. In this embodiment, as the conductive film 120, a sputtering apparatus is used to form a stacked film of a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm.

  Next, after a mask is formed at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120 s and 120 d (see FIG. 12C). .

  As a method for processing the conductive film 120, a wet etching method and / or a dry etching method can be used as appropriate. In this embodiment, the conductive film 120 is processed using a dry etching method to form the conductive films 120 s and 120 d.

  Through the above process, the transistor 100 illustrated in FIG. 1 can be manufactured.

  Note that a film (an insulating film, an oxide semiconductor film, a conductive film, or the like) included in the transistor 100 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, or an ALD (atom). It can be formed using a layer deposition method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is an MOCVD (metal organic chemical vapor deposition) method.

  In the thermal CVD method, the inside of a chamber is set to atmospheric pressure or reduced pressure, and a source gas and an oxidant are simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. Thus, the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that no defect is generated due to plasma damage.

  In the ALD method, film formation is performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, introducing and reacting a source gas for reaction into the chamber, and repeating this. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the source gas. For example, two or more kinds of source gases may be sequentially supplied to the chamber. At that time, an inert gas is introduced after the reaction of the first source gas so that a plurality of types of source gases are not mixed, and a second source gas is introduced. Alternatively, the second source gas may be introduced after the first source gas is exhausted by evacuation instead of introducing the inert gas. The first source gas is adsorbed and reacted on the surface of the substrate to form the first layer, and the second source gas introduced later is adsorbed and reacted to make the second layer the first layer. A thin film is formed by being laminated on top. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repeated gas introductions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

A thermal CVD method such as an MOCVD method can form a film such as the above-described conductive film, insulating film, oxide semiconductor film, or metal oxide film. For example, an In—Ga—Zn—O film is formed. In this case, trimethylindium (In (CH ₃ ) ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), and dimethyl zinc are used (Zn (CH ₃ ) ₂ ). Without being limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethylzinc. You can also

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or tetrakis (ethylmethylamide) hafnium) or the like, and two gases of ozone (O ₃ ) are used as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor is used. Two types of gas, H ₂ O, are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H ₂ gas. To form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, an In—O layer is formed using In (CH ₃ ) ₃ gas and O ₃ gas. Then, a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

<1-5. Manufacturing Method 2 of Semiconductor Device>
Next, an example of a method for manufacturing the transistor 100C illustrated in FIGS. 4A to 4C will be described with reference to FIGS. 13A to 16B are cross-sectional views in the channel length (L) direction and the channel width (W) direction, which illustrate a method for manufacturing the transistor 100C.

  First, the conductive film 106 is formed over the substrate 102. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film 107 is formed by processing the oxide semiconductor film into an island shape (see FIG. 13A).

  Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 13B).

  Next, after a mask is formed by lithography at a desired position over the insulating film 110_0, the insulating film 110_0 and part of the insulating film 104 are etched, so that an opening 143 reaching the conductive film 106 is formed (FIG. 13 (C)).

  Next, a conductive film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that oxygen is added from the conductive film 112_0 to the insulating film 110_0 when the conductive film 112_0 is formed (see FIG. 13D).

  Note that in FIG. 13D, oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, the conductive film 112_0 is formed so as to cover the opening 143, whereby the conductive film 106 and the conductive film 112_0 are electrically connected to each other.

  Next, a mask 140 is formed at a desired position over the conductive film 112_0 by a lithography process (see FIG. 14A).

  Next, etching is performed over the mask 140 to process the conductive film 112_0, so that the island-shaped conductive film 112 is formed (see FIG. 14B).

  In this embodiment, the conductive film 112_0 is processed using a wet etching method.

  Subsequently, the insulating film 110_0 is processed by etching from above the mask 140 to form the island-shaped insulating film 110 (see FIG. 14C).

  In this embodiment, the insulating film 110_0 is processed using a dry etching method.

  Next, after the mask 140 is removed, an impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 14D).

  Note that when the impurity element 145 is added, a large amount of impurities are added to a region where the surface of the oxide semiconductor film 107 is exposed (a region to be a source region 108s and a drain region 108d later). On the other hand, the conductive film 112 of the oxide semiconductor film 107 is not overlapped and the impurity element 145 is added to the region where the insulating film 110 overlaps (the region to be the region 108f later) through the insulating film 110. The amount of the impurity element 145 added is smaller than that of the source region 108s and the drain region 108d.

  In this embodiment, argon is added to the oxide semiconductor film 107 and the conductive film 112 as the impurity element 145 using a doping apparatus.

  Note that although the structure in which argon is added as the impurity element 145 is described in this embodiment, the present invention is not limited thereto, and for example, the step of adding the impurity element 145 may not be performed. When the step of adding the impurity element 145 is not performed, the region 108f has an impurity concentration equivalent to that of the channel region 108i.

  Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, the insulating film 110, and the conductive film 112. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 15A).

  Note that a region 108f is formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.

  Next, an insulating film 118 is formed over the insulating film 116 (see FIG. 15B).

  Next, after a mask is formed by lithography at a desired position of the insulating film 118, the insulating film 118 and a part of the insulating film 116 are etched, whereby the opening 141s reaching the source region 108s and the drain region 108d are formed. And an opening 141d to be reached (see FIG. 15C).

  Next, the insulating film 122 is formed over the insulating film 118 (see FIG. 15D).

  Note that the insulating film 122 functions as a planarization insulating film. In addition, the insulating film 122 has openings at positions overlapping with the openings 141 s and 141 d.

  In this embodiment mode, as the insulating film 122, a photosensitive acrylic resin is applied using a spin coater, and then a desired region of the acrylic resin is exposed to expose the insulating film 122 having an opening. Form.

  Next, the conductive film 120 is formed over the insulating film 122 so as to cover the openings 141s and 141d (see FIG. 16A).

  Next, after a mask is formed at a desired position on the conductive film 120 by a lithography process, a part of the conductive film 120 is etched to form the conductive films 120 s and 120 d (see FIG. 16B). .

  In this embodiment mode, a dry etching method is used for processing the conductive film 120. Further, when the conductive film 120 is processed, part of the upper portion of the insulating film 122 may be removed.

  Through the above steps, the transistor 100C illustrated in FIG. 4 can be manufactured.

  Note that in manufacturing the transistor 100C, the insulating film 104, the oxide semiconductor film 107, the insulating film 110_0, the conductive film 112_0, the impurity element 145, the insulating film 116, the insulating film 118, the openings 141s and 141d, and the conductive film As 120, <1-4. The semiconductor device can be formed by using the contents described in Manufacturing method 1> of semiconductor device.

  In this embodiment, an example in which a transistor includes an oxide semiconductor film is described; however, one embodiment of the present invention is not limited thereto. In one embodiment of the present invention, a transistor does not necessarily include an oxide semiconductor film. As an example, in a channel region of a transistor, in the vicinity of the channel region, in a source region or a drain region, a material having Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like is formed. May be.

  The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 2)
In this embodiment, the structure and the like of an oxide semiconductor will be described with reference to FIGS.

<2-1. Structure of oxide semiconductor>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

  From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

  Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

  In other words, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<2-2. CAAC-OS>
First, the CAAC-OS will be described.

  A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 17E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 17E is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 17E is considered to be due to the (110) plane or the like.

  In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

  FIG. 18A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

  From FIG. 18A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 18B and 18C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 18D and 18E are images obtained by performing image processing on FIGS. 18B and 18C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing a fast Fourier transform (FFT) process on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

  In FIG. 18D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

  In FIG. 18E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding lattice points around the lattice points near the dotted line. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the bond distance between atoms is not dense in the ab plane direction, or the bond distance between atoms changes when a metal element is substituted. This is thought to be possible.

  As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

  The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in a reverse view, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

  Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

  In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and a carrier of 1 × 10 ⁻⁹ / cm ³ or more. A dense oxide semiconductor can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<2-3. nc-OS>
Next, the nc-OS will be described.

  A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm parallel to the surface to be formed, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 19B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 19B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

  When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

  FIG. 19D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

  Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<2-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 20 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 20A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 20B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . 20A and 20B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

  Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

  As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

  First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 21 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 21, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons related to the acquisition of the TEM image or the like. From FIG. 21, the crystal part (also referred to as initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e ⁻ ) irradiation dose of 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 21 shows that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

  As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

  In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

  Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

  As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a display device including the transistor exemplified in the above embodiment will be described below with reference to FIGS.

<3. Configuration example of display device>
FIG. 22 is a cross-sectional view illustrating a part of a structure example of the display device of one embodiment of the present invention. The display device illustrated in FIG. 22 includes a transistor 202, a transistor 212, a transistor 221, a light-emitting element 204, and a photodiode 206. As the transistor 202, the transistor 212, and the transistor 221, the transistor described in the above embodiment is preferably used, and the transistor 212 preferably has a function of emitting light including infrared light.

  The transistor 212 includes a conductive film 2025 functioning as a gate electrode provided over a substrate 200 having an insulating surface, a conductive film 2021 functioning as a source electrode, a conductive film 2022 functioning as a drain electrode, an oxide semiconductor film 2020, an oxide A gate insulating film 2023 provided over the semiconductor film 2020 and a conductive film 2024 functioning as a gate electrode provided over the gate insulating film 2023 are included. Further, as the transistor 202 and the transistor 221, a transistor having a structure similar to that of the transistor 212 can be used. Note that here, an example in which the transistors 202, 212, and 221 are formed using an oxide semiconductor film is described; however, these transistors are formed using single crystal silicon, polycrystalline silicon, or amorphous silicon. It is also possible to do. Although an example in which the transistors 202, 212, and 221 are transistors having an s-channel structure is shown here, these structures may be a top gate type transistor, a bottom gate type transistor, or the like.

  The photodiode 206 may have any structure as long as it is a photodiode that generates a photocurrent when irradiated with infrared rays. As the photodiode 206, an element including selenium or a compound containing selenium, or an element including silicon (for example, an element in which a pin-type or pn-type junction is formed) can be used. The structure of the photodiode 206 is preferably selected according to the target wavelength. For example, a photodiode composed of amorphous silicon is preferably used to detect the wavelength region of visible light, and single crystal silicon or polycrystalline silicon is used to detect a wavelength region including infrared rays. It is preferable to apply a configured photodiode.

  Note that an insulating film 230 is provided over the transistors 202, 212, and 221. In addition, one of the source electrode and the drain electrode included in the transistors 202 and 221 is connected to the conductive film 241 and the conductive film 242 in the opening of the insulating film 230. Further, an insulating film 250 is provided over the conductive films 241 and 242.

  The light-emitting element 204 includes a conductive film 261 connected to the conductive film 241 in the opening of the insulating film 250, a light-emitting layer 270 provided over the conductive film 261, and a conductive film 280 provided over the light-emitting layer 270. Have. The photodiode 206 includes a conductive film 262 connected to the conductive film 242 in the opening of the insulating film 250, a photoelectric conversion layer 290 provided over the conductive film 262, and a conductive film provided over the photoelectric conversion layer 290. A film 280. As described above, the conductive film 280 may be shared in the light-emitting element 204 and the photodiode 206 illustrated in FIG. Thereby, a display element and an imaging element can be easily produced.

  Note that here, the light-emitting layer 270 can emit white light 2301 (W) by current generated between the conductive films 261 and 280. Alternatively, it may be light having at least one of the wavelength of light exhibiting red, the wavelength of light exhibiting green, the wavelength of light exhibiting blue, and the wavelength of light exhibiting yellow. For example, as the light-emitting element 204, a light-emitting element having a light-emitting organic material (also referred to as an organic electroluminescence element or an organic EL element) or a light-emitting element having a light-emitting quantum dot can be used. Here, the conductive film 280 is formed using a light-transmitting conductive film. Accordingly, the light-emitting element 204 can emit light 2301 (W) toward at least an electrode direction in which the conductive film 280 is provided. Further, here, partition walls 291 are provided at end portions of the conductive films 261 and 262 and an opening portion of the insulating film 250. Note that the partition wall is a layer made of an organic or inorganic insulator. By providing the partition wall 291, a short circuit between the conductive film 261, the conductive film 262, and the conductive film 280 can be prevented, and disconnection of the light-emitting layer 270 can be suppressed. Here, the light-emitting element 204 is provided so as to overlap with the transistor 202. Accordingly, the area of the light-emitting element 204 (the aperture ratio of the display device) can be improved.

  Further, the display device illustrated in FIG. 22 includes a sealing substrate 310 provided with a color filter 300 and having a light-transmitting property. Note that a region where the light-emitting element 204 or the like exists is sealed by the substrate 200 having an insulating surface and the sealing substrate 310. Accordingly, moisture can be prevented from entering the light-emitting element 204, the photodiode 206, and the like, and the reliability of the display device can be improved. The color filter 300 is provided immediately above the region where the light emitting element 204 is provided. The color filter 300 can absorb light in a specific range of wavelengths included in the white light 2301 (W) emitted from the light emitting element 204 and change the light into a light 2302 (C) that exhibits a chromatic color. is there. Here, it is assumed that the chromatic color is at least one of red, green, blue, or yellow.

  Further, the color filter 300 is not provided immediately above the transistor 212 and the photodiode 206. Therefore, in the display device illustrated in FIG. 22, infrared light 2201 (IR) having infrared rays emitted from the transistor 212 is irradiated onto the detection object 2101 such as a finger or a pen and reflected by the detection object 2101. By irradiating the photodiode 206 with light 2202 (IR) having, the object 2101 to be detected can be imaged.

  Note that the transistor 212 is preferably capable of emitting intense light instantaneously. Therefore, the current driving capability of the transistor 212 is preferably higher than the current driving capability of the transistors 202 and 212. For example, the (W / L) value of the transistor 212 is preferably larger than the (W / L) values of the transistor 202 and the transistor 221. Here, W represents the channel width, and L represents the channel length.

  In this manner, by performing imaging using invisible light (IR) including light having a wavelength in the infrared region, imaging can be performed without affecting the display on the display device. In addition, since the intensity of the invisible light (IR) can be increased without considering the influence on the display, it is possible to reduce the influence of external light on the imaging device and improve the detection accuracy. It becomes. In addition, since the display device captures an object to be detected with light having infrared rays, it can detect an object to be detected that is in contact with the display device and an object that is not in contact with the object. Even a plurality of them can be detected.

  The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described as an example in the above embodiment will be described below with reference to FIGS.

  FIG. 23 is a top view illustrating an example of the display device. A display device 700 illustrated in FIG. 23 includes a pixel portion 702 provided over a first substrate 701, a source driver 704 and a gate driver 706 provided over the first substrate 701, a pixel portion 702, a source driver 704, And a sealant 712 disposed so as to surround the gate driver 706 and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver 704, and the gate driver 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 23, a display element is provided between the first substrate 701 and the second substrate 705.

  In addition, the display device 700 includes a pixel portion 702, a source driver 704, a gate driver 706, and a gate driver 706 in a different region from the region surrounded by the sealant 712 on the first substrate 701. An FPC terminal portion 708 (FPC: Flexible printed circuit) connected to is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver 704, and the gate driver 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver 704, the gate driver 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver 704, the gate driver 706, and the FPC terminal portion 708 through the signal line 710.

  Further, the display device 700 may be provided with a plurality of gate drivers 706 and source drivers 704. In addition, as the display device 700, an example in which the source driver 704 and the gate driver 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver 706 may be formed on the first substrate 701, or only the source driver 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver, a gate driver, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702, the source driver 704, and the gate driver 706 included in the display device 700 each include a plurality of transistors, and a transistor that is a semiconductor device of one embodiment of the present invention can be used.

  In addition, the display device 700 can include various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror device (DMD), digital micro shutter (DMS) element, interferometric modulation (IMOD) element, etc.), piezoelectric ceramic display, and the like. The display device 700 may include a sensor, and the sensor preferably has a function of imaging an object to be detected with light having infrared rays.

  An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

  Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, a pixel for color display may be composed of pixels composed of four color elements of R, G, B, and W (white). Alternatively, as in a pen tile arrangement, one pixel may be configured by color elements for two colors of RGB, and other color elements may be added to perform color display. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

  In addition, a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (such as an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp) and display a full color display device. Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

  As a colorization method, a part of light emission from the white light emission described above is converted to red, green, and blue by passing a color filter (color filter method), and red, green, and blue light emission are also performed. A method using each of these (three-color method) or a method for converting a part of light emission from blue light emission to red or green (color conversion method, quantum dot method) may be applied.

  In this embodiment, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. Note that FIG. 24 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 23, in which a liquid crystal element is used as a display element. FIG. 25 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 23 and has a configuration using an EL element as a display element.

  First, common parts shown in FIGS. 24 and 25 will be described first, and then different parts will be described below.

<4-1. Explanation of common parts of display device>
A display device 700 illustrated in FIGS. 23 to 25 includes a lead wiring portion 711, a pixel portion 702, a source driver 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver 704 includes a transistor 752.

  The transistors 750 and 752 have a structure similar to that of the transistor 100 described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.

  The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

  The capacitor 790 includes a first oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, and a conductive material functioning as a source electrode and a drain electrode included in the transistor 750. A film and an upper electrode formed through a process of processing the same conductive film. In addition, a step of forming the same insulating film as the second insulating film and the insulating film functioning as the third insulating film included in the transistor 750 between the lower electrode and the upper electrode is performed. An insulating film formed through the above is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

  24 and 25, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

  As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Further, the planarization insulating film 770 may be omitted.

  The signal line 710 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a different process from the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same process as an oxide semiconductor film functioning as a gate electrode. A membrane may be used. For example, when a material containing copper is used for the signal line 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

  The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

  In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

  A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

  On the second substrate 705 side, a light-blocking film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the colored film 736 are provided.

<4-2. Configuration Example of Display Device Using Liquid Crystal Element>
A display device 700 illustrated in FIG. 24 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. A display device 700 illustrated in FIG. 24 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.

  The conductive film 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. The conductive film 772 functions as a reflective electrode. A display device 700 illustrated in FIG. 24 is a so-called reflective color liquid crystal display device that uses external light to reflect light through a conductive film 772 and display it through a colored film 736.

  As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

  In addition, in the display device 700 illustrated in FIG. 24, unevenness is provided in part of the planarization insulating film 770 in the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing the unevenness on the surface of the resin film. In addition, the conductive film 772 functioning as a reflective electrode is formed along the unevenness. Accordingly, when external light is incident on the conductive film 772, light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

  Note that although a reflective color liquid crystal display device is illustrated in FIGS. 24A and 24B, the display device 700 which is one embodiment of the present invention is not limited thereto. For example, the conductive film 772 has a light-transmitting property with respect to visible light. A transmissive color liquid crystal display device may be formed by using a certain conductive film. In the case of a transmissive color liquid crystal display device, the unevenness provided in the planarization insulating film 770 may not be provided.

  Note that although not illustrated in FIG. 24, an alignment film may be provided on each of the conductive films 772 and 774 in contact with the liquid crystal layer 776. Although not shown in FIG. 24, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

  When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

  In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.

  When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell) mode, A Compensated Birefringence (FLC) mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, and the like can be used.

  Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

<4-3. Display device using light emitting element>
A display device 700 illustrated in FIG. 25 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 25 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.

  The conductive film 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.

  In the display device 700 illustrated in FIG. 25, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers part of the conductive film 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 784 side or a dual emission structure in which light is emitted to both the conductive film 784 side and the conductive film 788 side can be used.

  In addition, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 25, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a circuit configuration of a semiconductor device in which stored contents can be held even when power is not supplied and the number of writings is not limited will be described with reference to FIGS.

<5-1. Circuit configuration>
FIG. 26 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 26, the first wiring (1st Line) and one of the source electrode and the drain electrode of the p-type transistor 1280a are electrically connected. In addition, the other of the source electrode and the drain electrode of the p-type transistor 1280a and one of the source electrode and the drain electrode of the n-type transistor 1280b are electrically connected. In addition, the other of the source electrode and the drain electrode of the n-type transistor 1280b is electrically connected to one of the source electrode and the drain electrode of the n-type transistor 1280c.

  The second wiring (2nd Line) and one of the source electrode and the drain electrode of the transistor 1282 are electrically connected. The other of the source electrode and the drain electrode of the transistor 1282 is electrically connected to one of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c.

  The third wiring (3rd Line) and the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b are electrically connected. In addition, the fourth wiring (4th Line) and the gate electrode of the transistor 1282 are electrically connected. The fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 1281 and the other of the source electrode and the drain electrode of the n-type transistor 1280c. The sixth wiring (6th Line) is electrically connected to the other of the source and drain electrodes of the p-type transistor 1280a and one of the source and drain electrodes of the n-type transistor 1280b.

  Note that the transistor 1282 can be formed using an oxide semiconductor (OS). Therefore, in FIG. 26, the symbol “OS” is added to the transistor 1282. Note that the transistor 1282 may be formed using a material other than an oxide semiconductor.

  In FIG. 26, a floating node (FN) is added to a connection portion between the other of the source electrode and the drain electrode of the transistor 1282, one of the electrodes of the capacitor 1281, and the gate electrode of the n-type transistor 1280c. It is. When the transistor 1282 is turned off, the potential applied to one of the floating node, the electrode of the capacitor 1281, and the gate electrode of the n-type transistor 1280c can be held.

  In the circuit configuration shown in FIG. 26, by utilizing the feature that the potential of the gate electrode of the n-type transistor 1280c can be held, information can be written, held, and read as follows.

<5-2. Writing and holding information>
First, writing and holding of information will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, so that the transistor 1282 is turned on. Accordingly, the potential of the second wiring is supplied to the gate electrode of the n-type transistor 1280c and the capacitor 1281. That is, a predetermined charge is given to the gate electrode of the n-type transistor 1280c (writing). After that, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, so that the transistor 1282 is turned off. Thereby, the charge given to the gate electrode of the n-type transistor 1280c is held (held).

  Since the off-state current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is held for a long time.

<5-3. Reading information>
Next, reading of information will be described. When the potential of the third wiring is set to a low level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is supplied to the sixth wiring. On the other hand, when the potential of the third wiring is set to a high level potential, the p-type transistor 1280a is turned off and the n-type transistor 1280b is turned on. At this time, the sixth wiring has different potentials depending on the amount of charge held in the floating node (FN). Therefore, the held information can be read (read) by looking at the potential of the sixth wiring.

  The transistor 1282 is an extremely low off-state transistor because an oxide semiconductor is used for a channel region. Since the off-state current of the transistor 1282 including an oxide semiconductor is 1 / 100,000 or less than that of a transistor formed using a silicon semiconductor or the like, the off-state current is accumulated in the floating node (FN) due to the leakage current of the transistor 1282 It is possible to ignore the loss of charge. In other words, the transistor 1282 including an oxide semiconductor can realize a nonvolatile memory circuit that can retain information even when power is not supplied.

  In addition, by using a semiconductor device having such a circuit configuration for a storage device such as a register or a cache memory, data in the storage device can be prevented from being lost due to supply of power supply voltage being stopped. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Therefore, power consumption can be suppressed because the entire storage device or one or a plurality of logic circuits included in the storage device can be stopped in a short time in a standby state. Further, by using the semiconductor device for a sensor, the influence of noise can be reduced, and the detection accuracy of the sensor can be increased. The sensor can use light having infrared rays.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, a structure of a pixel circuit that can be used for the semiconductor device of one embodiment of the present invention will be described below with reference to FIG.

<6-1. Configuration of pixel circuit>
FIG. 27A illustrates a structure of a pixel circuit. The circuit illustrated in FIG. 27A includes a photoelectric conversion element 1360, a transistor 1351, a transistor 1352, a transistor 1353, and a transistor 1354.

  The anode of the photoelectric conversion element 1360 is electrically connected to the wiring 1316 and the cathode is connected to one of the source electrode and the drain electrode of the transistor 1351. The other of the source electrode and the drain electrode of the transistor 1351 is connected to the charge accumulation portion (FD), and the gate electrode is connected to the wiring 1312 (TX). One of a source electrode and a drain electrode of the transistor 1352 is connected to the wiring 1314 (GND), the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the transistor 1354, and the gate electrode is a charge storage portion (FD). ). One of a source electrode and a drain electrode of the transistor 1353 is connected to the charge accumulation portion (FD), the other of the source electrode and the drain electrode is connected to a wiring 1317, and a gate electrode is connected to the wiring 1311 (RS). The other of the source electrode and the drain electrode of the transistor 1354 is connected to the wiring 1315 (OUT), and the gate electrode is connected to the wiring 1313 (SE). All the above connections are electrical connections.

  Note that a potential such as GND, VSS, or VDD may be supplied to the wiring 1314. Here, the potential and voltage are relative. Therefore, the magnitude of the potential of GND is not necessarily 0 volts.

  The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current corresponding to light incident on the pixel circuit. The transistor 1353 has a function of controlling charge accumulation in the charge accumulation portion (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal corresponding to the potential of the charge accumulation portion (FD). The transistor 1352 has a function of resetting the potential of the charge accumulation portion (FD). The transistor 1352 has a function of controlling selection of a pixel circuit at the time of reading.

  Note that the charge accumulation portion (FD) is a charge retention node and retains a charge that varies depending on the amount of light received by the photoelectric conversion element 1360.

  Note that the transistor 1352 and the transistor 1354 may be connected in series between the wiring 1315 and the wiring 1314. Therefore, the wiring 1314, the transistor 1352, the transistor 1354, and the wiring 1315 may be arranged in this order, or the wiring 1314, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

  The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) functions as a signal line for controlling the transistor 1351. The wiring 1313 (SE) functions as a signal line for controlling the transistor 1354. The wiring 1314 (GND) functions as a signal line for setting a reference potential (for example, GND). The wiring 1315 (OUT) functions as a signal line for reading a signal output from the transistor 1352. The wiring 1316 functions as a signal line for outputting charge from the charge accumulation portion (FD) through the photoelectric conversion element 1360, and is a low potential line in the circuit in FIG. The wiring 1317 functions as a signal line for resetting the potential of the charge accumulation portion (FD), and is a high potential line in the circuit in FIG.

  Next, the structure of each element illustrated in FIG.

<6-2. Photoelectric conversion element>
As the photoelectric conversion element 1360, an element including selenium or a compound containing selenium (hereinafter referred to as a selenium-based material) or an element including silicon (for example, an element in which a pin-type junction is formed) can be used. In addition, a combination of a transistor including an oxide semiconductor and a photoelectric conversion element including a selenium-based material is preferable because reliability can be increased.

<6-3. Transistor>
Although the transistor 1351, the transistor 1352, the transistor 1353, and the transistor 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon, an oxide semiconductor is used. It is preferable to use the transistor used. A transistor in which a channel region is formed using an oxide semiconductor has a characteristic of extremely low off-state current. For example, the transistor described in Embodiment 1 can be used as a transistor in which a channel region is formed using an oxide semiconductor.

  In particular, when the leakage current of the transistor 1351 and the transistor 1353 connected to the charge accumulation portion (FD) is large, the time for holding the charge accumulated in the charge accumulation portion (FD) becomes insufficient. Therefore, by using a transistor including an oxide semiconductor for at least the two transistors, unnecessary charge can be prevented from flowing out from the charge storage portion (FD).

  Further, in the transistor 1352 and the transistor 1354, if the leakage current is large, unnecessary charge is output to the wiring 1314 or the wiring 1315; therefore, transistors in which a channel region is formed using an oxide semiconductor are used as these transistors. It is preferable.

  FIG. 27A illustrates a transistor having one gate electrode structure; however, the present invention is not limited to this, and a structure having a plurality of gate electrodes may be employed, for example. As the transistor having a plurality of gate electrodes, for example, a structure in which a first gate electrode and a second gate electrode (also referred to as a back gate electrode) overlap with a semiconductor film in which a channel region is formed may be used. . As the back gate electrode, for example, the same potential as that of the first gate electrode, floating, or a potential different from that of the first gate electrode may be applied.

<6-4. Circuit operation timing chart>
Next, an example of operation of the circuit illustrated in FIG. 27A will be described with reference to a timing chart illustrated in FIG.

  In FIG. 27B, for simple explanation, the potential of each wiring is given as a signal that changes in binary. However, since each electric potential is an analog signal, actually, it can take various values without being limited to binary values depending on the situation. Note that a signal 1401 illustrated in FIG. 27B is the potential of the wiring 1311 (RS), the signal 1402 is the potential of the wiring 1312 (TX), the signal 1403 is the potential of the wiring 1313 (SE), and the signal 1404 is the charge accumulation portion (FD). ) And a signal 1405 correspond to the potential of the wiring 1315 (OUT). Note that the potential of the wiring 1316 is always “Low”, and the potential of the wiring 1317 is always “High”.

  At time A, when the potential of the wiring 1311 (signal 1401) is “High” and the potential of the wiring 1312 (signal 1402) is “High”, the potential of the charge accumulation portion (FD) (signal 1404) is the potential of the wiring 1317 (signal 1404). It is initialized to “High”) and the reset operation is started. Note that the potential of the wiring 1315 (signal 1405) is precharged to “High”.

  At time B, when the potential of the wiring 1311 (the signal 1401) is set to “Low”, the reset operation is completed and the accumulation operation is started. Here, since a reverse bias is applied to the photoelectric conversion element 1360, the charge accumulation portion (FD) (signal 1404) starts to decrease due to the reverse current. When the photoelectric conversion element 1360 is irradiated with light, the reverse current increases, so that the rate of decrease of the potential (signal 1404) of the charge storage portion (FD) changes in accordance with the amount of light irradiated. That is, the channel resistance between the source and the drain of the transistor 1354 changes in accordance with the amount of light with which the photoelectric conversion element 1360 is irradiated.

  At time C, when the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation ends, and the potential of the charge accumulation portion (FD) (signal 1404) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. That is, it changes in accordance with the amount of light applied to the photoelectric conversion element 1360. In addition, since the transistor 1351 and the transistor 1353 are formed using an oxide semiconductor and a channel region is formed with a very low off-state current, the transistor 1351 and the transistor 1353 are formed in the charge accumulation portion (FD) until a subsequent selection operation (read operation) is performed. It is possible to keep the potential constant.

  Note that when the potential of the wiring 1312 (the signal 1402) is set to “Low”, a change in the potential of the charge storage portion (FD) occurs due to parasitic capacitance between the wiring 1312 and the charge storage portion (FD). is there. When the amount of change in potential is large, the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation cannot be acquired accurately. In order to reduce the amount of change in the potential, the capacitance between the gate electrode and the source electrode (or the gate electrode and the drain electrode) of the transistor 1351 is reduced, the gate capacitance of the transistor 1352 is increased, and held in the charge accumulation portion (FD). Measures such as providing capacity are effective. Note that in this embodiment, the potential change can be ignored by these measures.

  At the time D, when the potential of the wiring 1313 (the signal 1403) is set to “High”, the transistor 1354 is turned on to start a selection operation, and the wiring 1314 and the wiring 1315 are turned on through the transistor 1352 and the transistor 1354. Then, the potential of the wiring 1315 (signal 1405) decreases. Note that the precharge of the wiring 1315 may be completed before the time D. Here, the rate at which the potential of the wiring 1315 (the signal 1405) decreases depends on the current between the source electrode and the drain electrode of the transistor 1352. That is, it changes in accordance with the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation.

  At time E, when the potential of the wiring 1313 (signal 1403) is set to “Low”, the transistor 1354 is cut off, the selection operation is finished, and the potential of the wiring 1315 (signal 1405) becomes a constant value. Here, the constant value changes in accordance with the amount of light that has been applied to the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation can be known.

  More specifically, when the light applied to the photoelectric conversion element 1360 is strong, the potential of the charge accumulation portion (FD), that is, the gate voltage of the transistor 1352 is decreased. Therefore, the current flowing between the source electrode and the drain electrode of the transistor 1352 is reduced, and the potential of the wiring 1315 (signal 1405) is slowly decreased. Accordingly, a relatively high potential can be read from the wiring 1315.

  On the other hand, when the light applied to the photoelectric conversion element 1360 is weak, the potential of the charge accumulation portion (FD), that is, the gate voltage of the transistor 1352 increases. Therefore, a current flowing between the source electrode and the drain electrode of the transistor 1352 is increased, and the potential of the wiring 1315 (signal 1405) is quickly decreased. Accordingly, a relatively low potential can be read from the wiring 1315.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<7-1. Configuration example of display device>
A display device illustrated in FIG. 28A includes a circuit portion (hereinafter, referred to as a pixel portion 502) including a pixel of a display element and a circuit that is disposed outside the pixel portion 502 and drives the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

  A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

  The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

  The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

  The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

  The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches.

  Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

  The protection circuit 506 illustrated in FIG. 28A is connected to, for example, the scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

  The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

  As shown in FIG. 28A, a protective circuit 506 is provided in each of the pixel portion 502 and the driver circuit portion 504, thereby increasing the resistance of the display device against an overcurrent generated by ESD (Electro Static Discharge) or the like. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

  FIG. 28A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

<7-2. Configuration example of pixel circuit>
A plurality of pixel circuits 501 illustrated in FIG. 28A can have a structure illustrated in FIG. 28B, for example.

  A pixel circuit 501 illustrated in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

  One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

  For example, a driving method of a display device including the liquid crystal element 570 includes a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric mode). , AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Host mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

  In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal.

  One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

  For example, in a display device including the pixel circuit 501 in FIG. 28R, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

  The plurality of pixel circuits 501 illustrated in FIG. 28A can have a structure illustrated in FIG. 28C, for example.

  A pixel circuit 501 illustrated in FIG. 28C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

  One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

  The transistor 552 has a function of controlling data writing of the data signal.

  One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.

  The capacitor 562 functions as a storage capacitor that stores written data.

  One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

  As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

  Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

  In the display device including the pixel circuit 501 in FIG. 28C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<8-1. Display module>
A display module 8000 shown in FIG. 29 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, a battery, between an upper cover 8001 and a lower cover 8002. 8011.

  The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

  The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

  As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel. The optical touch panel preferably uses light having infrared rays. Note that the optical touch panel can detect an object to be detected by light, and thus the object to be detected and the touch panel do not have to be in contact with each other.

  The backlight 8007 has a light source 8008. Note that although FIG. 29 illustrates the structure in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

  The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

  The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

  The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

<8-2. Electronic equipment>
30A to 30G illustrate electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared ), A microphone 9008, and the like.

  The electronic devices illustrated in FIGS. 30A to 30G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 30A to 30G are not limited to these, and can have various functions. Although not illustrated in FIGS. 30A to 30H, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.

  Details of the electronic devices illustrated in FIGS. 30A to 30G are described below.

  FIG. 30A is a perspective view illustrating a television device 9100. FIG. The television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.

  FIG. 30B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker, a connection terminal, a sensor, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

  As a material for the housing 9000, a material containing an alloy, plastic, ceramics, or carbon fiber can be used. As a material containing carbon fiber, carbon fiber reinforced resin composite (Carbon Fiber Reinforced Plastics: CFRP) is light in weight and has an advantage of not corroding, but is black and has a limited appearance and design. Further, CFRP can be said to be a kind of reinforced plastic, and the reinforced plastic may be made of glass fiber or KFRP using Kevlar. When subjected to a strong impact, the alloy is preferable because the fibers may be peeled off from the resin as compared to the alloy. Examples of the alloy include an aluminum alloy and a magnesium alloy. Among these, an amorphous alloy containing zirconium, copper, nickel, and titanium (also called metal glass) is excellent in terms of elastic strength. This amorphous alloy is an amorphous alloy having a glass transition region at room temperature, and is also called a bulk solidified amorphous alloy, and is an alloy having a substantially amorphous atomic structure. By solidification casting, an alloy material is cast into a mold of at least one casing and solidified to form a part of the casing of a bulk solidified amorphous alloy. The amorphous alloy may contain beryllium, silicon, niobium, boron, gallium, molybdenum, tungsten, manganese, iron, cobalt, yttrium, vanadium, phosphorus, carbon, and the like in addition to zirconium, copper, nickel, and titanium. The amorphous alloy is not limited to the solidification casting method, and may be formed by a vacuum deposition method, a sputtering method, an electrolytic plating method, an electroless plating method, or the like. In addition, the amorphous alloy may include microcrystals or nanocrystals as long as the amorphous alloy maintains a state having no long-range order (periodic structure) as a whole. The alloy includes both a complete solid solution alloy having a single solid phase structure and a partial solution having two or more phases. By using an amorphous alloy for the housing 9000, a housing having high elasticity can be realized. Therefore, even if the portable information terminal 9101 is dropped, if the housing 9000 is an amorphous alloy, it will return to its original state even if it is temporarily deformed at the moment when an impact is applied. Impact properties can be improved.

  FIG. 30C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

  FIG. 30D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

  The wristwatch-type portable information terminal 9200 may have a function of detecting a pulse. By detecting a pulse stay with a wristwatch-type portable information terminal 9200, the pulse can be measured regularly or periodically, which is preferable for health management. Infrared rays are preferably used for pulse detection, and the semiconductor element of one embodiment of the present invention is preferable.

  31A and 31B are diagrams illustrating the arrangement of light emitting elements and light receiving elements in a terminal having a function of detecting infrared rays. A terminal 9501 having a function of detecting infrared rays illustrated in FIG. 31A includes a light-receiving element and a plurality of light-emitting elements arranged over a substrate. The light receiving element 9601 has a function of detecting infrared rays, and the light emitting elements 9602, 9603, and 9604 have a function of emitting infrared rays.

  In the terminal 9501, the infrared light emitted from the light emitting elements 9602 to 9604 is applied to the detection target, and the detection target can be detected by detecting the reflected infrared light with the light receiving element 9601. Based on the magnitude of the reflected light from the detection target with respect to the light from the light emitting element, the position of the detection target can be detected.

  In addition, when the terminal 9501 includes the display portion 9001 as a display device, the light-emitting elements 9602 to 9604 that emit infrared light and the light-receiving element 9601 that detects infrared light are the same as the display portion 9001 of the display device as illustrated in FIG. 32A may be arranged on a surface different from the display portion 9001 of the display device as shown in FIG. 32A, and the lower portion of the display portion 9001 of the display device as shown in FIG. It may be.

  Note that as in a terminal 9502 illustrated in FIG. 31B, an arrangement of a light-receiving element 9601 and light-emitting elements 9602 to 9605 may be employed. Further, the light receiving element and the light emitting element may be singular or plural.

  Biological information such as a pulse can be detected by a terminal having the light emitting element and the light receiving element as described above. Note that the terminal illustrated in FIG. 31 only needs to include a light emitting element that exhibits infrared light and a light receiving element that detects infrared light, and is not limited to a terminal that detects a pulse.

  The semiconductor device of one embodiment of the present invention is suitable for an electronic device having a function of detecting biological information such as a vein, a pupil, and an iris. In sensing the human body, it is preferable to use light in the near-infrared wavelength region called a so-called biological window. The light in the wavelength region has a small absorption in water and is slightly absorbed by hemoglobin, and therefore can be suitably used for detection of biological information, particularly detection of a blood state. In addition, by using the semiconductor device of one embodiment of the present invention, the above-described biometric information can be detected with high definition, so that the accuracy of biometric authentication can be increased.

  30E, 30F, and 30G are perspective views illustrating a foldable portable information terminal 9201. FIG. FIG. 30E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 30F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other. FIG. 30G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

  The electronic device described in this embodiment includes a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

  In this example, a transistor of one embodiment of the present invention was manufactured, and electrical characteristics of the transistor were measured and a light emission state was observed.

A method for manufacturing the sample used in this example is described below. Note that in this example, the semiconductor element 1 was manufactured as a transistor corresponding to the transistor 100 illustrated in FIGS. Note that in the following description, components having functions similar to those of the transistor 100 illustrated in FIGS. 1A, 1B, and 1C are described using the same reference numerals. For comparison, a transistor having the structure shown in FIGS. 33A, 33 B, and 33 C was manufactured as the comparative semiconductor element 1.
<Production of Semiconductor Element 1>

  A conductive film 106 functioning as a first gate electrode was formed over the substrate 102 which is a glass substrate. As the conductive film 106, a 100-nm-thick tungsten film was formed using a sputtering apparatus.

  Next, an insulating film 104 functioning as a first gate insulating film was formed over the substrate 102 and the conductive film 106. Note that in this example, as the insulating film 104, the insulating film 104_1, the insulating film 104_2, the insulating film 104_3, and the insulating film 104_4 were sequentially formed in vacuum using a PECVD apparatus. Note that the insulating film 104_1 was a silicon nitride film with a thickness of 50 nm. The insulating film 104_2 is a silicon nitride film with a thickness of 300 nm. The insulating film 104_3 is a silicon nitride film with a thickness of 50 nm. The insulating film 104_4 was a silicon oxynitride film with a thickness of 50 nm.

  Next, an oxide semiconductor film was formed over the insulating film 104, and the oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film 108 was formed. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed. Note that a sputtering apparatus was used to form the oxide semiconductor film 108. A metal oxide of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] was used for the sputtering apparatus, and an AC power source was used as a power source for applying a bias voltage to the sputtering target. A wet etching method was used for processing the oxide semiconductor film 108.

  Next, an insulating film to be the insulating film 110 later was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a silicon oxynitride film with a thickness of 20 nm and a silicon oxynitride film with a thickness of 80 nm were successively formed in a vacuum using a PECVD apparatus.

  Next, heat treatment was performed. As the heat treatment, heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

  Next, an oxide semiconductor film was formed over the insulating film, and the oxide semiconductor film was processed into an island shape, so that the conductive film 112 functioning as a second gate electrode was formed. As the conductive film 112, a sputtering apparatus is used, and a metal oxide of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] is used as a sputtering target and applied to the sputtering target so as to have a thickness of 100 nm. As a power source to be used, an AC power source was used. Further, after the conductive film 112 was formed, the insulating film in contact with the lower side of the conductive film 112 was processed to form the insulating film 110 functioning as the second gate insulating film.

  Note that a wet etching method was used for processing the conductive film 112, and a dry etching method was used for processing the insulating film 110.

  Next, impurity element addition treatment was performed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the impurity element addition treatment, a doping apparatus was used, and argon was used as the impurity element.

  Next, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus.

  Next, an insulating film 118 was formed over the insulating film 116. As the insulating film 118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus.

  Next, a mask was formed over the insulating film 118, and openings 141s and 141d were formed in the insulating films 116 and 118 using the mask. Note that a dry etching apparatus was used for processing the openings 141s and 141d.

  Next, a conductive film is formed over the insulating film 118 so as to fill the openings 141s and 141d, and the conductive film is processed into an island shape, whereby the conductive film 120s functioning as a source electrode and a drain electrode and the conductive film are formed. A film 120d was formed.

  As the conductive films 120s and 120d, a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, a titanium film with a thickness of 100 nm, and a sputtering apparatus were successively formed in a vacuum.

  Through the above steps, the semiconductor element 1 which is a transistor corresponding to the transistor 100 illustrated in FIGS. 1A, 1B, and 1C was manufactured.

  The channel width W of the semiconductor element 1 was 50 μm and 100 μm, and the channel width L was 6 μm.

<Production of Comparative Semiconductor Element 1>
A conductive film 106 functioning as a first gate electrode was formed over the substrate 102 which is a glass substrate. As the conductive film 106, a 100-nm-thick tungsten film was formed using a sputtering apparatus.

  Next, insulating films 104 and 103 functioning as a first gate insulating film were formed over the substrate 102 and the conductive film 106. As the insulating film 104, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. As the insulating film 103, a silicon oxynitride film with a thickness of 50 nm was formed using a PECVD apparatus.

  Next, an oxide semiconductor film was formed over the insulating film 103, and the oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film 108 was formed. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 25 nm was formed. Note that as the oxide semiconductor film 108, a sputtering apparatus was used, and a metal oxide of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] was used as a sputtering target, and a power source applied to the sputtering target Used an AC power source.

  Next, a conductive film is formed over the insulating film 103 and the oxide semiconductor film 108, a resist mask is formed over the conductive film, and desired regions are etched, whereby the conductive film functioning as a source electrode and a drain electrode is formed. 120s and a conductive film 120d were formed. As the conductive films 120s and 120d, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film were successively formed in a vacuum using a sputtering apparatus. Note that the resist mask was removed after the formation of the conductive films 120s and 120d.

  Next, a phosphoric acid aqueous solution (an aqueous solution in which an aqueous solution having a phosphoric acid concentration of 85% is further diluted 100 times with pure water) is applied over the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. Then, part of the surface of the oxide semiconductor film 108 exposed from the conductive films 120s and 120d was removed.

  Next, the insulating film 114 and the insulating film 116 functioning as a second gate insulating film were formed over the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. As the insulating film 114, a 50-nm-thick silicon oxynitride film was formed using a PECVD apparatus. As the insulating film 116, a 400-nm-thick silicon oxynitride film was formed using a PECVD apparatus. Note that the insulating film 114 and the insulating film 116 were continuously formed in a vacuum by a PECVD apparatus.

  Next, a first heat treatment was performed. The first heat treatment was performed at 350 ° C. for 1 hour in an atmosphere containing nitrogen.

  Next, an oxide semiconductor film was formed over the insulating film 116, and the oxide semiconductor film was processed into an island shape, so that the conductive film 112 functioning as a second gate electrode was formed. As the conductive film 112, an oxide semiconductor film with a thickness of 100 nm was formed using a sputtering apparatus.

  Next, an insulating film 118 was formed over the insulating film 116 and the conductive film 112. As the insulating film 118, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus.

  Next, a second heat treatment was performed. The second heat treatment is the same as the first heat treatment.

  Through the above steps, a comparative semiconductor element 1 corresponding to the transistor shown in FIGS. 33A, 33B, and 33C was manufactured.

  As the comparative semiconductor element 1, the channel width W was 100 μm and the channel width L was 6 μm.

<Measurement of electrical characteristics>
34A and 34B show the drain current-gate voltage (Id-Vg) characteristic results of the semiconductor element 1.

34A shows the characteristics of the semiconductor element 1 with W / L = 50 μm / 6 μm, and FIG. 34B shows the characteristics of the semiconductor element 1 with W / L = 100 μm / 6 μm. In FIGS. 34A and 34B, the solid line curve indicates Id (A) corresponding to the first vertical axis, and the dotted line curve indicates field effect mobility (μFE (cm) corresponding to the second vertical axis. ² / Vs)) respectively. The horizontal axis is Vg (V).

  Note that measurement conditions for the Id-Vg characteristics of the transistor include a voltage applied to the conductive film 106 functioning as the first gate electrode of the transistor (hereinafter also referred to as a gate voltage (Vg)) and a second gate electrode. The voltage applied to the functional conductive film 112 (hereinafter also referred to as Vbg) was changed from −15 V to +20 V in steps of 0.25 V. In addition, a voltage applied to the conductive film 120s functioning as the source electrode (hereinafter also referred to as source voltage (Vs)) is set to 0 V (comm), and a voltage applied to the conductive film 120d functioning as the drain electrode (hereinafter referred to as drain voltage (hereinafter referred to as drain voltage) Vd)) was set to 1V or 20V.

  As shown in FIGS. 34A and 34B, it was shown that the transistor manufactured in this example had favorable electrical characteristics regardless of the channel length (L).

<Observation of light emission state>
Next, the observation of the light emission state of the semiconductor element 1 with W / L = 50 μm / 6 μm, the semiconductor element 1 with W / L = 100 μm / 6 μm, and the comparative semiconductor element 1 with W / L = 100 μm / 6 μm was manufactured. went. The observation results of the light emission state are shown in FIGS.

  Here, in order to make each semiconductor element emit light, Vg and Vbg were set to 20V, and Vd was set to 20V. In addition, a cooling CCD camera having a quantum efficiency of 65% or more from 400 nm to 750 nm is used for observation of light emission in the visible light region, and 65% or more from 900 nm to 1550 nm is used for observation of light emission in the near infrared region. An InGaAs camera (C8250-31, manufactured by Hamamatsu Photonics Co., Ltd.) having quantum efficiency was used.

  35A shows an observation result of light emission in the visible light region of the semiconductor element 1 with W / L = 100 μm / 6 μm, and FIG. 35B shows the observation result of the semiconductor element 1 with W / L = 100 μm / 6 μm. FIG. 36A shows the observation result of light emission in the near infrared region, FIG. 36A shows the observation result of light emission in the near infrared region of the semiconductor element 1 with W / L = 50 μm / 6 μm, and FIG. 36B shows W / L = 100 μm. The observation results of light emission in the near-infrared region of the / 6 μm comparative semiconductor element 1 are shown respectively.

  As shown in FIG. 36A, light emission in the near-infrared region was observed from the semiconductor element 1 with W / L = 50 μm / 6 μm. In addition, as shown in FIG. 35B, strong near-infrared light emission was observed from the semiconductor element 1 with W / L = 100 μm / 6 μm. Therefore, it is preferable that the channel width W is larger because light emission in the near infrared region can be strongly exhibited. In addition, as shown in FIG. 35A, light emission in the visible light region was hardly observed from the semiconductor element 1 with W / L = 100 μm / 6 μm. That is, the semiconductor element 1 which is a transistor of one embodiment of the present invention preferably has a function of selectively emitting light in the infrared region.

  On the other hand, as shown in FIG. 36B, almost no light emission in the near infrared region was observed from the comparative semiconductor element 1 with W / L = 100 μm / 6 μm. In the semiconductor element 1 of one embodiment of the present invention, the region where the oxide semiconductor film 108 and the conductive films 120s and 120d are in contact with each other is separated from the channel region as compared to the comparative semiconductor element 1. Therefore, heat or infrared energy generated in the channel region is unlikely to move to the conductive films 120s and 120d, and can effectively emit light in the infrared region.

  As described above, it was found that according to one embodiment of the present invention, a transistor having a function of emitting light in the near-infrared region can be manufactured.

  As described above, the structure described in this example can be combined as appropriate with any of the structures described in the other embodiments.

100 Transistor 100A Transistor 100B Transistor 100B Transistor 100C Transistor 100D Transistor 100E Transistor 100F Transistor 100G Transistor 102 Substrate 103 Insulating film 104 Insulating film 104_1 Insulating film 104_2 Insulating film 104_3 Insulating film 104_4 Insulating film 106 Conductive film 107 Oxide semiconductor film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 oxide semiconductor film 108_3 oxide semiconductor film 108d drain region 108f region 108i channel region 108s source region 110 insulating film 110_0 insulating film 112 conductive film 112_0 conductive film 114 insulating film 116 insulating film 118 insulating film 120 conductive film 120d Conductive film 120s Conductive film 122 Insulating film 140 Mask 141d Opening 141s Opening 143 Opening 145 Impurity element 147 Hollow region 200 Substrate 202 Transistor 204 Light emitting element 206 Photodiode 212 Transistor 221 Transistor 230 Insulating film 241 Conductive film 242 Conductive film 250 Insulating film 261 Conductive film 262 Conductive film 270 Light emitting layer 280 Conductive film 290 Photoelectric conversion layer 291 Partition 300 Color filter 310 Sealing substrate 501 Pixel circuit 502 Pixel portion 504 Drive circuit portion 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 554 Transistor 560 Capacitance element 562 Capacitance element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel portion 704 Source driver 705 Substrate 706 Gate driver 708 FPC terminal portion 710 Signal line 711 arrangement Line part 712 Seal material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light-emitting element 784 Conductive film 786 EL layer 788 Conductive film 790 Capacitor element 1280a P-type transistor 1280b N-type transistor 1280c N-type transistor 1281 Capacitor element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Transistor 1352 Transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 1404 Signal 1405 Signal 2020 Oxide semiconductor film 2021 Conductive film 2022 Conductive film 2023 Gate insulating film 2024 Conductive film 2025 Conductive film 2101 Detected object 2201 Light 2202 Light 2301 Light 2302 Light 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television apparatus 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal 9501 terminal 9502 terminal 9601 light receiving element 9602 light emitting element 9603 light emitting element 9604 light emitting element 9605 light emitting element

Claims (12)

A semiconductor device having a transistor,
The transistor is
A first gate electrode;
A first insulating film on the first gate electrode;
An oxide semiconductor film having a region overlapping with the first gate electrode with the first insulating film interposed therebetween;
A second insulating film on the oxide semiconductor film;
A second gate electrode having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween;
A third insulating film on the oxide semiconductor film and on the second gate electrode;
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film,
The channel region has a region that emits light;
The emission includes near infrared light,
Semiconductor device. A semiconductor device having a transistor,
The transistor is
A first gate electrode;
A first insulating film on the first gate electrode;
An oxide semiconductor film having a region overlapping with the first gate electrode with the first insulating film interposed therebetween;
A second insulating film on the oxide semiconductor film;
A second gate electrode having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween;
A third insulating film on the oxide semiconductor film and on the second gate electrode;
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film,
The channel region has a function of emitting light;
The light emission includes light in a wavelength region of 900 nm to 1550 nm,
Semiconductor device. In claim 1 or claim 2,
The transistor further comprises:
A source electrode electrically connected to the oxide semiconductor film in the source region through a first opening provided in the third insulating film;
A drain electrode electrically connected to the oxide semiconductor film in the drain region through a second opening provided in the third insulating film;
Semiconductor device. In claim 1 or claim 2,
The oxide semiconductor film includes In, Zn, and M (M is Al, Ga, Y, or Sn).
Semiconductor device. In claim 4,
The oxide semiconductor film has a region in which the In content is equal to or more than the M content.
Semiconductor device. In claim 4,
The second gate electrode includes In, Zn, and M (M is Al, Ga, Y, or Sn).
Semiconductor device. In claim 6,
The second gate electrode has a region in which the In content is equal to or more than the M content.
Semiconductor device. In claim 6,
The second gate electrode has a higher carrier density than the oxide semiconductor film;
Semiconductor device. In claim 1 or claim 2,
The third insulating film has at least one of nitrogen and hydrogen;
Semiconductor device. In claim 1 or claim 2,
The oxide semiconductor film has a crystal part,
The crystal part has c-axis orientation;
Semiconductor device. A semiconductor device according to claim 1 or 2,
A display element;
A display device. A semiconductor device according to claim 1 or 2,
A sensor,
Electronics.

Images