JP6736561B2 - Semiconductor device, display device, and electronic device - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and an electronic device including the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as a technical field of one embodiment of the present invention disclosed more specifically in this specification, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, a driving method thereof, or , Those manufacturing methods can be mentioned as an example.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one mode of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, etc.), and an electronic device may have a semiconductor device.

A technique for forming a transistor (also referred to as a thin film transistor (TFT) or a field effect transistor (FET)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image devices (display devices). As a semiconductor thin film applicable to a transistor, a semiconductor material typified by silicon is widely known, but an oxide semiconductor is drawing attention as another material.

For example, a technique of manufacturing a transistor using an In—Ga—Zn-based oxide as an oxide semiconductor is disclosed (see Patent Document 1). Further, a technique of manufacturing an oxide thin film transistor having a self-aligned top gate structure is disclosed (see Patent Document 2).

Further, in recent years, technological development of a display device having a function of inputting information has been advanced, and Patent Document 3 discloses an optical touch panel that reads input data by detecting infrared rays.

In addition, an electronic device having a function of detecting biological information such as a pulse, a vein, and a pupil is drawing attention, and a biological sensor using infrared rays has been developed (Patent Document 4).

JP, 2007-96055, A JP, 2009-278115, A JP 2012-22674 A JP-A-5-329116

In an optical touch panel having a light emitting diode (LED) that emits infrared rays, a sensor that detects infrared rays is provided on the display surface side of the display device, and an LED that emits infrared rays is used as a backlight. The position of the sensor that detects Therefore, the light in the detection environment or the light in the display device becomes noise, and the accuracy of infrared detection decreases.

Further, when an LED is used as a light emitting element that irradiates infrared rays in an electronic device that reads biometric information and the like, the LED can irradiate infrared rays over a wide range, but it is difficult to irradiate infrared rays to a minute area. .. Therefore, it is difficult to increase the detection accuracy and the detection precision only by increasing the precision of the sensor that detects infrared rays in order to detect fine information.

In view of the above problems, it is an object of one embodiment of the present invention to provide a semiconductor device including a transistor which emits infrared rays. Alternatively, according to one embodiment of the present invention, it is an object to provide a semiconductor device which exhibits infrared rays with high definition. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device which can detect infrared rays with high accuracy. Alternatively, it is an object of one embodiment of the present invention to provide a display device capable of detecting infrared rays with high accuracy. Another object of one embodiment of the present invention is to provide an electronic device that can detect infrared rays with high accuracy. Alternatively, it is an object of one embodiment of the present invention to provide a novel semiconductor device. Alternatively, it is an object of one embodiment of the present invention to provide a method for manufacturing a novel semiconductor device.

Note that the above description of the problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. The problems other than the above are obvious from the description of the specification and the like, and the problems other than the above can be extracted from the description of the specification and the like.

One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, which can efficiently emit infrared light. Alternatively, the semiconductor device has an oxide semiconductor film, which can emit infrared rays with high definition.

Therefore, one embodiment of the present invention is a semiconductor device including a transistor, which includes a first gate electrode, a first insulating film over the first gate electrode, and a first insulating film. An oxide semiconductor film having a region overlapping with the first gate electrode, a second insulating film over the oxide semiconductor film, and a second region having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween. And a third insulating film over the oxide semiconductor film and the second gate electrode, the oxide semiconductor film includes a channel region in contact with the second insulating film, and a third insulating film. A semiconductor device having a source region in contact with the film and a drain region in contact with the third insulating film, the channel region having a region emitting light, and the light emission including near-infrared light.

Another embodiment of the present invention is a semiconductor device including a transistor, which includes a first gate electrode, a first insulating film over the first gate electrode, and a first insulating film. An oxide semiconductor film having a region overlapping with the first gate electrode, a second insulating film over the oxide semiconductor film, and a region overlapping with the oxide semiconductor film through the second insulating film. An oxide semiconductor film, and a third insulating film over the oxide semiconductor film and the second gate electrode, the oxide semiconductor film including a channel region in contact with the second insulating film; 3 has a source region in contact with the third insulating film, and a drain region in contact with the third insulating film, the channel region has a function of emitting light, and the light emission emits light in a wavelength range of 900 nm to 1550 nm. Including, it is a semiconductor device.

In each of the above structures, the transistor further includes a source electrode electrically connected to the oxide semiconductor film in the source region through a first opening provided in the third insulating film, and a third electrode. A semiconductor device having a drain electrode electrically connected to an oxide semiconductor film in a drain region through a second opening provided in an insulating film.

In each of the above structures, the oxide semiconductor film preferably contains In, Zn, and M (M is Al, Ga, Y, or Sn). Further, the oxide semiconductor film preferably has a region in which the In content is greater than or equal to the M content. The oxide semiconductor film preferably has a crystal part, and the crystal part preferably has c-axis orientation.

In each of the above structures, the second gate electrode preferably contains In, Zn, and M (M is Al, Ga, Y, or Sn). In addition, the second gate electrode preferably has a region where the In content is equal to or higher than the M content. Further, the second gate electrode preferably has higher carrier density than the oxide semiconductor film.

In each of the above structures, the third insulating film preferably contains at least one of nitrogen and hydrogen.

Another embodiment of the present invention is a display device including the semiconductor device of each of the above embodiments and a display element. Another embodiment of the present invention is an electronic device including the semiconductor device of the above embodiment and a sensor.

According to one embodiment of the present invention, a semiconductor device including a transistor which emits infrared light can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which emits infrared rays with high precision can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can detect infrared rays with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, a display device which can detect infrared rays with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, an electronic device that can detect infrared rays with high accuracy can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other effects from the description of the specification, drawings, claims, etc. Is.

7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 6A to 6C each illustrate a cross section of a semiconductor device. 6A to 6C each illustrate a cross section of a semiconductor device. 6A to 6C each illustrate a cross section of a semiconductor device. 6A to 6C each illustrate a cross section of a semiconductor device. 6A to 6C each illustrate a cross section of a semiconductor device. The figure explaining a band structure. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 4A to 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 16A to 16C each illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD, and a selected area electron diffraction pattern of the CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a planar TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 10 is a diagram showing a change in a crystal part of an In—Ga—Zn oxide by electron irradiation. Sectional drawing which shows the structural example of a display apparatus. FIG. 6 is a top view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 9 illustrates a circuit configuration of a semiconductor device. 7A and 7B are diagrams illustrating a structure of a pixel circuit and a timing chart illustrating operation of the pixel circuit. 3A and 3B are a block diagram and a circuit diagram illustrating a display device. FIG. 6 illustrates a display module. 7A to 7C each illustrate an electronic device. FIG. 6 is a diagram illustrating an arrangement of a light emitting element and a light receiving element. 6A and 6B are diagrams illustrating an arrangement of a display portion and a light emitting element and a light receiving element. 7A and 7B are diagrams illustrating a top surface and a cross section of a transistor in an example. 7A and 7B are diagrams illustrating Id-Vg characteristics of a transistor in an example. 7A and 7B are diagrams illustrating a light emitting state of a transistor in an example. 7A and 7B are diagrams illustrating a light emitting state of a transistor in an example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and its form and details can be variously modified without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that the position, size, range, or the like of each structure illustrated in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

In addition, in this specification and the like, the ordinal numbers attached as the first and second terms are used for convenience, and do not indicate a process order or a stacking order. Therefore, for example, the description can be made by appropriately replacing "first" with "second" or "third". In addition, the ordinal numbers described in this specification and the like may be different from the ordinal numbers used to specify one embodiment of the present invention.

In this specification, terms such as “above” and “below” are used for convenience in order to explain the positional relationship between the components with reference to the drawings. Further, the positional relationship between the components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, but can be paraphrased appropriately according to the situation.

Further, in this specification and the like, in describing the structure of the present invention with reference to the drawings, the same reference numerals are used in common in different drawings.

In addition, in this specification and the like, even when it is referred to as a “semiconductor”, it may have a property as an “insulator” when conductivity is sufficiently low, for example. In addition, the boundary between “semiconductor” and “insulator” is ambiguous, and in some cases cannot be strictly distinguished. Therefore, the “semiconductor” described in this specification and the like can be referred to as an “insulator” in some cases. Similarly, the “insulator” described in this specification and the like can be called a “semiconductor” in some cases. Alternatively, the “insulator” described in this specification and the like can be referred to as a “semi-insulator” in some cases.

Further, in this specification and the like, even when it is referred to as a “semiconductor”, it may have characteristics as a “conductor” if the conductivity is sufficiently high, for example. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and in some cases cannot be strictly distinguished. Therefore, the “semiconductor” described in this specification and the like can be called a “conductor” in some cases. Similarly, the “conductor” described in this specification and the like can be called a “semiconductor” in some cases.

In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, the channel region, and the source. Can be done. Note that in this specification and the like, a channel region refers to a region in which a current mainly flows.

In addition, the functions of the source and the drain may be switched when a transistor of different polarity is used or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be interchanged.

Note that the channel length is, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor in which current flows) and a gate electrode overlap with each other in a top view of a transistor, or a region where a channel is formed. In, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification and the like, the channel length is any one value, a maximum value, a minimum value, or an average value in a region where a channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when the transistor is in an on state) and a gate electrode overlap with each other, or a source and a drain face each other in a region where a channel is formed. It means the length of the part. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification and the like, the channel width is any one value, a maximum value, a minimum value, or an average value in a region where a channel is formed.

In addition, in this specification and the like, the term “electrically connected” includes the case of being connected through “something having an electrical action”. Here, the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets. For example, “things having some kind of electrical action” include electrodes and wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In addition, the voltage often indicates a potential difference between a certain potential and a reference potential (eg, a ground potential (GND) or a source potential). Therefore, the voltage can be restated as the potential.

In addition, in this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term “insulating film” to the term “insulating layer”.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30° or more and 30° or less. In addition, “vertical” means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

(Embodiment 1)
In this embodiment, an example of a semiconductor device of one embodiment of the present invention and a method for manufacturing the semiconductor device will be described below with reference to FIGS.

<1-1. Configuration example 1 of semiconductor device>
FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 illustrated in FIG. 1A, and FIG. 1C illustrates a dashed-dotted line Y1- illustrated in FIG. It corresponds to a cross-sectional view of the cut surface along Y2. Note that in FIG. 1A, some of components of the transistor 100 (the substrate 102, an insulating film, and the like) are omitted for clarity.

The dashed-dotted line X1-X2 direction in FIG. 1A may be referred to as a channel length (L) direction of the transistor 100, and the dashed-dotted line Y1-Y2 direction may be referred to as a channel width (W) direction of the transistor 100.

The transistor 100 includes a conductive film 106 which functions as a first gate electrode (also referred to as a bottom gate electrode) over the substrate 102, an insulating film 104 over the substrate 102 and the conductive film 106, and an oxide semiconductor film over the insulating film 104. 108, the insulating film 110 over the oxide semiconductor film 108, the conductive film 112 functioning as a second gate electrode (also referred to as a top gate electrode) over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, And an insulating film 116 over the conductive film 112. The oxide semiconductor film 108 has a channel region 108i in which the conductive film 112 is overlapped and in contact with the insulating film 110, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116.

In addition, the transistor 100 is electrically connected to the oxide semiconductor film 108 in the source region 108s through the insulating film 118 over the insulating film 116, the insulating film 116, and the opening portion 141s provided in the insulating film 118. And a conductive film 120d electrically connected to the oxide semiconductor film 108 in the drain region 108d through the opening 141d provided in the insulating film 116 and the insulating film 118.

Note that in this specification and the like, the insulating film 104 is the first insulating film, the insulating film 110 is the second insulating film, the insulating film 116 is the third insulating film, and the insulating film 118 is the fourth insulating film. May be called respectively. In the transistor 100, the insulating film 104 has a function as a first gate insulating film and the insulating film 110 has a function as a second gate insulating film. Therefore, in this specification and the like, the insulating film 104 may be referred to as a first gate insulating film and the insulating film 110 may be referred to as a second gate insulating film. The conductive film 120s functions as a source electrode and the conductive film 120d functions as a drain electrode.

In addition, in the transistor 100, the side end portion of the insulating film 110 and the side end portion of the conductive film 112 preferably have a region where they are aligned with each other. In other words, in the transistor 100, the upper end portion of the insulating film 110 and the lower end portion of the conductive film 112 are substantially aligned. For example, the above structure can be obtained by processing the insulating film 110 using the conductive film 112 as a mask.

In the transistor 100, the conductive film 106 and the conductive film 112 are electrically connected to each other through the opening 143 provided in the insulating film 104 and the insulating film 110. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112.

Thus, the transistor 100 has a structure in which the conductive films functioning as gate electrodes are provided above and below the oxide semiconductor film 108.

<<s-channel structure>>
The oxide semiconductor film 108 is sandwiched between the conductive film 106 and the conductive film 112 with the first gate insulating film and the second gate insulating film interposed therebetween. The length of the conductive film 106 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. Further, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. Further, since the conductive film 106 and the conductive film 112 are electrically connected to each other in the opening 143 provided in the insulating film 104 and the insulating film 110, at least one of side surfaces of the oxide semiconductor film 108 in the channel width direction is formed. , And is opposed to the conductive film 112 via the insulating film 110. That is, the entire channel width direction of the oxide semiconductor film 108 is covered with the conductive film 106 and the conductive film 112 with the first gate insulating film and the second gate insulating film interposed therebetween.

In other words, in the channel width direction of the transistor 100, the conductive film 106 and the conductive film 112 surround the oxide semiconductor film 108 with the first gate insulating film and the second gate insulating film interposed therebetween.

With such a structure, the oxide semiconductor film 108 included in the transistor 100 is electrically surrounded by the electric fields of the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. be able to. A device structure of a transistor, such as the transistor 100, which electrically surrounds an oxide semiconductor film in which a channel region is formed by an electric field of a first gate electrode and a second gate electrode is referred to as a surrounded channel (s-channel) structure. Can be called.

Since the transistor 100 has an s-channel structure, an electric field for inducing a channel by the conductive films 106 and 112 can be effectively applied to the oxide semiconductor film 108. Therefore, the current driving capability of the transistor 100 is improved and high on-state current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100 can be miniaturized. Further, since the transistor 100 has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100 can be increased.

With the above structure, the regions where carriers flow in the oxide semiconductor film 108 are the insulating film 104 side of the oxide semiconductor film 108, the insulating film 110 side of the oxide semiconductor film 108, and the oxide semiconductor. Since the film 108 has a wide area in the film, the amount of carrier movement in the transistor 100 is increased. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is increased, specifically, the field effect mobility is 10 cm ² /V·s or higher. Note that the field-effect mobility here is not an approximate value of mobility as a physical property value of an oxide semiconductor film but an index of current driving force in a saturation region of a transistor and an apparent field-effect mobility.

Note that in FIG. 1C (in the channel width direction of the transistor 100), an opening different from the opening 143 is formed on the opposite side of the place where the opening 143 is formed and the oxide semiconductor film 108. Good.

Further, different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. That is, the signal A may be applied to one gate electrode and the fixed potential Vb may be applied to the other gate electrode. Further, the signal A may be supplied to one gate electrode and the signal B may be supplied to the other gate electrode. Further, the fixed potential Va may be applied to one gate electrode and the fixed potential Vb may be applied to the other gate electrode.

When a fixed potential is applied to both gate electrodes of the transistor, the transistor can function as a resistance element in some cases. For example, in the case where the transistor is an n-channel type, in some cases, the effective resistance of the transistor can be reduced (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by the transistor having only one gate may be obtained.

As described above, since the transistor 100 has the s-channel structure, high on-state current characteristics can be obtained. However, when a current is applied to the channel region 108i in the oxide semiconductor film 108, one of its electric energy is reduced. The part may be converted into heat as Joule heat. In addition, the transistor 100 further includes an insulating film 116 and an insulating film 118 over the conductive film 112 which functions as the second gate electrode. Therefore, the channel region 108i in the oxide semiconductor film 108 has a structure sandwiched between the conductive film 106, the insulating film 104, the insulating film 110, the conductive film 112, the insulating film 116, and the insulating film 118. Therefore, the heat retention effect is excellent, and heat generated when a current is applied to the transistor 100 is less likely to be dissipated. That is, the transistor 100 has a structure in which the temperature is likely to be high when a current is applied and the infrared rays generated by heat are easily emitted. In particular, it is possible to strongly emit an infrared ray having a short wavelength due to a high temperature, easily emit a near infrared ray in a wavelength range of 780 nm to 2500 nm among infrared rays, and particularly emit a near infrared ray in a wavelength range of 900 nm or more and 1550 nm or less. Cheap.

Note that in order to obtain higher on-state current characteristics, the channel width of the transistor 100 is preferably larger, specifically, 50 μm or more, more preferably 100 μm or more.

In addition, the size ( _diw ) of the oxide semiconductor film 108 in the channel width direction overlaps with the oxide semiconductor film 108 so that heat is less likely to propagate from the oxide semiconductor film 108 to the conductive films 120s and 120d. It is preferable that the region have a size that is approximately the same as the size of the conductive film 120s in the channel width direction (d _sw ) and the size of the conductive film 120d in the channel width direction (d _dw ). _{Or, d iw} is preferably has a _{d sw} and _{d dw} larger region. That is, the transistor 100 preferably has a region in which d _iw ≧d _sw and d _iw ≧d _dw .

In addition, in the conductive film 120s, a size in the channel width direction in a region which does not overlap with the oxide semiconductor film 108 ( _dsw ′) is a size in the channel width direction in a region that overlaps with the oxide semiconductor film 108 ( _dsw ). It is preferable to have a smaller (d _sw >d _sw ′) region. In addition, in the conductive film 120d, the size in the channel width direction in a region which does not overlap with the oxide semiconductor film 108 (d _dw ′) is the size in the channel width direction in a region that overlaps with the oxide semiconductor film 108 (d _dw ). More preferably, it has a smaller (d _dw >d _dw ′) region.

In addition, a distance (d _si ) between the channel region 108i in the oxide semiconductor film 108 and a region where the oxide semiconductor film 108 is connected to the conductive film 120s in the opening 141s, the channel region 108i, and the oxide in the opening 141d. By increasing the distance (d _di ) from the region where the semiconductor film 108 is connected to the conductive film 120d, it is possible to prevent heat generated in the channel region 108i from being easily transferred to the conductive films 120s and 120d. Therefore, it is preferably 5 μm or more, and more preferably 10 μm or more.

In addition, it is preferable to reduce the size of the openings 141s and 141d because heat generated in the channel region 108i can be hardly propagated to the conductive films 120s and 120d.

The conductive films 120s and 120d which are conductive films connected to the oxide semiconductor film 108 are preferably substances having low thermal conductivity.

With the above structure, the transistor 100 can be a transistor which easily emits near infrared light.

<1-2. Components of semiconductor device>
The components included in the semiconductor device of this embodiment will be described in detail below.

<<Oxide semiconductor film>>
The oxide semiconductor film 108 in the transistor 100 which is one embodiment of the present invention preferably contains a metal oxide, and the metal oxide preferably contains at least indium (In) or zinc (Zn).

When the oxide semiconductor film contains In, carrier mobility (electron mobility) is increased, for example. Further, when the oxide semiconductor film contains Zn, crystallization of the oxide semiconductor film easily occurs.

When the oxide semiconductor film contains the element M having a function as a stabilizer, for example, the energy gap (Eg) of the oxide semiconductor film becomes large. An oxide semiconductor film suitable for one embodiment of the present invention has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Thus, by using a metal oxide having a wide energy gap for the oxide semiconductor film 108, off-state current of the transistor 100 can be reduced. The element M is an element having a high binding energy with oxygen and has a binding energy with oxygen higher than that of In.

As the oxide semiconductor film suitable for the semiconductor device of one embodiment of the present invention, typically, an In-Zn oxide, an In-M oxide, or an In-M-Zn oxide can be used. Above all, it is preferable to use an In-M-Zn oxide (M represents aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)). In particular, it is preferable to use an In-Ga-Zn oxide (hereinafter sometimes referred to as IGZO) in which M is Ga.

Note that when the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic ratio of In and M is higher than 25 atomic% and M is lower than 75 atomic% when the sum of In and M is 100 atomic%. Or In is higher than 34 atomic% and M is lower than 66 atomic %. In particular, the oxide semiconductor film 108 preferably has a region where the atomic ratio of In is greater than or equal to the atomic ratio of M.

The oxide semiconductor film 108 has a region in which the atomic ratio of In is greater than or equal to the atomic ratio of M, so that the field-effect mobility of the transistor 100 (simply referred to as mobility or μFE) is increased. You can Specifically, the field-effect mobility of the transistor 100 can be higher than 10 cm ² /V·s, and more preferably, the field-effect mobility of the transistor 100 can be higher than 30 cm ² /V·s.

For example, since a transistor having high field-effect mobility can have a small channel width, the transistor has a scan line driver circuit (also referred to as a gate driver) that generates a gate signal or a shift line included in the scan line driver circuit. By using the demultiplexer connected to the output terminal of the register, the size of the scan line driver circuit can be reduced, and a semiconductor device or a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Alternatively, since the gate voltage of the transistor used in the circuit can be reduced, power consumption of the display device can be reduced. The details of the scanning line drive circuit will be described later.

Further, the display device can have high definition by increasing the field-effect mobility of the transistor. For example, pixels of a high-definition display device represented by 4K×2K (horizontal pixel number=3840, vertical pixel number=2160) or 8K×4K (horizontal pixel number=7680, vertical pixel number=4320) The above transistor is suitable as a transistor of a circuit or a driver circuit.

The thickness of the oxide semiconductor film 108 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 60 nm or less.

In the case where the oxide semiconductor film 108 is formed using an In-M-Zn oxide, the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is such that In is M or more and Zn is Preferably satisfies M or more. Alternatively, in the sputtering target, the atomic ratio of metal elements _{In: M: Zn = x b} : y b: When _{z b} [atomic _ratio], x b / _{y b} is 1/3 to 6, further Is 1 or more and 6 or less, and z _b /y _b is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that by setting z _b /y _b to be 1 or more and 6 or less, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film described later can be easily formed as the oxide semiconductor film 108. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:. 1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4: 2:4.1, In:M:Zn=5:1:7, and the like are preferable.

Note that the atomic ratio of the oxide semiconductor film 108 includes a variation of ±40% in the above atomic ratio as an error. For example, in the case where an atomic ratio of In:Ga:Zn=4:2:4.1 is used as a sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn=4:2. : There are cases where it is close to 3. Alternatively, when the atomic ratio of In:Ga:Zn=1:1:1.2 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn=1:1. :1 There may be a vicinity. Alternatively, when an atomic ratio of In:Ga:Zn=5:1:7 is used as a sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn=5:1:6. It may be in the vicinity.

Further, impurities such as hydrogen or moisture mixed in the channel region 108i in the oxide semiconductor film 108 cause a problem because they affect transistor characteristics. Therefore, it is preferable that the channel region 108i in the oxide semiconductor film 108 contain less impurities such as hydrogen or moisture.

Hydrogen contained in the oxide semiconductor film 108 reacts with oxygen bonded to a metal atom to be water, and oxygen vacancies are formed in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen which is combined with a metal atom to generate an electron which is a carrier. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to have negative electrical characteristics (also referred to as normally-on characteristics).

Therefore, in the channel region 108i of the oxide semiconductor film 108, hydrogen is preferably reduced as much as possible. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms. /Cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, less than 5×10 ¹⁸ atoms/cm ³ , preferably 1×10 ¹⁸ atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm 3. ³ or less, and more preferably 1×10 ¹⁶ atoms/cm ³ or less. As a result, the transistor has electric characteristics in which the threshold voltage of the transistor is positive (also referred to as normally-off characteristics).

Further, in the oxide semiconductor film 108, when silicon or carbon which is one of Group 14 elements is contained, oxygen vacancies are increased, which might result in n-type conductivity. Therefore, in the oxide semiconductor film 108, particularly in the channel region 108i, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) is 2×10 ¹⁸ atoms/cm ³ or less, or 2×10 ¹⁷ atoms. /Cm ³ or less. As a result, the transistor has electric characteristics in which the threshold voltage is positive (also referred to as normally-off characteristics).

In addition, in the channel region 108i, the concentration of an alkali metal or an alkaline earth metal obtained by secondary ion mass spectrometry is less than or equal to 1×10 ¹⁸ atoms/cm ³ or less than or equal to 2×10 ¹⁶ atoms/cm ^3. You can Alkali metal and alkaline earth metal may generate carriers when combined with an oxide semiconductor, which might increase off-state current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has electric characteristics in which the threshold voltage is positive (also referred to as normally-off characteristics).

In addition, when nitrogen is contained in the channel region 108i, electrons that are carriers are generated, carrier density is increased, and n-type conductivity may be generated in some cases. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the channel region 108i. For example, the nitrogen concentration obtained by secondary ion mass spectrometry may be 5×10 ¹⁸ atoms/cm ³ or less.

Further, by reducing the impurity element in the channel region 108i, the carrier density of the oxide semiconductor film 108 can be reduced. Therefore, in the channel region 108i, the carrier density is 1×10 ¹⁷ /cm ³ or less, or 1×10 ¹⁵ /cm ³ or less, or 1×10 ¹³ /cm ³ or less, or 1×10 ¹¹ /cm ³ or less. Can be

By using the oxide semiconductor film 108 having a low impurity concentration and a low density of defect states as the channel region 108i, a transistor having further excellent electrical characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high-purity intrinsic or substantially high-purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources and thus can have a low carrier density in some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film tends to have positive threshold voltage (i.e., normally-off characteristics). Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have characteristics in which off-state current is extremely small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a highly reliable transistor with small variation in electric characteristics.

Note that an impurity of a semiconductor means a substance other than a main component forming a semiconductor film. For example, an element whose concentration is less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be lowered, and crystallinity may be lowered. When the semiconductor includes an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component. In particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by the mixture of impurities such as hydrogen. In the case where the semiconductor has silicon, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, and a Group 15 element other than oxygen and hydrogen.

In addition, a transistor in which a channel region is formed in a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film tends to have positive threshold voltage (also referred to as normally-off characteristic). Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.

A transistor including a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly small off-state current, a channel width of 1×10 ⁶ μm, and a channel length L of 10 μm. Also, in the case where the voltage (drain voltage) between the source electrode and the drain electrode is in the range of 1V to 10V, it is possible to obtain the characteristic that the off current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1×10 ⁻¹³ A or less. .. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has low variation in electric characteristics and has high reliability.

In addition, in this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is in an off state (also referred to as a non-conducting state or a blocking state). Unless otherwise specified, the off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor may be a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of a transistor may depend on Vgs. Therefore, the off-state current of a transistor is less than or equal to I may mean that there is a value of Vgs at which the off-state current of a transistor is less than or equal to I. The off-state current of a transistor may refer to an off-state at a predetermined Vgs, an off-state at Vgs within a predetermined range, an off-state at Vgs at which a sufficiently reduced off-state is obtained, or the like.

As an example, the threshold voltage Vth is 0.5V, Vgs is the drain current is 1 × ^{10 -9} A in 0.5V, the drain current Vgs is at 0.1V is located at 1 × ^{10- 13} A , And the drain current at Vgs of −0.5 V is 1×10 ⁻¹⁹ A, and the drain current at Vgs of −0.8 V is 1×10 ⁻²² A. The drain current of the transistor is 1×10 ⁻¹⁹ A or lower at Vgs of −0.5 V or in the range of Vgs of −0.5 V to −0.8 V; therefore, the off-state current of the transistor is 1 It may be said that it is ×10 ⁻¹⁹ A or less. Since there is Vgs at which the drain current of the transistor is 1×10 ⁻²² A or lower, the off-state current of the transistor is 1×10 ⁻²² A or lower in some cases.

The off-state current of a transistor may depend on temperature. In the present specification, off-state current may represent off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C., unless otherwise specified. Alternatively, at a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed or at a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 °C to 35 °C). Off current may be expressed. The off-state current of a transistor is less than or equal to I means room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which reliability of a semiconductor device including the transistor is guaranteed, or the transistor includes the transistor. In some cases, it means that there is a value of Vgs at which the off-state current of the transistor is less than or equal to I at the temperature at which the semiconductor device or the like is used (e.g., any one temperature of 5 °C to 35 °C).

The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In the present specification, the off-state current has Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V unless otherwise specified. , Or off current at 20V. Alternatively, it may represent Vds at which reliability of a semiconductor device or the like including the transistor is guaranteed or off-state current at Vds used in the semiconductor device or the like including the transistor. The off-state current of the transistor is I or less means that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V. There is a value of Vgs that guarantees the reliability of the semiconductor device including the transistor, or Vgs at which the off-state current of the transistor in Vds used in the semiconductor device including the transistor becomes I or less. Sometimes referred to.

In the above description of the off-state current, the drain may be read as the source. That is, the off-state current may refer to a current flowing through the source when the transistor is off.

In addition, in this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, the off-state current may refer to a current flowing between the source and the drain when the transistor is off, for example.

Note that the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear and may behave like fixed charge. Therefore, electric characteristics of a transistor in which a channel region is formed in an oxide semiconductor film with high trap level density might be unstable. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like.

In addition, oxygen vacancies formed in the channel region 108i in the oxide semiconductor film 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region 108i of the oxide semiconductor film 108, hydrogen is bonded to the oxygen vacancies and serves as a carrier supply source. When a carrier supply source is generated in the channel region 108i of the oxide semiconductor film 108, the electric characteristics of the transistor 100 including the oxide semiconductor film 108 is changed, typically, the threshold voltage is shifted. Therefore, it is preferable that the number of oxygen vacancies in the channel region 108i of the oxide semiconductor film 108 be as small as possible.

Thus, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film, specifically, the insulating film 104 formed below the oxide semiconductor film 108 and the insulating film 104 formed above the oxide semiconductor film 108 are formed. The insulating film 110 has a structure containing excess oxygen. By moving oxygen or excess oxygen from the insulating film 104 and the insulating film 110 to the oxide semiconductor film 108, oxygen vacancies in the oxide semiconductor film 108 can be reduced. Therefore, it is possible to suppress variations in the electrical characteristics of the transistor 100, particularly variations in the electrical characteristics of the transistor 100 during light irradiation.

In addition, in one embodiment of the present invention, a manufacturing method in which the number of manufacturing steps is not increased or the number of manufacturing steps is extremely small is used because the insulating film 104 and the insulating film 110 contain excess oxygen. Therefore, the yield of the transistor 100 can be increased.

Specifically, in the step of forming the oxide semiconductor film 108, the oxide semiconductor film 108 is formed in an atmosphere containing oxygen gas by a sputtering method, so that the surface where the oxide semiconductor film 108 is formed is formed. Oxygen or excess oxygen is added to the insulating film 104.

The transistor 100 having such a structure has extremely few defects in the channel region 108i in the oxide semiconductor film 108, and thus has improved electrical characteristics. Typically, the on-state current of the transistor 100 can be increased and the field-effect mobility can be improved. Further, the transistor 100 has a small amount of change in threshold voltage in the BT stress test and the optical BT stress test, which are examples of the stress test, and has high reliability. Note that the BT stress test is a kind of accelerated test, and a characteristic change (that is, secular change) of a transistor which occurs due to long-term use can be evaluated in a short time. In particular, the amount of fluctuation in the threshold voltage of the transistor before and after the BT stress test is an important index for examining the reliability. It can be said that a transistor having higher reliability has a smaller threshold voltage variation before and after the BT stress test.

On the other hand, the source region 108s and the drain region 108d are in contact with the insulating film 116. Since the source region 108s and the drain region 108d are in contact with the insulating film 116, one or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density is increased. ..

Note that the oxide semiconductor film 108 is not limited to the above structure and may have an appropriate composition depending on required semiconductor characteristics and electric characteristics of a transistor (field effect mobility, threshold voltage, or the like). Good. In addition, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the oxide semiconductor film must be appropriate. Is preferred.

The oxide semiconductor film 108 may have a non-single crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest defect level density and the CAAC-OS has the lowest defect level density.

Note that the oxide semiconductor film 108 has a single-layer film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Alternatively, the film may have a laminated structure.

Note that in the oxide semiconductor film 108, the crystallinity of the channel region 108i may be different from that of the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when the impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged and the crystallinity is lowered.

The source region 108s and the drain region 108d included in the oxide semiconductor film 108 may each include an element that forms oxygen vacancies. Typical examples of the element that forms oxygen vacancies (also referred to as an impurity element) include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon.

When the impurity element is added to the oxide semiconductor film, the bond between the metal element in the oxide semiconductor film and oxygen is broken and oxygen vacancies are formed. Alternatively, when the impurity element is added to the oxide semiconductor film, oxygen which is bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, oxygen is released from the metal element, and oxygen vacancies are formed. It As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

<< substrate >>
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a particular substrate. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, a plastic substrate, a metal substrate, a stainless steel substrate, and a stainless steel foil. A substrate having a film, a substrate having a tungsten film, a substrate having a tungsten foil, a flexible substrate, a bonding film, a paper containing a fibrous material, a base film, or the like. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, the base film and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). Alternatively, as an example, there is a synthetic resin such as acrylic resin. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like. Alternatively, for example, polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, paper, or the like can be given. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, shape, high current capability, or small size can be manufactured. .. When a circuit is formed using such transistors, low power consumption of the circuit or high integration of the circuit can be achieved.

When a glass substrate is used as the substrate 102, the sixth generation (1500 mm×1850 mm), the seventh generation (1870 mm×2200 mm), the eighth generation (2200 mm×2400 mm), the ninth generation (2400 mm×2800 mm), the tenth generation A large-sized display device can be manufactured by using a large-area substrate of a generation (2950 mm×3400 mm) or the like.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. The peeling layer can be used for separating a semiconductor device over the peeling layer, separating it from the substrate 102, and transferring it to another substrate. At that time, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate. Note that, for the above-described release layer, for example, a structure having a stacked structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed over a substrate, or the like can be used.

As an example of the substrate on which the transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) (Including silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester, etc.), leather substrate, or rubber substrate. By using these substrates, formation of a transistor with excellent characteristics, formation of a transistor with low power consumption, manufacture of a device that is not easily broken, heat resistance imparted, weight reduction, or thickness reduction can be achieved.

<<Insulating film that functions as the first gate insulating film>>
The insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. The insulating film 104 can be formed as a single layer or a stacked layer of an oxide insulating film and a nitride insulating film, for example. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region of the insulating film 104 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. By using an oxide insulating film which releases oxygen by heating as the insulating film 104, oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By thickening the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 can be obtained. Oxygen deficiency contained in 108i can be reduced.

As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used and can be provided as a single layer or a stacked layer. In this embodiment, the insulating film 104 has a stacked-layer structure of a silicon nitride film and a silicon oxynitride film. As described above, with the insulating film 104 having a stacked structure and using the silicon nitride film as the lower layer and the silicon oxynitride film as the upper layer, oxygen can be efficiently introduced into the oxide semiconductor film 108.

Note that in this specification and the like, silicon oxynitride refers to a composition in which the content of oxygen is higher than that of nitrogen, preferably 55 atomic% or more and 65 atomic% or less of oxygen, and 1 atomic% or more of nitrogen. 20 at% or less, silicon at 25 at% or more and 35 at% or less, and hydrogen in the range of 0.1 at% or more and 10 at% or less. Silicon oxynitride refers to one having a higher nitrogen content than oxygen as its composition, preferably 55 atomic% or more and 65 atomic% or less of nitrogen, 1 atomic% or more and 20 atomic% or less of oxygen, and 25 atomic% of silicon. It means one containing at least 35 atomic% and not more than 0.1 atomic% and not more than 10 atomic% of hydrogen.

Note that at least a region of the insulating film 104, which is in contact with the oxide semiconductor film 108, is preferably an oxide insulating film and has a region containing oxygen in excess of the stoichiometric composition (oxygen excess region). More preferable. In other words, the insulating film 104 is an insulating film capable of releasing oxygen. In order to provide the oxygen excess region in the insulating film 104, the insulating film 104 may be formed in an oxygen atmosphere, for example. Alternatively, oxygen may be added to the formed insulating film 104. A method for adding oxygen to the formed insulating film 104 will be described later.

In addition, as the insulating film 104, hafnium silicate (HfSiO _x ), nitrogen-added hafnium silicate (HfSi _x O _y N _z ), nitrogen-added hafnium aluminate (HfAl _x O _y N _z ), hafnium oxide, A high-k material such as yttrium oxide can be preferably used. The material containing hafnium or yttrium has a higher relative dielectric constant than silicon oxide or silicon oxynitride. Therefore, by using the above-described high-k material for the insulating film 104, the film thickness can be increased as compared with the case where a silicon oxide film is used, so that leakage current due to a tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystalline structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure in order to obtain a transistor with a low off-state current. Examples of the crystal structure include monoclinic system and cubic system. However, one embodiment of the present invention is not limited to these.

Note that in this embodiment, the insulating film 104 is formed by stacking a silicon nitride film on the conductive film 106 side and a silicon oxide film on the oxide semiconductor film 108 side. The silicon nitride film has a higher relative permittivity than the silicon oxide film, and has a large film thickness necessary to obtain a capacitance equivalent to that of the silicon oxide film. Therefore, by including the silicon nitride film as the first gate insulating film of the transistor 100, the first gate insulating film can be physically thickened. Therefore, a decrease in withstand voltage of the transistor 100 can be suppressed, and further, the withstand voltage can be improved and electrostatic breakdown of the transistor 100 can be suppressed.

<<Insulating film that functions as the second gate insulating film>>
The insulating film 110 can be formed as a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region of the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used and can be provided as a single layer or a stacked layer.

Further, by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like as the insulating film 110, diffusion of oxygen from the oxide semiconductor film 108 to the outside and hydrogen from the outside to the oxide semiconductor film 108 are performed. It is possible to prevent intrusion of water, etc. Examples of the insulating film having a blocking effect against oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like.

As the insulating film 110, hafnium silicate (HfSiO _x ), nitrogen-added hafnium silicate (HfSi _x O _y N _z ), nitrogen-added hafnium aluminate (HfAl _x O _y N _z ), hafnium oxide, Gate leakage of the transistor can be reduced by using a high-k material such as yttrium oxide.

By using an oxide insulating film which releases oxygen by heating as the insulating film 110, oxygen contained in the insulating film 110 can be moved to the oxide semiconductor film 108 by heat treatment.

For that purpose, the insulating film 110 preferably includes at least an oxide insulating film containing oxygen in excess of the stoichiometric composition. Note that the second gate insulating film can be formed to have one layer or two or more layers as appropriate. In these cases, it is preferable to have an oxide insulating film containing at least oxygen in excess of the stoichiometric composition.

The thickness of the insulating film 110 can be 5 nm to 400 nm inclusive, 50 nm to 300 nm inclusive, or 10 nm to 250 nm inclusive.

<<A conductive film functioning as a first gate electrode and a pair of electrodes>>
The conductive film 106 and the conductive films 120s and 120d can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. The conductive films 120s and 120d are, for example, metal elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or alloys containing the above metal elements as components. It can be formed using an alloy or the like in which the above metal elements are combined. Further, a metal element selected from one or more of manganese and zirconium may be used. The conductive films 120s and 120d may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure of laminating a titanium film on an aluminum film, a two-layer structure of laminating a titanium film on a titanium nitride film, and a nitriding film. Two-layer structure in which a tungsten film is stacked on a titanium film, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, a titanium film A two-layer structure in which a copper film is laminated on a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure is formed by further forming a titanium film on the titanium film, and a copper film is laminated on a copper film containing manganese. In addition, there is a three-layer structure in which a copper film containing manganese is further formed thereon. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

In addition, the conductive films 120s and 120d include indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide, indium zinc oxide, or indium tin oxide containing silicon (also referred to as ITSO) can be used. Alternatively, a stacked-layer structure of the above light-transmitting conductive material and the above metal element can be used.

The thickness of the conductive films 120s and 120d can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

<<Conductive Film 112 Functioning as Second Gate Electrode>>
The conductive film 112 functioning as the second gate electrode is formed using the same material and manufacturing method as those of the conductive film 106 functioning as the first gate electrode and the conductive films 120s and 120d functioning as a pair of electrodes described above. Can be formed. Alternatively, a laminated structure of these may be used.

The conductive film 112 can be formed using a material and a manufacturing method similar to those of the oxide semiconductor film 108 described above. For example, as the conductive film 112, an In oxide, an In—Sn oxide, an In—Zn oxide, an In—Ga oxide, a Zn oxide, an Al—Zn oxide, an In—Ga—Zn oxide, or the like is used. Can be used. In particular, it is preferable to use an In—Sn oxide or an In—Ga—Zn oxide. For the conductive film 112, a material such as indium tin oxide (ITO) or indium tin oxide to which silicon oxide is added (ITSO) can be used. Further, when the conductive film 112 and the oxide semiconductor film 108 have the same metal element, manufacturing cost can be suppressed.

For example, in the case where an In-M-Zn oxide is used as the conductive film 112, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is a region where In is M or more. It is preferable to have As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:7 and the vicinity thereof. Note that the conductive film 112 is not limited to the above composition of the sputtering target. The conductive film 112 can have a single-layer structure or a stacked structure of two or more layers.

In addition, the conductive film 112 has a function of supplying oxygen to the insulating film 110. Since the conductive film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen can be contained in the insulating film 110. When the insulating film 110 has an excess oxygen region, the excess oxygen can be supplied to the oxide semiconductor film 108, more specifically, the channel region 108i. Therefore, a highly reliable semiconductor device can be provided.

Note that in order to supply excess oxygen into the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. However, in this case, oxygen contained in the insulating film 104 can be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance in the source region 108s and the drain region 108d may increase.

On the other hand, with the structure in which the insulating film 110 formed over the oxide semiconductor film 108 contains excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density of the source region 108s and the drain region 108d may be selectively increased.

Further, in the conductive film 112, after supplying oxygen to the insulating film 110, one or both of nitrogen and hydrogen are supplied from the insulating film 116, so that a donor level is formed in the vicinity of the conduction band and carrier density is increased. Becomes higher. In other words, the conductive film 112 also has a function as an oxide conductor (OC: Oxide Conductor). Therefore, the conductive film 112 has higher carrier density than the oxide semiconductor film 108.

In general, an oxide semiconductor has a large energy gap and thus has a property of transmitting visible light. On the other hand, the oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the oxide conductor is less affected by absorption by the donor level and has a light-transmitting property similar to that of an oxide semiconductor with respect to visible light. Therefore, by using an oxide conductor for the conductive film 112, infrared rays emitted from the channel region 108i can be efficiently extracted.

≪Third insulating film≫
The insulating film 116 has one or both of nitrogen and hydrogen. With the structure in which the insulating film 116 contains either or both of nitrogen and hydrogen, either or both of nitrogen and hydrogen can be supplied to the oxide semiconductor film 108 and the conductive film 112. Examples of the insulating film 116 include a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The hydrogen concentration in the insulating film 116 is preferably 1×10 ²² atoms/cm ³ or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. The insulating film 116 is in contact with the conductive film 112. Therefore, the concentration of hydrogen in the source region 108s, the drain region 108d, and the conductive film 112 which are in contact with the insulating film 116 is high, so that the carrier density of the source region 108s, the drain region 108d, and the conductive film 112 can be increased. Note that the source region 108s, the drain region 108d, and the conductive film 112 may each have a region where the hydrogen concentration in the film is the same by being in contact with the insulating film 116.

<<Fourth Insulating Film>>
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used and can be provided as a single layer or a stacked layer.

The insulating film 118 is preferably a film which functions as a barrier film against hydrogen, water, and the like from the outside.

The thickness of the insulating film 118 can be 30 nm to 500 nm, or 100 nm to 400 nm.

<1-3. Configuration Examples 2 to 6 of Semiconductor Device>
Next, a structure which is different from that of the semiconductor device illustrated in FIGS. 1A to 1C will be described with reference to FIGS.

<<Structure example 2 of semiconductor device>>
2A is a top view of the transistor 100A, FIG. 2B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 2A, and FIG. 2C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2.

A transistor 100A illustrated in FIGS. 2A, 2B, and 2C includes an insulating film 104 formed over a substrate 102, an oxide semiconductor film 108 over the insulating film 104, and an insulating film over the oxide semiconductor film 108. 110, the conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112. The oxide semiconductor film 108 includes a channel region 108i in contact with the insulating film 110, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116.

The transistor 100A is different from the transistor 100 described above in that the conductive film 106 and the opening 143 are not provided.

Thus, the transistor 100A illustrated in FIGS. 2A, 2B, and 2C is different from the transistor 100 described above in that the transistor 100A has a conductive film functioning as a gate electrode only over the oxide semiconductor film 108. is there. As shown in the transistor 100A, the use of one gate electrode facilitates manufacturing, and thus can be manufactured at low cost.

<<Structure Example 3 of Semiconductor Device>>
Next, a structure different from the semiconductor device illustrated in FIGS. 1A, 1B, and 1C will be described with reference to FIGS.

3A is a top view of the transistor 100B, FIG. 3B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 3A, and FIG. 3C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2.

A transistor 100B illustrated in FIGS. 3A, 3B, and 3C is different in the shape of the conductive film 112 from the transistor 100 described above. Specifically, the lower end portion of the conductive film 112 included in the transistor 100B is formed inside the upper end portion of the insulating film 110. In other words, the side end of the insulating film 110 is located outside the side end of the conductive film 112.

For example, the conductive film 112 and the insulating film 110 are processed with the same mask, the conductive film 112 is processed by a wet etching method, and the insulating film 110 is processed by a dry etching method, whereby the above structure can be obtained. ..

When the conductive film 112 has the above structure, the region 108f may be formed in the oxide semiconductor film 108 in some cases. The region 108f is formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.

The region 108f functions as either a high resistance region or a low resistance region. The high-resistance region is a region that has resistance equal to that of the channel region 108i and does not overlap with the conductive film 112 which functions as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the channel length (L) direction in order to suppress decrease in on-state current of the transistor 100B.

The low resistance region is a region having a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, the electric field in the drain region can be relaxed, so that variation in the threshold voltage of the transistor due to the electric field in the drain region can be reduced.

Note that in the case where the region 108f is a low resistance region, for example, either or both of hydrogen and nitrogen are supplied from the insulating film 116 to the region 108f, or the insulating film 110 and the conductive film 112 are used as masks for conductivity. An impurity element is added from above the film 112, so that the impurity is added to the oxide semiconductor film 108 through the insulating film 110.

<<Structure Example 4 of Semiconductor Device>>
Next, modifications of the semiconductor device shown in FIGS. 3A, 3B, and 3C will be described with reference to FIGS.

4A and 4B are cross-sectional views of the transistor 100C. A top view of the transistor 100C is similar to that of the transistor 100B illustrated in FIG. 3A, and thus will be described with reference to FIG. 4A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 3A, and FIG. 4B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 3A.

The transistor 100C is different from the transistor 100B described above in that the insulating film 122 functioning as a planarization insulating film is provided. The rest of the configuration is the same as that of the transistor 100B described above, and has the same effect.

The insulating film 122 has a function of flattening unevenness and the like due to transistors and the like. The insulating film 122 only needs to have insulating properties and is formed using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, and aluminum nitride. Examples of the organic material include photosensitive resin materials such as acrylic resin and polyimide resin.

Note that in FIGS. 4A and 4B, the shape of the opening portion included in the insulating film 122 is smaller than the shape of the opening portions 141s and 141d; however, the shape is not limited to this, and for example, the opening portions 141s and 141d. The shape may be the same as or the shape larger than the openings 141s and 141d.

4A and 4B illustrate the structure in which the conductive films 120s and 120d are provided over the insulating film 122, the invention is not limited to this. For example, the conductive films 120s and 120d are provided over the insulating film 118. Alternatively, the insulating film 122 may be provided over the conductive films 120s and 120d.

<<Structure Example 5 of Semiconductor Device>>
Next, modifications of the semiconductor device shown in FIGS. 2A, 2B, and 2C will be described with reference to FIGS.

5A and 5B are cross-sectional views of the transistor 100D. A top view of the transistor 100D is similar to that of the transistor 100 illustrated in FIG. 2A, and thus will be described with reference to FIG. 5A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 2A, and FIG. 5B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 2A.

The transistor 100D differs from the above-described transistor 100A in the shape of the insulating film 110. The rest of the configuration is the same as that of the transistor 100A described above, and has the same effect.

The insulating film 110 included in the transistor 100D is located inside the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end of the conductive film 112. For example, after processing the conductive film 112, the insulating film 110 is side-etched using an etchant or the like, so that the structure illustrated in FIGS. 5A and 5B can be obtained. Note that by forming the insulating film 110 with the above structure, a hollow region 147 is formed below the conductive film 112.

The hollow region 147 has air and functions as a part of the gate insulating film. The relative permittivity of the hollow region 147 is approximately 1 as in air. Therefore, with the structure of the transistor 100D, when a voltage is applied to the conductive film 112 functioning as a gate electrode, the voltage applied to the channel region 108i below the hollow region 147 is changed to the channel region below the insulating film 110. It will be lower than the voltage applied to 108i. Therefore, the channel region 108i below the hollow region 147 effectively functions as an overlap region (also referred to as a Lov region). Note that the Lov region is a region which overlaps with the conductive film 112 functioning as a gate electrode and has lower resistance than the channel region 108i.

6A and 6B are cross-sectional views of the transistor 100E. A top view of the transistor 100E is similar to that of the transistor 100 in FIG. 2A; therefore, description is made with reference to FIG. 9A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 2A, and FIG. 9B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 2A.

The transistor 100E is different from the above-described transistor 100A in the shapes of the insulating film 110 and the insulating film 116. The rest of the configuration is the same as that of the transistor 100A described above, and has the same effect.

The insulating film 110 included in the transistor 100E is located inside the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end of the conductive film 112. For example, after the conductive film 112 is processed, the insulating film 110 is side-etched using an etchant or the like, so that the structure illustrated in FIGS. 6A and 6B can be obtained. In addition, after the insulating film 110 has the above structure, the insulating film 116 is formed, so that the insulating film 116 also enters the lower side of the conductive film 112 and the insulating film 116 is oxidized below the conductive film 112. In contact with the semiconductor film 108.

With the above structure, the source region 108s and the drain region 108d are located inside the lower end portion of the conductive film 112. Therefore, the transistor 100E has a Lov region.

With the structure including the Lov region like the transistor 100D and the transistor 100E, a high-resistance region is not formed between the channel region 108i and the source region 108s and the drain region 108d; thus, the on-state current of the transistor is increased. Is possible.

<<Structure Example 6 of Semiconductor Device>>
Next, modifications of the semiconductor device shown in FIGS. 1A, 1B, and 1C will be described with reference to FIGS.

7A and 7B are cross-sectional views of the transistor 100F. A top view of the transistor 100F is similar to that of the transistor 100 in FIG. 1A; therefore, description is made with reference to FIG. 7A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 1A, and FIG. 7B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 1A.

The structure of the oxide semiconductor film 108 of the transistor 100F is different from that of the transistor 100 described above. The rest of the configuration is the same as that of the transistor 100 described above, and has the same effect.

The oxide semiconductor film 108 included in the transistor 100F includes the oxide semiconductor film 108_1 over the insulating film 116, the oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and the oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. With.

The channel region 108i, the source region 108s, and the drain region 108d each have a stacked-layer structure of three layers of an oxide semiconductor film 108_1, an oxide semiconductor film 108_2, and an oxide semiconductor film 108_3.

8A and 8B are cross-sectional views of the transistor 100G. A top view of the transistor 100G is similar to that of the transistor 100 in FIG. 1A; therefore, description is made with reference to FIG. 8A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 1A, and FIG. 8B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 1A.

The transistor 100G is different from the above-described transistor 100 in the structure of the oxide semiconductor film 108. The rest of the configuration is the same as that of the transistor 100 described above, and has the same effect.

The oxide semiconductor film 108 included in the transistor 100G includes the oxide semiconductor film 108_2 over the insulating film 116 and the oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.

The channel region 108i, the source region 108s, and the drain region 108d each have a stacked-layer structure of two layers of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3.

In the channel region 108i, the transistor 100G has a stacked-layer structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3.

≪Band structure≫
Here, a band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110, and a band structure of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110 are illustrated in FIGS. Will be explained.

FIG. 9A illustrates an example of a band structure in a film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110. 9B illustrates an example of a band structure in a film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. Note that the band structure indicates an energy level (Ec) at the bottom of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110 for easy understanding.

In addition, in FIG. 9A, a silicon oxide film is used as the insulating films 104 and 110, and a metal oxide target in which the atomic ratio of metal elements is In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_1. And a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=4:2:4.1 is used as the oxide semiconductor film 108_2. An oxide semiconductor film is used, and an oxide semiconductor film formed by using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film 108_3. It is a band figure.

In FIG. 9B, a silicon oxide film is used as the insulating films 104 and 110, and the oxide semiconductor film 108_2 has a metal element atomic ratio of In:Ga:Zn=4:2:4.1. Using an oxide semiconductor film formed using a metal target, and the oxide semiconductor film 108_3 is formed using a metal oxide target in which the atomic ratio of metal elements is In:Ga:Zn=1:3:2. FIG. 11 is a band diagram of a structure including an oxide semiconductor film.

As illustrated in FIG. 9A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the bottom of the conduction band changes gently. In addition, as illustrated in FIG. 9B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the bottom of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.

In order to form a continuous bond on the oxide semiconductor films 108_1, 108_2, and 108_3, a film formation apparatus (sputtering apparatus) of a multi-chamber method provided with a load lock chamber is used, and each film is continuously exposed to the atmosphere. It is necessary to stack them.

With the structure illustrated in FIGS. 9A and 9B, the oxide semiconductor film 108_2 serves as a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. Recognize.

Note that by providing the oxide semiconductor films 108_1 and 108_3, a trap level which can be formed in the oxide semiconductor film 108_2 can be separated from the oxide semiconductor film 108_2.

In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the bottom of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, so that electrons are likely to be accumulated in the trap level. .. The accumulation of electrons in the trap level causes a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the trap level be closer to the vacuum level than the energy level (Ec) at the bottom of the conduction band of the oxide semiconductor film 108_2. By doing so, electrons are less likely to be accumulated in the trap level, the on-current of the transistor can be increased, and the field-effect mobility can be increased.

In the oxide semiconductor films 108_1 and 108_3, the energy level at the bottom of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 108_2, and typically, the energy level at the bottom of the conduction band of the oxide semiconductor film 108_2. And the energy level at the bottom of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or higher, or 0.5 eV or higher and 2 eV or lower, or 1 eV or lower. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or higher, or 0.5 eV or higher and 2 eV or lower, or 1 eV or lower.

With such a structure, the oxide semiconductor film 108_2 serves as a main current path. That is, the oxide semiconductor film 108_2 has a function as a channel region and the oxide semiconductor films 108_1 and 108_3 have a function as oxide insulating films. For the oxide semiconductor films 108_1 and 108_3, it is preferable to use an oxide semiconductor film including one or more metal elements included in the oxide semiconductor film 108_2 in which the channel region is formed. With such a structure, interface scattering is unlikely to occur at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Therefore, carrier movement is not hindered at the interface, so that the field-effect mobility of the transistor is increased.

Further, for the oxide semiconductor films 108_1 and 108_3, a material having sufficiently low conductivity is used in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films due to their physical properties and/or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is smaller than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is oxide. A material having a difference (band offset) from the energy level at the bottom of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress a difference in threshold voltage depending on the magnitude of the drain voltage, the energy levels at the bottoms of the conduction bands of the oxide semiconductor films 108_1 and 108_3 are set to the conduction levels of the oxide semiconductor film 108_2. It is preferable to use a material closer to the vacuum level by 0.2 eV than the energy level at the lower end of the band, preferably 0.5 eV or more and a material closer to the vacuum level.

Further, it is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel-type crystal structure in the film. In the case where the oxide semiconductor films 108_1 and 108_3 each include a spinel crystal structure, the constituent elements of the conductive films 120s and 120d are transferred to the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. It may spread. Note that when the oxide semiconductor films 108_1 and 108_3 are CAAC-OS, a blocking property of a constituent element of the conductive films 120s and 120d, for example, a copper element is high, which is preferable.

Further, in this embodiment, as the oxide semiconductor films 108_1 and 108_3, oxide semiconductors formed using a metal oxide target in which the atomic ratio of metal elements is In:Ga:Zn=1:3:2. Although the configuration using the membrane has been illustrated, the invention is not limited to this. For example, as the oxide semiconductor films 108_1 and 108_3, In:Ga:Zn=1:1:1 [atomic ratio], In:Ga:Zn=1:1:1.2 [atomic ratio], In:Ga :Zn=1:3:4 [atomic ratio], or In:Ga:Zn=1:3:6 [atomic ratio], and an oxide semiconductor formed using a metal oxide target in the vicinity thereof. Membranes may be used.

Note that in the case where a metal oxide target of In:Ga:Zn=1:1:1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 have In:Ga:Zn. =1: β1 (0<β1≦2):β2 (0<β2≦2) in some cases. In the case where a metal oxide target of In:Ga:Zn=1:3:4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 have In:Ga:Zn. =1: β3 (1≦β3≦5):β4 (2≦β4≦6) in some cases. In the case where a metal oxide target with In:Ga:Zn=1:3:6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 have In:Ga:Zn. =1: β5 (1≦β5≦5): β6 (4≦β6≦8) in some cases.

<1-4. Semiconductor device manufacturing method 1>
Next, an example of a method for manufacturing the transistor 100 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 10A to 12C are cross-sectional views in the channel length (L) direction and the channel width (W) direction each illustrating a method for manufacturing the transistor 100.

First, a conductive film to be the conductive film 106 is formed over the substrate 102, and then the conductive film is processed into an island shape, so that the conductive film 106 is formed. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and the oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the oxide semiconductor film 107 is formed (see FIG. 10A).

The conductive film 106 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a 100-nm-thick tungsten film is formed as the conductive film 106 by a sputtering method.

The insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a PECVD apparatus is used as the insulating film 104 to form a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film.

Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. The oxygen added to the insulating film 104 includes oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, and the like. Further, as an addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Alternatively, after forming a film which suppresses desorption of oxygen over the insulating film, oxygen may be added to the insulating film 104 through the film.

As the above-mentioned film that suppresses desorption of oxygen, a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, the above-mentioned metal element is a component. A material having conductivity such as an alloy, a combination of the above metal elements, a metal nitride containing the above metal elements, a metal oxide containing the above metal elements, and a metal nitride oxide containing the above metal elements. Can be formed by using.

When oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulse laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that the oxide semiconductor film 107 can be processed by forming a mask over the oxide semiconductor film by a lithography process and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-separated oxide semiconductor film 107 may be directly formed by a printing method.

When the oxide semiconductor film is formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as a power supply device for generating plasma as appropriate. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Note that in forming the oxide semiconductor film, for example, when a sputtering method is used, the substrate temperature is 150 °C to 750 °C, or 150 °C to 450 °C, or 200 °C to 350 °C inclusive. It is preferable to form a film because crystallinity can be increased.

Note that in this embodiment, a sputtering apparatus is used as the oxide semiconductor film 107 and an In—Ga—Zn metal oxide (In:Ga:Zn=1:1:1.2 [atomic ratio ]) is used to form an oxide semiconductor film having a thickness of 40 nm.

Further, after the oxide semiconductor film 107 is formed, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate strain point, 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

The heat treatment can be performed in a rare gas such as helium, neon, argon, xenon, or krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, and the like. The processing time may be 3 minutes or more and 24 hours or less.

An electric furnace, an RTA device, or the like can be used for the heat treatment. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The oxide semiconductor film is formed with heating, or after the oxide semiconductor film is formed, heat treatment is performed so that the hydrogen concentration in the oxide semiconductor film obtained by secondary ion mass spectrometry is 5×10 5. ¹⁹ atoms/cm ³ or less, or 1×10 ¹⁹ atoms/cm ³ or less, 5×10 ¹⁸ atoms/cm ³ or less, or 1×10 ¹⁸ atoms/cm ³ or less, or 5×10 ¹⁷ atoms/cm ³ or less, Alternatively, it can be 1×10 ¹⁶ atoms/cm ³ or less.

Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 10B).

As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method. In this case, it is preferable to use a deposition gas containing silicon and an oxidizing gas as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Further, as the insulating film 110_0, a PECVD method in which the oxidizing gas with respect to the deposition gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the treatment chamber is less than 100 Pa or less than 50 Pa is used. Thus, a silicon oxynitride film with a small amount of defects can be formed.

As the insulating film 110_0, a substrate placed in a vacuum-evacuated processing chamber of a PECVD apparatus is held at 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa or higher. Hereinafter, more preferably, 100 Pa or more and 250 Pa or less, and a dense silicon oxide film or a silicon oxynitride film can be formed as the insulating film 110_0 by supplying high-frequency power to the electrode provided in the treatment chamber.

Alternatively, the insulating film 110_0 may be formed by a plasma CVD method using a microwave. Microwave refers to a frequency range of 300 MHz to 300 GHz. In microwave, electron temperature is low and electron energy is small. Further, in the supplied electric power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of a larger number of molecules, and high density plasma (high density plasma) can be excited. .. Therefore, the insulating film 110_0 with less plasma damage to the deposition surface and the deposit can be formed with few defects.

Further, the insulating film 110_0 can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si(OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si(CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane. (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane _{(SiH (OC 2 H 5)} 3), or trisdimethylaminosilane _{(SiH (N (CH 3)} 2) 3) be a silicon-containing compound such as it can. By using the CVD method using an organic silane gas, the insulating film 110_0 with high coverage can be formed.

In this embodiment, as the insulating film 110_0, a PECVD apparatus is used and a 100-nm-thick silicon oxynitride film is formed.

Next, after forming a mask by lithography at a desired position on the insulating film 110_0, part of the insulating film 110_0 and the insulating film 104 is etched, so that an opening 143 reaching the conductive film 106 is formed.

As a method for forming the opening 143, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment mode, the opening 143 is formed by a dry etching method.

Next, the conductive film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that oxygen is added from the conductive film 112_0 to the insulating film 110_0 when the conductive film 112_0 is formed (see FIG. 10C).

As a method for forming the conductive film 112_0, a sputtering method is preferably used, and the conductive film 112_0 is preferably formed in an atmosphere containing oxygen gas. By forming the conductive film 112_0 in an atmosphere containing oxygen gas during formation, oxygen can be favorably added to the insulating film 110_0.

Note that in FIG. 10C, oxygen added to the insulating film 110_0 is schematically represented by an arrow. By forming the conductive film 112_0 so as to cover the opening 143, the conductive film 106 and the conductive film 112_0 are electrically connected to each other. Note that the conductive film 112_0 can be formed using the same material as the above-described oxide semiconductor film 107.

In this embodiment, a sputtering device is used as the conductive film 112_0 and an In—Ga—Zn metal oxide (In:Ga:Zn=4:2:4.1 [atomic ratio]) is used as a sputtering target. Thus, an oxide semiconductor film with a thickness of 100 nm is formed.

Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process (see FIG. 10D).

Next, the conductive film 112_0 and the insulating film 110_0 are processed by etching over the mask 140, and then the mask 140 is removed to remove the island-shaped conductive film 112 and the island-shaped insulating film. And 110 (see FIG. 11A).

In this embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by a dry etching method.

Note that when the conductive film 112 and the insulating film 110 are processed, the thickness of the oxide semiconductor film 107 in a region where the conductive film 112 does not overlap may be thin in some cases. Alternatively, when the conductive film 112 and the insulating film 110 are processed, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 is not overlapped may be thin.

Next, the impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 11B).

As a method for adding the impurity element 145, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. In the case of the plasma treatment method, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing plasma treatment. As a device for generating the plasma, a dry etching device, an ashing device, a plasma CVD device, a high density plasma CVD device, or the like can be used.

Note that, as a source gas of the impurity element 145, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H _2, and a rare gas are used. One or more gases can be used. Alternatively, one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. The impurity element 145 is added to the oxide semiconductor film 107 with one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas. When added to the conductive film 112, one or more of rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 107 and the conductive film 112.

Alternatively, after adding a rare gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ is added. The above may be added to the oxide semiconductor film 107 and the conductive film 112.

Alternatively, one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ is added, and then diluted. Gas may be added to the oxide semiconductor film 107 and the conductive film 112.

The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose amount. For example, when argon is added by the ion implantation method, the acceleration voltage may be 10 kV or more and 100 kV or less, and the dose amount may be 1×10 ¹³ ions/cm ² or more and 1×10 ¹⁶ ions/cm ² or less, for example, 1×. It may be 10 ¹⁴ ions/cm ² . When phosphorus ions are added by an ion implantation method, an acceleration voltage of 30 kV and a dose amount of 1×10 ¹³ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less, for example, 1×10 ¹⁵ ions /Cm ² is sufficient.

Further, although the structure in which the impurity element 145 is added after the mask 140 is removed is described in this embodiment mode, the present invention is not limited to this. For example, the impurity element 145 can be removed with the mask 140 left. You may add.

In addition, in this embodiment, as the impurity element 145, argon is added to the oxide semiconductor film 107 and the conductive film 112 by using a doping apparatus. Note that although a structure in which argon is added as the impurity element 145 is described as an example in this embodiment, the present invention is not limited to this, and the step of adding the impurity element 145 may not be performed, for example.

Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112. Note that by forming the insulating film 116, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. The oxide semiconductor film 107 which is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 which is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 11C).

The insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. In this embodiment, as the insulating film 116, a PECVD apparatus is used to form a 100-nm-thick silicon nitride film.

By using a silicon nitride film as the insulating film 116, hydrogen in the silicon nitride film enters the conductive film 112, the source region 108s, and the drain region 108d which are in contact with the insulating film 116, so that the conductive film 112, the source region 108s, and the drain are formed. The carrier density of the region 108d can be increased.

Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 11D).

The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. In this embodiment, a 300-nm-thick silicon oxynitride film is formed as the insulating film 118 with a PECVD apparatus.

Next, after forming a mask at a desired position of the insulating film 118 by lithography, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141s reaching the source region 108s and the drain region 108d are formed. And an opening 141d that reaches (see FIG. 12A).

As a method for etching the insulating films 118 and 116, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment, the insulating film 118 and the insulating film 116 are processed by a dry etching method.

Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 141s and 141d (see FIG. 12B).

The conductive film 120 can be formed by selecting a material that can be used for the conductive films 120s and 120d. In this embodiment, as the conductive film 120, a stacked film of a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm is formed with a sputtering apparatus.

Next, after forming a mask at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120s and 120d (see FIG. 12C). ..

As a method for processing the conductive film 120, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment mode, the conductive film 120 is processed by a dry etching method to form the conductive films 120s and 120d.

Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

Note that a film (an insulating film, an oxide semiconductor film, a conductive film, or the like) included in the transistor 100 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, an ALD (atom). It can be formed using a layer deposition method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is a MOCVD (metal organic chemical vapor deposition) method.

In the thermal CVD method, the inside of a chamber is set to atmospheric pressure or reduced pressure, a source gas and an oxidizing agent are simultaneously sent into the chamber, and a film is formed by reacting in the vicinity of the substrate or on the substrate and depositing it on the substrate. As described above, the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that defects are not generated due to plasma damage.

In the ALD method, the inside of the chamber is kept at atmospheric pressure or reduced pressure, a source gas for reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the raw material gas. For example, two or more kinds of source gases may be sequentially supplied to the chamber. At that time, an inert gas is introduced and a second source gas is introduced after the reaction of the first source gas so that a plurality of types of source gases are not mixed. Alternatively, instead of introducing the inert gas, the second raw material gas may be introduced after exhausting the first raw material gas by evacuation. The first source gas is adsorbed/reacted on the surface of the substrate to form a first layer, and the second source gas introduced later is adsorbed/reacted, so that the second layer is the first layer. A thin film is formed by laminating on top. By repeating the gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times gas is introduced repeatedly, it is possible to precisely adjust the film thickness, which is suitable for manufacturing a fine FET.

A film such as the conductive film, the insulating film, the oxide semiconductor film, or the metal oxide film described above can be formed by a thermal CVD method such as an MOCVD method. For example, an In-Ga-Zn-O film is formed. in this case, trimethyl indium _{(in (CH 3) 3)} , trimethyl gallium _{(Ga (CH 3) 3)} , and using dimethylzinc _{(Zn (CH 3) 2)} . Not limited to these combinations, triethylgallium (Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn(C ₂ H ₅ ) ₂ ) can be used instead of dimethylzinc. You can also

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH ₃ ) ₂ ] ₄ ) ) Or tetrakis(ethylmethylamide)hafnium or other hafnium amide) is used as a source gas, and ozone (O ₃ ) is used as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH ₃ ) ₃ ) or the like) is used. Two types of gas, H ₂ O, are used as the oxidant. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of an oxidizing gas (O ₂ , nitrous oxide) are supplied to adsorb the hexachlorodisilane. React with things.

For example, when forming a tungsten film by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are formed. And are used to form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case of forming an oxide semiconductor film, for example, an In—Ga—Zn—O film with a film formation apparatus utilizing ALD, an In—O layer is formed using In(CH ₃ ) ₃ gas and O ₃ gas. Is formed, and then a GaO layer is formed by using Ga(CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed by using Zn(CH ₃ ) ₂ gas and O ₃ gas. The order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

<1-5. Semiconductor device manufacturing method 2>
Next, an example of a method for manufacturing the transistor 100C illustrated in FIG. 4 is described with reference to FIGS. Note that FIGS. 13A to 16C are cross-sectional views in the channel length (L) direction and the channel width (W) direction each illustrating a method for manufacturing the transistor 100C.

First, the conductive film 106 is formed over the substrate 102. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and the oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the oxide semiconductor film 107 is formed (see FIG. 13A).

Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 13B).

Next, after forming a mask by lithography at a desired position on the insulating film 110_0, part of the insulating film 110_0 and the insulating film 104 is etched to form an opening 143 reaching the conductive film 106 (FIG. 13(C)).

Next, the conductive film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that oxygen is added from the conductive film 112_0 to the insulating film 110_0 when the conductive film 112_0 is formed (see FIG. 13D).

Note that in FIG. 13D, the oxygen added to the insulating film 110_0 is schematically represented by an arrow. By forming the conductive film 112_0 so as to cover the opening 143, the conductive film 106 and the conductive film 112_0 are electrically connected to each other.

Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process (see FIG. 14A).

Next, the conductive film 112_0 is processed by etching from above the mask 140, so that the island-shaped conductive film 112 is formed (see FIG. 14B).

In this embodiment, the conductive film 112_0 is processed by a wet etching method.

Next, the insulating film 110_0 is processed by etching over the mask 140, so that the island-shaped insulating film 110 is formed (see FIG. 14C).

In this embodiment, the insulating film 110_0 is processed by a dry etching method.

Next, after removing the mask 140, the impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 14D).

Note that when the impurity element 145 is added, many impurities are added to a region where the surface of the oxide semiconductor film 107 is exposed (a region to be the source region 108s and the drain region 108d later). On the other hand, the impurity element 145 is added through the insulating film 110 to a region where the conductive films 112 of the oxide semiconductor film 107 do not overlap and the insulating film 110 overlaps (a region to be a region 108f later). The amount of the impurity element 145 added is smaller than that in the source region 108s and the drain region 108d.

In addition, in this embodiment, as the impurity element 145, argon is added to the oxide semiconductor film 107 and the conductive film 112 by using a doping apparatus.

Note that although a structure in which argon is added as the impurity element 145 is described as an example in this embodiment, the present invention is not limited to this, and the step of adding the impurity element 145 may not be performed, for example. When the step of adding the impurity element 145 is not performed, the region 108f has an impurity concentration equivalent to that of the channel region 108i.

Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, the insulating film 110, and the conductive film 112. Note that by forming the insulating film 116, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. The oxide semiconductor film 107 which is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 which is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 15A).

A region 108f is formed between the channel region 108i and the source region 108s and between the channel region 108i and the drain region 108d.

Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 15B).

Next, after forming a mask at a desired position of the insulating film 118 by lithography, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141s reaching the source region 108s and the drain region 108d are formed. And an opening 141d that reaches (see FIG. 15C).

Next, the insulating film 122 is formed over the insulating film 118 (see FIG. 15D).

Note that the insulating film 122 has a function as a planarization insulating film. In addition, the insulating film 122 has openings 141s and openings at positions overlapping with the openings 141d.

In this embodiment mode, a photosensitive acrylic resin is applied as the insulating film 122 using a spin coater device, and then a desired region of the acrylic resin is exposed to light, whereby the insulating film 122 having an opening portion is formed. To form.

Next, the conductive film 120 is formed over the insulating film 122 so as to cover the openings 141s and 141d (see FIG. 16A).

Next, after forming a mask at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120s and 120d (see FIG. 16B). ..

In this embodiment mode, a dry etching method is used for processing the conductive film 120. Further, when the conductive film 120 is processed, part of the upper portion of the insulating film 122 may be removed.

Through the above steps, the transistor 100C illustrated in FIG. 4 can be manufactured.

Note that at the time of manufacturing the above transistor 100C, the insulating film 104, the oxide semiconductor film 107, the insulating film 110_0, the conductive film 112_0, the impurity element 145, the insulating film 116, the insulating film 118, the openings 141s and 141d, and the conductive film. As 120, <1-4. The semiconductor device can be formed by incorporating the contents described in Manufacturing Method 1>.

Further, although an example of the case where the transistor includes an oxide semiconductor film is described in this embodiment, one embodiment of the present invention is not limited to this. In one embodiment of the present invention, the transistor does not need to have an oxide semiconductor film. As an example, the channel region of the transistor, the vicinity of the channel region, the source region, or the drain region is formed using a material including Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like. You may.

As described above, the structure and the method described in this embodiment can be combined with any of the structures and methods described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a structure and the like of an oxide semiconductor will be described with reference to FIGS.

<2-1. Structure of oxide semiconductor>
Oxide semiconductors are classified into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystal oxide semiconductor), or a pseudo-amorphous oxide semiconductor (a-like oxide OS). : Amorphous-like oxide semiconductor) and an amorphous oxide semiconductor.

From another viewpoint, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, or the like can be given.

Amorphous structure is generally isotropic and does not have a heterogeneous structure, metastable state in which the arrangement of atoms is not fixed, bond angle is flexible, short-range order but long-range order It is said that they do not have

From the opposite point of view, a stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, the a-like OS is not isotropic but has an unstable structure including a void (also referred to as a void). The a-like OS is physically similar to an amorphous oxide semiconductor in that it is unstable.

<2-2. CAAC-OS>
First, the CAAC-OS will be described.

The CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when the CAAC-OS including InGaZnO ₄ crystals classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) is obtained as illustrated in FIG. Shows a peak near 31°. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, in the CAAC-OS, the crystal has c-axis orientation and the c-axis is a plane which forms a film of the CAAC-OS (formation target). It is also confirmed that it is oriented in a direction substantially perpendicular to the upper surface). In addition to the peak near 2θ of 31°, a peak may appear near 2θ of 36°. The peak near 2θ of 36° is due to the crystal structure classified into the space group Fd-3m. Therefore, CAAC-OS preferably does not show the peak.

On the other hand, when a structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to the formation surface, a peak appears at 2θ of around 56°. This peak is assigned to the (110) plane of the InGaZnO ₄ crystal. Then, even if 2θ is fixed at around 56° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. No peak appears. On the other hand, when 2θ is fixed to around 56° and φ scan is performed on single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. 17C. To be done. Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular a-axis and b-axis orientations.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam having a probe diameter of 300 nm is incident on the CAAC-OS including InGaZnO ₄ crystals in parallel to the surface where the CAAC-OS is formed, a diffraction pattern (restricted field) as shown in FIG. Electron diffraction pattern) may appear. This diffraction pattern contains spots due to the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction also shows that the pellets included in the CAAC-OS have c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 17E shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 17E, a ring-shaped diffraction pattern is confirmed. Therefore, even by electron diffraction using an electron beam with a probe diameter of 300 nm, it is found that the a-axis and the b-axis of the pellet included in the CAAC-OS do not have orientation. Note that the first ring in FIG. 17E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. The second ring in FIG. 17E is considered to be derived from the (110) plane and the like.

When a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. You can On the other hand, even in a high-resolution TEM image, a boundary between pellets, that is, a grain boundary (also referred to as a grain boundary) may not be clearly confirmed in some cases. Therefore, it can be said that in the CAAC-OS, electron mobility is less likely to be reduced due to the crystal grain boundaries.

FIG. 18A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. A spherical aberration correction (Spherical Aberration Corrector) function was used for the observation of the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 18A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be called a nanocrystal (nc). Further, the CAAC-OS can be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects unevenness on the surface where the CAAC-OS film is formed or on the upper surface, and is parallel to the surface where the CAAC-OS is formed and the upper surface.

Further, FIGS. 18B and 18C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. 18D and 18E are images obtained by performing image processing on FIG. 18B and FIG. 18C, respectively. The method of image processing will be described below. First, an FFT image is acquired by performing a fast Fourier transform (FFT: Fast Fourier Transform) process of FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT) processing to obtain an image-processed image. The image thus obtained is called an FFT filtered image. The FFT filtered image is an image obtained by extracting the periodic component from the Cs-corrected high resolution TEM image, and shows a lattice arrangement.

In FIG. 18(D), the places where the lattice arrangement is disturbed are indicated by broken lines. The area surrounded by the broken line is one pellet. And the part shown by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 18E, a portion where the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform is indicated by a dotted line, and a change in the orientation of the lattice arrangement is indicated. It is indicated by a broken line. Even in the vicinity of the dotted line, no clear grain boundary can be confirmed. A distorted hexagon can be formed by connecting the surrounding grid points around the grid point near the dotted line. That is, it is understood that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate strain because the bond distance between atoms is not dense in the ab plane direction, the bond distance between atoms is changed by substitution with a metal element, or the like. It is thought to be possible.

As described above, the CAAC-OS has a c-axis orientation and has a strained crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be lowered due to entry of impurities or generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies) from the opposite viewpoint.

Note that the impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor deprives the oxide semiconductor of oxygen, which disturbs the atomic arrangement of the oxide semiconductor and reduces crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or a molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes deterioration of crystallinity.

When the oxide semiconductor has impurities or defects, characteristics thereof may be changed by light, heat, or the like. For example, an impurity contained in the oxide semiconductor may serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor might serve as carrier traps or serve as carrier generation sources by capturing hydrogen.

The CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and a carrier of 1×10 ⁻⁹ /cm ³ or more. A dense oxide semiconductor can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<2-3. nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by the out-of-plane method, no peak showing orientation is observed. That is, the nc-OS crystal has no orientation.

In addition, for example, when an nc-OS including a crystal of InGaZnO ₄ is thinned and an electron beam with a probe diameter of 50 nm is made incident on a region with a thickness of 34 nm in parallel to a formation surface, FIG. A ring-shaped diffraction pattern (nano-beam electron diffraction pattern) as shown is observed. Further, FIG. 19B shows a diffraction pattern (nano-beam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 19B, a plurality of spots are observed in the ring-shaped region. Therefore, in the nc-OS, ordering is not confirmed when an electron beam having a probe diameter of 50 nm is incident, but ordering is confirmed when an electron beam having a probe diameter of 1 nm is incident.

When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon is observed as shown in FIG. There are cases where Therefore, it is found that the nc-OS has a highly ordered region, that is, a crystal in the thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where a regular electron diffraction pattern is not observed.

FIG. 19D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed in a direction substantially parallel to the formation surface. In the high-resolution TEM image, the nc-OS has a region where crystal parts can be confirmed, such as a portion indicated by an auxiliary line, and a region where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm to 10 nm, in particular, a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal portion is greater than 10 nm and 100 nm or less is referred to as a microcrystalline oxide semiconductor in some cases. In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

As described above, the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, in particular, a region of 1 nm to 3 nm). Further, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

In addition, since the crystal orientations between pellets (nanocrystals) do not have regularity, nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than the a-like OS or an amorphous oxide semiconductor. However, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<2-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.

FIG. 20 shows a high-resolution cross-sectional TEM image of a-like OS. Here, FIG. 20A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 20B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) at 4.3×10 ⁸ e ⁻ /nm ² . From FIGS. 20A and 20B, it is found that a stripe-like bright region extending in the vertical direction is observed in the a-like OS from the start of electron irradiation. Also, it is found that the shape of the bright region changes after the electron irradiation. The bright region is presumed to be a void or a low density region.

The a-like OS has an unstable structure because it has a void. In the following, since the a-like OS has a more unstable structure than the CAAC-OS and the nc-OS, a structure change due to electron irradiation is shown.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. All the samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, each sample has a crystal part.

Note that a unit cell of a crystal of InGaZnO ₄ has a structure in which three layers of In—O layers and six layers of Ga—Zn—O layers, nine layers in total, are layered in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, a portion in which the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less is regarded as the InGaZnO ₄ crystal part. Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 21 is an example in which the average size of the crystal parts (22 to 30 points) of each sample was investigated. The length of the above-mentioned lattice fringes is the size of the crystal part. From FIG. 21, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image and the like. From FIG. 21, the crystal part (also referred to as an initial nucleus), which had a size of about 1.2 nm in the initial observation by TEM, had a cumulative irradiation dose of electrons (e ⁻ ) of 4.2×10 ⁸ e ⁻ /nm. ^In No. ² , it can be seen that it has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2×10 ⁸ e ⁻ /nm ^2. I understand. It can be seen from FIG. 21 that the crystal part sizes of the nc-OS and the CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative electron irradiation dose. For electron beam irradiation and TEM observation, a Hitachi Transmission Electron Microscope H-9000NAR was used. The electron beam irradiation conditions were such that the acceleration voltage was 300 kV, the current density was 6.7×10 ⁵ e ⁻ /(nm ² ·s), and the diameter of the irradiation region was 230 nm.

As described above, in the a-like OS, crystal growth may be observed by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, almost no crystal part growth due to electron irradiation is observed. That is, it is found that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. The nc-OS density and the CAAC-OS density are 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a single crystal density of less than 78%.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ^3. .. In addition, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g/cm ³ or more and 6.3 g/cm ³ or more. It is less than cm ³ .

When single crystals having the same composition do not exist, the density corresponding to the single crystal having the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to a ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics. Note that the oxide semiconductor may be, for example, a stacked film including two or more kinds of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

As described above, the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a display device including the transistor described in any of the above embodiments will be described below with reference to FIGS.

<3. Display device configuration example>
FIG. 22 is a cross-sectional view illustrating a partial structural example of a display device of one embodiment of the present invention. The display device illustrated in FIG. 22 includes a transistor 202, a transistor 212, a transistor 221, a light emitting element 204, and a photodiode 206. For the transistor 202, the transistor 212, and the transistor 221, it is preferable to use the transistors illustrated in the above embodiments, and the transistor 212 preferably has a function of exhibiting light including infrared rays.

The transistor 212 includes a conductive film 2025 functioning as a gate electrode provided over the substrate 200 having an insulating surface, a conductive film 2021 functioning as a source electrode, a conductive film 2022 functioning as a drain electrode, an oxide semiconductor film 2020, an oxide. A gate insulating film 2023 provided over the semiconductor film 2020 and a conductive film 2024 functioning as a gate electrode provided over the gate insulating film 2023 are included. Further, as the transistor 202 and the transistor 221, a transistor having a structure similar to that of the transistor 212 can be used. Although an example in which the transistors 202, 212, and 221 are formed using an oxide semiconductor film is shown here, a structure in which these are formed using single crystal silicon, polycrystalline silicon, or amorphous silicon is given. It is also possible to do so. Further, here, an example in which the transistors 202, 212, and 221 are transistors having an s-channel structure is shown; however, these structures may be top-gate transistors, bottom-gate transistors, or the like.

The photodiode 206 may have any structure as long as it is a photodiode that generates a photocurrent when irradiated with infrared light. As the photodiode 206, an element including selenium or a compound containing selenium or an element including silicon (for example, an element in which a pin-type junction or a pn-type junction is formed) can be used. Further, the structure of the photodiode 206 is preferably selected according to the target wavelength. For example, it is preferable to use a photodiode including amorphous silicon to detect a wavelength region of visible light, and to detect a wavelength region including infrared light, single crystal silicon or polycrystalline silicon is used. It is preferable to apply a constructed photodiode.

Note that an insulating film 230 is provided over the transistors 202, 212, and 221. Further, one of a source electrode and a drain electrode included in the transistors 202 and 221 is connected to the conductive film 241 and the conductive film 242 in the opening portion of the insulating film 230. Further, an insulating film 250 is provided over the conductive films 241 and 242.

The light emitting element 204 includes a conductive film 261 connected to the conductive film 241 in the opening of the insulating film 250, a light emitting layer 270 provided on the conductive film 261, and a conductive film 280 provided on the light emitting layer 270. Have. In the photodiode 206, the conductive film 262 connected to the conductive film 242 in the opening of the insulating film 250, the photoelectric conversion layer 290 provided over the conductive film 262, and the conductivity provided over the photoelectric conversion layer 290. And a membrane 280. As described above, in the light emitting element 204 and the photodiode 206 illustrated in FIG. 22, the conductive film 280 may be shared. This makes it possible to easily manufacture the display element and the imaging element.

Note that here, the light-emitting layer 270 can emit white light 2301 (W) due to a current generated between the conductive film 261 and the conductive film 280. Alternatively, it may be light having at least one of the wavelength of light that exhibits red, the wavelength of light that exhibits green, the wavelength of light that exhibits blue, and the wavelength of light that exhibits yellow. For example, as the light-emitting element 204, a light-emitting element including a light-emitting organic material (also referred to as an organic electroluminescence element or an organic EL element) or a light-emitting element including a light-emitting quantum dot can be used. Further, here, the conductive film 280 is formed using a conductive film having a light-transmitting property. Accordingly, the light emitting element 204 can emit light 2301 (W) toward at least the electrode direction where the conductive film 280 is provided. Further, here, a partition 291 is provided at an end portion of the conductive films 261 and 262 and an opening portion of the insulating film 250. The partition wall is a layer made of an organic or inorganic insulator. By providing the partition wall 291, a short circuit of the conductive film 261 or the conductive film 262 and the conductive film 280 can be prevented, and disconnection of the light-emitting layer 270 can be suppressed. Further, here, the light-emitting element 204 is provided so as to overlap with the transistor 202. Accordingly, the area of the light emitting element 204 (aperture ratio of the display device) can be improved.

Further, the display device illustrated in FIG. 22 includes a color filter 300 and a light-transmitting sealing substrate 310. Note that the region where the light-emitting element 204 and the like exist is sealed with the substrate 200 having an insulating surface and the sealing substrate 310. Accordingly, it is possible to prevent moisture from entering the light emitting element 204, the photodiode 206, and the like, and improve the reliability of the display device. Further, the color filter 300 is provided immediately above the region where the light emitting element 204 is provided. The color filter 300 can absorb light in a specific range included in the white light 2301 (W) emitted from the light-emitting element 204 and change the light into chromatic light 2302 (C). is there. Note that here, the chromatic color is at least one of red, green, blue, or yellow.

Further, the color filter 300 is not provided immediately above the transistor 212 and the photodiode 206. Therefore, in the display device illustrated in FIG. 22, light 2201 (IR) having infrared rays emitted from the transistor 212 is applied to an object to be detected 2101 such as a finger or a pen and infrared rays reflected by the object to be detected 2101. By irradiating the photodiode 206 with the light 2202 (IR) having light, it is possible to image the detected object 2101.

Note that the transistor 212 is preferably capable of instantaneously emitting strong light. Therefore, the current drivability of the transistor 212 is preferably higher than the current drivability of the transistors 202 and 212. For example, the (W/L) value of the transistor 212 is preferably larger than the (W/L) values of the transistor 202 and the transistor 221. Here, W represents the channel width and L represents the channel length.

In this way, by performing imaging using invisible light (IR) including light having a wavelength in the infrared region, imaging can be performed without affecting display on the display device. Further, since it is possible to increase the intensity of the invisible light (IR) without considering the influence on the display, it is possible to reduce the influence of external light in the image pickup by the image pickup device and improve the detection accuracy. Becomes Further, since the display device images an object to be detected with light having infrared rays, it is possible to detect an object to be contacted and an object to be contacted with the display device, and the number of objects to be detected is singular. It is possible to detect even a plurality of them.

As described above, the structure and the method described in this embodiment can be combined with any of the structures and methods described in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described in any of the above embodiments will be described below with reference to FIGS.

FIG. 23 is a top view showing an example of a display device. A display device 700 illustrated in FIG. 23 includes a pixel portion 702 provided over a first substrate 701, a source driver 704 and a gate driver 706 provided over the first substrate 701, a pixel portion 702, a source driver 704, And a sealant 712 arranged so as to surround the gate driver 706, and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver 704, and the gate driver 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 23, a display element is provided between the first substrate 701 and the second substrate 705.

In addition, in the display device 700, the pixel portion 702, the source driver 704, the gate driver 706, and the gate driver 706 are electrically connected to a region different from a region surrounded by the sealant 712 on the first substrate 701, respectively. An FPC terminal portion 708 (FPC: Flexible printed circuit) connected to the FPC terminal is provided. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver 704, and the gate driver 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver 704, the gate driver 706, and the FPC terminal portion 708. Various signals supplied by the FPC 716 are given to the pixel portion 702, the source driver 704, the gate driver 706, and the FPC terminal portion 708 through the signal line 710.

Further, the display device 700 may be provided with a plurality of gate drivers 706 and source drivers 704. Further, although the display device 700 shows an example in which the source driver 704 and the gate driver 706 are formed over the same first substrate 701 as the pixel portion 702, the present invention is not limited to this structure. For example, only the gate driver 706 may be formed on the first substrate 701, or only the source driver 704 may be formed on the first substrate 701. In this case, a structure in which a source driver, a gate driver, or the like is formed (eg, a driver circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. The connecting method of the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver 704, and the gate driver 706 included in the display device 700 include a plurality of transistors, and the transistor which is a semiconductor device of one embodiment of the present invention can be applied.

In addition, the display device 700 can include various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element containing an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, etc.), a light emitting transistor element (a transistor that emits light in response to a current), an electron. Emitting element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display (PDP), MEMS (micro electro mechanical system) display (eg, grating light valve (GLV), digital micromirror device) (DMD), digital micro shutter (DMS) element, interferometric modulation (IMOD) element, etc.), piezoelectric ceramic display and the like. Further, the display device 700 may include a sensor, and the sensor preferably has a function of capturing an image of an object to be detected with light having infrared rays.

An example of a display device using an EL element is an EL display. Examples of a display device using an electron-emitting device include a field emission display (FED) or a SED-type flat-panel display (SED: Surface-conduction Electron-emitter Display). As an example of a display device using a liquid crystal element, there is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have a function as a reflective electrode. For example, part or all of the pixel electrode may include aluminum, silver, or the like. Further, in that case, a memory circuit such as SRAM can be provided below the reflective electrode. Thereby, the power consumption can be further reduced.

Note that the display device 700 can use a progressive system, an interlace system, or the like as a display system. Further, the color elements controlled by the pixels when performing color display are not limited to the three colors of RGB (R represents red, G represents green, B represents blue). For example, the pixel for color display may be composed of pixels composed of four color elements of R, G, B, and W (white). Alternatively, like a pen tile array, one pixel may be configured with color elements of two colors of RGB, and other color elements may be added to perform color display. Alternatively, one or more colors of yellow, cyan, magenta, etc. may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device and can be applied to a monochrome display device.

Further, a colored layer (also referred to as a color filter) is used in order to display a display device in full color by using white light emission (W) for a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. For the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be used in appropriate combination. By using the colored layer, color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, by arranging the region having the colored layer and the region not having the colored layer, the white light in the region having no colored layer may be directly used for display. By arranging a region that does not have a coloring layer in part, it is possible to reduce the decrease in luminance due to the coloring layer during bright display, and to reduce power consumption by about 20 to 30% in some cases. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from the elements having the respective emission colors. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) of converting a part of the light emission from the above white light emission into red, green, and blue by passing through a color filter, red, green, and blue light emission May be used (three-color method), or a method of converting a part of light emission from blue light emission to red or green (color conversion method, quantum dot method) may be applied.

In this embodiment mode, a structure using a liquid crystal element and an EL element as a display element will be described with reference to FIGS. Note that FIG. 24 is a cross-sectional view taken along dashed-dotted line QR in FIG. 23 and has a structure in which a liquid crystal element is used as a display element. In addition, FIG. 25 is a cross-sectional view taken along alternate long and short dash line QR shown in FIG. 23, in which an EL element is used as a display element.

First, common parts shown in FIGS. 24 and 25 will be described first, and then different parts will be described below.

<4-1. Description of common parts of display device>
The display device 700 illustrated in FIGS. 23 to 25 includes a lead wiring portion 711, a pixel portion 702, a source driver 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 has a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver 704 includes a transistor 752.

The transistors 750 and 752 have a structure similar to that of the transistor 100 described above. Note that for the structures of the transistor 750 and the transistor 752, any of the other transistors described in the above embodiments may be used.

The transistor used in this embodiment has a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be low. Therefore, the holding time of an electric signal such as an image signal can be extended and the writing interval can be set long in the power-on state. Therefore, the frequency of refresh operations can be reduced, which leads to an effect of suppressing power consumption.

In addition, the transistor used in this embodiment can have relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over one substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, in the pixel portion as well, a high-quality image can be provided by using a transistor which can be driven at high speed.

The capacitor 790 includes a first oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, and conductivity that functions as a source electrode and a drain electrode included in the transistor 750. A film and an upper electrode formed through a step of processing the same conductive film. In addition, a step of forming the same insulating film between the lower electrode and the upper electrode as an insulating film functioning as a second insulating film and a third insulating film included in the transistor 750 is performed. An insulating film is formed after that. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

24 and 25, the planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the planarization insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed of these materials. Alternatively, the planarization insulating film 770 may be omitted.

In addition, the signal line 710 is formed through the same steps as a conductive film functioning as a source electrode and a drain electrode of the transistors 750 and 752. Note that the signal line 710 is formed using a conductive film formed through a step different from that of the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same step as an oxide semiconductor film functioning as a gate electrode. Membranes may be used. When a material containing copper, for example, is used as the signal line 710, signal delay or the like due to wiring resistance is small, and display on a large screen is possible.

Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same steps as a conductive film functioning as a source electrode and a drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, flexible substrates may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

Further, on the second substrate 705 side, a light-shielding film 738 which functions as a black matrix, a coloring film 736 which functions as a color filter, and an insulating film 734 which is in contact with the light-shielding film 738 and the coloring film 736 are provided.

<4-2. Configuration example of display device using liquid crystal element>
The display device 700 illustrated in FIG. 24 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700 illustrated in FIG. 24 can display an image by controlling the transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 by the voltage applied to the conductive films 772 and 774.

The conductive film 772 is connected to a conductive film which functions as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. In addition, the conductive film 772 has a function as a reflective electrode. The display device 700 illustrated in FIG. 24 is a so-called reflective color liquid crystal display device which reflects light by the conductive film 772 using external light and displays the light through the coloring film 736.

As the conductive film 772, a conductive film which transmits visible light or a conductive film which reflects visible light can be used. As the conductive film having a property of transmitting visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which reflects visible light, for example, a material containing aluminum or silver may be used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

In addition, in the display device 700 illustrated in FIG. 24, unevenness is provided in part of the planarization insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing unevenness on the surface of the resin film. Further, the conductive film 772 which functions as a reflective electrode is formed along the unevenness. Therefore, when external light enters the conductive film 772, light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

Note that FIG. 24 illustrates the reflective color liquid crystal display device; however, the display device 700 which is one embodiment of the present invention is not limited to this. For example, the conductive film 772 transmits visible light. A transmission type color liquid crystal display device may be formed by using a certain conductive film. In the case of a transmissive color liquid crystal display device, the unevenness provided in the planarization insulating film 770 may not be provided.

Although not shown in FIG. 24, an alignment film may be provided on each of the conductive films 772 and 774 which is in contact with the liquid crystal layer 776. Although not shown in FIG. 24, an optical member (optical substrate) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

In the case of adopting the horizontal electric field method, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing a chiral agent of several wt% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. Further, since it is not necessary to provide an alignment film, rubbing treatment is not necessary, so that electrostatic damage caused by the rubbing treatment can be prevented and defects and damages of the liquid crystal display device during a manufacturing process can be reduced. .. A liquid crystal material exhibiting a blue phase has a small viewing angle dependence.

In the case of using a liquid crystal element as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially symmetric Micro-Ocillary Ocell) mode, and A Compensated Birefringence mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.

Further, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode, and for example, a MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode and the like can be used.

<4-3. Display device using light emitting element>
The display device 700 illustrated in FIG. 25 includes a light emitting element 782. The light emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 25 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.

The conductive film 784 is connected to a conductive film which functions as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film having a property of transmitting visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which reflects visible light, for example, a material containing aluminum or silver may be used.

In the display device 700 illustrated in FIG. 25, the insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers part of the conductive film 784. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. Although the top emission structure is illustrated in the present embodiment, the present invention is not limited to this. For example, the invention can be applied to a bottom emission structure that emits light to the conductive film 784 side and a dual emission structure that emits light to both the conductive film 784 side and the conductive film 788 side.

A colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver 704. Further, the coloring film 736 and the light shielding film 738 are covered with the insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that, in the display device 700 shown in FIG. 25, the configuration in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by coating separately, the coloring film 736 may be omitted.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 5)
In this embodiment mode, an example of a circuit structure of a semiconductor device in which stored contents can be held even when power is not supplied and the number of times of writing is not limited is described with reference to FIGS.

<5-1. Circuit configuration>
FIG. 26 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 26, the first wiring (1st Line) and one of the source electrode and the drain electrode of the p-type transistor 1280a are electrically connected. Further, the other of the source electrode and the drain electrode of the p-type transistor 1280a and one of the source electrode and the drain electrode of the n-type transistor 1280b are electrically connected. Further, the other of the source electrode and the drain electrode of the n-type transistor 1280b and one of the source electrode and the drain electrode of the n-type transistor 1280c are electrically connected.

In addition, the second wiring (2nd Line) and one of a source electrode and a drain electrode of the transistor 1282 are electrically connected to each other. The other of the source electrode and the drain electrode of the transistor 1282 is electrically connected to one of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c.

The third wiring (3rd Line) and the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b are electrically connected. In addition, the fourth wiring (4th Line) and the gate electrode of the transistor 1282 are electrically connected. In addition, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitor 1281 and the other of the source electrode and the drain electrode of the n-type transistor 1280c. Further, the sixth wiring (6th Line) is electrically connected to the other of the source electrode and the drain electrode of the p-type transistor 1280a and the one of the source electrode and the drain electrode of the n-type transistor 1280b.

Note that the transistor 1282 can be formed using an oxide semiconductor (OS). Therefore, in FIG. 26, the symbol “OS” is added to the transistor 1282. Note that the transistor 1282 may be formed using a material other than an oxide semiconductor.

In addition, in FIG. 26, a floating node (FN) is added to a connection portion between the other of the source electrode and the drain electrode of the transistor 1282, one of the electrodes of the capacitor 1281, and the gate electrode of the n-type transistor 1280c. There is. By turning off the transistor 1282, the potentials given to the floating node, one of the electrodes of the capacitor 1281, and the gate electrode of the n-type transistor 1280c can be held.

In the circuit configuration shown in FIG. 26, by utilizing the characteristic that the potential of the gate electrode of the n-type transistor 1280c can be held, information can be written, held, and read as follows.

<5-2. Writing and retaining information>
First, writing and holding of information will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, so that the transistor 1282 is turned on. Accordingly, the potential of the second wiring is applied to the gate electrode of the n-type transistor 1280c and the capacitor 1281. That is, a predetermined charge is applied to the gate electrode of the n-type transistor 1280c (writing). After that, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, so that the transistor 1282 is turned off. As a result, the charge applied to the gate electrode of the n-type transistor 1280c is retained (retained).

Since the off-state current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is held for a long time.

<5-3. Read information>
Next, reading of information will be described. When the potential of the third wiring is set to the Low level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, when the potential of the third wiring is set to the High level potential, the p-type transistor 1280a is turned off and the n-type transistor 1280b is turned on. At this time, the sixth wiring has a different potential depending on the amount of charge held in the floating node (FN). Therefore, the held information can be read (reading) by observing the potential of the sixth wiring.

Further, the transistor 1282 is an extremely small off-state current because an oxide semiconductor is used for the channel region. The off-state current of the transistor 1282 including an oxide semiconductor is 1/100,000 or less that of a transistor formed using a silicon semiconductor or the like, and thus is accumulated in a floating node (FN) due to leakage current of the transistor 1282. It is possible to ignore the loss of charge. That is, the transistor 1282 including an oxide semiconductor can realize a nonvolatile memory circuit which can hold data without being supplied with power.

Further, by using the semiconductor device having such a circuit structure for a storage device such as a register or a cache memory, data loss in the storage device due to supply stop of power supply voltage can be prevented. Moreover, after the supply of the power supply voltage is restarted, the state before the power supply is stopped can be restored in a short time. Therefore, in the entire memory device or in one or a plurality of logic circuits included in the memory device, power supply can be stopped for a short time in the standby state, so that power consumption can be suppressed. Further, by using the semiconductor device for a sensor, the influence of noise can be reduced and the detection accuracy of the sensor can be improved. The sensor can use light having infrared rays.

As described above, the structure, the method, and the like described in this embodiment can be combined with the structure, the method, and the like described in other embodiments as appropriate.

(Embodiment 6)
In this embodiment, the structure of a pixel circuit that can be used in the semiconductor device of one embodiment of the present invention will be described below with reference to FIG.

<6-1. Pixel circuit configuration>
FIG. 27A is a diagram illustrating a structure of a pixel circuit. The circuit illustrated in FIG. 27A includes a photoelectric conversion element 1360, a transistor 1351, a transistor 1352, a transistor 1353, and a transistor 1354.

The photoelectric conversion element 1360 has an anode electrically connected to the wiring 1316, and a cathode connected to one of a source electrode and a drain electrode of the transistor 1351. The other of the source electrode and the drain electrode of the transistor 1351 is connected to the charge storage portion (FD) and the gate electrode is connected to the wiring 1312 (TX). One of a source electrode and a drain electrode of the transistor 1352 is connected to the wiring 1314 (GND), the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the transistor 1354, and a gate electrode thereof is a charge storage portion (FD). ) Is connected. One of a source electrode and a drain electrode of the transistor 1353 is connected to the charge storage portion (FD), the other of the source electrode and the drain electrode is connected to the wiring 1317, and a gate electrode thereof is connected to the wiring 1311 (RS). The other of the source electrode and the drain electrode of the transistor 1354 is connected to the wiring 1315 (OUT) and the gate electrode is connected to the wiring 1313 (SE). Note that all the above connections are electrical connections.

Note that the wiring 1314 may be supplied with a potential such as GND, VSS, or VDD. Here, the potential and the voltage are relative. Therefore, the magnitude of the GND potential is not necessarily 0 volt.

The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current according to light incident on the pixel circuit. The transistor 1353 has a function of controlling charge accumulation in the charge accumulation portion (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal according to the potential of the charge storage portion (FD). The transistor 1352 has a function of resetting the potential of the charge storage portion (FD). The transistor 1352 has a function of controlling selection of a pixel circuit at the time of reading.

Note that the charge storage portion (FD) is a charge holding node and holds a charge that changes depending on the amount of light received by the photoelectric conversion element 1360.

Note that the transistors 1352 and 1354 may be connected in series between the wiring 1315 and the wiring 1314. Therefore, the wiring 1314, the transistor 1352, the transistor 1354, and the wiring 1315 may be arranged in this order, or the wiring 1314, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) has a function as a signal line for controlling the transistor 1351. The wiring 1313 (SE) functions as a signal line for controlling the transistor 1354. The wiring 1314 (GND) has a function as a signal line for setting a reference potential (eg GND). The wiring 1315 (OUT) functions as a signal line for reading a signal output from the transistor 1352. The wiring 1316 has a function as a signal line for outputting charges from the charge storage portion (FD) through the photoelectric conversion element 1360 and is a low potential line in the circuit in FIG. The wiring 1317 has a function as a signal line for resetting the potential of the charge storage portion (FD) and is a high potential line in the circuit in FIG. 27A.

Next, the structure of each element illustrated in FIG. 27A will be described.

<6-2. Photoelectric conversion element>
As the photoelectric conversion element 1360, an element including selenium or a compound containing selenium (hereinafter referred to as a selenium-based material) or an element including silicon (eg, an element in which a pin-type junction is formed) can be used. Further, it is preferable to combine a transistor including an oxide semiconductor and a photoelectric conversion element including a selenium-based material because reliability can be increased.

<6-3. Transistor>
Although the transistors 1351, 1352, 1353, and 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon, an oxide semiconductor is used. It is preferable to form the transistor used. A transistor in which a channel region is formed using an oxide semiconductor has a characteristic of extremely low off-state current. As the transistor in which the channel region is formed using an oxide semiconductor, the transistor described in Embodiment 1 can be used, for example.

In particular, when the leakage current of the transistor 1351 and the transistor 1353 connected to the charge storage portion (FD) is large, the time when the charge stored in the charge storage portion (FD) can be held becomes insufficient. Therefore, by using a transistor including an oxide semiconductor for at least the two transistors, unnecessary charge can be prevented from flowing out from the charge storage portion (FD).

In addition, in the transistors 1352 and 1354, when leakage current is large, unnecessary charge is output to the wiring 1314 or the wiring 1315; therefore, a transistor in which a channel region is formed using an oxide semiconductor is used as these transistors. It is preferable.

Although the transistor having one gate electrode is illustrated in FIG. 27A, the invention is not limited to this, and the transistor may have a plurality of gate electrodes, for example. As a transistor including a plurality of gate electrodes, for example, a structure including a first gate electrode and a second gate electrode (also referred to as a back gate electrode) which overlap with a semiconductor film in which a channel region is formed may be used. .. As the back gate electrode, for example, the same potential as that of the first gate electrode, floating, or a potential different from that of the first gate electrode may be applied.

<6-4. Timing chart of circuit operation>
Next, an example of operation of the circuit illustrated in FIG. 27A will be described with reference to a timing chart in FIG.

In FIG. 27B, for simplification of explanation, the potential of each wiring is given as a binary changing signal. However, since each potential is an analog signal, it can actually take various values, not limited to two values, depending on the situation. Note that a signal 1401 illustrated in FIG. 27B is a potential of the wiring 1311 (RS), a signal 1402 is a potential of the wiring 1312 (TX), a signal 1403 is a potential of the wiring 1313 (SE), and a signal 1404 is a charge accumulation portion (FD). ), the signal 1405 corresponds to the potential of the wiring 1315 (OUT). Note that the potential of the wiring 1316 is always “Low” and the potential of the wiring 1317 is always “High”.

At Time A, when the potential of the wiring 1311 (signal 1401) is “High” and the potential of the wiring 1312 (signal 1402) is “High”, the potential of the charge accumulation portion (FD) (signal 1404) is the potential of the wiring 1317 ( "High") and the reset operation is started. Note that the potential of the wiring 1315 (the signal 1405) is precharged to “High”.

At Time B, the potential of the wiring 1311 (signal 1401) is set to “Low”, the reset operation is completed, and the accumulation operation is started. Here, since the reverse bias is applied to the photoelectric conversion element 1360, the charge storage portion (FD) (signal 1404) starts to decrease due to the reverse current. In the photoelectric conversion element 1360, the reverse current increases when light is emitted, and thus the decrease rate of the potential (signal 1404) of the charge storage portion (FD) changes depending on the amount of light that is emitted. That is, the channel resistance between the source and the drain of the transistor 1354 changes in accordance with the amount of light with which the photoelectric conversion element 1360 is irradiated.

At time C, the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation ends, and the potential of the charge accumulation portion (FD) (signal 1404) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. That is, it changes according to the amount of light with which the photoelectric conversion element 1360 is irradiated. In addition, since the transistor 1351 and the transistor 1353 each include a transistor in which a channel region is formed using an oxide semiconductor and the off-state current is extremely low, the transistor 1351 and the transistor 1353 have a charge storage portion (FD) until a later selection operation (read operation) is performed. It is possible to keep the potential constant.

Note that when the potential of the wiring 1312 (the signal 1402) is set to “Low”, the potential of the charge storage portion (FD) may be changed due to parasitic capacitance between the wiring 1312 and the charge storage portion (FD). is there. When the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation cannot be accurately acquired. In order to reduce the amount of change in the potential, the gate electrode-source electrode (or gate electrode-drain electrode) capacitance of the transistor 1351 is reduced, the gate capacitance of the transistor 1352 is increased, and the charge is stored in the charge storage portion (FD). Measures such as provision of capacity are effective. Note that in this embodiment, the change in the potential can be ignored by these measures.

At Time D, when the potential of the wiring 1313 (the signal 1403) is set to “High”, the transistor 1354 is turned on and a selection operation is started, and the wiring 1314 and the wiring 1315 are turned on through the transistor 1352 and the transistor 1354. Then, the potential of the wiring 1315 (the signal 1405) decreases. Note that the precharge of the wiring 1315 may be completed before time D. Here, the speed at which the potential of the wiring 1315 (the signal 1405) decreases depends on the current between the source electrode and the drain electrode of the transistor 1352. That is, it changes according to the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation.

At Time E, when the potential of the wiring 1313 (the signal 1403) is set to “Low”, the transistor 1354 is cut off, the selection operation is completed, and the potential of the wiring 1315 (the signal 1405) becomes a constant value. Here, the constant value changes depending on the amount of light with which the photoelectric conversion element 1360 is irradiated. Therefore, by acquiring the potential of the wiring 1315, the amount of light with which the photoelectric conversion element 1360 is irradiated during the accumulation operation can be known.

More specifically, when the light applied to the photoelectric conversion element 1360 is strong, the potential of the charge storage portion (FD), that is, the gate voltage of the transistor 1352 decreases. Therefore, the current flowing between the source electrode and the drain electrode of the transistor 1352 becomes small, and the potential of the wiring 1315 (the signal 1405) slowly decreases. Therefore, a relatively high potential can be read from the wiring 1315.

On the contrary, when the light applied to the photoelectric conversion element 1360 is weak, the potential of the charge storage portion (FD), that is, the gate voltage of the transistor 1352 becomes high. Therefore, a current flowing between the source electrode and the drain electrode of the transistor 1352 is increased and the potential of the wiring 1315 (the signal 1405) is quickly reduced. Therefore, a relatively low potential can be read from the wiring 1315.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<7-1. Display device configuration example>
The display device illustrated in FIG. 28A includes a region including a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion provided outside the pixel portion 502 and including a circuit for driving the pixel (hereinafter referred to as a pixel portion 502). , A drive circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may not be provided.

It is preferable that part or all of the driver circuit portion 504 be formed over the same substrate as the pixel portion 502. As a result, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

The pixel portion 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) Y columns (Y is a natural number of 2 or more). The driving circuit portion 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel ( Hereinafter, a driver circuit such as the source driver 504b) is included.

The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register through the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling potentials of wirings (hereinafter referred to as scan lines GL_1 to GL_X) to which scan signals are given. Note that a plurality of gate drivers 504a may be provided and the scan lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the invention is not limited to this, and the gate driver 504a can supply another signal.

The source driver 504b includes a shift register and the like. The source driver 504b receives a signal for driving the shift register and a signal (image signal) which is a source of the data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on an image signal. Further, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. Further, the source driver 504b has a function of controlling the potential of a wiring to which a data signal is applied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches and the like. The source driver 504b can output a signal obtained by time-sharing an image signal as a data signal by sequentially turning on a plurality of analog switches.

A pulse signal is input to each of the plurality of pixel circuits 501 through one of the plurality of scan lines GL to which a scan signal is supplied, and a data signal is received through one of the plurality of data lines DL to which a data signal is supplied. Is entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data of a data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and the n-th column, a pulse signal is input from the gate driver 504a through the scan line GL_m (m is a natural number less than or equal to X), and the data line DL_n(n Is a natural number less than or equal to Y) and a data signal is input from the source driver 504b.

The protection circuit 506 illustrated in FIG. 28A is connected to the scan line GL which is a wiring between the gate driver 504a and the pixel circuit 501, for example. Alternatively, the protection circuit 506 is connected to the data line DL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit which, when a potential outside a certain range is applied to a wiring to which the protection circuit 506 is connected, brings the wiring and another wiring into a conductive state.

As shown in FIG. 28A, a protection circuit 506 is provided in each of the pixel portion 502 and the driver circuit portion 504, so that the display device has higher resistance to an overcurrent generated by ESD (Electro Static Discharge) or the like. be able to. However, the structure of the protection circuit 506 is not limited to this, and for example, the gate driver 504a may be connected to the protection circuit 506 or the source driver 504b may be connected to the protection circuit 506. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

28A illustrates an example in which the driver circuit portion 504 is formed by the gate driver 504a and the source driver 504b, the invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a separately prepared substrate on which a source driver circuit is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

<7-2. Pixel circuit configuration example>
The plurality of pixel circuits 501 illustrated in FIG. 28A can have the structure illustrated in FIG. 28B, for example.

The pixel circuit 501 illustrated in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in any of the above embodiments can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate in accordance with the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and a FLC (Ferroelectric) mode. , AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may be used. Further, as a driving method of the display device, in addition to the above-described driving method, there are an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Liquid) mode, and a guest mode such as a host. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 550 is electrically connected to the data line DL_n and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. It The gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling writing of data of the data signal.

One of a pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. It Note that the value of the potential of the potential supply line VL is set as appropriate in accordance with the specifications of the pixel circuit 501. The capacitor 560 has a function as a storage capacitor that holds written data.

For example, in the display device including the pixel circuit 501 in FIG. 28R, for example, the pixel driver 501 in each row is sequentially selected by the gate driver 504a illustrated in FIG. Write the data.

The pixel circuit 501 in which the data is written enters a holding state by turning off the transistor 550. An image can be displayed by sequentially performing this for each row.

The plurality of pixel circuits 501 illustrated in FIG. 28A can have the structure illustrated in FIG. 28C, for example.

The pixel circuit 501 illustrated in FIG. 28C includes transistors 552 and 554, a capacitor 562, and a light emitting element 572. The transistor described in any of the above embodiments can be applied to either or both of the transistor 552 and the transistor 554.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is applied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is given (hereinafter referred to as a scan line GL_m).

The transistor 552 has a function of controlling writing of data of the data signal.

One of a pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. To be done.

The capacitor 562 has a function as a storage capacitor which holds written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.

In the display device including the pixel circuit 501 in FIG. 28C, for example, the pixel driver 501 in each row is sequentially selected by the gate driver 504a illustrated in FIG. 28A, the transistor 552 is turned on, and data of a data signal is output. Write.

The pixel circuit 501 to which data has been written is brought into a holding state by turning off the transistor 552. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with a luminance corresponding to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 8)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<8-1. Display module>
A display module 8000 shown in FIG. 29 includes a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, a printed board 8010, a battery between an upper cover 8001 and a lower cover 8002. 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a touch panel of a resistance film type or a capacitance type can be used by being superimposed on the display panel 8006. Alternatively, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. Further, an optical sensor can be provided in each pixel of the display panel 8006 to form an optical touch panel. The optical touch panel preferably uses light having infrared rays. Since the optical touch panel can detect an object to be detected by light, the object to be detected and the touch panel do not have to be in contact with each other.

The backlight 8007 has a light source 8008. Note that although FIG. 29 illustrates the structure in which the light source 8008 is provided over the backlight 8007, the invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusion plate may be used. Note that in the case of using a self-luminous light emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may be omitted.

The frame 8009 has a function of protecting the display panel 8006 and a function of an electromagnetic shield for blocking an electromagnetic wave generated by the operation of the printed circuit board 8010. The frame 8009 may also have a function as a heat dissipation plate.

The printed circuit board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply by a battery 8011 provided separately. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate and a prism sheet.

<8-2. Electronics>
30A to 30G are diagrams illustrating electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, Rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays ), a microphone 9008, etc.

The electronic devices illustrated in FIGS. 30A to 30G can have various functions. For example, a function of displaying various information (still image, moving image, text image, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), Wireless communication function, function of connecting to various computer networks using wireless communication function, function of transmitting or receiving various data using wireless communication function, reading and displaying program or data recorded in recording medium It can have a function of displaying on a part, and the like. Note that the functions of the electronic devices in FIGS. 30A to 30G are not limited to these and can have various functions. Although not shown in FIGS. 30A to 30H, the electronic device may have a plurality of display portions. Further, a camera or the like is provided in the electronic device, a function of shooting a still image, a function of shooting a moving image, a function of saving a captured image in a recording medium (external or built in the camera), a captured image displayed on a display portion. It may have a function to do, and the like.

Details of the electronic devices illustrated in FIGS. 30A to 30G are described below.

FIG. 30A is a perspective view showing the television device 9100. The television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with 50 inches or more, or 100 inches or more.

FIG. 30B is a perspective view showing the portable information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker, a connection terminal, a sensor, and the like. Further, the mobile information terminal 9101 can display characters and image information on its plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display portion 9001. Note that, as an example of the information 9051, a display for notifying an incoming call such as an email or SNS (social networking service) or a telephone, a title of the email or the SNS, a sender name of the email or the SNS, a date and time, a time , Battery level, antenna reception strength, etc. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

As a material of the casing 9000, a material containing an alloy, plastic, ceramics, or carbon fiber can be used. As a material containing carbon fiber, carbon fiber reinforced resin composite material (Carbon Fiber Reinforced Plastics: CFRP) is lightweight and has the advantage of not corroding, but it is black, and its appearance and design are limited. Further, CFRP can be said to be a kind of reinforced plastic, and the reinforced plastic may use glass fiber or KFRP using Kevlar. The alloy is preferable because the fiber may be separated from the resin when subjected to a strong impact as compared with the alloy. Examples of the alloy include an aluminum alloy and a magnesium alloy. Among them, an amorphous alloy containing zirconium, copper, nickel, and titanium (also referred to as metallic glass) is excellent in elastic strength. This amorphous alloy is an amorphous alloy that has a glass transition region at room temperature, is also called a bulk solidified amorphous alloy, and is an alloy that has a substantially amorphous atomic structure. By the solidification casting method, the alloy material is cast into the mold of at least one housing and solidified to form a part of the housing with the bulk solidified amorphous alloy. The amorphous alloy may contain beryllium, silicon, niobium, boron, gallium, molybdenum, tungsten, manganese, iron, cobalt, yttrium, vanadium, phosphorus, carbon, etc. in addition to zirconium, copper, nickel, and titanium. The amorphous alloy is not limited to the solidification casting method, and may be formed by a vacuum vapor deposition method, a sputtering method, an electrolytic plating method, an electroless plating method, or the like. Further, the amorphous alloy may contain microcrystals or nanocrystals as long as it maintains a state of not having long-range order (periodic structure) as a whole. Note that the alloy includes both a complete solid solution alloy having a single solid phase structure and a partial solution having two or more phases. By using an amorphous alloy for the housing 9000, a housing having high elasticity can be realized. Therefore, even if the portable information terminal 9101 is dropped, if the housing 9000 is an amorphous alloy, it will return to the original state even if it is temporarily deformed at the moment when a shock is applied. Impact resistance can be improved.

FIG. 30C is a perspective view showing the portable information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example in which the information 9052, the information 9053, and the information 9054 are displayed on different surfaces is shown. For example, the user of the mobile information terminal 9102 can confirm the display (here, information 9053) in a state where the mobile information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position that can be observed from above the portable information terminal 9102. The user can confirm the display and determine whether to receive the call without removing the portable information terminal 9102 from the pocket.

FIG. 30D is a perspective view showing a wristwatch type portable information terminal 9200. The mobile information terminal 9200 can execute various applications such as mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and display can be performed along the curved display surface. The mobile information terminal 9200 is also capable of performing near field communication that is a communication standard. For example, by communicating with a headset capable of wireless communication, a hands-free call can be made. The mobile information terminal 9200 has a connection terminal 9006 and can directly exchange data with another information terminal through a connector. Further, charging can be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

The wristwatch-type portable information terminal 9200 may have a function of detecting a pulse. By detecting the pulsation with the wristwatch type portable information terminal 9200, the pulse can be measured constantly or regularly, which is preferable for health management. Infrared rays are preferably used for detecting the pulse, and the semiconductor element of one embodiment of the present invention is preferable.

31A and 31B are diagrams illustrating the arrangement of the light emitting element and the light receiving element in the terminal having a function of detecting infrared rays. A terminal 9501 having a function of detecting infrared rays illustrated in FIG. 31A includes a light-receiving element and a plurality of light-emitting elements arranged over a substrate. The light receiving element 9601 has a function of detecting infrared rays, and the light emitting elements 9602, 9603, and 9604 have a function of presenting infrared rays.

In the terminal 9501, infrared rays emitted from the light-emitting elements 9602 to 9604 are applied to the detection target object, and the reflected infrared ray is detected by the light-receiving element 9601, whereby the detection target object can be detected. The position and the like of the detection target can be detected based on the magnitude of the reflected light from the detection target with respect to the light from the light emitting element.

Further, when the terminal 9501 includes the display portion 9001 as a display device, the light-emitting elements 9602 to 9604 which emit infrared light and the light-receiving element 9601 which detects infrared light are the same as the display portion 9001 of the display device as in FIG. 32A, it may be arranged on a surface different from the display portion 9001 of the display device, as shown in FIG. 32A, and a lower portion of the display portion 9001 of the display device, as shown in FIG. It may be there.

Note that as in the terminal 9502 illustrated in FIG. 31B, the light-receiving element 9601 and the light-emitting elements 9602 to 9605 may be arranged. Further, each of the light receiving element and the light emitting element may be singular or plural.

Biological information such as a pulse can be detected by the terminal having the light emitting element and the light receiving element as described above. Note that the terminal illustrated in FIG. 31 is not limited to a terminal that detects a pulse as long as it has a light emitting element that emits infrared light and a light receiving element that detects infrared light.

Further, the semiconductor device of one embodiment of the present invention is suitable for an electronic device having a function of detecting biological information such as a vein, a pupil, or an iris. In sensing the human body, it is preferable to use light in the near-infrared wavelength region, which is a so-called biological window. Light in the wavelength region has a small absorption in water and is only slightly absorbed by hemoglobin, and thus can be suitably used for detecting biological information, particularly for detecting a blood state. With the use of the semiconductor device of one embodiment of the present invention, the above biometric information can be detected with high precision, so that the accuracy of biometric authentication can be improved.

30E, 30F, and 30G are perspective views each showing a portable information terminal 9201 which can be folded. 30E is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. 30F is a state in which the mobile information terminal 9201 is in an unfolded state or a folded state in the middle of changing from one to the other. 30G is a perspective view of the mobile information terminal 9201 in a folded state. The portable information terminal 9201 is excellent in portability in a folded state, and is excellent in displayability in a folded state due to a wide display area without a seam. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm to 150 mm.

The electronic devices described in this embodiment each include a display portion for displaying some information. However, the semiconductor device of one embodiment of the present invention can be applied to an electronic device without a display portion.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this example, a transistor of one embodiment of the present invention was manufactured, the electrical characteristics of the transistor were measured, and the light emitting state was observed.

The method for manufacturing the sample used in this example is described below. Note that in this example, the semiconductor element 1 was manufactured as a transistor corresponding to the transistor 100 shown in FIGS. 1A, 1B, and 1C. Note that in the following description, structures having the same functions as the structures of the transistor 100 illustrated in FIGS. 1A, 1B, and 1C are described using the same reference numerals. For comparison, a transistor having a structure shown in FIGS. 33A, 33B, and 33C was manufactured as a comparative semiconductor element 1.
<Production of semiconductor element 1>

A conductive film 106 functioning as a first gate electrode was formed over the substrate 102 which was a glass substrate. As the conductive film 106, a 100-nm-thick tungsten film was formed with a sputtering apparatus.

Next, the insulating film 104 functioning as a first gate insulating film was formed over the substrate 102 and the conductive film 106. Note that in this embodiment, as the insulating film 104, the insulating film 104_1, the insulating film 104_2, the insulating film 104_3, and the insulating film 104_4 are sequentially formed in vacuum by using a PECVD apparatus. Note that the insulating film 104_1 was a silicon nitride film with a thickness of 50 nm. The insulating film 104_2 is a silicon nitride film with a thickness of 300 nm. The insulating film 104_3 is a silicon nitride film with a thickness of 50 nm. The insulating film 104_4 is a silicon oxynitride film with a thickness of 50 nm.

Next, an oxide semiconductor film was formed over the insulating film 104, and the oxide semiconductor film was processed into an island shape, so that the oxide semiconductor film 108 was formed. As the oxide semiconductor film 108, an oxide semiconductor film having a thickness of 40 nm was formed. Note that a sputtering device was used for forming the oxide semiconductor film 108. A metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was used for the sputtering device, and an AC power supply was used as a power supply for applying a bias voltage to the sputtering target. A wet etching method was used for processing the oxide semiconductor film 108.

Next, an insulating film to be the insulating film 110 later was formed over the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a 20-nm-thick silicon oxynitride film and a 80-nm-thick silicon oxynitride film were successively formed in a vacuum using a PECVD apparatus.

Next, heat treatment was performed. The heat treatment was performed at 350° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

Next, an oxide semiconductor film was formed over the insulating film, and the oxide semiconductor film was processed into an island shape, so that the conductive film 112 functioning as a second gate electrode was formed. As the conductive film 112, a sputtering apparatus is used, and a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] is used as a sputtering target and applied to the sputtering target so that the thickness is 100 nm. An AC power source was used as the power source for the operation. After the conductive film 112 is formed, the insulating film in contact with the lower side of the conductive film 112 is processed, so that the insulating film 110 functioning as a second gate insulating film is formed.

The conductive film 112 was processed by a wet etching method, and the insulating film 110 was processed by a dry etching method.

Next, an impurity element was added over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. A doping apparatus was used for the impurity element addition treatment, and argon was used as the impurity element.

Next, the insulating film 116 was formed over the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus.

Next, the insulating film 118 was formed over the insulating film 116. As the insulating film 118, a 300-nm-thick silicon oxynitride film was formed with a PECVD apparatus.

Next, a mask was formed over the insulating film 118, and the openings 141s and 141d were formed in the insulating films 116 and 118 using the mask. A dry etching apparatus was used to process the openings 141s and 141d.

Next, a conductive film is formed over the insulating film 118 so as to fill the openings 141s and 141d, and the conductive film is processed into an island shape, so that the conductive film 120s and the conductive film functioning as a source electrode and a drain electrode are formed. The film 120d was formed.

As the conductive films 120s and 120d, a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, a titanium film with a thickness of 100 nm, and a titanium film were sequentially formed in a vacuum using a sputtering apparatus.

Through the above steps, the semiconductor element 1 which is a transistor corresponding to the transistor 100 illustrated in FIGS. 1A to 1C is manufactured.

The channel width W of the semiconductor element 1 was 50 μm and 100 μm, and the channel width L was 6 μm.

<Production of Comparative Semiconductor Element 1>
A conductive film 106 functioning as a first gate electrode was formed over the substrate 102 which was a glass substrate. As the conductive film 106, a 100-nm-thick tungsten film was formed with a sputtering apparatus.

Next, insulating films 104 and 103 functioning as first gate insulating films were formed over the substrate 102 and the conductive film 106. As the insulating film 104, a 400-nm-thick silicon nitride film was formed with a PECVD apparatus. As the insulating film 103, a 50-nm-thick silicon oxynitride film was formed with a PECVD apparatus.

Next, an oxide semiconductor film was formed over the insulating film 103, and the oxide semiconductor film was processed into an island shape, so that the oxide semiconductor film 108 was formed. As the oxide semiconductor film 108, an oxide semiconductor film having a thickness of 25 nm was formed. Note that as the oxide semiconductor film 108, a sputtering apparatus is used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] is used as a sputtering target, and a power source is applied to the sputtering target. Used an AC power supply.

Next, a conductive film is formed over the insulating film 103 and the oxide semiconductor film 108, a resist mask is formed over the conductive film, and a desired region is etched, so that the conductive film functions as a source electrode and a drain electrode. 120s and the conductive film 120d were formed. As the conductive films 120s and 120d, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film were successively formed in a vacuum using a sputtering apparatus. Note that the resist mask was removed after the conductive films 120s and 120d were formed.

Next, a phosphoric acid aqueous solution (an aqueous solution having a phosphoric acid concentration of 85% and further diluted 100 times with pure water) is applied on the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. Then, part of the surface of the oxide semiconductor film 108 exposed from the conductive films 120s and 120d is removed.

Next, the insulating film 114 and the insulating film 116 which function as a second gate insulating film were formed over the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. As the insulating film 114, a 50-nm-thick silicon oxynitride film was formed with a PECVD apparatus. As the insulating film 116, a 400-nm-thick silicon oxynitride film was formed with a PECVD apparatus. Note that the insulating film 114 and the insulating film 116 were continuously formed in a vacuum by a PECVD apparatus.

Next, the 1st heat processing was performed. The first heat treatment was performed at 350° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide semiconductor film was formed over the insulating film 116, and the oxide semiconductor film was processed into an island shape, so that the conductive film 112 functioning as a second gate electrode was formed. As the conductive film 112, an oxide semiconductor film having a thickness of 100 nm was formed with a sputtering apparatus.

Next, the insulating film 118 was formed over the insulating film 116 and the conductive film 112. As the insulating film 118, a 100-nm-thick silicon nitride film was formed with a PECVD apparatus.

Next, a second heat treatment was performed. The second heat treatment is similar to the first heat treatment.

Through the above steps, the comparative semiconductor element 1 corresponding to the transistors shown in FIGS. 33A, 33B, and 33C was manufactured.

As the comparative semiconductor device 1, the channel width W was 100 μm and the channel width L was 6 μm.

<Measurement of electrical characteristics>
34A and 34B show drain current-gate voltage (Id-Vg) characteristic results of the semiconductor device 1.

34A shows the characteristics of the semiconductor element 1 with W/L=50 μm/6 μm, and FIG. 34B shows the characteristics of the semiconductor element 1 with W/L=100 μm/6 μm. In addition, in FIGS. 34A and 34B, a field indicated by a solid line indicates Id(A) corresponding to the first vertical axis, and a curve indicated by a dotted line indicates a field effect mobility (μFE(cm) corresponding to the second vertical axis. ² /Vs)) respectively. The horizontal axis is Vg (V).

Note that the measurement conditions of the Id-Vg characteristics of the transistor include a voltage applied to the conductive film 106 functioning as a first gate electrode of the transistor (hereinafter also referred to as a gate voltage (Vg)) and a second gate electrode. The voltage applied to the functional conductive film 112 (hereinafter, also referred to as Vbg) was changed from -15V to +20V in steps of 0.25V. Further, the voltage applied to the conductive film 120s functioning as a source electrode (hereinafter, also referred to as source voltage (Vs)) is set to 0 V (comm), and the voltage applied to the conductive film 120d functioning as a drain electrode (hereinafter, drain voltage ( Vd)) was set to 1V or 20V.

As shown in FIGS. 34A and 34B, the transistor manufactured in this example is shown to have favorable electrical characteristics without being caused by the length of the channel length (L).

<Observation of light emission state>
Next, the light emitting states of the above-produced semiconductor device 1 having W/L=50 μm/6 μm, semiconductor device 1 having W/L=100 μm/6 μm, and comparative semiconductor device 1 having W/L=100 μm/6 μm were observed. went. The observation results of the light emitting state are shown in FIGS. 35 and 36.

Here, Vg and Vbg were set to 20V and Vd was set to 20V in order to make each semiconductor element emit light. In addition, a cooled CCD camera having a quantum efficiency of 65% or more at 400 nm or more and 750 nm or less is used for observation of light emission in the visible light region, and 65% or more of 900 nm or more and 1550 nm or less for observation of light emission in the near infrared region. An InGaAs camera (C8250-31 manufactured by Hamamatsu Photonics KK) having quantum efficiency was used.

Note that FIG. 35A shows an observation result of light emission in the visible light region of the semiconductor element 1 with W/L=100 μm/6 μm, and FIG. 35B shows that of the semiconductor element 1 with W/L=100 μm/6 μm. The observation result of light emission in the near infrared region is shown in FIG. 36A, and the observation result of light emission in the near infrared region of the semiconductor element 1 with W/L=50 μm/6 μm is shown in FIG. 36B. The observation results of the emission in the near infrared region of the comparative semiconductor element 1 of /6 μm are shown respectively.

As shown in FIG. 36A, light emission in the near-infrared region was observed from the semiconductor element 1 with W/L=50 μm/6 μm. In addition, as shown in FIG. 35B, strong light emission in the near infrared region was observed from the semiconductor element 1 with W/L=100 μm/6 μm. Therefore, it is preferable that the channel width W is larger because the light emission in the near infrared region can be strongly exhibited. In addition, as shown in FIG. 35A, almost no light emission in the visible light region was observed from the semiconductor element 1 with W/L=100 μm/6 μm. That is, the semiconductor element 1 which is a transistor of one embodiment of the present invention preferably has a function of selectively emitting light in an infrared region.

On the other hand, as shown in FIG. 36(B), almost no light emission in the near infrared region was observed from the comparative semiconductor device 1 with W/L=100 μm/6 μm. In the semiconductor element 1 of one embodiment of the present invention, the region where the oxide semiconductor film 108 and the conductive films 120s and 120d are in contact is separated from the channel region as compared with the comparative semiconductor element 1. Therefore, heat or infrared energy generated in the channel region does not easily move to the conductive films 120s and 120d, and light emission in the infrared region can be effectively exhibited.

As described above, according to one embodiment of the present invention, a transistor having a function of exhibiting light emission in a near infrared region can be manufactured.

As described above, the structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

100 transistor 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 100F transistor 100G transistor 102 substrate 103 insulating film 104 insulating film 104_1 insulating film 104_2 insulating film 104_3 insulating film 104_4 insulating film 106 conductive film 107 oxide semiconductor film 108 oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d Drain region 108f Region 108i Channel region 108s Source region 110 Insulating film 110_0 Insulating film 112 Conductive film 112_0 Conductive film 114 Insulating film 116 Insulating film 118 Insulating film 120 Conductive film 120d Conductive film 120s Conductive film 122 Insulating film 140 Mask 141d Opening part 141s Opening part 143 Opening part 145 Impurity element 147 Hollow region 200 Substrate 202 Transistor 204 Light emitting element 206 Photodiode 212 Transistor 221 Transistor 230 Insulating film 241 Conductive film 242 Conductive film 250 Insulating film Film 261 Conductive film 262 Conductive film 270 Light emitting layer 280 Conductive film 290 Photoelectric conversion layer 291 Partition wall 300 Color filter 310 Encapsulating substrate 501 Pixel circuit 502 Pixel portion 504 Drive circuit portion 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 transistor 554 transistor 560 capacitor element 562 capacitor element 570 liquid crystal element 572 light emitting element 700 display device 701 substrate 702 pixel portion 704 source driver 705 substrate 706 gate driver 708 FPC terminal portion 710 signal line 711 wiring portion 712 sealing material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Coloring film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light emitting element 784 conductive film 786 EL layer 788 conductive film 790 capacitance element 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 capacitance element 1282 transistor 1311 wiring 1312 wiring 1313 wiring 1314 wiring 1315 wiring 1316 wiring 1317 wiring 1351 transistor 1352 transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 1404 Signal 1405 Signal 2020 Oxide semiconductor film 2021 Conductive film 2022 Conductive film 2023 Gate insulating film 2024 Conductive film 2025 Conductive film 2101 Detected object 2201 light 2202 light 2301 light 2302 light 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Housing 9001 Display 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television device 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal 9501 terminal 9502 terminal 9601 light receiving element 9602 light emitting element 9603 light emitting element 9604 light emitting element 9605 light emitting element

Claims (12)

A semiconductor device having a transistor,
The transistor is
A first gate electrode,
A first insulating film on the first gate electrode,
An oxide semiconductor film having a region overlapping with the first gate electrode with the first insulating film interposed therebetween;
A second insulating film on the oxide semiconductor film;
A second gate electrode having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween;
A third insulating film on the oxide semiconductor film and on the second gate electrode,
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film.
The channel region has a region that emits light,
The emission including semiconductors devices near-infrared light. A semiconductor device having a transistor,
The transistor is
A first gate electrode,
A first insulating film on the first gate electrode,
An oxide semiconductor film having a region overlapping with the first gate electrode with the first insulating film interposed therebetween;
A second insulating film on the oxide semiconductor film;
A second gate electrode having a region overlapping with the oxide semiconductor film with the second insulating film interposed therebetween;
A third insulating film on the oxide semiconductor film and on the second gate electrode,
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film.
The channel region has a function of emitting light,
The emission including semiconductors device light in a wavelength range of not less than 900 nm 1550 nm. In claim 1 or claim 2,
The transistor further comprises
A source electrode electrically connected to the oxide semiconductor film in the source region through a first opening provided in the third insulating film;
The third through the second opening provided in the insulating film, semi-conductor devices that have a, a drain electrode electrically connected to the oxide semiconductor film in said drain region. In claim 1 or claim 2,
The oxide semiconductor film includes a In, and Zn, M (M is Al, Ga, Y or Sn,) and, that have a semi-conductor device. In claim 4,
The oxide semiconductor film, the content of the In is, semi-conductor devices that have a region is at least the amount of the M. In claim 4,
The second gate electrode includes a In, and Zn, M (M is Al, Ga, Y or Sn,) and, that have a semi-conductor device. In claim 6,
The second gate electrode, the content of the In is, semi-conductor devices that have a region is at least the amount of the M. In claim 6,
The second gate electrode, the oxide semiconductor film semiconductors device carrier density is not higher than. In claim 1 or claim 2,
The third insulating film, semi-conductor devices that have a least one of nitrogen and hydrogen. In claim 1 or claim 2,
The oxide semiconductor film has a crystal part,
The crystal part is semi-conductor devices that have a c-axis orientation. A semiconductor device according to claim 1 or 2,
Display device having a display element. A semiconductor device according to claim 1 or 2,
Child equipment power that Yusuke and the sensor.

Images