JP6942845B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device having an oxide semiconductor film and an electronic device having the semiconductor device.

One aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, methods for driving them, or , Their manufacturing methods, can be given as an example.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. An image pickup device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, etc.), and an electronic device may have a semiconductor device.

Attention is being paid to a technique for constructing a transistor (also referred to as a thin film transistor (TFT) or a field effect transistor (FET)) using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image devices (display devices). Semiconductor materials typified by silicon are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a transistor using an In-Ga-Zn-based oxide as an oxide semiconductor is disclosed (see Patent Document 1). Further, a technique for producing an oxide thin film transistor having a self-aligned top gate structure is disclosed (see Patent Document 2).

Further, in recent years, technological development of a display device having a function of inputting information has been promoted, and Patent Document 3 discloses an optical touch panel that reads input data by detecting infrared rays.

Further, electronic devices having a function of detecting biological information such as a pulse, a vein, and a pupil have been attracting attention, and a biological sensor using infrared rays has been developed (Patent Document 4).

JP-A-2007-96055 Japanese Unexamined Patent Publication No. 2009-278115 Japanese Unexamined Patent Publication No. 2012-22674 Japanese Unexamined Patent Publication No. 5-329116

In an optical touch panel having a light emitting diode (LED) that emits infrared rays, a sensor that detects infrared rays is provided on the display surface side of the display device, and an LED that exhibits infrared rays is provided as a backlight. The position of the sensor that detects infrared rays is far away. Therefore, the light in the detection environment and the light in the display device become noise, and the infrared detection accuracy is lowered.

Further, when an LED is used as a light emitting element that irradiates infrared rays in an electronic device that reads biological information or the like, the LED can irradiate infrared rays in a wide range, but it is difficult to irradiate a minute region with infrared rays. .. Therefore, it is difficult to improve the detection accuracy and the detection definition only by increasing the definition of the sensor that detects infrared rays in order to detect minute information.

In view of the above problems, one of the problems in one aspect of the present invention is to provide a semiconductor device having a transistor exhibiting infrared rays. Alternatively, one aspect of the present invention is to provide a semiconductor device that exhibits high-definition infrared rays. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of detecting infrared rays with high accuracy. Alternatively, one aspect of the present invention is to provide a display device capable of detecting infrared rays with high accuracy. Alternatively, one aspect of the present invention is to provide an electronic device capable of detecting infrared rays with high accuracy. Alternatively, one aspect of the present invention is to provide a novel semiconductor device. Alternatively, one aspect of the present invention is to provide a method for manufacturing a novel semiconductor device.

The description of the above-mentioned problem does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily have to solve all of these problems. Issues other than the above are self-evident from the description of the specification and the like, and it is possible to extract problems other than the above from the description of the specification and the like.

One aspect of the present invention is a semiconductor device having an oxide semiconductor film capable of efficiently exhibiting infrared rays. Alternatively, it is a semiconductor device having an oxide semiconductor film capable of exhibiting infrared rays with high definition.

Therefore, one aspect of the present invention is a semiconductor device having a transistor, and the transistor passes through a first gate electrode, a first insulating film on the first gate electrode, and a first insulating film. A second having an oxide semiconductor film having a region overlapping with the first gate electrode, a second insulating film on the oxide semiconductor film, and a region overlapping with the oxide semiconductor film via the second insulating film. The gate electrode has a third insulating film on the oxide semiconductor film and the second gate electrode, and the oxide semiconductor film has a channel region in contact with the second insulating film and a third insulation. A semiconductor device having a source region in contact with a film and a drain region in contact with a third insulating film, a channel region having a region exhibiting light emission, and emitting light including near-infrared light.

Further, another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor has a first gate electrode, a first insulating film on the first gate electrode, and a first insulating film. An oxide semiconductor film having a region that overlaps with the first gate electrode via the first gate electrode, a second insulating film on the oxide semiconductor film, and a region that overlaps with the oxide semiconductor film via the second insulating film. It has a second gate electrode having a second gate electrode and a third insulating film on the oxide semiconductor film and the second gate electrode, and the oxide semiconductor film has a channel region in contact with the second insulating film and a second. It has a source region in contact with the insulating film of No. 3 and a drain region in contact with the third insulating film, and the channel region has a function of exhibiting light emission, and the light emission emits light in a wavelength region of 900 nm or more and 1550 nm or less. Including, it is a semiconductor device.

Further, in each of the above configurations, the transistor further includes a source electrode that is electrically connected to the oxide semiconductor film in the source region through a first opening provided in the third insulating film, and a third. It is a semiconductor device having a drain electrode that is electrically connected to an oxide semiconductor film in a drain region through a second opening provided in the insulating film.

Further, in each of the above configurations, the oxide semiconductor film preferably contains In, Zn, and M (M is Al, Ga, Y, or Sn). Further, the oxide semiconductor film preferably has a region in which the In content is equal to or higher than the M content. Further, it is preferable that the oxide semiconductor film has a crystal portion, and the crystal portion has a c-axis orientation.

Further, in each of the above configurations, it is preferable that the second gate electrode has In, Zn, and M (M is Al, Ga, Y, or Sn). Further, it is preferable that the second gate electrode has a region in which the In content is equal to or higher than the M content. Further, it is preferable that the second gate electrode has a higher carrier density than the oxide semiconductor film.

Further, in each of the above configurations, the third insulating film preferably has at least one of nitrogen and hydrogen.

Further, another aspect of the present invention is a display device having the semiconductor device and the display element of each of the above aspects. Further, another aspect of the present invention is an electronic device having the semiconductor device and the sensor of the above aspect.

According to one aspect of the present invention, it is possible to provide a semiconductor device having a transistor exhibiting infrared rays. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device that exhibits infrared rays with high definition. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of detecting infrared rays with high accuracy. Alternatively, according to one aspect of the present invention, it is possible to provide a display device capable of detecting infrared rays with high accuracy. Alternatively, according to one aspect of the present invention, it is possible to provide an electronic device capable of detecting infrared rays with high accuracy. Alternatively, one aspect of the present invention can provide a novel semiconductor device. Alternatively, one aspect of the present invention can provide a method for manufacturing a novel semiconductor device.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

The figure explaining the upper surface and the cross section of a semiconductor device. The figure explaining the upper surface and the cross section of a semiconductor device. The figure explaining the upper surface and the cross section of a semiconductor device. The figure explaining the cross section of a semiconductor device. The figure explaining the cross section of a semiconductor device. The figure explaining the cross section of a semiconductor device. The figure explaining the cross section of a semiconductor device. The figure explaining the cross section of a semiconductor device. The figure explaining the band structure. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The cross-sectional view explaining the manufacturing method of the semiconductor device. The figure explaining the structural analysis of CAAC-OS and a single crystal oxide semiconductor by XRD, and the figure which shows the selected area electron diffraction pattern of CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a flat TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. The figure which shows the change of the crystal part by electron irradiation of In-Ga-Zn oxide. A cross-sectional view showing a configuration example of a display device. Top view showing one aspect of a display device. A cross-sectional view showing one aspect of a display device. A cross-sectional view showing one aspect of a display device. The figure explaining the circuit structure of the semiconductor device. A diagram for explaining the configuration of the pixel circuit and a timing chart for explaining the operation of the pixel circuit. A block diagram and a circuit diagram illustrating a display device. The figure explaining the display module. The figure explaining the electronic device. The figure explaining the arrangement of a light emitting element and a light receiving element. The figure explaining the arrangement of a display part, a light emitting element and a light receiving element. The figure explaining the upper surface and cross section of a transistor in an Example. The figure explaining the Id-Vg characteristic of a transistor in an Example. The figure explaining the light emitting state of a transistor in an Example. The figure explaining the light emitting state of a transistor in an Example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and its form and details can be variously changed without departing from the gist and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

Note that the positions, sizes, ranges, etc. of each configuration shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

Further, in the present specification and the like, the ordinal numbers attached as the first, second and the like are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Further, in the present specification, terms indicating the arrangement such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. In addition, the positional relationship between the configurations changes as appropriate according to the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

Further, in the present specification and the like, in explaining the structure of the invention using drawings, reference numerals indicating the same thing are commonly used among different drawings.

Further, even when the term "semiconductor" is used in the present specification or the like, for example, when the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, the boundary between "semiconductor" and "insulator" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in the present specification and the like may be paraphrased as an "insulator". Similarly, the "insulator" described in the present specification and the like may be paraphrased as "semiconductor". Alternatively, it may be possible to paraphrase the "insulator" described in the present specification and the like into a "semi-insulator".

Further, even when the term "semiconductor" is used in the present specification or the like, for example, when the conductivity is sufficiently high, it may have characteristics as a "conductor". In addition, the boundary between "semiconductor" and "conductor" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in the present specification and the like may be paraphrased as a "conductor". Similarly, the "conductor" described in the present specification and the like may be paraphrased as a "semiconductor".

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. Then, a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, the channel region and the source. Can be done. In the present specification and the like, the channel region refers to a region in which a current mainly flows.

Further, the functions of the source and the drain may be interchanged when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

The channel length is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other in a top view of a transistor, or a region in which a channel is formed. Refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification and the like, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, the source and the drain facing each other in the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the region where the channel is formed. The length of the part that is being used. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification and the like, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Further, in the present specification and the like, "electrically connected" includes a case where they are connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In addition, the voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, it is possible to paraphrase voltage as electric potential.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

(Embodiment 1)
In the present embodiment, an example of the semiconductor device according to the present invention and the method for manufacturing the semiconductor device will be described below with reference to FIGS. 1 to 13.

<1-1. Semiconductor device configuration example 1>
FIG. 1A is a top view of a transistor 100, which is a semiconductor device according to an aspect of the present invention. Further, FIG. 1B corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 1A, and FIG. 1C corresponds to the alternate long and short dash line Y1-shown in FIG. 1A. It corresponds to a cross-sectional view of the cut surface between Y2. In FIG. 1A, for clarity, some of the constituent elements of the transistor 100 (the substrate 102, the insulating film, etc.) are omitted.

Further, the alternate long and short dash line X1-X2 direction in FIG. 1A may be referred to as the channel length (L) direction of the transistor 100, and the alternate long and short dash line Y1-Y2 direction may be referred to as the channel width (W) direction of the transistor 100.

The transistor 100 includes a conductive film 106 that functions as a first gate electrode (also referred to as a bottom gate electrode) on the substrate 102, an insulating film 104 on the substrate 102 and the conductive film 106, and an oxide semiconductor film on the insulating film 104. 108, an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 functioning as a second gate electrode (also referred to as a top gate electrode) on the insulating film 110, an insulating film 104, an oxide semiconductor film 108, And an insulating film 116 on the conductive film 112. Further, the oxide semiconductor film 108 has a channel region 108i on which the conductive film 112 is superimposed and in contact with the insulating film 110, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116.

Further, the transistor 100 is electrically connected to the oxide semiconductor film 108 in the source region 108s via the insulating film 118 on the insulating film 116, the insulating film 116, and the opening 141s provided in the insulating film 118. The conductive film 120s and the conductive film 120d are electrically connected to the oxide semiconductor film 108 in the drain region 108d via the insulating film 116 and the opening 141d provided in the insulating film 118.

In the present specification and the like, the insulating film 104 is the first insulating film, the insulating film 110 is the second insulating film, the insulating film 116 is the third insulating film, and the insulating film 118 is the fourth insulating film. , Each may be called. Further, in the transistor 100, the insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film. Therefore, in the present specification and the like, the insulating film 104 may be referred to as a first gate insulating film, and the insulating film 110 may be referred to as a second gate insulating film. Further, the conductive film 120s has a function as a source electrode, and the conductive film 120d has a function as a drain electrode.

Further, in the transistor 100, it is preferable that the side end portion of the insulating film 110 and the side end portion of the conductive film 112 have a aligned region. In other words, in the transistor 100, the upper end portion of the insulating film 110 and the lower end portion of the conductive film 112 are substantially aligned. For example, the above structure can be obtained by processing the insulating film 110 using the conductive film 112 as a mask.

Further, in the transistor 100, the conductive film 106 and the conductive film 112 are electrically connected via the insulating film 104 and the opening 143 provided in the insulating film 110. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112.

As described above, the transistor 100 has a structure having conductive films that function as gate electrodes above and below the oxide semiconductor film 108.

≪s-channel structure≫
The oxide semiconductor film 108 is sandwiched between the conductive film 106 and the conductive film 112 via the first gate insulating film and the second gate insulating film. The length of the conductive film 106 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. Further, the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction. Further, since the conductive film 106 and the conductive film 112 are electrically connected at the opening 143 provided in the insulating film 104 and the insulating film 110, at least one of the side surfaces of the oxide semiconductor film 108 in the channel width direction is , Facing the conductive film 112 via the insulating film 110. That is, the entire channel width direction of the oxide semiconductor film 108 is covered with the conductive film 106 and the conductive film 112 via the first gate insulating film and the second gate insulating film.

In other words, the conductive film 106 and the conductive film 112 surround the oxide semiconductor film 108 via the first gate insulating film and the second gate insulating film in the channel width direction of the transistor 100.

With such a configuration, the oxide semiconductor film 108 of the transistor 100 is electrically surrounded by the electric fields of the conductive film 106 that functions as the first gate electrode and the conductive film 112 that functions as the second gate electrode. be able to. Like the transistor 100, the device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by the electric fields of the first gate electrode and the second gate electrode is defined as a s-channel structure. Can be called.

Since the transistor 100 has an s-channel structure, an electric field for inducing a channel by the conductive film 106 and the conductive film 112 can be effectively applied to the oxide semiconductor film 108. Therefore, the current drive capability of the transistor 100 is improved, and a high on-current characteristic can be obtained. Further, since the on-current can be increased, the transistor 100 can be miniaturized. Further, since the transistor 100 has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100 can be increased.

Further, with the above configuration, the region in which the carrier flows in the oxide semiconductor film 108 is the insulating film 104 side of the oxide semiconductor film 108, the insulating film 110 side of the oxide semiconductor film 108, and further the oxide semiconductor. Since the range in the film of the film 108 is wide, the amount of carrier movement of the transistor 100 increases. As a result, the on-current of the transistor 100 becomes large, and the electric field effect mobility becomes large. Specifically, the electric field effect mobility becomes 10 cm ² / V · s or more. The field effect mobility here is not an approximate value of the mobility as a physical property value of the oxide semiconductor film, but an index of the current driving force in the saturation region of the transistor, and is an apparent field effect mobility.

In FIG. 1C (in the channel width direction of the transistor 100), an opening different from the opening 143 is formed on the opposite side of the oxide semiconductor film 108 from the portion where the opening 143 is formed. May be good.

Further, different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. That is, a signal A may be given to one gate electrode, and a fixed potential Vb may be given to the other gate electrode. Further, a signal A may be given to one gate electrode and a signal B may be given to the other gate electrode. Further, a fixed potential Va may be given to one gate electrode, and a fixed potential Vb may be given to the other gate electrode.

Further, when a fixed potential is applied to both gate electrodes of the transistor, the transistor may be able to function as an element equivalent to a resistance element. For example, when the transistor is an n-channel type, the effective resistance of the transistor may be lowered (high) by raising (lowering) the fixed potential Va or the fixed potential Vb. By increasing (lowering) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by a transistor having only one gate may be obtained.

As described above, since the transistor 100 has an s-channel structure, it is possible to obtain high on-current characteristics, but when a current is passed through the channel region 108i of the oxide semiconductor film 108, it is one of the electric energies. The part may be converted into heat as Joule heat. Further, the transistor 100 further has an insulating film 116 and an insulating film 118 on the conductive film 112 that functions as a second gate electrode. Therefore, the channel region 108i in the oxide semiconductor film 108 has a structure sandwiched between the conductive film 106, the insulating film 104, the insulating film 110, the conductive film 112, the insulating film 116, and the insulating film 118. Therefore, the heat retention effect is excellent, and the heat generated when a current is passed through the transistor 100 is not easily dissipated. That is, the transistor 100 has a structure in which the temperature tends to be high when an electric current is passed and infrared rays generated by the heat are easily emitted. In particular, it is possible to strongly emit infrared rays having a short wavelength due to high temperature, and it is easy to emit near infrared rays in the wavelength region of 780 nm to 2500 nm among infrared rays, and in particular, it emits near infrared rays in the wavelength region of 900 nm or more and 1550 nm or less. Cheap.

In order to obtain higher on-current characteristics, the channel width of the transistor 100 is preferably large, specifically, preferably 50 μm or more, and more preferably 100 μm or more.

_{Further, the size (diw} ) of the oxide semiconductor film 108 in the channel width direction is superimposed on the oxide semiconductor film 108 so that heat is not easily propagated from the oxide semiconductor film 108 to the conductive film 120s and the conductive film 120d. It is preferable to have a region having the same _{size as the size (d sw} ) of the conductive film 120s in the channel width direction and the size (d _dw ) of the conductive film 120 d in the channel width direction in the region. _{Or, d iw} is preferably has a _{d sw} and _{d dw} larger region. That is, it is preferable that the transistor 100 has a region in which _diw ≧ d _sw and _diw ≧ d _dw.

The conductive film 120s is an oxide semiconductor film 108 and the size of the channel width direction of the region which does not overlap _{(d sw} ') is, the oxide semiconductor film 108 and the size of the channel width direction of the region which overlaps _{(d sw)} It is preferable to have a smaller (d _sw > d _{sw') region.} The conductive film 120d is an oxide semiconductor film 108 and the size of the channel width direction of the region which does not overlap _{(d dw} ') is, the oxide semiconductor film 108 and the size of the channel width direction of the region which overlaps _{(d dw)} It is preferable to have a smaller (d _dw > d _{dw') region.}

_{Further, the distance (d si} ) between the channel region 108i in the oxide semiconductor film 108 and the region where the oxide semiconductor film 108 connects to the conductive film 120s in the opening 141s, and the oxide in the channel region 108i and the opening 141d. _{By increasing the distance (d di} ) between the semiconductor film 108 and the region connecting the conductive film 120d, it is possible to make it difficult for the heat generated in the channel region 108i to propagate to the conductive film 120s and the conductive film 120d. Therefore, it is preferable, specifically, it is preferably 5 μm or more, and more preferably 10 μm or more.

Further, it is preferable to reduce the sizes of the openings 141s and 141d because it is possible to make it difficult for the heat generated in the channel region 108i to propagate to the conductive films 120s and 120d.

Further, the conductive film 120s and the conductive film 120d, which are conductive films connected to the oxide semiconductor film 108, are preferably substances having low thermal conductivity.

With the above configuration, it is possible to make the transistor 100 a transistor that easily emits near infrared rays.

<1-2. Components of semiconductor devices>
The components included in the semiconductor device of the present embodiment will be described in detail below.

≪Oxide semiconductor film≫
The oxide semiconductor film 108 in the transistor 100, which is one aspect of the present invention, preferably has a metal oxide, and the metal oxide preferably has at least indium (In) or zinc (Zn).

When the oxide semiconductor film has In, for example, the carrier mobility (electron mobility) becomes high. Further, when the oxide semiconductor film has Zn, crystallization of the oxide semiconductor film is likely to occur.

Further, when the oxide semiconductor film has the element M having a function as a stabilizer, for example, the energy gap (Eg) of the oxide semiconductor film becomes large. The oxide semiconductor film suitable for one aspect of the present invention has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As described above, by using the metal oxide having a large energy gap for the oxide semiconductor film 108, the off-current of the transistor 100 can be reduced. The element M is an element having a high binding energy with oxygen, and has a higher binding energy with oxygen than In.

As the oxide semiconductor film suitable for the semiconductor device of one aspect of the present invention, In-Zn oxide, In-M oxide, and In-M-Zn oxide can be typically used. Of these, it is preferable to use In—M—Zn oxide (M represents aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)). In particular, it is preferable to use an In-Ga-Zn oxide (hereinafter, may be referred to as IGZO) having M as Ga.

When the oxide semiconductor film 108 is an In—M—Zn oxide, the atomic number ratio of In and M is higher than 25 atomic% when the sum of In and M is 100 atomic%, and M is less than 75 atomic%. , Or In is higher than 34 atomic% and M is less than 66 atomic%. In particular, the oxide semiconductor film 108 preferably has a region in which the atomic number ratio of In is equal to or higher than the atomic number ratio of M.

The oxide semiconductor film 108 has a region in which the atomic number ratio of In is equal to or higher than the atomic number ratio of M, thereby increasing the electric field effect mobility (sometimes simply referred to as mobility or μFE) of the transistor 100. Can be done. Specifically, the field-effect mobility of the transistor 100 ^{can be greater than 10 cm 2} / V · s, and more preferably the field-effect mobility of the transistor 100 ^{can be greater than 30 cm 2} / V · s.

For example, since the transistor having a high field effect mobility can reduce the channel width, the transistor is shifted by a scanning line drive circuit (also referred to as a gate driver) that generates a gate signal or a scanning line drive circuit. By using the demultiplexer connected to the output terminal of the register, the size of the scanning line drive circuit can be reduced, and a semiconductor device or a display device having a narrow frame width (also referred to as a narrow frame) can be provided. Alternatively, since the gate voltage of the transistor used in the circuit can be reduced, the power consumption of the display device can be reduced. The details of the scanning line drive circuit will be described later.

Further, by increasing the electric field effect mobility of the transistor, the display device can be made high-definition. For example, pixels of a high-definition display device typified by 4K x 2K (horizontal pixel count = 3840, vertical pixel count = 2160) or 8K x 4K (horizontal pixel count = 7680, vertical pixel count = 4320). The above-mentioned transistor is suitable as a transistor of a circuit or a drive circuit.

The thickness of the oxide semiconductor film 108 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 60 nm or less.

When the oxide semiconductor film 108 is formed of In-M-Zn oxide, the atomic number ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is M or more for In and Zn. Preferably satisfies M or more. Alternatively, in the sputtering target, if the atomic number ratio of the metal element is In: M: Zn = x _b : y _b : z _b [atomic number ratio] _, x _b / y _b is 1/3 or more and 6 or less, and further. Is 1 or more and 6 or less, and z _b / y _b is preferably 1/3 or more and 6 or less, and more preferably 1 or more and 6 or less. By _{setting z b} / y _b to 1 or more and 6 or less, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, which will be described later, is easily formed as the oxide semiconductor film 108. The atomic number ratio of the metal element of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1. 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, etc., and the vicinity thereof are preferable.

The atomic number ratio of the oxide semiconductor film 108 includes a fluctuation of plus or minus 40% of the atomic number ratio as an error. For example, when the atomic number ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic number ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 4: 2. : May be near 3. Alternatively, when the atomic number ratio of In: Ga: Zn = 1: 1: 1.2 is used as the sputtering target, the atomic number ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 1: 1. It may be in the vicinity of 1. Alternatively, when the atomic number ratio of In: Ga: Zn = 5: 1: 7 is used as the sputtering target, the atomic number ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 5: 1: 6. It may be in the vicinity.

Further, impurities such as hydrogen or water mixed in the channel region 108i in the oxide semiconductor film 108 affect the transistor characteristics, which causes a problem. Therefore, in the channel region 108i in the oxide semiconductor film 108, it is preferable that there are few impurities such as hydrogen and water.

The hydrogen contained in the oxide semiconductor film 108 reacts with oxygen bonded to a metal atom to become water, and at the same time, forms an oxygen deficiency in the oxygen-desorbed lattice (or the oxygen-desorbed portion). When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen, which is bonded to a metal atom, to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor film containing hydrogen tends to have an electrical characteristic (also referred to as a normal-on characteristic) in which the threshold voltage becomes negative.

Therefore, it is preferable that hydrogen is reduced as much as possible in the channel region 108i of the oxide semiconductor film 108. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms. / Cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ^{less than 3} , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm. ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less. As a result, it has an electrical characteristic (also referred to as a normally-off characteristic) in which the threshold voltage of the transistor becomes positive.

Further, when silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor film 108, oxygen deficiency increases and the oxide semiconductor film 108 may become n-type. Therefore, in the oxide semiconductor film 108, particularly in the channel region 108i, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁷ atoms. / cm ³ it can be less. As a result, the transistor has an electrical characteristic (also referred to as a normally-off characteristic) in which the threshold voltage becomes positive.

Further, in the channel region 108i, the concentration of the alkali metal or alkaline earth metal obtained by the secondary ion mass spectrometry shall be 1 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁶ atoms / cm ³ or less. Can be done. Alkali metals and alkaline earth metals may form carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has an electrical characteristic (also referred to as a normally-off characteristic) in which the threshold voltage becomes positive.

Further, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density increases, and the n-type may be formed. As a result, the transistor using the oxide semiconductor film containing nitrogen tends to have a normally-on characteristic. Therefore, it is preferable that nitrogen is reduced as much as possible in the channel region 108i. For example, the nitrogen concentration obtained by the secondary ion mass spectrometry may be 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, by reducing the impurity elements in the channel region 108i, the carrier density of the oxide semiconductor film 108 can be reduced. Therefore, in the channel region 108i, the carrier density is 1 × 10 ¹⁷ / cm ³ or less, or 1 × 10 ¹⁵ / cm ³ or less, or 1 × 10 ¹³ / cm ³ or less, or 1 × 10 ¹¹ / cm ³ or less. Can be.

By using the oxide semiconductor film 108 having a low impurity concentration and a low defect level density as the channel region 108i, a transistor having further excellent electrical characteristics can be manufactured. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Alternatively, it is called true or substantially true. Oxide semiconductors having high-purity intrinsics or substantially high-purity intrinsics may have a low carrier density due to the small number of carrier sources. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film tends to have an electrical characteristic (also referred to as a normally-off characteristic) in which the threshold voltage is positive. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low. Further, the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity can obtain the property that the off-current is remarkably small. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film may be a highly reliable transistor with little fluctuation in electrical characteristics.

The semiconductor impurities refer to other than the main components constituting the semiconductor film. For example, an element having a concentration of less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be lowered, crystallinity may be lowered, and the like. When the semiconductor has an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 element, Group 2 element, Group 14 element, Group 15 element, transition metal other than the main component, and the like. In particular, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of oxide semiconductors, oxygen deficiency may be formed due to the mixing of impurities such as hydrogen. When the semiconductor has silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

Further, a transistor in which a channel region is formed in an oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity tends to have an electrical characteristic (also referred to as a normally-off characteristic) in which a threshold voltage is positive. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

Moreover, the transistor including the highly purified intrinsic or substantially oxide semiconductor film is highly purified intrinsic, the off current is extremely small, the channel width is a semiconductor device channel length L 10μm at 1 × 10 ⁶ μm In addition, when the voltage (drain voltage) between the source electrode and the drain electrode is in the range of 1 V to 10 V, the off current can be obtained in ^{the measurement limit of the semiconductor parameter analyzer or less, that is, 1 × 10 -13 A or less.} .. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film has a small fluctuation in electrical characteristics and is a highly reliable transistor.

Further, in the present specification and the like, unless otherwise specified, the off current means a drain current when the transistor is in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor. Is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off current of the transistor may depend on Vgs. Therefore, the fact that the off-current of the transistor is I or less may mean that there is a value of Vgs in which the off-current of the transistor is I or less. The off-current of a transistor may refer to an off-current in a predetermined Vgs, an off-state in Vgs within a predetermined range, an off-state in Vgs in which a sufficiently reduced off-current can be obtained, and the like.

As an example, the threshold voltage Vth is 0.5 V, the drain current at Vgs is 0.5 V is 1 × 10 ^-9 A, and the drain current at Vgs is 0.1 V is 1 × 10 ^-13 A. Assume an n-channel transistor having a drain current of 1 × 10 ^-19 A at Vgs of −0.5 V and a drain current of 1 × 10 ^{-22 A at Vgs of −0.8 V. Since the drain current of the transistor is 1 × 10 -19} A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off current of the transistor is 1. It may be said that it is ^{× 10-19 A or less.} Since there are Vgs in which the drain current of the transistor is 1 × ^10-22 A or less, it may be said that the off current of the transistor is 1 × ^10-22 A or less.

The off current of the transistor may depend on the temperature. In the present specification, the off-current may represent an off-current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C., unless otherwise specified. Alternatively, at a temperature at which the reliability of the semiconductor device or the like containing the transistor is guaranteed, or at a temperature at which the semiconductor device or the like containing the transistor is used (for example, any one of 5 ° C. to 35 ° C.). May represent off-current. The off-current of a transistor is I or less, which means room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed, or the transistor is included. It may indicate that there is a value of Vgs in which the off-current of the transistor is I or less at the temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

The off-current of the transistor may depend on the voltage Vds between the drain and the source. In the present specification, the off-current has Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. , Or may represent off-current at 20V. Alternatively, it may represent Vds in which the reliability of the semiconductor device or the like including the transistor is guaranteed, or the off-current in Vds used in the semiconductor device or the like including the transistor. When the off current of the transistor is I or less, Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V. , Vds in which the reliability of the semiconductor device including the transistor is guaranteed, or Vgs in which the off current of the transistor in Vds used in the semiconductor device including the transistor is I or less exists. May point to.

In the above description of the off-current, the drain may be read as the source. That is, the off-current may refer to the current flowing through the source when the transistor is in the off state.

Further, in the present specification and the like, it may be described as a leak current in the same meaning as an off current. Further, in the present specification and the like, the off current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state.

The charge captured at the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed on an oxide semiconductor film having a high trap level density may have unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals and the like.

Further, the oxygen deficiency formed in the channel region 108i in the oxide semiconductor film 108 affects the transistor characteristics, which causes a problem. For example, when an oxygen deficiency is formed in the channel region 108i of the oxide semiconductor film 108, hydrogen is bonded to the oxygen deficiency and becomes a carrier supply source. When a carrier supply source is generated in the channel region 108i of the oxide semiconductor film 108, fluctuations in the electrical characteristics of the transistor 100 having the oxide semiconductor film 108, typically a shift in the threshold voltage occur. Therefore, in the channel region 108i of the oxide semiconductor film 108, the smaller the oxygen deficiency, the more preferable.

Therefore, in one aspect of the present invention, the insulating film in contact with the oxide semiconductor film, specifically, the insulating film 104 formed below the oxide semiconductor film 108 and above the oxide semiconductor film 108 is formed. The insulating film 110 is configured to contain excess oxygen. By moving oxygen or excess oxygen from the insulating film 104 and the insulating film 110 to the oxide semiconductor film 108, it is possible to reduce oxygen deficiency in the oxide semiconductor film 108. Therefore, it is possible to suppress fluctuations in the electrical characteristics of the transistor 100, particularly fluctuations in the electrical characteristics of the transistor 100 due to light irradiation.

Further, in one aspect of the present invention, in order to make the insulating film 104 and the insulating film 110 contain excess oxygen, a manufacturing method in which there is no increase in the manufacturing steps or the increase in the manufacturing steps is extremely small is used. Therefore, it is possible to increase the yield of the transistor 100.

Specifically, in the step of forming the oxide semiconductor film 108, the oxide semiconductor film 108 is formed in an atmosphere containing oxygen gas by using a sputtering method, so that the oxide semiconductor film 108 becomes a surface to be formed. Oxygen or excess oxygen is added to the insulating film 104.

The transistor 100 having such a structure has extremely few defects in the channel region 108i of the oxide semiconductor film 108, so that the electrical characteristics are improved. Typically, it is possible to increase the on-current of the transistor 100 and improve the field effect mobility. Further, the transistor 100 has a small fluctuation amount of the threshold voltage in the BT stress test and the optical BT stress test, which are examples of the stress test, and has high reliability. The BT stress test is a kind of accelerated test, and changes in transistor characteristics (that is, changes over time) caused by long-term use can be evaluated in a short time. In particular, the fluctuation amount of the threshold voltage of the transistor before and after the BT stress test is an important index for examining the reliability. Before and after the BT stress test, it can be said that the smaller the fluctuation amount of the threshold voltage is, the higher the reliability of the transistor is.

On the other hand, the source region 108s and the drain region 108d are in contact with the insulating film 116. When the source region 108s and the drain region 108d are in contact with the insulating film 116, either or both of hydrogen and nitrogen are added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density becomes high. ..

The oxide semiconductor film 108 is not limited to the above structure, and a film having an appropriate composition according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor may be used. good. In addition, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the oxide semiconductor film shall be appropriate. Is preferable.

Further, the oxide semiconductor film 108 may have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Crystal Ductor) described later, a polycrystalline structure, a microcrystal structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

A monolayer film in which the oxide semiconductor film 108 has two or more types of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Alternatively, the structure may be such that the films are laminated.

In the oxide semiconductor film 108, the crystallinity of the channel region 108i and the source region 108s and the drain region 108d may be different. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when an impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged and the crystallinity is lowered.

Further, the source region 108s and the drain region 108d of the oxide semiconductor film 108 may each have an element that forms an oxygen deficiency. Typical examples of the element forming the oxygen deficiency (also referred to as an impurity element) include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and noble gas. Typical examples of noble gas elements include helium, neon, argon, krypton, xenon and the like.

When an impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and an oxygen deficiency is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is combined with the impurity element, oxygen is desorbed from the metal element, and an oxygen deficiency is formed. NS. As a result, the carrier density of the oxide semiconductor film is increased and the conductivity is increased.

≪Board≫
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a specific one. Examples of substrates include semiconductor substrates (for example, single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, ceramic substrates, sapphire substrates, plastic substrates, metal substrates, stainless steel substrates, and stainless still foils. Such as a substrate having a substrate, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, the base film and the like are as follows. For example, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). Alternatively, as an example, there is a synthetic resin such as acrylic. Alternatively, as an example, there are polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride and the like. Alternatively, examples include polyamides, polyimides, aramids, epoxies, inorganic vapor-deposited films, or papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to manufacture a transistor having a high current capacity and a small size with little variation in characteristics, size, or shape. .. When the circuit is composed of such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

When a glass substrate is used as the substrate 102, the 6th generation (1500 mm × 1850 mm), the 7th generation (1870 mm × 2200 mm), the 8th generation (2200 mm × 2400 mm), the 9th generation (2400 mm × 2800 mm), and the 10th generation. A large display device can be manufactured by using a large area substrate of a generation (2950 mm × 3400 mm) or the like.

Further, a flexible substrate may be used as the substrate 102, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistor. The release layer can be used for separating the semiconductor device from the substrate 102 and reprinting it on another substrate after the semiconductor device is partially or completely completed on the release layer. At that time, the transistor can be reprinted on a substrate having inferior heat resistance or a flexible substrate. For the above-mentioned release layer, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is laminated, a structure in which an organic resin film such as polyimide is formed on a substrate, or the like can be used.

As an example of the substrate on which the transistor is transferred, in addition to the substrate capable of forming the above-mentioned transistor, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, and a cloth substrate (natural fiber). (Including silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, or rubber substrates. By using these substrates, it is possible to form a transistor having good characteristics, to form a transistor having low power consumption, to manufacture a device that is hard to break, to impart heat resistance, to reduce the weight, or to reduce the thickness.

≪Insulating film that functions as the first gate insulating film≫
The insulating film 104 can be formed by appropriately using a sputtering method, a CVD method, a thin film deposition method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like. Further, the insulating film 104 can be formed, for example, by forming an oxide insulating film and a nitride insulating film in a single layer or by laminating them. In order to improve the interface characteristics with the oxide semiconductor film 108, it is preferable that at least the region of the insulating film 104 in contact with the oxide semiconductor film 108 is formed of the oxide insulating film. Further, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, it is possible to move oxygen contained in the insulating film 104 to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By thickening the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108. It is possible to reduce the oxygen deficiency contained in 108i.

As the insulating film 104, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and the insulating film 104 may be provided as a single layer or laminated. In the present embodiment, a laminated structure of a silicon nitride film and a silicon oxide film is used as the insulating film 104. As described above, by using the insulating film 104 as a laminated structure, using the silicon nitride film on the lower layer side, and using the silicon oxide nitride film on the upper layer side, oxygen can be efficiently introduced into the oxide semiconductor film 108.

In the present specification and the like, the silicon oxide nitride refers to a composition having an oxygen content higher than that of nitrogen, preferably 55 atomic% or more and 65 atomic% or less of oxygen, and 1 atomic% or more of nitrogen. 20 atomic% or less, silicon is contained in the range of 25 atomic% or more and 35 atomic% or less, and hydrogen is contained in the range of 0.1 atomic% or more and 10 atomic% or less. The composition of silicon nitride oxide means that the content of nitrogen is higher than that of oxygen, and preferably nitrogen is 55 atomic% or more and 65 atomic% or less, oxygen is 1 atomic% or more and 20 atomic% or less, and silicon is 25. It refers to those containing atomic% or more and 35 atomic% or less and hydrogen in a concentration range of 0.1 atomic% or more and 10 atomic% or less.

In the insulating film 104, at least the region in contact with the oxide semiconductor film 108 is preferably an oxide insulating film, and may have a region containing oxygen in excess of the stoichiometric composition (oxygen excess region). More preferable. In other words, the insulating film 104 is an insulating film capable of releasing oxygen. In order to provide the oxygen excess region in the insulating film 104, for example, the insulating film 104 may be formed in an oxygen atmosphere. Alternatively, oxygen may be added to the insulating film 104 after the film formation. The method of adding oxygen to the insulating film 104 after the film formation will be described later.

Further, as the insulating film 104, a hafnium silicate (HfSiO _x), hafnium silicate to which nitrogen is added _{(HfSi x O y N z)} , hafnium aluminate to which nitrogen is added _{(HfAl x O y N z)} , hafnium oxide, A high-k material such as yttrium oxide can be preferably used. The material having hafnium or yttrium has a higher relative permittivity than silicon oxide or silicon oxide. Therefore, by using the high-k material for the insulating film 104, the film thickness can be increased as compared with the case where the silicon oxide film is used, so that the leakage current due to the tunnel current can be reduced. That is, it is possible to realize a transistor having a small off-current. Further, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure in order to obtain a transistor having a small off-current. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

In the present embodiment, the insulating film 104 is formed by laminating a silicon nitride film on the conductive film 106 side and a silicon oxide film on the oxide semiconductor film 108 side. The silicon nitride film has a higher relative permittivity than the silicon oxide film, and the film thickness required to obtain a capacitance equivalent to that of the silicon oxide film is large. Therefore, by including the silicon nitride film as the first gate insulating film of the transistor 100, the first gate insulating film can be physically thickened. Therefore, it is possible to suppress a decrease in the withstand voltage of the transistor 100, further improve the withstand voltage, and suppress electrostatic breakdown of the transistor 100.

≪Insulating film that functions as the second gate insulating film≫
The insulating film 110 can be formed by forming a single layer or a laminate of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the oxide semiconductor film 108, it is preferable that at least the region of the insulating film 110 in contact with the oxide semiconductor film 108 is formed by using the oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and the insulating film 110 may be provided in a single layer or in a laminated manner.

Further, by providing an insulating film having a blocking effect of oxygen, hydrogen, water, etc. as the insulating film 110, oxygen from the oxide semiconductor film 108 can be diffused to the outside and hydrogen from the outside to the oxide semiconductor film 108 can be diffused to the outside. , Water, etc. can be prevented from entering. Examples of the insulating film having a blocking effect on oxygen, hydrogen, water and the like include aluminum oxide, aluminum nitride, gallium oxide, gallium nitride, yttrium oxide, yttrium oxide, hafnium oxide, and hafnium oxide.

Further, as the insulating film 110, a hafnium silicate (HfSiO _x), hafnium silicate to which nitrogen is added _{(HfSi x O y N z)} , hafnium aluminate to which nitrogen is added _{(HfAl x O y N z)} , hafnium oxide, By using a high-k material such as yttrium oxide, the gate leak of the transistor can be reduced.

Further, by using an oxide insulating film that releases oxygen by heating as the insulating film 110, it is possible to move oxygen contained in the insulating film 110 to the oxide semiconductor film 108 by heat treatment.

For that purpose, the insulating film 110 preferably has an oxide insulating film containing at least more oxygen than oxygen satisfying the stoichiometric composition. The second gate insulating film may have one layer or two or more layers as appropriate. In these cases, it is preferable to have an oxide insulating film containing at least more oxygen than oxygen satisfying the stoichiometric composition.

The thickness of the insulating film 110 can be 5 nm or more and 400 nm or less, 5 nm or more and 300 nm or less, or 10 nm or more and 250 nm or less.

<< First gate electrode and conductive film that functions as a pair of electrodes >>
The conductive film 106 and the conductive films 120s and 120d can be formed by using a sputtering method, a vacuum vapor deposition method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. The conductive films 120s and 120d include, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above-mentioned metal element as a component. It can be formed by using an alloy or the like in which the above-mentioned metal elements are combined. Further, a metal element selected from any one or more of manganese and zirconium may be used. Further, the conductive films 120s and 120d may have a single-layer structure or a laminated structure having two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and nitrided. Two-layer structure in which a tungsten film is laminated on a titanium film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, and an upper titanium film. A two-layer structure in which a copper film is laminated on the surface, a titanium film, an aluminum film laminated on the titanium film, and a three-layer structure in which the titanium film is formed on the titanium film, and a copper film is laminated on a copper film containing manganese. Further, there is a three-layer structure in which a copper film containing manganese is formed on the copper film. Further, an alloy film or a nitride film in which one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be combined with aluminum may be used.

Further, the conductive films 120s and 120d include indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. It is also possible to apply a translucent conductive material such as indium tin oxide, indium zinc oxide, and indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO). Further, it is also possible to form a laminated structure of the conductive material having the translucency and the metal element.

The thickness of the conductive films 120s and 120d can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

<< Conductive film 112 that functions as a second gate electrode >>
The conductive film 112 that functions as the second gate electrode uses the same materials and manufacturing methods as those of the conductive film 106 that functions as the first gate electrode and the conductive films 120s and 120d that function as a pair of electrodes. Can be formed. Alternatively, these laminated structures may be used.

Further, the conductive film 112 can be formed by using the same material and manufacturing method as the oxide semiconductor film 108 shown above. For example, as the conductive film 112, In oxide, In—Sn oxide, In—Zn oxide, In—Ga oxide, Zn oxide, Al—Zn oxide, In—Ga—Zn oxide and the like can be used. Can be used. In particular, it is preferable to use In-Sn oxide or In-Ga-Zn oxide. Further, as the conductive film 112, a material such as indium tin oxide (ITO) or indium tin oxide (ITSO) to which silicon oxide is added can be used. Further, by forming the conductive film 112 and the oxide semiconductor film 108 to have the same metal element, it is possible to suppress the manufacturing cost.

For example, when In-M-Zn oxide is used as the conductive film 112, the atomic number ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is a region where In is M or more. It is preferable to have. As the atomic number ratio of the metal element of such a sputtering target, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4. 1, In: M: Zn = 5: 1: 7 and the like and their vicinity can be mentioned. The conductive film 112 is not limited to the composition of the sputtering target described above. Further, the structure of the conductive film 112 may be a single-layer structure or a laminated structure of two or more layers.

Further, the conductive film 112 has a function of supplying oxygen to the insulating film 110. Since the conductive film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen can be contained in the insulating film 110. When the insulating film 110 has an excess oxygen region, the excess oxygen can be supplied into the oxide semiconductor film 108, more specifically, the channel region 108i. Therefore, it is possible to provide a highly reliable semiconductor device.

In order to supply excess oxygen to the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. However, in this case, the oxygen contained in the insulating film 104 can also be supplied to the source region 108s and the drain region 108d of the oxide semiconductor film 108. When excess oxygen is supplied into the source region 108s and the drain region 108d, the resistance in the source region 108s and the drain region 108d may increase.

On the other hand, by configuring the insulating film 110 formed above the oxide semiconductor film 108 to have excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier densities of the source region 108s and the drain region 108d may be selectively increased.

Further, in the conductive film 112, oxygen is supplied to the insulating film 110, and then either one or both of nitrogen and hydrogen are supplied from the insulating film 116, so that a donor level is formed in the vicinity of the conduction band and the carrier density is increased. Will be higher. In other words, the conductive film 112 also has a function as an oxide conductor (OC). Therefore, the conductive film 112 has a higher carrier density than the oxide semiconductor film 108.

In general, oxide semiconductors have a large energy gap and therefore have translucency with respect to visible light. On the other hand, the oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the oxide conductor is less affected by absorption by the donor level and has the same level of translucency as the oxide semiconductor with respect to visible light. Therefore, by using an oxide conductor for the conductive film 112, infrared rays emitted in the channel region 108i can be efficiently extracted.

≪Third insulating film≫
The insulating film 116 has one or both of nitrogen and hydrogen. By configuring the insulating film 116 to have either or both of nitrogen and hydrogen, it is possible to supply either or both of nitrogen and hydrogen to the oxide semiconductor film 108 and the conductive film 112. Examples of the insulating film 116 include a nitride insulating film. The nitride insulating film can be formed by using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride or the like. The hydrogen concentration contained in the insulating film 116 ^{is preferably 1 × 10 22} atoms / cm ³ or more. Further, the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Further, the insulating film 116 is in contact with the conductive film 112. Therefore, the hydrogen concentration in the source region 108s, the drain region 108d, and the conductive film 112 in contact with the insulating film 116 is increased, and the carrier density of the source region 108s, the drain region 108d, and the conductive film 112 can be increased. The source region 108s, the drain region 108d, and the conductive film 112 may have regions having the same hydrogen concentration in the film when they are in contact with the insulating film 116, respectively.

≪Fourth insulating film≫
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or laminated. As the insulating film 118, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and the insulating film 118 may be provided as a single layer or laminated.

Further, the insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, etc. from the outside.

The thickness of the insulating film 118 can be 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less.

<1-3. Semiconductor device configuration examples 2 to 6>
Next, a configuration different from the semiconductor device shown in FIGS. 1 (A), (B), and (C) will be described with reference to FIGS. 2 to 9.

<< Semiconductor device configuration example 2 >>
2A is a top view of the transistor 100A, FIG. 2B is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 2A, and FIG. 2C is FIG. 2A. It is sectional drawing between one-dot chain line Y1-Y2.

The transistors 100A shown in FIGS. 2 (A), (B) and (C) have an insulating film 104 formed on the substrate 102, an oxide semiconductor film 108 on the insulating film 104, and an insulating film on the oxide semiconductor film 108. It has 110, a conductive film 112 on the insulating film 110, an insulating film 104, an oxide semiconductor film 108, and an insulating film 116 on the conductive film 112. Further, the oxide semiconductor film 108 has a channel region 108i in contact with the insulating film 110, a source region 108s in contact with the insulating film 116, and a drain region 108d in contact with the insulating film 116.

The transistor 100A is different from the configuration of the transistor 100 shown above in that it does not have the conductive film 106 and the opening 143.

As described above, the transistor 100A shown in FIGS. 2A, 2B, and 2C has a structure having a conductive film that functions as a gate electrode only on the oxide semiconductor film 108, unlike the transistor 100 described above. be. As shown in the transistor 100A, by using one gate electrode, the production becomes easy, so that the production can be inexpensive.

<< Semiconductor device configuration example 3 >>
Next, a configuration different from the semiconductor device shown in FIGS. 1 (A), (B), and (C) will be described with reference to FIGS. 3 (A), (B), and (C).

3 (A) is a top view of the transistor 100B, FIG. 3 (B) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 3 (A), and FIG. 3 (C) is FIG. 3 (A). It is sectional drawing between one-dot chain line Y1-Y2.

The transistor 100B shown in FIGS. 3A, 3B and 3C has a different shape of the conductive film 112 from the transistor 100 shown above. Specifically, the lower end portion of the conductive film 112 included in the transistor 100B is formed inside the upper end portion of the insulating film 110. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the conductive film 112.

For example, the conductive film 112 and the insulating film 110 are processed with the same mask, the conductive film 112 is processed by a wet etching method, and the insulating film 110 is processed by a dry etching method, whereby the above structure can be obtained. ..

Further, when the conductive film 112 has the above structure, the region 108f may be formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

The region 108f functions as either a high resistance region or a low resistance region. The high resistance region is a region having resistance equivalent to that of the channel region 108i and in which the conductive film 112 functioning as a gate electrode is not superimposed. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. When the region 108f functions as an offset region, the region 108f may be set to 1 μm or less in the channel length (L) direction in order to suppress a decrease in the on-current of the transistor 100B.

The low resistance region is a region having a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. When the region 108f functions as the LDD region, the electric field in the drain region can be relaxed, so that the fluctuation of the threshold voltage of the transistor due to the electric field in the drain region can be reduced.

When the region 108f is a low resistance region, for example, either one or both of hydrogen and nitrogen are supplied from the insulating film 116 to the region 108f, or the insulating film 110 and the conductive film 112 are used as masks to conduct conductivity. By adding an impurity element from above the film 112, the impurity is added to the oxide semiconductor film 108 via the insulating film 110.

<< Semiconductor device configuration example 4 >>
Next, a modification of the semiconductor device shown in FIGS. 3 (A), (B), and (C) will be described with reference to FIGS. 4 (A) and 4 (B).

4 (A) and 4 (B) are cross-sectional views of the transistor 100C. Since the top view of the transistor 100C is the same as that of the transistor 100B shown in FIG. 3A, FIG. 3A will be referred to for description. 4 (A) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 3 (A), and FIG. 4 (B) is a cross-sectional view between the alternate long and short dash lines Y1-Y2 of FIG. 3 (A).

The transistor 100C is different in that the transistor 100B described above is provided with an insulating film 122 that functions as a flattening insulating film. Other configurations are the same as those of the transistor 100B shown above, and the same effect is obtained.

The insulating film 122 has a function of flattening irregularities and the like caused by transistors and the like. The insulating film 122 may be insulating, and is formed by using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, aluminum oxide, and aluminum nitride. Examples of the organic material include a photosensitive resin material such as an acrylic resin or a polyimide resin.

In FIGS. 4A and 4B, the shape of the opening of the insulating film 122 is smaller than that of the openings 141s and 141d, but the shape is not limited to this, and for example, the openings 141s and 141d. It may have the same shape as the above, or a shape larger than the openings 141s and 141d.

Further, in FIGS. 4A and 4B, the configuration in which the conductive films 120s and 120d are provided on the insulating film 122 is illustrated, but the present invention is not limited to this, and for example, the conductive films 120s and 120d are provided on the insulating film 118. The insulating film 122 may be provided on the conductive films 120s and 120d.

<< Semiconductor device configuration example 5 >>
Next, a modification of the semiconductor device shown in FIGS. 2 (A), (B), and (C) will be described with reference to FIGS. 5 and 6.

5 (A) and 5 (B) are cross-sectional views of the transistor 100D. Since the top view of the transistor 100D is the same as that of the transistor 100 shown in FIG. 2 (A), FIG. 2 (A) will be referred to for description. 5 (A) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 2 (A), and FIG. 5 (B) is a cross-sectional view of the alternate long and short dash lines Y1-Y2 of FIG. 2 (A).

The transistor 100D has a different shape of the insulating film 110 from the transistor 100A shown above. Other configurations are the same as those of the transistor 100A shown above, and the same effect is obtained.

The insulating film 110 included in the transistor 100D is located inside the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end of the conductive film 112. For example, after processing the conductive film 112, the insulating film 110 is side-etched using an etchant or the like to obtain the configuration shown in FIGS. 5A and 5B. By making the insulating film 110 have the above structure, a hollow region 147 is formed below the conductive film 112.

The hollow region 147 has air and functions as a part of the gate insulating film. The relative permittivity of the hollow region 147 is approximately 1, which is the same as that of air. Therefore, by adopting the structure of the transistor 100D, when a voltage is applied to the conductive film 112 that functions as a gate electrode, the voltage applied to the channel region 108i below the hollow region 147 is the channel region below the insulating film 110. It will be lower than the voltage given to 108i. Therefore, the channel region 108i below the hollow region 147 effectively functions as an overlap region (also referred to as a Lov region). The Lov region is a region that overlaps with the conductive film 112 that functions as a gate electrode and has a lower resistance than the channel region 108i.

6 (A) and 6 (B) are cross-sectional views of the transistor 100E. Since the top view of the transistor 100E is the same as that of the transistor 100 shown in FIG. 2 (A), FIG. 2 (A) will be referred to for description. 9 (A) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 2 (A), and FIG. 9 (B) is a cross-sectional view of the alternate long and short dash lines Y1-Y2 of FIG. 2 (A).

The transistor 100E is different in the shape of the insulating film 116 from the transistor 100A shown above and the insulating film 110. Other configurations are the same as those of the transistor 100A shown above, and the same effect is obtained.

The insulating film 110 included in the transistor 100E is located inside the conductive film 112. In other words, the side surface of the insulating film 110 is located inside the lower end of the conductive film 112. For example, after processing the conductive film 112, the insulating film 110 is side-etched using an etchant or the like to obtain the configuration shown in FIGS. 6A and 6B. Further, by forming the insulating film 116 after forming the insulating film 110 into the above structure, the insulating film 116 also penetrates under the conductive film 112, and the insulating film 116 is oxidized located below the conductive film 112. It is in contact with the object semiconductor film 108.

With the above configuration, the source region 108s and the drain region 108d are located inside the lower end portion of the conductive film 112. Therefore, the transistor 100E has a Lov region.

By adopting a structure having a Lov region like the transistor 100D and the transistor 100E, a high resistance region is not formed between the channel region 108i and the source region 108s and the drain region 108d, so that the on-current of the transistor is increased. Is possible.

<< Semiconductor device configuration example 6 >>
Next, a modification of the semiconductor device shown in FIGS. 1 (A), (B), and (C) will be described with reference to FIGS. 7 to 9.

7 (A) and 7 (B) are cross-sectional views of the transistor 100F. Since the top view of the transistor 100F is the same as that of the transistor 100 shown in FIG. 1 (A), FIG. 1 (A) will be referred to for description. 7 (A) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 1 (A), and FIG. 7 (B) is a cross-sectional view of the alternate long and short dash lines Y1-Y2 of FIG. 1 (A).

The transistor 100F has a structure of the oxide semiconductor film 108 different from that of the transistor 100 shown above. Other configurations are the same as those of the transistor 100 shown above, and the same effect is obtained.

The oxide semiconductor film 108 included in the transistor 100F includes an oxide semiconductor film 108_1 on the insulating film 116, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_2 on the oxide semiconductor film 108_2. , Have.

Further, the channel region 108i, the source region 108s, and the drain region 108d have a three-layer laminated structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3, respectively.

8 (A) and 8 (B) are cross-sectional views of the transistor 100G. Since the top view of the transistor 100G is the same as that of the transistor 100 shown in FIG. 1 (A), FIG. 1 (A) will be referred to and described. 8 (A) is a cross-sectional view between the alternate long and short dash lines X1-X2 of FIG. 1 (A), and FIG. 8 (B) is a cross-sectional view of the alternate long and short dash lines Y1-Y2 of FIG. 1 (A).

The transistor 100G has a structure of the oxide semiconductor film 108 different from that of the transistor 100 shown above. Other configurations are the same as those of the transistor 100 shown above, and the same effect is obtained.

The oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 on the insulating film 116 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2.

Further, the channel region 108i, the source region 108s, and the drain region 108d are two-layer laminated structures of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3, respectively.

Further, the transistor 100G has a laminated structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 in the channel region 108i.

≪Band structure≫
Here, the band structures of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the insulating film 110, and the band structures of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110 are shown in FIG. Will be described using.

FIG. 9A is an example of a band structure in the film thickness direction of a laminated structure having an insulating film 104, an oxide semiconductor film 108_1, 108_2, 108_3, and an insulating film 110. Further, FIG. 9B is an example of a band structure in the film thickness direction of the laminated structure having the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110. The band structure shows the energy level (Ec) of the insulating film 104, the oxide semiconductor films 108_1, 108_2, 108_3, and the lower end of the conduction band of the insulating film 110 for easy understanding.

Further, FIG. 9A shows a metal oxide target in which silicon oxide films are used as the insulating films 104 and 110 and the atomic number ratio of the metal element is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. It is formed as an oxide semiconductor film 108_2 by using a metal oxide target having an atomic number ratio of a metal element of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed by using a metal oxide target having an atomic number ratio of metal elements of In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_3 is used. It is a band diagram.

Further, FIG. 9B shows metal oxidation in which silicon oxide films are used as the insulating films 104 and 110 and the atomic number ratio of the metal element is In: Ga: Zn = 4: 2: 4.1 as the oxide semiconductor film 108_2. An oxide semiconductor film formed by using an object target is used, and the oxide semiconductor film 108_3 is formed by using a metal oxide target having an atomic number ratio of a metal element of In: Ga: Zn = 1: 3: 2. It is a band diagram of the structure using an oxide semiconductor film.

As shown in FIG. 9A, in the oxide semiconductor films 108_1, 108_2, 108_3, the energy level at the lower end of the conduction band changes gently. Further, as shown in FIG. 9B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band structure, at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_2, the trap center or the recombination center is located. It is assumed that there are no impurities forming such a defect level.

In order to form a continuous bond on the oxide semiconductor films 108_1, 108_2, 108_3, a multi-chamber type film forming apparatus (sputtering apparatus) equipped with a load lock chamber is used to continuously make each film continuous without exposing them to the atmosphere. It is necessary to stack them.

With the configuration shown in FIGS. 9A and 9B, the oxide semiconductor film 108_2 becomes a well, and the channel region can be formed on the oxide semiconductor film 108_2 in the transistor using the laminated structure. Recognize.

By providing the oxide semiconductor films 108_1 and 108_3, the trap level that can be formed on the oxide semiconductor film 108_2 can be kept away from the oxide semiconductor film 108_2.

In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 that functions as a channel region, and electrons are likely to accumulate in the trap level. .. The accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. By doing so, it becomes difficult for electrons to accumulate at the trap level, the on-current of the transistor can be increased, and the field effect mobility can be increased.

Further, the oxide semiconductor films 108_1 and 108_3 have an energy level at the lower end of the conduction band closer to the vacuum level than the oxide semiconductor film 108_2, and typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2 is closer. The difference between the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, and 2 eV or less, or 1 eV or less.

With such a configuration, the oxide semiconductor film 108_2 becomes the main current path. That is, the oxide semiconductor film 108_2 has a function as a channel region, and the oxide semiconductor films 108_1 and 108_3 have a function as an oxide insulating film. Further, as the oxide semiconductor films 108_1 and 108_3, it is preferable to use an oxide semiconductor film composed of one or more of the metal elements constituting the oxide semiconductor film 108_2 on which the channel region is formed. With such a configuration, interfacial scattering is unlikely to occur at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2, or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Therefore, since the movement of the carrier is not hindered at the interface, the electric field effect mobility of the transistor is increased.

Further, the oxide semiconductor films 108_1 and 108_3 are made of materials having sufficiently low conductivity in order to prevent them from functioning as a part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be called oxide insulating films because of their physical properties and / or functions. Alternatively, the oxide semiconductor films 108_1 and 108_3 have an electron affinity (difference between the vacuum level and the energy level at the lower end of the conduction band) smaller than that of the oxide semiconductor film 108_2, and the energy level at the lower end of the conduction band is oxide. It is assumed that a material having a difference (band offset) with the energy level at the lower end of the conduction band of the semiconductor film 108_2 is used. Further, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is the conduction of the oxide semiconductor film 108_2. It is preferable to apply a material closer to the vacuum level than 0.2 eV than the energy level at the lower end of the band, preferably 0.5 eV or more and closer to the vacuum level.

Further, it is preferable that the oxide semiconductor films 108_1 and 108_3 do not contain a spinel-type crystal structure in the film. When the spinel-type crystal structure is contained in the oxide semiconductor films 108_1 and 108_3, the constituent elements of the conductive films 120s and 120d are transferred to the oxide semiconductor film 108_2 at the interface between the spinel-type crystal structure and another region. It may spread. When the oxide semiconductor films 108_1 and 108_3 are CAAC-OS, the blocking properties of the constituent elements of the conductive films 120s and 120d, for example, copper element, are high, which is preferable.

Further, in the present embodiment, oxide semiconductors formed as oxide semiconductor films 108_1 and 108_3 using a metal oxide target having an atomic number ratio of metal elements of In: Ga: Zn = 1: 3: 2. The configuration using a membrane has been illustrated, but the present invention is not limited to this. For example, as the oxide semiconductor films 108_1 and 108_3, In: Ga: Zn = 1: 1: 1 [atomic number ratio], In: Ga: Zn = 1: 1: 1.2 [atom number ratio], In: Ga. : Zn = 1: 3: 4 [atomic number ratio], or In: Ga: Zn = 1: 3: 6 [atomic number ratio], and oxide semiconductors formed using metal oxide targets in the vicinity thereof. A membrane may be used.

When a metal oxide target having In: Ga: Zn = 1: 1: 1 [atomic number ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2) may be obtained. When a metal oxide target having In: Ga: Zn = 1: 3: 4 [atomic number ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) may be obtained. When a metal oxide target having In: Ga: Zn = 1: 3: 6 [atomic number ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) may be obtained.

<1-4. Manufacturing method of semiconductor device 1>
Next, an example of the method for manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 10 to 12. 10 to 12 are cross-sectional views in the channel length (L) direction and the channel width (W) direction for explaining the method for manufacturing the transistor 100.

First, a conductive film to be a conductive film 106 is formed on the substrate 102, and then the conductive film is processed into an island shape to form the conductive film 106. Next, the insulating film 104 is formed on the substrate 102 and the conductive film 106, and the oxide semiconductor film is formed on the insulating film 104. Then, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107 (see FIG. 10 (A)).

The conductive film 106 can be formed by appropriately using a sputtering method, a CVD method, a thin film deposition method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like. In the present embodiment, a tungsten film having a thickness of 100 nm is formed as the conductive film 106 by a sputtering method.

The insulating film 104 can be formed by appropriately using a sputtering method, a CVD method, a thin film deposition method, a pulse laser deposition (PLD) method, a printing method, a coating method, or the like. In the present embodiment, a PECVD apparatus is used as the insulating film 104 to form a silicon nitride film having a thickness of 400 nm and a silicon oxide film having a thickness of 50 nm.

Further, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecule ions and the like. Further, as the addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Further, after forming a film that suppresses the desorption of oxygen on the insulating film, oxygen may be added to the insulating film 104 via the film.

As the above-mentioned film that suppresses the desorption of oxygen, a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, and the above-mentioned metal element are contained. Materials having conductivity such as alloys, alloys combining the above-mentioned metal elements, metal nitrides having the above-mentioned metal elements, metal oxides having the above-mentioned metal elements, and metal nitride oxides having the above-mentioned metal elements. Can be formed using.

Further, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulse laser vapor deposition method, a laser ablation method, a thermal CVD method, or the like. The oxide semiconductor film 107 can be processed by forming a mask on the oxide semiconductor film by a lithography step and then etching a part of the oxide semiconductor film using the mask. Further, the oxide semiconductor film 107 in which the elements are separated may be directly formed by using a printing method.

When the oxide semiconductor film is formed by the sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be appropriately used as the power supply device for generating plasma. Further, as the sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), an oxygen, a rare gas, and a mixed gas of oxygen are appropriately used. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

When forming an oxide semiconductor film, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. or higher and 750 ° C. or lower, or 150 ° C. or higher and 450 ° C. or lower, or 200 ° C. or higher and 350 ° C. or lower. It is preferable to form a film because the crystallinity can be enhanced.

In the present embodiment, a sputtering apparatus is used as the oxide semiconductor film 107, and an In—Ga—Zn metal oxide (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio] is used as the sputtering target. ]) Is used to form an oxide semiconductor film having a film thickness of 40 nm.

Further, after forming the oxide semiconductor film 107, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, or 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

The heat treatment can be carried out in an atmosphere of a rare gas such as helium, neon, argon, xenon, krypton, or an inert gas containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. It is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water or the like. The processing time may be 3 minutes or more and 24 hours or less.

An electric furnace, an RTA device, or the like can be used for the heat treatment. By using the RTA device, the heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

By forming a film while heating the oxide semiconductor film, or by performing heat treatment after forming the oxide semiconductor film, the hydrogen concentration obtained by the secondary ion mass analysis method in the oxide semiconductor film is 5 × 10. ¹⁹ atoms / cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, Alternatively, it can be 1 × 10 ¹⁶ atoms / cm ^{3 or less.}

Next, the insulating film 110_0 is formed on the insulating film 104 and the oxide semiconductor film 107 (see FIG. 10B).

As the insulating film 110_0, a silicon oxide film or a silicon nitride nitride film can be formed by using the PECVD method. In this case, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, fluorinated silane and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide and the like.

Further, as the insulating film 110_0, a PECVD method is used in which the oxidizing gas with respect to the deposited gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the treatment chamber is less than 100 Pa or 50 Pa or less. Therefore, a silicon oxide film having a small amount of defects can be formed.

Further, as the insulating film 110_0, the substrate placed in the vacuum-exhausted processing chamber of the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the treatment chamber at 20 Pa or higher and 250 Pa or higher. Hereinafter, more preferably, it is set to 100 Pa or more and 250 Pa or less, and a dense silicon oxide film or silicon oxide nitride film can be formed as the insulating film 110_0 under the condition of supplying high frequency power to the electrodes provided in the processing chamber.

Further, the insulating film 110_0 may be formed by using a plasma CVD method using microwaves. Microwave refers to the frequency range of 300 MHz to 300 GHz. In microwaves, the electron temperature is low and the electron energy is low. In addition, the supplied power has a small proportion used for accelerating electrons, can be used for dissociation and ionization of more molecules, and can excite a high-density plasma (high-density plasma). .. Therefore, it is possible to form the insulating film 110_0 with less plasma damage to the surface to be filmed and deposits and less defects.

Further, the insulating film 110_0 can be formed by using a CVD method using an organic silane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. Silicon-containing compounds such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), and trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) _{3) can be used.} can. By using the CVD method using an organic silane gas, an insulating film 110_0 having a high coating property can be formed.

In the present embodiment, a PECVD apparatus is used as the insulating film 110_0 to form a silicon oxide film having a thickness of 100 nm.

Next, a mask is formed at a desired position on the insulating film 110_0 by lithography, and then a part of the insulating film 110_0 and the insulating film 104 is etched to form an opening 143 reaching the conductive film 106.

As a method for forming the opening 143, a wet etching method and / or a dry etching method can be appropriately used. In the present embodiment, the dry etching method is used to form the opening 143.

Next, the conductive film 112_0 is formed on the insulating film 110_0 so as to cover the opening 143. When the conductive film 112_0 is formed, oxygen is added from the conductive film 112_0 into the insulating film 110_0 (see FIG. 10C).

As a method for forming the conductive film 112_0, it is preferable to use a sputtering method and form the conductive film 112_0 in an atmosphere containing oxygen gas at the time of formation. By forming the conductive film 112_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be suitably added to the insulating film 110_0.

In FIG. 10C, the oxygen added to the insulating film 110_0 is schematically represented by an arrow. Further, by forming the conductive film 112_0 so as to cover the opening 143, the conductive film 106 and the conductive film 112_0 are electrically connected. As the conductive film 112_0, the same material as the oxide semiconductor film 107 described above can be used.

In the present embodiment, a sputtering apparatus is used as the conductive film 112_0, and an In-Ga-Zn metal oxide (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) is used as the sputtering target. Then, an oxide semiconductor film having a film thickness of 100 nm is formed.

Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process (see FIG. 10 (D)).

Next, the conductive film 112_0 and the insulating film 110_0 are processed by etching from above the mask 140, and then the island-shaped conductive film 112 and the island-shaped insulating film are removed by removing the mask 140. It forms with 110 (see FIG. 11 (A)).

In the present embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by using a dry etching method.

When the conductive film 112 and the insulating film 110 are processed, the film thickness of the oxide semiconductor film 107 in the region where the conductive film 112 does not overlap may be reduced. Alternatively, when the conductive film 112 and the insulating film 110 are processed, the film thickness of the insulating film 104 in the region where the oxide semiconductor film 107 does not overlap may be reduced.

Next, the impurity element 145 is added from the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 11B).

Examples of the method for adding the impurity element 145 include an ion doping method, an ion implantation method, and a plasma treatment method. In the case of the plasma treatment method, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. As the device for generating the plasma, a dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, or the like can be used.

The raw material gas for the impurity element 145 is B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H _2, and noble. One or more of the gases can be used. Alternatively, one or more of _{B 2} H ₆ , PH ₃ , N ₂ , NH ₃ , Al _{H 3} , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. Oxide semiconductor film 107 and one or more of _{B 2} H ₆ , PH ₃ , N ₂ , NH ₃ , Al _{H 3} , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas. By adding to the conductive film 112, one or more of rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 107 and the conductive film 112.

Alternatively, after adding the noble gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , Al H ₃ , AlCl ₃ , SiH ₄ , Si _{2 H 6} , F ₂ , HF, and H ₂ . The above may be added to the oxide semiconductor film 107 and the conductive film 112.

Alternatively, after adding one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H _{2, rare.} Gas may be added to the oxide semiconductor film 107 and the conductive film 112.

The addition of the impurity element 145 may be controlled by appropriately setting injection conditions such as an acceleration voltage and a dose amount. For example, when argon is added by the ion implantation method, the acceleration voltage may be 10 kV or more and 100 kV or less, and the dose amount may be 1 × 10 ¹³ ions / cm ² or more and 1 × 10 ¹⁶ ions / cm ² or less. It may be ^{10 14} ions / cm ^2. When phosphorus ions are added by the ion implantation method, the acceleration voltage may be 30 kV and the dose amount may be 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less. For example, 1 × 10 ¹⁵ ions. It may be set to / cm ^2.

Further, in the present embodiment, the configuration in which the impurity element 145 is added after removing the mask 140 has been illustrated, but the present invention is not limited to this, and for example, the impurity element 145 is added while the mask 140 remains. Additions may be made.

Further, in the present embodiment, as the impurity element 145, argon is added to the oxide semiconductor film 107 and the conductive film 112 by using a doping device. In the present embodiment, the configuration in which argon is added as the impurity element 145 has been illustrated, but the present invention is not limited to this, and for example, the step of adding the impurity element 145 may not be performed.

Next, the insulating film 116 is formed on the insulating film 104, the oxide semiconductor film 107, and the conductive film 112. By forming the insulating film 116, the oxide semiconductor film 107 in contact with the insulating film 116 becomes a source region 108s and a drain region 108d. Further, the oxide semiconductor film 107 that is not in contact with the insulating film 116, or in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110, is in the channel region 108i. As a result, an oxide semiconductor film 108 having a channel region 108i, a source region 108s, and a drain region 108d is formed (see FIG. 11C).

The insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. In the present embodiment, a PECVD apparatus is used as the insulating film 116 to form a silicon nitride film having a thickness of 100 nm.

By using a silicon nitride film as the insulating film 116, hydrogen in the silicon nitride film enters the conductive film 112, the source region 108s, and the drain region 108d in contact with the insulating film 116, and the conductive film 112, the source region 108s, and the drain The carrier density of the region 108d can be increased.

Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 11 (D)).

The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. In the present embodiment, a PECVD apparatus is used as the insulating film 118 to form a silicon oxide nitride film having a thickness of 300 nm.

Next, a mask is formed at a desired position of the insulating film 118 by lithography, and then a part of the insulating film 118 and the insulating film 116 is etched to form an opening 141s reaching the source region 108s and a drain region 108d. An opening 141d is formed (see FIG. 12 (A)).

As a method for etching the insulating film 118 and the insulating film 116, a wet etching method and / or a dry etching method can be appropriately used. In the present embodiment, the insulating film 118 and the insulating film 116 are processed by using a dry etching method.

Next, the conductive film 120 is formed on the insulating film 118 so as to cover the openings 141s and 141d (see FIG. 12B).

The conductive film 120 can be formed by selecting a material that can be used for the conductive films 120s and 120d. In the present embodiment, a sputtering device is used as the conductive film 120 to form a laminated film of a titanium film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm.

Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then a part of the conductive film 120 is etched to form conductive films 120s and 120d (see FIG. 12C). ..

As a processing method of the conductive film 120, a wet etching method and / or a dry etching method can be appropriately used. In the present embodiment, the conductive film 120 is processed by using the dry etching method to form the conductive films 120s and 120d.

By the above steps, the transistor 100 shown in FIG. 1 can be manufactured.

The films (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 include a sputtering method, a chemical vapor deposition (CVD) method, a vacuum vapor deposition method, a pulse laser deposition (PLD) method, and an ALD (atomic layer). It can be formed by using the layer deposition method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may also be used. An example of the thermal CVD method is the MOCVD (organometallic chemical vapor deposition) method.

In the thermal CVD method, a film is formed by setting the inside of the chamber under atmospheric pressure or reduced pressure, sending the raw material gas and the oxidizing agent into the chamber at the same time, reacting them in the vicinity of the substrate or on the substrate, and depositing them on the substrate. As described above, since the thermal CVD method is a film forming method that does not generate plasma, it has an advantage that defects are not generated due to plasma damage.

Further, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, the raw material gas for the reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas (argon, nitrogen, etc.) may be introduced as a carrier gas together with the raw material gas. For example, two or more kinds of raw material gases may be supplied to the chamber in order. At that time, after the reaction of the first raw material gas, the inert gas is introduced and the second raw material gas is introduced so that the plurality of kinds of raw material gases are not mixed. Alternatively, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum exhaust, and then the second raw material gas may be introduced. The first raw material gas is adsorbed and reacted on the surface of the substrate to form a first layer, and the second raw material gas introduced later is adsorbed and reacted, and the second layer is the first layer. It is laminated on top to form a thin film. By repeating this process a plurality of times until the desired thickness is obtained while controlling the gas introduction order, a thin film having excellent step covering property can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction is repeated, the film thickness can be precisely adjusted, which is suitable for manufacturing a fine FET.

A thermal CVD method such as the MOCVD method can form a film such as the conductive film, an insulating film, an oxide semiconductor film, or a metal oxide film described above, and for example, an In-Ga-Zn-O film is formed. In some cases, trimethylgallium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and dimethylzinc are used (Zn (CH ₃ ) ₂ ). The combination is not limited to these, and triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used _{instead of trimethylgallium, and diethylzinc (Zn (C 2} H ₅ ) ₂ ) can be used instead of dimethylzinc. You can also do it.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDHA, Hf [N (CH ₃ ) ₂ ] _{2] 4} ) and and tetrakis (ethylmethylamido) material gases hafnium amide) is vaporized, such as hafnium, using two types of gas ozone (O ₃₎ as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al (CH ₃ ) ₃ ), etc.) is vaporized with a raw material gas. , using two types of gases _{H 2} O as the oxidizing agent. Other materials include tris (dimethylamide) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptaneto) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the surface to be formed _{, and radicals of an oxidizing gas (O 2} , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are formed. To form a tungsten film using. In addition, _{SiH 4} gas may be used instead of _{B 2} H _{6 gas.}

For example, when an oxide semiconductor film, for example, an In-Ga-Zn-O film is formed by a film forming apparatus using ALD, an In-O layer is formed using _{In (CH 3} ) ₃ gas and O _{3 gas.} After that, a GaO layer is formed using _{Ga (CH 3} ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using _{Zn (CH 3} ) ₂ gas and O _{3 gas.} The order of these layers is not limited to this example. Further, these gases may be used to form a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, and a Ga—Zn—O layer. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

<1-5. Manufacturing method of semiconductor device 2>
Next, an example of the method for manufacturing the transistor 100C shown in FIG. 4 will be described with reference to FIGS. 13 to 16. 13 to 16 are cross-sectional views in the channel length (L) direction and the channel width (W) direction for explaining the method for manufacturing the transistor 100C.

First, the conductive film 106 is formed on the substrate 102. Next, the insulating film 104 is formed on the substrate 102 and the conductive film 106, and the oxide semiconductor film is formed on the insulating film 104. Then, the oxide semiconductor film is processed into an island shape to form the oxide semiconductor film 107 (see FIG. 13 (A)).

Next, the insulating film 110_0 is formed on the insulating film 104 and the oxide semiconductor film 107 (see FIG. 13B).

Next, a mask is formed at a desired position on the insulating film 110_0 by lithography, and then a part of the insulating film 110_0 and the insulating film 104 is etched to form an opening 143 reaching the conductive film 106 (FIG. FIG. 13 (C)).

Next, the conductive film 112_0 is formed on the insulating film 110_0 so as to cover the opening 143. When the conductive film 112_0 is formed, oxygen is added from the conductive film 112_0 into the insulating film 110_0 (see FIG. 13 (D)).

In FIG. 13D, the oxygen added to the insulating film 110_0 is schematically represented by an arrow. Further, by forming the conductive film 112_0 so as to cover the opening 143, the conductive film 106 and the conductive film 112_0 are electrically connected.

Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process (see FIG. 14 (A)).

Next, the conductive film 112_0 is processed by etching from above the mask 140 to form an island-shaped conductive film 112 (see FIG. 14B).

In the present embodiment, the conductive film 112_0 is processed by using the wet etching method.

Subsequently, the insulating film 110_0 is processed by etching from above the mask 140 to form the island-shaped insulating film 110 (see FIG. 14C).

In the present embodiment, the insulating film 110_0 is processed by using a dry etching method.

Next, after removing the mask 140, the impurity element 145 is added from the insulating film 104, the oxide semiconductor film 107, and the conductive film 112 (see FIG. 14D).

When the impurity element 145 is added, many impurities are added to the region where the surface of the oxide semiconductor film 107 is exposed (the region that later becomes the source region 108s and the drain region 108d). On the other hand, the impurity element 145 is added via the insulating film 110 to the region where the conductive film 112 of the oxide semiconductor film 107 does not overlap and the insulating film 110 overlaps (the region which later becomes the region 108f). , The amount of the impurity element 145 added is smaller than that of the source region 108s and the drain region 108d.

Further, in the present embodiment, as the impurity element 145, argon is added to the oxide semiconductor film 107 and the conductive film 112 by using a doping device.

In the present embodiment, the configuration in which argon is added as the impurity element 145 has been illustrated, but the present invention is not limited to this, and for example, the step of adding the impurity element 145 may not be performed. When the step of adding the impurity element 145 is not performed, the region 108f has an impurity concentration equivalent to that of the channel region 108i.

Next, the insulating film 116 is formed on the insulating film 104, the oxide semiconductor film 107, the insulating film 110, and the conductive film 112. By forming the insulating film 116, the oxide semiconductor film 107 in contact with the insulating film 116 becomes a source region 108s and a drain region 108d. Further, the oxide semiconductor film 107 that is not in contact with the insulating film 116, or in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110, is in the channel region 108i. As a result, an oxide semiconductor film 108 having a channel region 108i, a source region 108s, and a drain region 108d is formed (see FIG. 15 (A)).

A region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 15B).

Next, a mask is formed at a desired position of the insulating film 118 by lithography, and then a part of the insulating film 118 and the insulating film 116 is etched to form an opening 141s reaching the source region 108s and a drain region 108d. An opening 141d is formed (see FIG. 15C).

Next, the insulating film 122 is formed on the insulating film 118 (see FIG. 15 (D)).

The insulating film 122 has a function as a flattening insulating film. Further, the insulating film 122 has an opening at a position overlapping the opening 141s and the opening 141d.

In the present embodiment, the insulating film 122 has an opening by applying a photosensitive acrylic resin as the insulating film 122 using a spin coater device and then exposing a desired region of the acrylic resin to light. To form.

Next, the conductive film 120 is formed on the insulating film 122 so as to cover the openings 141s and 141d (see FIG. 16A).

Next, a mask is formed at a desired position on the conductive film 120 by a lithography process, and then a part of the conductive film 120 is etched to form conductive films 120s and 120d (see FIG. 16B). ..

In the present embodiment, a dry etching method is used for processing the conductive film 120. Further, when the conductive film 120 is processed, a part of the upper part of the insulating film 122 may be removed.

By the above steps, the transistor 100C shown in FIG. 4 can be manufactured.

At the time of manufacturing the above transistor 100C, the insulating film 104, the oxide semiconductor film 107, the insulating film 110_0, the conductive film 112_0, the impurity element 145, the insulating film 116, the insulating film 118, the openings 141s, 141d, and the conductive film. As 120, <1-4. It can be formed by referring to the contents described in Method 1> for manufacturing a semiconductor device.

Further, in the present embodiment, an example in which the transistor has an oxide semiconductor film has been shown, but one aspect of the present invention is not limited to this. In one aspect of the invention, the transistor does not have to have an oxide semiconductor film. As an example, it is formed of a material having Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. in the channel region, the vicinity of the channel region, the source region, or the drain region of the transistor. You may.

As described above, the configuration and method shown in this embodiment can be used in appropriate combination with the configuration and method shown in other embodiments.

(Embodiment 2)
In the present embodiment, the structure of the oxide semiconductor and the like will be described with reference to FIGS. 17 to 21.

<2-1. Structure of oxide semiconductor>
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis-aligned crystal linear semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphic oxide semiconductor (a-like). : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic and have no heterogeneous structure, are in a metastable state with unfixed atomic arrangements, have flexible bond angles, have short-range order but long-range order. It is said that it does not have.

From the opposite point of view, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic, but has an unstable structure having voids (also referred to as voids). In terms of instability, the a-like OS is physically close to an amorphous oxide semiconductor.

<2-2. CAAC-OS>
First, CAAC-OS will be described.

CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis oriented crystal portions (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when a structural analysis by the out-of-plane method is performed on CAAC-OS having crystals of _{InGaZnO 4} classified in the space group R-3m, the diffraction angle (2θ) is as shown in FIG. 17 (A). A peak appears near 31 °. Since this peak is _{attributed to the (009) plane of the InGaZnO 4} crystal, in CAAC-OS, the crystal has c-axis orientation and the c-axis forms the CAAC-OS film (formed). It can be confirmed that the surface is oriented substantially perpendicular to the surface) or the upper surface. In addition to the peak where 2θ is in the vicinity of 31 °, a peak may appear in the vicinity where 2θ is in the vicinity of 36 °. The peak in which 2θ is in the vicinity of 36 ° is due to the crystal structure classified in the space group Fd-3m. Therefore, it is preferable that CAAC-OS does not show the peak.

On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction parallel to the surface to be formed, a peak appears in the vicinity of 2θ at 56 °. This peak is attributed to the (110) plane of _{the InGaZnO 4 crystal.} Then, even if 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), it is clear as shown in FIG. 17 (B). No peak appears. On the other hand, _{when 2θ is fixed in the vicinity of 56 ° and φ-scanned with respect to the single crystal InGaZnO 4} , six peaks assigned to the crystal plane equivalent to the (110) plane are observed as shown in FIG. 17 (C). Will be done. Therefore, from the structural analysis using XRD, it can be confirmed that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, _{when an electron beam having a probe diameter of 300 nm is incident on a CAAC-OS having a crystal of InGaZnO 4} in parallel with the surface to be formed of the CAAC-OS, a diffraction pattern (selected area) as shown in FIG. An electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of _{the InGaZnO 4 crystal.} Therefore, even by electron diffraction, it can be seen that the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 17 (E) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 17 (E), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction using an electron beam having a probe diameter of 300 nm. It is considered that the first ring in FIG. 17 (E) is caused by the (010) plane and the (100) plane of the crystal of _{InGaZnO 4.} Further, it is considered that the second ring in FIG. 17 (E) is caused by the surface (110) and the like.

In addition, when observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of pellets can be confirmed. Can be done. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) may not be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

FIG. 18A shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface. The spherical aberration correction (Spherical Aberration Director) function was used for observing the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 18A, pellets, which are regions in which metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, pellets can also be referred to as nanocrystals (nc: nanocrystals). Further, CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals). The pellet reflects the unevenness of the surface to be formed or the upper surface of the CAAC-OS film, and is parallel to the surface to be formed or the upper surface of CAAC-OS.

Further, FIGS. 18B and 18C show Cs-corrected high-resolution TEM images of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. 18 (D) and 18 (E) are images obtained by image-processing FIGS. 18 (B) and 18 (C), respectively. The image processing method will be described below. First, an FFT image is acquired by subjecting FIG. 18B to a fast Fourier transform (FFT) process. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image obtained in this way is called an FFT filtering image. The FFT filtering image is an image obtained by extracting periodic components from a Cs-corrected high-resolution TEM image, and shows a grid array.

In FIG. 18D, the disordered portion of the lattice arrangement is shown by a broken line. The area surrounded by the broken line is one pellet. The part indicated by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 18 (E), the portion where the orientation of the lattice arrangement is changed between the region where the grid arrangement is aligned and the region where another grid arrangement is aligned is shown by a dotted line, and the change in the orientation of the grid arrangement is shown by a dotted line. It is shown by a broken line. A clear grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding grid points around the grid points near the dotted line. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because CAAC-OS allows distortion due to the fact that the bond distance between atoms is not dense in the ab plane direction and that the bond distance between atoms changes due to the replacement of metal elements. It is thought that it can be done.

As shown above, CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, CAAC-OS can also be referred to as CAA crystal (c-axis-aligned a-b-plane-anchored crystal).

CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the mixing of impurities or the formation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.) from the opposite viewpoint.

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than a metal element constituting an oxide semiconductor, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in an oxide semiconductor may serve as a carrier trap or a carrier generation source. For example, oxygen deficiency in an oxide semiconductor may become a carrier trap, or may become a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor having a low carrier density. Specifically, carriers of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 / cm ³ or more. It can be a density oxide semiconductor. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

<2-3. nc-OS>
Next, nc-OS will be described.

The case where nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on nc-OS by the out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

Further, for example, when _{nc-OS having a crystal of InGaZnO 4} is sliced and an electron beam having a probe diameter of 50 nm is incident on a region having a thickness of 34 nm in parallel with the surface to be formed, FIG. 19 (A) shows. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. Further, FIG. 19B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 19B, a plurality of spots are observed in the ring-shaped region. Therefore, the order of the nc-OS is not confirmed by injecting an electron beam having a probe diameter of 50 nm, but the order is confirmed by injecting an electron beam having a probe diameter of 1 nm.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. 19C. May occur. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in the range of the thickness of less than 10 nm. Since the crystals are oriented in various directions, there are some regions where a regular electron diffraction pattern is not observed.

FIG. 19D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the surface to be formed. In a high-resolution TEM image, the nc-OS has a region where a crystal portion can be confirmed, such as a portion indicated by an auxiliary line, and a region where a clear crystal portion cannot be confirmed. The crystal portion contained in nc-OS has a size of 1 nm or more and 10 nm or less, and in particular, it often has a size of 1 nm or more and 3 nm or less. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, the crystal grain boundaries may not be clearly confirmed. It should be noted that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, in the following, the crystal part of nc-OS may be referred to as a pellet.

As described above, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor having higher regularity than the amorphous oxide semiconductor. Therefore, the defect level density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, the defect level density of nc-OS is higher than that of CAAC-OS.

<2-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

FIG. 20 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 20A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 20 (B) is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ^{− ) of 4.3 × 10 8} e ⁻ / nm ^2. From FIGS. 20 (A) and 20 (B), it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is presumed to be a void or a low density region.

Due to its porosity, the a-like OS has an unstable structure. In the following, in order to show that the a-like OS has an unstable structure as compared with CAAC-OS and nc-OS, the structural change due to electron irradiation is shown.

As samples, a-like OS, nc-OS and CAAC-OS are prepared. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. According to the high-resolution cross-sectional TEM image, each sample has a crystal part.

The unit cell of the crystal of InGaZnO ₄ has a structure in which a total of 9 layers are layered in the c-axis direction, having 3 In—O layers and 6 Ga—Zn—O layers. Are known. The distance between these adjacent layers is about the same as the grid plane distance (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, in the following, the portion where the interval between the plaids is 0.28 nm or more and 0.30 nm or less is regarded as the crystal portion of _{InGaZnO 4.} The plaids correspond to the ab planes of _{the InGaZnO 4 crystal.}

FIG. 21 is an example of investigating the average size of the crystal portions (22 to 30 locations) of each sample. The length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 21, it can be seen that in the a-like OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image and the like. From FIG. 21, in the initially observed by TEM (also referred to as initial nuclei.) Crystal portion was a size of about 1.2nm and electrons (e ^-) cumulative dose is 4.2 × ¹⁰ 8 ^e of the - / nm ^It can be seen that in No. 2, it has grown to a size of about 1.9 nm. On the other hand, in nc-OS and CAAC-OS, there is no change in the size of the crystal part in the range where ^{the cumulative electron irradiation amount is 4.2 × 10 8} e ⁻ / nm ^{2 from the start of electron irradiation.} I understand. From FIG. 21, it can be seen that the sizes of the crystal portions of nc-OS and CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative irradiation amount of electrons. A Hitachi transmission electron microscope H-9000 NAR was used for electron beam irradiation and TEM observation. Electron beam irradiation conditions, the acceleration voltage 300 kV, current density ^{6.7 × 10 5 e - / (} nm 2 · s), the diameter of the irradiated area was 230 nm.

As described above, in the a-like OS, growth of the crystal portion may be observed by electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of the crystal part due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a structure having a lower density than that of the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Further, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], _{the density of the single crystal InGaZnO 4} having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. .. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm ³ or more and 6.3 g /. It will be less than cm ^3.

When single crystals having the same composition do not exist, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics. The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

As described above, the configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a display device having a transistor illustrated in the previous embodiment will be described below with reference to FIG. 22.

<3. Display device configuration example>
FIG. 22 is a cross-sectional view showing a configuration example of a part of the display device according to one aspect of the present invention. The display device shown in FIG. 22 includes a transistor 202, a transistor 212, a transistor 221 and a light emitting element 204, and a photodiode 206. As the transistor 202, the transistor 212, and the transistor 221, it is preferable to use the transistor exemplified in the above embodiment, and it is preferable that the transistor 212 has a function of exhibiting light including infrared rays.

The transistor 212 includes a conductive film 2025 that functions as a gate electrode, a conductive film 2021 that functions as a source electrode, a conductive film 2022 that functions as a drain electrode, an oxide semiconductor film 2020, and an oxide provided on a substrate 200 having an insulating surface. It has a gate insulating film 2023 provided on the semiconductor film 2020, and a conductive film 2024 provided on the gate insulating film 2023 and functioning as a gate electrode. Further, as the transistor 202 and the transistor 221 it is possible to apply a transistor having the same structure as the transistor 212. Here, an example in which the transistors 202, 212, and 221 are configured by using an oxide semiconductor film has been shown, but these are configured by using single crystal silicon, polycrystalline silicon, or amorphous silicon. It is also possible to do. Further, although the examples in which the transistors 202, 212, and 221 have an s-channel structure are shown here, these structures may be top gate type or bottom gate type transistors.

The photodiode 206 may have any structure as long as it is a photodiode that generates a photocurrent when irradiated with infrared rays. As the photodiode 206, an element having selenium or a compound containing selenium, or an element having silicon (for example, an element having a pin-type or pn-type junction formed) can be used. Further, the structure of the photodiode 206 is preferably selected according to a target wavelength. For example, it is preferable to use a photodiode composed of amorphous silicon to detect the wavelength region of visible light, and single crystal silicon or polycrystalline silicon is used to detect the wavelength region including infrared rays. It is preferable to apply a configured photodiode.

An insulating film 230 is provided on the transistors 202, 212, and 221. Further, one of the source electrode and the drain electrode included in the transistors 202 and 221 is connected to the conductive film 241 and the conductive film 242 at the opening of the insulating film 230. Further, an insulating film 250 is provided on the conductive film 241 and the conductive film 242.

The light emitting element 204 comprises a conductive film 261 connected to the conductive film 241 at the opening of the insulating film 250, a light emitting layer 270 provided on the conductive film 261 and a conductive film 280 provided on the light emitting layer 270. Have. Further, the photodiode 206 has a conductive film 262 connected to the conductive film 242 at the opening of the insulating film 250, a photoelectric conversion layer 290 provided on the conductive film 262, and a conductivity provided on the photoelectric conversion layer 290. It has a membrane 280 and. As described above, the conductive film 280 may be shared in the light emitting element 204 and the photodiode 206 shown in FIG. This makes it possible to easily manufacture a display element and an imaging element.

Here, the light emitting layer 270 can emit light 2301 (W) that exhibits white color due to the current generated between the conductive film 261 and the conductive film 280. Alternatively, the light may have at least one of a wavelength of light exhibiting red, a wavelength of light exhibiting green, a wavelength of light exhibiting blue, and a wavelength of light exhibiting yellow. For example, as the light emitting element 204, a light emitting element having a light emitting organic material (also referred to as an organic electroluminescence element or an organic EL element) or a light emitting element having a light emitting quantum dot can be applied. Further, here, the conductive film 280 is formed of a conductive film having translucency. As a result, the light emitting element 204 can emit light 2301 (W) at least in the direction of the electrode provided with the conductive film 280. Further, here, the partition wall 291 is provided at the ends of the conductive films 261 and 262 and at the opening of the insulating film 250. The partition wall is a layer made of an organic or inorganic insulating material. By providing the partition wall 291, it is possible to prevent a short circuit between the conductive film 261 or the conductive film 262 and the conductive film 280, and it is possible to suppress the step breakage of the light emitting layer 270. Further, here, the light emitting element 204 is provided so as to overlap with the transistor 202. This makes it possible to improve the area of the light emitting element 204 (opening ratio of the display device).

Further, the display device shown in FIG. 22 has a sealing substrate 310 provided with a color filter 300 and having translucency. The region where the light emitting element 204 and the like are present is sealed by the substrate 200 having an insulating surface and the sealing substrate 310. This makes it possible to prevent water from entering the light emitting element 204, the photodiode 206, and the like, and improve the reliability of the display device. Further, the color filter 300 is provided directly above the region where the light emitting element 204 is provided. The color filter 300 can absorb light having a wavelength in a specific range contained in the white light 2301 (W) emitted from the light emitting element 204 and change it into chromatic light 2302 (C). be. Here, the chromatic color is at least one of red, green, blue, and yellow.

Further, the color filter 300 is not provided directly above the transistor 212 and the photodiode 206. Therefore, in the display device shown in FIG. 22, the infrared rays 2201 (IR) having infrared rays emitted by the transistor 212 are applied to the detected object 2101 such as a finger or a pen, and the infrared rays reflected by the detected object 2101. By irradiating the photodiode 206 with the light 2202 (IR) having the light 2202 (IR), it is possible to take an image of the object to be detected 2101.

It is preferable that the transistor 212 can emit strong light instantaneously. Therefore, the current drive capability of the transistor 212 is preferably higher than the current drive capability of the transistor 202 and the transistor 212. For example, it is preferable that the (W / L) value of the transistor 212 is larger than the (W / L) value of the transistor 202 and the transistor 221. Here, W represents the channel width and L represents the channel length.

In this way, by performing imaging using invisible light (IR) including light having a wavelength in the infrared region, imaging can be performed without affecting the display on the display device. Further, since it is possible to increase the intensity of the invisible light (IR) without considering the influence on the display, it is possible to reduce the influence of external light on the image pickup in the image sensor and improve the detection accuracy. It becomes. Further, since the display device images the object to be detected by light having infrared rays, it is possible to detect the object to be detected and the object to be detected that do not come into contact with the display device, and the number of objects to be detected is singular. It can be detected even if there are a plurality of them.

As described above, the configuration and method shown in this embodiment can be used in appropriate combination with the configuration and method shown in other embodiments.

(Embodiment 4)
In the present embodiment, an example of the display device having the transistor illustrated in the previous embodiment will be described below with reference to FIGS. 23 to 25.

FIG. 23 is a top view showing an example of the display device. The display device 700 shown in FIG. 23 includes a pixel unit 702 provided on the first substrate 701, a source driver 704 and a gate driver 706 provided on the first substrate 701, a pixel unit 702, and a source driver 704. And a sealing material 712 arranged so as to surround the gate driver 706, and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealing material 712. That is, the pixel portion 702, the source driver 704, and the gate driver 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 23, a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display device 700 electrically has a pixel portion 702, a source driver 704, a gate driver 706, and a gate driver 706 in a region different from the region surrounded by the sealing material 712 on the first substrate 701. An FPC terminal unit 708 (FPC: Flexible printed circuit board) connected to the FPC terminal unit 708 (FPC) is provided. Further, the FPC 716 is connected to the FPC terminal unit 708, and various signals and the like are supplied to the pixel unit 702, the source driver 704, and the gate driver 706 by the FPC 716. Further, a signal line 710 is connected to each of the pixel unit 702, the source driver 704, the gate driver 706, and the FPC terminal unit 708. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver 704, the gate driver 706, and the FPC terminal unit 708 via the signal line 710.

Further, the display device 700 may be provided with a plurality of gate drivers 706 and source drivers 704. Further, as the display device 700, an example in which the source driver 704 and the gate driver 706 are formed on the same first substrate 701 as the pixel portion 702 is shown, but the present invention is not limited to this configuration. For example, only the gate driver 706 may be formed on the first substrate 701, or only the source driver 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver, a gate driver, or the like is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. The method for connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Further, the pixel unit 702, the source driver 704, and the gate driver 706 of the display device 700 have a plurality of transistors, and the transistor which is the semiconductor device of one aspect of the present invention can be applied.

Further, the display device 700 can have various elements. Examples of the element include an electroluminescence (EL) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element, an LED, etc.), a light emitting transistor element (a transistor that emits light according to a current), and an electron. Emission element, liquid crystal element, electronic ink element, electrophoresis element, electrowetting element, plasma display (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror device) (DMD), digital micro shutter (DMS) devices, interferometric modulation (IMOD) devices, etc.), piezoelectric ceramic displays, and the like. Further, the display device 700 may have a sensor, and it is preferable that the sensor has a function of imaging an object to be detected by light having infrared rays.

Further, as an example of a display device using an EL element, there is an EL display or the like. An example of a display device using an electron emitting element is a field emission display (FED) or a surface-conduction electron-emitter display (SED). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using an electronic ink element or an electrophoresis element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display device 700, a progressive method, an interlaced method, or the like can be used. Further, the color elements controlled by the pixels at the time of color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, the pixels for color display may be composed of pixels composed of four color elements of R, G, B, and W (white). Alternatively, as in the pentile array, one pixel may be composed of color elements for two colors of RGB, and other color elements may be added for color display. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

Further, in order to display the display device in full color by using white light emission (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.), a colored layer (also referred to as a color filter) may be used. good. As the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be appropriately combined and used. By using the colored layer, the color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part thereof, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% at the time of bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from an element having each emission color. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) in which a part of the light emission from the above-mentioned white light emission is converted into red, green, and blue by passing through a color filter, red, green, and blue light emission. (Three-color method) or a method of converting a part of the light emitted from the blue light to red or green (color conversion method, quantum dot method) may be applied.

In the present embodiment, a configuration in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 24 and 25. Note that FIG. 24 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 23, and has a configuration in which a liquid crystal element is used as the display element. Further, FIG. 25 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 23, and has a configuration in which an EL element is used as a display element.

First, the common parts shown in FIGS. 24 and 25 will be described first, and then the different parts will be described below.

<4-1. Explanation of common parts of display devices>
The display device 700 shown in FIGS. 23 to 25 includes a routing wiring unit 711, a pixel unit 702, a source driver 704, and an FPC terminal unit 708. Further, the routing wiring portion 711 has a signal line 710. Further, the pixel unit 702 has a transistor 750 and a capacitance element 790. Further, the source driver 704 has a transistor 752.

The transistor 750 and the transistor 752 have the same configuration as the transistor 100 shown above. Regarding the configuration of the transistor 750 and the transistor 752, other transistors shown in the previous embodiment may be used.

The transistor used in this embodiment has an oxide semiconductor film that is highly purified and suppresses the formation of oxygen deficiency. The transistor can reduce the off-current. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, the transistor used in the present embodiment can be driven at high speed because a relatively high field effect mobility can be obtained. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, also in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

The capacitive element 790 has a first oxide semiconductor film of the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, and a conductivity that functions as a source electrode and a drain electrode of the transistor 750. It has a film and an upper electrode formed through a step of processing the same conductive film. Further, a step of forming the same insulating film as the insulating film that functions as the second insulating film of the transistor 750 and the insulating film that functions as the third insulating film is formed between the lower electrode and the upper electrode. An insulating film is provided through the process. That is, the capacitive element 790 has a laminated structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

Further, in FIGS. 24 and 25, a flattening insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitive element 790.

As the flattening insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. The flattening insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials. Further, the flattening insulating film 770 may not be provided.

Further, the signal line 710 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. The signal line 710 is a conductive film formed through a process different from that of the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same process as an oxide semiconductor film functioning as a gate electrode. A membrane may be used. When, for example, a material containing copper is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen becomes possible.

Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778.

Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

<4-2. Configuration example of a display device using a liquid crystal element>
The display device 700 shown in FIG. 24 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the side of the second substrate 705 and has a function as a counter electrode. The display device 700 shown in FIG. 24 can display an image by controlling the transmission and non-transmission of light by changing the orientation state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774.

Further, the conductive film 772 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. Further, the conductive film 772 has a function as a reflective electrode. The display device 700 shown in FIG. 24 is a so-called reflective color liquid crystal display device that uses external light to reflect light by the conductive film 772 and display the light through the colored film 736.

As the conductive film 772, a conductive film that is translucent in visible light or a conductive film that is reflective in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective in visible light, for example, a material containing aluminum or silver may be used. In the present embodiment, as the conductive film 772, a conductive film having a reflective property in visible light is used.

Further, in the display device 700 shown in FIG. 24, unevenness is provided on a part of the flattening insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming a flattening insulating film 770 with a resin film and providing unevenness on the surface of the resin film. Further, the conductive film 772 that functions as a reflective electrode is formed along the unevenness. Therefore, when the external light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772, and the visibility can be improved.

Although the reflective color liquid crystal display device is illustrated in FIG. 24, the display device 700 according to one aspect of the present invention is not limited to this, for example, the conductive film 772 is transparent to visible light. A transmissive color liquid crystal display device may be obtained by using a certain conductive film. In the case of the transmissive color liquid crystal display device, the unevenness provided on the flattening insulating film 770 may not be provided.

Although not shown in FIG. 24, an alignment film may be provided on each side of the conductive films 772 and 774 in contact with the liquid crystal layer 776. Further, although not shown in FIG. 24, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an orientation treatment because it has a short response rate and is optically isotropic. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .. Further, the liquid crystal material showing the blue phase has a small viewing angle dependence.

When a liquid crystal element is used as the display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Birefringent Micro-Cell) mode, a Micro-cell mode A Compensated Birefringence mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.

Further, a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device adopting a vertical orientation (VA) mode may be used. As the vertical orientation mode, for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV mode and the like can be used.

<4-3. Display device using light emitting element>
The display device 700 shown in FIG. 25 has a light emitting element 782. The light emitting element 782 has a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 25 can display an image by emitting light from the EL layer 786 of the light emitting element 782.

Further, the conductive film 784 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that is translucent in visible light or a conductive film that is reflective in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective in visible light, for example, a material containing aluminum or silver may be used.

Further, in the display device 700 shown in FIG. 25, an insulating film 730 is provided on the flattening insulating film 770 and the conductive film 784. The insulating film 730 covers a part of the conductive film 784. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits the light emitted by the EL layer 786. In the present embodiment, the top emission structure is illustrated, but the present invention is not limited to this. For example, it can be applied to a bottom emission structure that emits light to the conductive film 784 side and a dual emission structure that emits light to both the conductive film 784 side and the conductive film 788 side.

Further, a colored film 736 is provided at a position where it overlaps with the light emitting element 782, and a light shielding film 738 is provided at a position where it overlaps with the insulating film 730, the routing wiring portion 711, and the source driver 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Further, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 25, a configuration in which the colored film 736 is provided has been illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed by different coating, the colored film 736 may not be provided.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 5)
In the present embodiment, an example of a circuit configuration of a semiconductor device capable of retaining the stored contents even in a situation where power is not supplied and having an unlimited number of writes will be described with reference to FIG. 26.

<5-1. Circuit configuration>
FIG. 26 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 26, the first wiring (1st Line) and one of the source electrode and the drain electrode of the p-type transistor 1280a are electrically connected. Further, the other of the source electrode or the drain electrode of the p-type transistor 1280a and one of the source electrode or the drain electrode of the n-type transistor 1280b are electrically connected. Further, the other of the source electrode or the drain electrode of the n-type transistor 1280b and one of the source electrode or the drain electrode of the n-type transistor 1280c are electrically connected.

Further, the second wiring (2nd Line) and one of the source electrode and the drain electrode of the transistor 1282 are electrically connected. Further, the other of the source electrode or the drain electrode of the transistor 1282, one of the electrodes of the capacitive element 1281 and the gate electrode of the n-type transistor 1280c are electrically connected.

Further, the third wiring (3rd Line) and the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b are electrically connected. Further, the fourth wiring (4th line) and the gate electrode of the transistor 1282 are electrically connected. Further, the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitive element 1281 and the other of the source electrode or drain electrode of the n-type transistor 1280c. Further, the sixth wiring (6th Line) and the other of the source electrode or drain electrode of the p-type transistor 1280a and one of the source electrode or drain electrode of the n-type transistor 1280b are electrically connected.

The transistor 1282 can be formed of an oxide semiconductor (OS). Therefore, in FIG. 26, the symbol “OS” is added to the transistor 1282. The transistor 1282 may be formed of a material other than the oxide semiconductor.

Further, in FIG. 26, a floating node (FN) is added at a connection point between the other of the source electrode or drain electrode of the transistor 1282, one of the electrodes of the capacitive element 1281, and the gate electrode of the n-type transistor 1280c. There is. By turning off the transistor 1282, it is possible to hold the potential given to the floating node, one of the electrodes of the capacitive element 1281, and the gate electrode of the n-type transistor 1280c.

In the circuit configuration shown in FIG. 26, information can be written, held, and read as follows by taking advantage of the feature that the potential of the gate electrode of the n-type transistor 1280c can be held.

<5-2. Writing and retaining information>
First, writing and holding of information will be described. The potential of the fourth wiring is set to the potential at which the transistor 1282 is in the ON state, and the transistor 1282 is in the ON state. As a result, the potential of the second wiring is given to the gate electrode of the n-type transistor 1280c and the capacitance element 1281. That is, a predetermined charge is given to the gate electrode of the n-type transistor 1280c (writing). After that, the potential of the fourth wiring is set to the potential at which the transistor 1282 is turned off, and the transistor 1282 is turned off. As a result, the electric charge given to the gate electrode of the n-type transistor 1280c is retained (retained).

Since the off-current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is retained for a long time.

<5-3. Reading information>
Next, reading information will be described. When the potential of the third wiring is set to the Low level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is given to the sixth wiring. On the other hand, when the potential of the third wiring is set to the high level potential, the p-type transistor 1280a is turned off and the n-type transistor 1280b is turned on. At this time, the sixth wiring takes different potentials depending on the amount of electric charge held in the floating node (FN). Therefore, the retained information can be read out (reading) by observing the potential of the sixth wiring.

Further, since the transistor 1282 uses an oxide semiconductor in the channel region, it is a transistor having an extremely small off-current. Since the off-current of the transistor 1282 using the oxide semiconductor is less than 1 / 100,000 of the off-current of the transistor formed of a silicon semiconductor or the like, it is accumulated in the floating node (FN) due to the leakage current of the transistor 1282. It is possible to ignore the loss of charge. That is, the transistor 1282 using the oxide semiconductor makes it possible to realize a non-volatile storage circuit capable of holding information without supplying electric power.

Further, by using a semiconductor device having such a circuit configuration as a storage device such as a register or a cache memory, it is possible to prevent data loss in the storage device due to a stop supply of the power supply voltage. Further, after restarting the power supply voltage supply, it is possible to return to the state before the power supply supply is stopped in a short time. Therefore, the power consumption of the entire storage device or one or a plurality of logic circuits constituting the storage device can be suppressed because the power supply can be stopped even for a short time in the standby state. Further, by using the semiconductor device for the sensor, the influence of noise can be reduced and the detection accuracy of the sensor can be improved. The sensor can use light having infrared rays.

As described above, the configurations and methods shown in the present embodiment can be used in appropriate combinations with the configurations and methods shown in other embodiments.

(Embodiment 6)
In the present embodiment, the configuration of the pixel circuit that can be used in the semiconductor device of one aspect of the present invention will be described below with reference to FIG. 27 (A).

<6-1. Pixel circuit configuration>
FIG. 27A is a diagram illustrating a configuration of a pixel circuit. The circuit shown in FIG. 27 (A) includes a photoelectric conversion element 1360, a transistor 1351, a transistor 1352, a transistor 1353, and a transistor 1354.

The anode of the photoelectric conversion element 1360 is electrically connected to the wiring 1316, and the cathode is connected to either the source electrode or the drain electrode of the transistor 1351. The other of the source electrode or drain electrode of the transistor 1351 is connected to the charge storage unit (FD), and the gate electrode is connected to the wiring 1312 (TX). One of the source electrode or drain electrode of transistor 1352 is connected to the wiring 1314 (GND), the other of the source electrode or drain electrode is connected to one of the source electrode or drain electrode of transistor 1354, and the gate electrode is a charge storage unit (FD). ) Is connected. One of the source or drain electrodes of the transistor 1353 is connected to the charge storage unit (FD), the other of the source or drain electrodes is connected to the wiring 1317, and the gate electrode is connected to the wiring 1311 (RS). The other of the source or drain electrodes of the transistor 1354 is connected to the wire 1315 (OUT) and the gate electrode is connected to the wire 1313 (SE). All of the above connections are electrical connections.

A potential such as GND, VSS, and VDD may be supplied to the wiring 1314. Here, the potential and voltage are relative. Therefore, the magnitude of the potential of GND is not always 0 volts.

The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current corresponding to the light incident on the pixel circuit. The transistor 1353 has a function of controlling the charge accumulation in the charge storage unit (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal corresponding to the potential of the charge storage unit (FD). The transistor 1352 has a function of resetting the potential of the charge storage unit (FD). The transistor 1352 has a function of controlling the selection of the pixel circuit at the time of reading.

The charge storage unit (FD) is a charge holding node and holds a charge that changes according to the amount of light received by the photoelectric conversion element 1360.

The transistor 1352 and the transistor 1354 may be connected in series between the wiring 1315 and the wiring 1314. Therefore, the wiring 1314, the transistor 1352, the transistor 1354, and the wiring 1315 may be arranged in this order, or the wiring 1314, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

The wiring 1311 (RS) has a function as a signal line for controlling the transistor 1353. The wiring 1312 (TX) has a function as a signal line for controlling the transistor 1351. The wiring 1313 (SE) has a function as a signal line for controlling the transistor 1354. The wiring 1314 (GND) has a function as a signal line for setting a reference potential (for example, GND). The wiring 1315 (OUT) has a function as a signal line for reading a signal output from the transistor 1352. The wiring 1316 has a function as a signal line for outputting a charge from the charge storage unit (FD) via the photoelectric conversion element 1360, and is a low potential line in the circuit of FIG. 27 (A). Further, the wiring 1317 has a function as a signal line for resetting the potential of the charge storage unit (FD), and is a high potential line in the circuit of FIG. 27 (A).

Next, the configuration of each element shown in FIG. 27 (A) will be described.

<6-2. Photoelectric conversion element>
As the photoelectric conversion element 1360, an element having selenium or a compound containing selenium (hereinafter, referred to as a selenium-based material) or an element having silicon (for example, an element in which a pin-type junction is formed) can be used. Further, it is preferable to combine a transistor using an oxide semiconductor and a photoelectric conversion element using a selenium-based material because reliability can be improved.

<6-3. Transistor>
The transistor 1351, transistor 1352, transistor 1353, and transistor 1354 can be formed by using silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon, but oxide semiconductors can be used. It is preferably formed by the transistor used. A transistor in which a channel region is formed of an oxide semiconductor has a characteristic of exhibiting extremely low off-current characteristics. Further, as the transistor in which the channel region is formed of the oxide semiconductor, for example, the transistor shown in the first embodiment can be used.

In particular, if the leakage current of the transistor 1351 and the transistor 1353 connected to the charge storage unit (FD) is large, the time that the charge stored in the charge storage unit (FD) can be held becomes insufficient. Therefore, by using a transistor using an oxide semiconductor for at least the two transistors, it is possible to prevent unnecessary charge from flowing out from the charge storage unit (FD).

Further, also in the transistor 1352 and the transistor 1354, if the leakage current is large, an unnecessary charge output occurs in the wiring 1314 or the wiring 1315. Therefore, as these transistors, a transistor having a channel region formed of an oxide semiconductor is used. Is preferable.

Further, in FIG. 27 (A), a transistor having one gate electrode configuration has been illustrated, but the present invention is not limited to this, and for example, a configuration having a plurality of gate electrodes may be used. The transistor having a plurality of gate electrodes may have, for example, a configuration having a first gate electrode and a second gate electrode (also referred to as a back gate electrode) that overlap the semiconductor film on which the channel region is formed. .. As the back gate electrode, for example, the same potential as the first gate electrode, floating, or a potential different from that of the first gate electrode may be applied.

<6-4. Circuit operation timing chart>
Next, an example of the operation of the circuit shown in FIG. 27 (A) will be described with reference to the timing chart shown in FIG. 27 (B).

For the sake of brief description in FIG. 27 (B), the potential of each wiring is given as a signal that changes by two values. However, since each potential is an analog signal, it can actually take various values, not limited to binary values, depending on the situation. The signal 1401 shown in FIG. 27 (B) is the potential of the wiring 1311 (RS), the signal 1402 is the potential of the wiring 1312 (TX), the signal 1403 is the potential of the wiring 1313 (SE), and the signal 1404 is the charge storage unit (FD). ), The signal 1405 corresponds to the potential of the wiring 1315 (OUT). The potential of the wiring 1316 is always "Low", and the potential of the wiring 1317 is always "High".

At time A, assuming that the potential of the wiring 1311 (signal 1401) is "High" and the potential of the wiring 1312 (signal 1402) is "High", the potential of the charge storage unit (FD) (signal 1404) is the potential of the wiring 1317 (signal 1404). It is initialized to "High") and the reset operation is started. The potential (signal 1405) of the wiring 1315 is precharged to "High".

At time B, when the potential (signal 1401) of the wiring 1311 is set to "Low", the reset operation ends and the accumulation operation starts. Here, since the photoelectric conversion element 1360 is subjected to the reverse bias, the charge storage unit (FD) (signal 1404) begins to decrease due to the reverse current. Since the reverse current of the photoelectric conversion element 1360 increases when the light is irradiated, the rate of decrease of the potential (signal 1404) of the charge storage unit (FD) changes according to the amount of the irradiated light. That is, the channel resistance between the source and drain of the transistor 1354 changes according to the amount of light irradiating the photoelectric conversion element 1360.

At time C, when the potential (signal 1402) of the wiring 1312 is set to “Low”, the storage operation ends, and the potential (signal 1404) of the charge storage unit (FD) becomes constant. Here, the potential is determined by the amount of electric charge generated by the photoelectric conversion element 1360 during the storage operation. That is, it changes according to the amount of light radiated to the photoelectric conversion element 1360. Further, since the transistor 1351 and the transistor 1353 are composed of a transistor having a channel region formed of an oxide film semiconductor and having an extremely low off-current, the charge storage unit (FD) of the charge storage unit (FD) is used until a later selection operation (reading operation) is performed. It is possible to keep the potential constant.

When the potential (signal 1402) of the wiring 1312 is set to "Low", the potential of the charge storage unit (FD) may change due to the parasitic capacitance between the wiring 1312 and the charge storage unit (FD). be. If the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 1360 during the storage operation cannot be accurately acquired. To reduce the amount of change in the potential, reduce the capacitance between the gate electrode and the source electrode (or the gate electrode and the drain electrode) of the transistor 1351, increase the gate capacitance of the transistor 1352, and hold it in the charge storage unit (FD). Measures such as providing capacity are effective. In the present embodiment, the change in the potential can be ignored by these measures.

When the potential (signal 1403) of the wiring 1313 is set to "High" at time D, the transistor 1354 conducts and the selection operation is started, and the wiring 1314 and the wiring 1315 conduct with each other via the transistor 1352 and the transistor 1354. Then, the potential (signal 1405) of the wiring 1315 decreases. The precharging of the wiring 1315 may be completed before the time D. Here, the speed at which the potential (signal 1405) of the wiring 1315 drops depends on the current between the source electrode and the drain electrode of the transistor 1352. That is, it changes according to the amount of light radiated to the photoelectric conversion element 1360 during the storage operation.

When the potential of the wiring 1313 (signal 1403) is set to "Low" at time E, the transistor 1354 is cut off, the selection operation ends, and the potential of the wiring 1315 (signal 1405) becomes a constant value. Here, the value that becomes a constant value changes according to the amount of light that has been applied to the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, it is possible to know the amount of light radiated to the photoelectric conversion element 1360 during the storage operation.

More specifically, when the light irradiating the photoelectric conversion element 1360 is strong, the potential of the charge storage unit (FD), that is, the gate voltage of the transistor 1352 decreases. Therefore, the current flowing between the source electrode and the drain electrode of the transistor 1352 becomes small, and the potential (signal 1405) of the wiring 1315 slowly decreases. Therefore, a relatively high potential can be read out from the wiring 1315.

On the contrary, when the light irradiating the photoelectric conversion element 1360 is weak, the potential of the charge storage unit (FD), that is, the gate voltage of the transistor 1352 becomes high. Therefore, the current flowing between the source electrode and the drain electrode of the transistor 1352 becomes large, and the potential (signal 1405) of the wiring 1315 drops rapidly. Therefore, a relatively low potential can be read out from the wiring 1315.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 7)
In the present embodiment, a display device having the semiconductor device of one aspect of the present invention will be described with reference to FIG. 28.

<7-1. Display device configuration example>
The display device shown in FIG. 28A has a region having pixels of the display element (hereinafter referred to as pixel unit 502) and a circuit unit (hereinafter referred to as pixel unit 502) arranged outside the pixel unit 502 and having a circuit for driving the pixels. , Drive circuit unit 504), a circuit having an element protection function (hereinafter referred to as protection circuit 506), and a terminal unit 507. The protection circuit 506 may not be provided.

It is desirable that a part or all of the drive circuit unit 504 is formed on the same substrate as the pixel unit 502. As a result, the number of parts and the number of terminals can be reduced. When a part or all of the drive circuit unit 504 is not formed on the same substrate as the pixel unit 502, a part or all of the drive circuit unit 504 is formed by COG or TAB (Tape Implemented Bonding). Can be implemented.

The pixel unit 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a gate driver 504a). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which the scanning signal is given. A plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can also supply another signal.

The source driver 504b has a shift register and the like. In the source driver 504b, in addition to the signal for driving the shift register, a signal (image signal) that is the source of the data signal is input via the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. Further, the source driver 504b has a function of controlling the output of the data signal according to the pulse signal obtained by inputting the start pulse, the clock signal and the like. Further, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is given. Alternatively, the source driver 504b has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured by using, for example, a plurality of analog switches. The source driver 504b can output a time-division signal of an image signal as a data signal by sequentially turning on a plurality of analog switches.

In each of the plurality of pixel circuits 501, a pulse signal is input via one of the plurality of scanning lines GL to which the scanning signal is given, and the data signal is transmitted through one of the plurality of data line DLs to which the data signal is given. Entered. Also. In each of the plurality of pixel circuits 501, the writing and holding of data of the data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and n-th column, a pulse signal is input from the gate driver 504a via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (n) is input according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), and a data signal is input from the source driver 504b.

The protection circuit 506 shown in FIG. 28A is connected to, for example, a scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. The terminal portion 507 refers to a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit that makes a wiring connected to itself in a conductive state when a potential outside a certain range is applied to the wiring and another wiring.

As shown in FIG. 28 (A), by providing protection circuits 506 in the pixel unit 502 and the drive circuit unit 504, respectively, the resistance of the display device to overcurrent generated by ESD (Electrostatic Discharge) or the like is enhanced. be able to. However, the configuration of the protection circuit 506 is not limited to this, and for example, the configuration may be such that the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

Further, FIG. 28A shows an example in which the drive circuit unit 504 is formed by the gate driver 504a and the source driver 504b, but the present invention is not limited to this configuration. For example, a configuration in which only the gate driver 504a is formed and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

<7-2. Pixel circuit configuration example>
The plurality of pixel circuits 501 shown in FIG. 28 (A) can have the configuration shown in FIG. 28 (B), for example.

The pixel circuit 501 shown in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitance element 560. The transistor shown in the previous embodiment can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of each row.

For example, as a method of driving a display device including a liquid crystal element 570, there are TN mode, STN mode, VA mode, ASM (Axially Synmetrical Defined Micro-cell) mode, OCB (Optically IPSlied Birefringence) mode, and FLC (Ferric crystal display) mode. , AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Partnered Vertical Birefringence) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode and the like may be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, or the like, or a PNLC (Polymer Network Liquid Crystal) mode. However, the present invention is not limited to this, and various liquid crystal elements and various driving methods thereof can be used.

In the pixel circuit 501 of the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. NS. Further, the gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling data writing of a data signal.

One of the pair of electrodes of the capacitive element 560 is electrically connected to the wiring to which the potential is supplied (hereinafter, the potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. NS. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitance element 560 has a function as a holding capacitance for holding the written data.

For example, in the display device having the pixel circuit 501 of FIG. 28 (B), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 28 (A), the transistor 550 is turned on, and the data signal is displayed. Write data.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 550 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, the plurality of pixel circuits 501 shown in FIG. 28 (A) can have the configuration shown in FIG. 28 (C), for example.

Further, the pixel circuit 501 shown in FIG. 28 (C) includes transistors 552 and 554, a capacitance element 562, and a light emitting element 572. The transistor shown in the previous embodiment can be applied to either one or both of the transistor 552 and the transistor 554.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n) to which a data signal is given. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is given.

The transistor 552 has a function of controlling data writing of a data signal.

One of the pair of electrodes of the capacitive element 562 is electrically connected to the wiring to which the potential is applied (hereinafter referred to as the potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Will be done.

The capacitance element 562 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

One of the potential supply line VL_a and the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display device having the pixel circuit 501 of FIG. 28 (C), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 28 (A), the transistor 552 is turned on, and the data of the data signal is input. Write.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 8)
In the present embodiment, the display module and the electronic device having the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 29 and 30.

<8-1. Display module>
The display module 8000 shown in FIG. 29 has a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. It has 8011.

The semiconductor device of one aspect of the present invention can be used, for example, in the display panel 8006.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be used by superimposing a resistive film type or capacitance type touch panel on the display panel 8006. It is also possible to provide the opposite substrate (sealing substrate) of the display panel 8006 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel. The optical touch panel preferably uses light having infrared rays. Since the optical touch panel can detect the object to be detected by light, the object to be detected and the touch panel do not have to come into contact with each other.

The backlight 8007 has a light source 8008. In FIG. 29, the configuration in which the light source 8008 is arranged on the backlight 8007 has been illustrated, but the present invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be used. When a self-luminous light emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 8007 may not be provided.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010, in addition to the protective function of the display panel 8006. Further, the frame 8009 may have a function as a heat sink.

The printed circuit board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying electric power to the power supply circuit may be an external commercial power source or a power source supplied by a separately provided battery 8011. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

<8-2. Electronic equipment>
30 (A) to 30 (G) are diagrams showing electronic devices. These electronic devices include a housing 9000, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular speed, etc.). Includes the ability to measure speed, distance, light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared light. ), Microphone 9008, and the like.

The electronic devices shown in FIGS. 30 (A) to 30 (G) can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read and display programs or data recorded on recording media It can have a function of displaying on a unit, and the like. The functions that the electronic devices shown in FIGS. 30A to 30G can have are not limited to these, and can have various functions. Further, although not shown in FIGS. 30A to 30H, the electronic device may have a configuration having a plurality of display units. In addition, the electronic device is provided with a camera or the like, and has a function of shooting a still image, a function of shooting a moving image, a function of saving the shot image in a recording medium (external or built in the camera), and displaying the shot image on a display unit. It may have a function to perform, etc.

Details of the electronic devices shown in FIGS. 30 (A) to 30 (G) will be described below.

FIG. 30A is a perspective view showing the television device 9100. The television device 9100 can incorporate the display unit 9001 into a large screen, for example, a display unit 9001 having a size of 50 inches or more, or 100 inches or more.

FIG. 30B is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. The mobile information terminal 9101 may be provided with a speaker, a connection terminal, a sensor, and the like. Further, the mobile information terminal 9101 can display character and image information on a plurality of surfaces thereof. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display unit 9001. Further, the information 9051 indicated by the broken line rectangle can be displayed on the other surface of the display unit 9001. As an example of information 9051, a display notifying an incoming call of e-mail, SNS (social networking service), telephone, etc., a title of e-mail, SNS, etc., a sender name of e-mail, SNS, etc., date and time, time. , Battery level, antenna reception strength, etc. Alternatively, the operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

As the material of the housing 9000, a material containing alloy, plastic, ceramics, and carbon fiber can be used. As a material containing carbon fibers, a carbon fiber reinforced resin composite material (Carbon Fiber Reinforced Plastics: CFRP) has an advantage of being lightweight and not corroding, but is black, and its appearance and design are limited. Further, CFRP can be said to be a kind of reinforced plastic, and glass fiber may be used as the reinforced plastic, or KFRP using Kevlar may be used. Alloys are preferred because the fibers may peel off from the resin when subjected to a strong impact as compared to alloys. Examples of alloys include aluminum alloys and magnesium alloys. Among them, amorphous alloys containing zirconium, copper, nickel and titanium (also called metallic glass) are excellent in terms of elastic strength. This amorphous alloy is an amorphous alloy having a glass transition region at room temperature, is also called a bulk solidified amorphous alloy, and is an alloy having a substantially amorphous atomic structure. By the solidification casting method, an alloy material is cast into a mold of at least one housing and solidified to form a part of the housing with a bulk solidified amorphous alloy. The amorphous alloy may contain berylium, silicon, niobium, boron, gallium, molybdenum, tungsten, manganese, iron, cobalt, yttrium, vanadium, phosphorus, carbon and the like in addition to zirconium, copper, nickel and titanium. Further, the amorphous alloy is not limited to the solidification casting method, and may be formed by a vacuum vapor deposition method, a sputtering method, an electroplating method, an electroless plating method, or the like. Further, the amorphous alloy may contain microcrystals or nanocrystals as long as it maintains a state without long-range order (periodic structure) as a whole. The alloy includes both a complete solid solution alloy having a single solid phase structure and a partial solution having two or more phases. By using an amorphous alloy for the housing 9000, a housing having high elasticity can be realized. Therefore, even if the mobile information terminal 9101 is dropped, if the housing 9000 is an amorphous alloy, it will return to its original state even if it is temporarily deformed at the moment when an impact is applied. Impact resistance can be improved.

FIG. 30C is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, the user of the mobile information terminal 9102 can check the display (here, information 9053) with the mobile information terminal 9102 stored in the chest pocket of the clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position that can be observed from above the mobile information terminal 9102. The user can check the display and determine whether or not to receive the call without taking out the mobile information terminal 9102 from the pocket.

FIG. 30D is a perspective view showing a wristwatch-type portable information terminal 9200. The personal digital assistant 9200 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games. Further, the display unit 9001 is provided with a curved display surface, and can display along the curved display surface. In addition, the personal digital assistant 9200 can execute short-range wireless communication standardized for communication. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the mobile information terminal 9200 has a connection terminal 9006, and can directly exchange data with another information terminal via a connector. It is also possible to charge via the connection terminal 9006. The charging operation may be performed by wireless power supply without going through the connection terminal 9006.

Further, the wristwatch-type portable information terminal 9200 may have a function of detecting a pulse. By detecting the pulse rate with the wristwatch-type portable information terminal 9200, the pulse rate can be measured constantly or periodically, which is preferable for health management. Infrared rays are preferably used for pulse detection, and the semiconductor device according to one aspect of the present invention is suitable.

31 (A) and 31 (B) are diagrams for explaining the arrangement of the light emitting element and the light receiving element in the terminal having a function of detecting infrared rays. The terminal 9501 having a function of detecting infrared rays shown in FIG. 31A has a light receiving element arranged on a substrate and a plurality of light emitting elements. The light receiving element 9601 has a function of detecting infrared rays, and the light emitting elements 9602, 9603, 9604 have a function of exhibiting infrared rays.

In the terminal 9501, the infrared rays emitted from the light emitting elements 9602 to 9604 are applied to the detection target object, and the reflected infrared rays are detected by the light receiving element 9601, whereby the detection target object can be detected. The position of the detection target and the like can be detected based on the magnitude of the reflected light from the detection target with respect to the light from the light emitting element.

Further, when the terminal 9501 has a display unit 9001 as a display device, the light emitting elements 9602 to 9604 that emit infrared rays and the light receiving element 9601 that detects infrared rays are the same as the display unit 9001 of the display device as shown in FIG. 31 (C). It may be arranged on a surface, or may be arranged on a surface different from the display unit 9001 of the display device as shown in FIG. 32 (A), and may be arranged on a surface different from the display unit 9001 of the display device, as shown in FIG. 32 (B). May be there.

Note that the light receiving element 9601 and the light emitting element 9602 to the light emitting element 9605 may be arranged as in the terminal 9502 shown in FIG. 31 (B). Further, the light receiving element and the light emitting element may be singular or plural, respectively.

Biological information such as a pulse can be detected by a terminal having a light emitting element and a light receiving element as described above. The terminal illustrated in FIG. 31 may have a light emitting element that exhibits infrared rays and a light receiving element that detects infrared rays, and is not limited to a terminal that detects a pulse.

Further, the semiconductor device according to one aspect of the present invention is suitable for an electronic device having a function of detecting biological information such as veins, pupils, and irises. In the sensing of the human body, it is preferable to use light in the near-infrared wavelength region, which is a so-called window of a living body. Since light in the wavelength region is hardly absorbed by water and is slightly absorbed by hemoglobin, it can be suitably used for detecting biological information, particularly blood state. Further, by using the semiconductor device of one aspect of the present invention, the biometric information as described above can be detected with high definition, so that the accuracy of biometric authentication can be improved.

30 (E), (F), and (G) are perspective views showing a foldable mobile information terminal 9201. Further, FIG. 30 (E) is a perspective view of a state in which the mobile information terminal 9201 is unfolded, and FIG. 30 (F) is a state in which the mobile information terminal 9201 is in the process of changing from one of the unfolded state or the folded state to the other. 30 (G) is a perspective view of the mobile information terminal 9201 in a folded state. The mobile information terminal 9201 is excellent in portability in the folded state, and is excellent in display listability due to a wide seamless display area in the unfolded state. The display unit 9001 included in the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

The electronic device described in the present embodiment is characterized by having a display unit for displaying some information. However, the semiconductor device of one aspect of the present invention can also be applied to an electronic device having no display unit.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.
[Example]

In this embodiment, a transistor according to one aspect of the present invention was produced, the electrical characteristics of the transistor were measured, and the light emitting state was observed.

The method for preparing the sample used in this example will be described below. In this embodiment, the semiconductor element 1 is manufactured as a transistor corresponding to the transistor 100 shown in FIGS. 1A, 1B, and 1C. In the following description, a configuration having the same function as that of the transistor 100 shown in FIGS. 1 (A), (B), and (C) will be described with reference to the same reference numerals. For comparison, a transistor having the structure shown in FIGS. 33 (A), (B), and (C) was manufactured as the comparative semiconductor element 1.
<Manufacturing of semiconductor element 1>

A conductive film 106 that functions as a first gate electrode was formed on a substrate 102 that is a glass substrate. As the conductive film 106, a tungsten film having a thickness of 100 nm was formed using a sputtering apparatus.

Next, an insulating film 104 functioning as a first gate insulating film was formed on the substrate 102 and the conductive film 106. In this embodiment, as the insulating film 104, the insulating film 104_1, the insulating film 104_2, the insulating film 104_3, and the insulating film 104___ were sequentially formed in this order in a vacuum using a PECVD apparatus. The insulating film 104_1 was a silicon nitride film having a thickness of 50 nm. The insulating film 104_2 was a silicon nitride film having a thickness of 300 nm. The insulating film 104_3 was a silicon nitride film having a thickness of 50 nm. The insulating film 104_4 was a silicon oxide film having a thickness of 50 nm.

Next, an oxide semiconductor film was formed on the insulating film 104, and the oxide semiconductor film was processed into an island shape to form the oxide semiconductor film 108. As the oxide semiconductor film 108, an oxide semiconductor film having a thickness of 40 nm was formed. A sputtering apparatus was used to form the oxide semiconductor film 108. A metal oxide having an In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] was used for the sputtering apparatus, and an AC power source was used as the power source for applying the bias voltage to the sputtering target. A wet etching method was used for processing the oxide semiconductor film 108.

Next, an insulating film that later became the insulating film 110 was formed on the insulating film 104 and the oxide semiconductor film 108. As the insulating film, a silicon oxide film having a thickness of 20 nm and a silicon oxide film having a thickness of 80 nm were continuously formed in a vacuum using a PECVD apparatus.

Next, heat treatment was performed. The heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

Next, an oxide semiconductor film was formed on the insulating film, and the oxide semiconductor film was processed into an island shape to form a conductive film 112 that functions as a second gate electrode. As the conductive film 112, a sputtering device is used, and a metal oxide having In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] is used as the sputtering target and applied to the sputtering target so as to have a thickness of 100 nm. An AC power source was used as the power source to be used. Further, after the conductive film 112 was formed, the insulating film in contact with the lower side of the conductive film 112 was subsequently processed to form the insulating film 110 functioning as the second gate insulating film.

A wet etching method was used for processing the conductive film 112, and a dry etching method was used for processing the insulating film 110.

Next, an impurity element was added from the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. A doping device was used as the treatment for adding the impurity element, and argon was used as the impurity element.

Next, the insulating film 116 was formed on the insulating film 104, the oxide semiconductor film 108, the insulating film 110, and the conductive film 112. As the insulating film 116, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus.

Next, the insulating film 118 was formed on the insulating film 116. As the insulating film 118, a silicon oxide nitride film having a thickness of 300 nm was formed using a PECVD apparatus.

Next, a mask was formed on the insulating film 118, and openings 141s and 141d were formed in the insulating films 116 and 118 using the mask. A dry etching apparatus was used to process the openings 141s and 141d.

Next, a conductive film is formed so as to fill the openings 141s and 141d on the insulating film 118, and the conductive film is processed into an island shape to function as a source electrode and a drain electrode. A film 120d was formed.

The conductive films 120s and 120d were continuously formed in a vacuum using a titanium film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm.

Through the above steps, the semiconductor element 1 which is a transistor corresponding to the transistor 100 shown in FIGS. 1 (A), (B), and (C) was manufactured.

The channel width W of the semiconductor element 1 was set to 50 μm and 100 μm, and the channel width L was set to 6 μm.

<Manufacturing of comparative semiconductor element 1>
A conductive film 106 that functions as a first gate electrode was formed on a substrate 102 that is a glass substrate. As the conductive film 106, a tungsten film having a thickness of 100 nm was formed using a sputtering apparatus.

Next, insulating films 104 and 103 functioning as the first gate insulating film were formed on the substrate 102 and the conductive film 106. As the insulating film 104, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. Further, as the insulating film 103, a silicon oxide nitride film having a thickness of 50 nm was formed by using a PECVD apparatus.

Next, an oxide semiconductor film was formed on the insulating film 103, and the oxide semiconductor film was processed into an island shape to form the oxide semiconductor film 108. As the oxide semiconductor film 108, an oxide semiconductor film having a thickness of 25 nm was formed. As the oxide semiconductor film 108, a sputtering apparatus is used, a metal oxide having In: Ga: Zn = 4: 2: 4.1 [atomic number ratio] is used as a sputtering target, and as a power source to be applied to the sputtering target. Used an AC power supply.

Next, a conductive film is formed on the insulating film 103 and the oxide semiconductor film 108, a resist mask is formed on the conductive film, and a desired region is etched to function as a source electrode and a drain electrode. 120s and a conductive film 120d were formed. As the conductive films 120s and 120d, a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm were continuously formed in a vacuum using a sputtering apparatus. After forming the conductive films 120s and 120d, the resist mask was removed.

Next, an aqueous phosphoric acid solution (an aqueous solution having a phosphoric acid concentration of 85% diluted 100-fold with pure water) is applied over the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. Then, a part of the surface of the oxide semiconductor film 108 exposed from the conductive films 120s and 120d was removed.

Next, an insulating film 114 and an insulating film 116 functioning as a second gate insulating film were formed on the insulating film 103, the oxide semiconductor film 108, and the conductive films 120s and 120d. As the insulating film 114, a silicon oxide nitride film having a thickness of 50 nm was formed using a PECVD apparatus. Further, as the insulating film 116, a silicon oxide nitride film having a thickness of 400 nm was formed by using a PECVD apparatus. The insulating film 114 and the insulating film 116 were continuously formed in a vacuum by a PECVD apparatus.

Next, the first heat treatment was performed. The first heat treatment was carried out at 350 ° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide semiconductor film was formed on the insulating film 116, and the oxide semiconductor film was processed into an island shape to form a conductive film 112 that functions as a second gate electrode. As the conductive film 112, an oxide semiconductor film having a thickness of 100 nm was formed using a sputtering apparatus.

Next, the insulating film 118 was formed on the insulating film 116 and the conductive film 112. As the insulating film 118, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus.

Next, a second heat treatment was performed. The second heat treatment is the same as the first heat treatment.

Through the above steps, the comparative semiconductor element 1 corresponding to the transistor shown in FIGS. 33 (A), (B), and (C) was manufactured.

As the comparative semiconductor element 1, the channel width W was set to 100 μm and the channel width L was set to 6 μm.

<Measurement of electrical characteristics>
FIGS. 34 (A) and 34 (B) show the results of the drain current-gate voltage (Id-Vg) characteristic of the semiconductor element 1.

Note that FIG. 34 (A) shows the characteristics of the semiconductor element 1 having W / L = 50 μm / 6 μm, and FIG. 34 (B) shows the characteristics of the semiconductor element 1 having W / L = 100 μm / 6 μm. Further, in FIGS. 34 (A) and 34 (B), the curve shown by the solid line corresponds to Id (A) on the first vertical axis, and the curve shown by the dotted line corresponds to the electric field effect mobility (μFE (cm)). ² / Vs)) are represented respectively. The horizontal axis is Vg (V).

The measurement conditions for the Id-Vg characteristic of the transistor include a voltage applied to the conductive film 106 that functions as the first gate electrode of the transistor (hereinafter, also referred to as a gate voltage (Vg)) and a second gate electrode. The voltage applied to the functioning conductive film 112 (hereinafter, also referred to as Vbg) was changed from -15V to + 20V in steps of 0.25V. Further, the voltage applied to the conductive film 120s functioning as the source electrode (hereinafter, also referred to as source voltage (Vs)) is set to 0V (com), and the voltage applied to the conductive film 120d functioning as the drain electrode (hereinafter, drain voltage (hereinafter, drain voltage)). Vd)) was set to 1V or 20V.

As shown in FIGS. 34 (A) and 34 (B), it was shown that the transistors produced in this example have good electrical characteristics regardless of the length of the channel length (L).

<Observation of light emission state>
Next, the light emitting state of the manufactured semiconductor element 1 having W / L = 50 μm / 6 μm, the semiconductor element 1 having W / L = 100 μm / 6 μm, and the comparative semiconductor element 1 having W / L = 100 μm / 6 μm was observed. went. The observation results of the light emitting state are shown in FIGS. 35 and 36.

Here, in order to make each semiconductor element emit light, Vg and Vbg were set to 20V, and Vd was set to 20V. A cooled CCD camera having a quantum efficiency of 65% or more at 400 nm or more and 750 nm or less is used for observing light emission in the visible light region, and 65% or more is used for observing light emission in the near infrared region at 900 nm or more and 1550 nm or less. An InGaAs camera with quantum efficiency (C8250-31, manufactured by Hamamatsu Photonics Co., Ltd.) was used.

In addition, FIG. 35 (A) shows the observation result of light emission in the visible light region of the semiconductor element 1 having W / L = 100 μm / 6 μm, and FIG. 35 (B) shows the observation result of the semiconductor element 1 having W / L = 100 μm / 6 μm. Observation results of light emission in the near-infrared region, FIG. 36 (A) shows observation results of light emission in the near-infrared region of the semiconductor device 1 with W / L = 50 μm / 6 μm, and FIG. 36 (B) shows W / L = 100 μm. The observation results of light emission in the near-infrared region of the comparative semiconductor element 1 of / 6 μm are shown.

As shown in FIG. 36 (A), light emission in the near infrared region was observed from the semiconductor element 1 having W / L = 50 μm / 6 μm. Further, as shown in FIG. 35 (B), strong light emission in the near infrared region was observed from the semiconductor element 1 having W / L = 100 μm / 6 μm. Therefore, it is preferable that the channel width W is large because the light emission in the near infrared region can be strongly exhibited. Further, as shown in FIG. 35 (A), almost no light emission in the visible light region was observed from the semiconductor element 1 having W / L = 100 μm / 6 μm. That is, the semiconductor element 1 which is the transistor of one aspect of the present invention is preferable because it has a function of selectively emitting light in the infrared region.

On the other hand, as shown in FIG. 36 (B), almost no light emission in the near infrared region was observed from the comparative semiconductor element 1 having W / L = 100 μm / 6 μm. In the semiconductor element 1 of one aspect of the present invention, the region where the oxide semiconductor film 108 and the conductive films 120s and 120d are in contact with each other is separated from the channel region as compared with the comparative semiconductor element 1. Therefore, the heat or infrared energy generated in the channel region is difficult to move to the conductive films 120s and 120d, and the light emission in the infrared region can be effectively exhibited.

As described above, it has been found that a transistor having a function of exhibiting light emission in the near infrared region can be produced by one aspect of the present invention.

As described above, the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

100 Transistor 100A Transistor 100B Transistor 100C Transistor 100D Transistor 100E Transistor 100F Transistor 100G Transistor 102 Substrate 103 Insulation film 104 Insulation film 104_1 Insulation film 104_2 Insulation film 104___ Insulation film 104___ Insulation film 106 Conductive film 107 Oxide semiconductor film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d Drain region 108f region 108i Channel region 108s Source region 110 Insulation film 110_Insulation film 112 Conductive 112_ Conductive film 114 Insulation film 116 Insulation film 118 Insulation film 120 Conductive film 120d Conductive 120s Conductive 122 Insulating film 140 Mask 141d Opening 141s Opening 143 Opening 145 Impure element 147 Hollow region 200 Substrate 202 Transistor 204 Light emitting element 206 Photo diode 212 Transistor 221 Transistor 230 Insulating film 241 Conductive film 242 Conductive 250 Insulation Film 261 Conductive 262 Conductive 270 Light emitting layer 280 Conductive 290 Photoelectric conversion layer 291 Partition 300 Color filter 310 Encapsulating substrate 501 Pixel circuit 502 Pixel 504 Drive circuit 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 571 Light emitting element 700 Display device 701 Board 702 Pixel part 704 Source driver 705 Board 706 Gate driver 708 FPC terminal part 710 Signal line 711 Wiring part 712 Sealing material 716 FPC
730 Insulation film 732 Encapsulation film 734 Insulation film 736 Colored film 738 Light-shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulation film 772 Conductive 774 Conductive 775 Liquid crystal element 767 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light emitting element 784 Conductive element 786 EL layer 788 Conductive element 780 Capacitive element 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 Capacitive element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 1404 Signal 1405 Signal 2020 Oxide semiconductor film 2021 Conductive 2022 Conductive 2023 Gate insulating film 2024 Conductive 2025 Conductive 2101 Detected object 2201 Light 2202 Light 2301 Light 2302 Light 8000 Display module 8001 Top cover 8002 Bottom cover 8003 FPC
8004 touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Print board 8011 Battery 9000 Housing 9001 Display 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hing 9100 Television device 9101 Mobile information terminal 9102 Mobile information terminal 9200 Mobile information terminal 9201 Mobile information terminal 9501 Terminal 9502 Terminal 9601 Light receiving element 9602 Light emitting element 9603 Light emitting element 9604 Light emitting element 9605 Light emitting element

Claims (2)

A semiconductor device having a transistor
The transistor is
The oxide semiconductor film on the first insulating film and
The second insulating film on the oxide semiconductor film and
A first gate electrode having a region that overlaps with the oxide semiconductor film via the second insulating film, and a first gate electrode.
It has a third insulating film on the oxide semiconductor film and on the first gate electrode.
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film.
The channel region has a region exhibiting light emission and has a region.
The light emission is a semiconductor device including near infrared light. A semiconductor device having a transistor
The transistor is
The oxide semiconductor film on the first insulating film and
The second insulating film on the oxide semiconductor film and
A first gate electrode having a region that overlaps with the oxide semiconductor film via the second insulating film, and a first gate electrode.
It has a third insulating film on the oxide semiconductor film and on the first gate electrode.
The oxide semiconductor film has a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film.
The channel region has a function of exhibiting light emission, and has a function of exhibiting light emission.
The light emission is a semiconductor device containing light in a wavelength region of 900 nm or more and 1550 nm or less.

Images