JP2020127016A - Semiconductor device - Google Patents

Abstract

To provide a transistor including an oxide semiconductor, in which a change in its electrical characteristics is prevented and its reliability is improved.SOLUTION: A transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, a first oxide semiconductor film over the first gate insulating film, a second gate insulating film over the first oxide semiconductor film, and a second oxide semiconductor film over the second gate insulating film. The first oxide semiconductor film includes a channel region where the second oxide semiconductor film overlaps, a source region provided in contact with the channel region, and a drain region provided in contact with the channel region. The channel region includes a first layer and a second layer which is in contact with the top face of the first layer and covers a side face of the first channel layer in a channel width direction. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture or composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic unit, and a memory device are one mode of the semiconductor device. The imaging device, the display device, the liquid crystal display device, the light emitting device, the electro-optical device, the power generation device (including the thin film solar cell, the organic thin film solar cell, etc.), and the electronic device are
It may have a semiconductor device.

A technique for forming a transistor (also referred to as a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). A semiconductor material typified by silicon is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor is drawing attention as another material.

For example, a technique of manufacturing a transistor using an amorphous oxide containing In, Zn, Ga, Sn, or the like as an oxide semiconductor is disclosed (see Patent Document 1). Further, a technique of manufacturing an oxide thin film transistor having a self-aligned top gate structure is disclosed (see Patent Document 2).

Further, a semiconductor device in which an insulating layer which releases oxygen by heating is used for a base insulating layer of an oxide semiconductor layer which forms a channel and oxygen deficiency of the oxide semiconductor layer is reduced is disclosed (see Patent Document 3). ).

JP, 2006-165529, A JP, 2009-278115, A JP2012-009836A

Examples of the transistor including an oxide semiconductor film include an inverted staggered type (also referred to as a bottom gate structure), a staggered type (also referred to as a top gate structure), and the like. When a transistor including an oxide semiconductor film is applied to a display device, an inverted staggered transistor may be used as compared with a staggered transistor because the manufacturing process is relatively simple and manufacturing cost can be suppressed. Many. However, the screen of the display device is enlarged or the image quality of the display device is increased (for example, 4k×2k (horizontal pixel number=3840 pixels, vertical pixel number=2160 pixels) or 8k×4k (horizontal pixel number). Number = 7680 pixels, vertical pixel number =
High-definition display device typified by 4320 pixels), a reverse stagger type transistor has a parasitic capacitance between a gate electrode and a source electrode and a drain electrode. Therefore, the parasitic capacitance causes a signal delay or the like. However, there is a problem in that the image quality of the display device deteriorates due to the large size. Therefore, for a staggered transistor having an oxide semiconductor film, development of a structure having stable semiconductor characteristics and high reliability is desired.

In the case where a transistor is manufactured using an oxide semiconductor film for a channel region, oxygen vacancies formed in the channel region of the oxide semiconductor film are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the channel region of the oxide semiconductor film, carriers are generated due to the oxygen vacancies. When carriers are generated in the channel region of the oxide semiconductor film, variation in electric characteristics of a transistor including the oxide semiconductor film in the channel region,
A threshold voltage shift typically occurs. In addition, there is a problem that the electrical characteristics vary from transistor to transistor. Therefore, in the channel region of the oxide semiconductor film, the smaller the oxygen vacancies, the more preferable. On the other hand, in a transistor including an oxide semiconductor film in a channel region, the oxide semiconductor film in contact with the source electrode and the drain electrode has many oxygen vacancies in order to reduce contact resistance with the source electrode and the drain electrode, and has a high resistance. The lower the better.

In view of the above problems, one object of one embodiment of the present invention is to suppress variation in electric characteristics of a transistor including an oxide semiconductor and improve reliability. Or
One object of one embodiment of the present invention is to provide a staggered transistor including an oxide semiconductor. Another object of one embodiment of the present invention is to provide a transistor including an oxide semiconductor and having high on-state current. Another object of one embodiment of the present invention is to provide a transistor including an oxide semiconductor and having low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.
Alternatively, it is an object of one embodiment of the present invention to provide a novel semiconductor device.

Note that the description of the above problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not necessarily need to solve all of these problems. Problems other than the above are naturally clarified from the description in the specification and the like, and problems other than the above can be extracted from the description in the specification and the like.

One embodiment of the present invention is a semiconductor device including a transistor, the transistor having a first structure.
Gate electrode, a first gate insulating film on the first gate electrode, a first oxide semiconductor film on the first gate insulating film, and a second gate on the first oxide semiconductor film. An insulating film and a second oxide semiconductor film over the second gate insulating film, and the first oxide semiconductor film has a channel region where the second oxide semiconductor film overlaps, and a channel region. A source region provided in contact with the channel region and a drain region provided in contact with the channel region, the channel region including the first layer,
A second layer that is in contact with the upper surface of the first layer and covers a side surface of the first layer in the channel width direction, the second oxide semiconductor film being more than the first oxide semiconductor film. This is a semiconductor device having a high carrier density.

Another embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first gate electrode, a first gate insulating film over the first gate electrode, and a first gate insulating film. A first oxide semiconductor film over the film, a second gate insulating film over the first oxide semiconductor film,
A second oxide semiconductor film over the second gate insulating film, and the first oxide semiconductor film is provided in contact with the channel region and the channel region where the second oxide semiconductor film overlaps. A source region and a drain region provided in contact with the channel region, and the first oxide semiconductor film is in contact with the channel region where the second oxide semiconductor film overlaps with the second insulating film. The channel region has a source region and a drain region in contact with the second insulating film, and the channel region is in contact with the first layer and the upper surface of the first layer and has a side surface in the channel width direction of the first layer. And a second layer that covers the lower surface of the first layer and a third layer that is in contact with a lower surface of the first layer, and the second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film. is there.

In the above embodiment, the transistor is further provided in the insulating film over the second oxide semiconductor film, a source electrode connected to the source region through an opening provided in the insulating film, and the insulating film. And a drain electrode connected to the drain region through the opening.

In the above embodiment, the source region and the drain region preferably contain one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, or a rare gas.

In the above embodiment, one or both of the first oxide semiconductor film and the second oxide semiconductor film are In, Zn, and M (M is Al, Ga, Y, or Sn). , Are preferred. In the above embodiment, it is preferable that one or both of the first oxide semiconductor film and the second oxide semiconductor film have a crystal part and the crystal part have c-axis orientation.

Another aspect of the present invention is a display device including the semiconductor device and the display element according to any one of the above aspects. Another embodiment of the present invention is a display module including the display device and a touch sensor. Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of the above embodiments, the display device, or the display module, and an operation key or a battery.

According to one embodiment of the present invention, in a transistor including an oxide semiconductor, variation in electric characteristics can be suppressed and reliability can be improved. Alternatively, according to one embodiment of the present invention,
A staggered transistor including an oxide semiconductor can be provided. Alternatively, according to one embodiment of the present invention, a transistor including an oxide semiconductor and having high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor including an oxide semiconductor and having low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are apparent from the description of the specification, drawings, claims, etc., and the effects other than these can be extracted from the description of the specification, drawings, claims, etc. Is.

7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. 7A and 7B are diagrams illustrating a top surface and a cross section of a semiconductor device. The figure explaining a band structure. 6A to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device. 6A to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device. 6A to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device. 6A to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device. 16A to 16C each illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD, and a selected area electron diffraction pattern of the CAAC-OS. A cross-sectional TEM image of the CAAC-OS, a plane TEM image, and an image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 10 is a diagram showing a change in a crystal part of an In—Ga—Zn oxide due to electron irradiation. FIG. 6 is a top view illustrating one embodiment of a display device. FIG. 13 is a cross-sectional view illustrating one embodiment of a display device. FIG. 13 is a cross-sectional view illustrating one embodiment of a display device. FIG. 6 illustrates a circuit configuration of a semiconductor device. 6A and 6B are diagrams illustrating a structure of a pixel circuit and a timing chart illustrating operation of the pixel circuit. 3A and 3B are a block diagram and a circuit diagram illustrating a display device. 3A and 3B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. 16A and 16B are graphs and circuit diagrams each illustrating one embodiment of the present invention. 3A and 3B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. 3A and 3B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. Sectional drawing which shows an example of an input/output device. FIG. 6 illustrates a display module. 7A to 7C each illustrate an electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and that the modes and details can be variously changed without departing from the spirit and the scope thereof. .. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to that scale. It should be noted that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers “first”, “second”, and “third” used in this specification are added to avoid confusion among constituent elements, and are not meant to be numerically limited. Add note.

In addition, in the present specification, terms such as “above” and “below” are used for convenience in order to explain the positional relationship between components with reference to the drawings. Further, the positional relationship between the components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, and can be paraphrased appropriately according to the situation.

In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, the channel region, and the source. Is something that can be done. Note that in this specification and the like, a channel region refers to a region in which a current mainly flows.

Further, the functions of the source and the drain may be switched when a transistor of different polarity is used or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms source and drain can be interchanged.

In addition, in this specification and the like, the term “electrically connected” includes the case of being connected through “an object having some electrical action”. Here, the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets. For example, “things having some kind of electrical action” include electrodes and wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10° to 10°. Therefore, a case of -5° or more and 5° or less is also included. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

In addition, in this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Or, for example, the term “insulating film” is replaced with “insulating layer”.
It may be possible to change to the term.

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is in an off state (also referred to as a non-conduction state or a cutoff state). The off state is the voltage V between the gate and the source of the n-channel transistor unless otherwise noted.
This is a state in which gs is lower than the threshold voltage Vth, and in a p-channel transistor, a voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor means that the voltage Vgs between the gate and the source is the threshold voltage Vt.
It may be referred to as a drain current when it is lower than h.

The off-state current of a transistor may depend on Vgs. Therefore, the off-state current of a transistor is less than or equal to I may mean that there is a value of Vgs at which the off-state current of a transistor is less than or equal to I. The off-state current of a transistor may refer to an off-state at a predetermined Vgs, an off-state at Vgs within a predetermined range, an off-state at Vgs at which a sufficiently reduced off-state current is obtained, or the like.

As an example, the threshold voltage Vth is 0.5V, the drain current when Vgs is 0.5V is 1×10 −9 A, and the drain current when Vgs is 0.1V is 1×10 −1.
3A, drain current at Vgs of −0.5V is 1×10 −19A, Vg
Assume an n-channel transistor having a drain current of 1×10 −22 A when s is −0.8V. Since the drain current of the transistor is 1×10 −19 A or lower at Vgs of −0.5 V or in the range of Vgs of −0.5 V to −0.8 V, the off-state current of the transistor is 1×. It may be said that it is 10-19 A or less. Since there is Vgs at which the drain current of the transistor is 1×10 −22 A or lower, the off-state current of the transistor is 1×10 −22 A or lower in some cases.

In addition, in this specification and the like, the off-state current of a transistor having a channel width W may be expressed as a current value flowing per channel width W. Further, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off current may be represented by a unit having a dimension of current/length (for example, A/μm).

The off-state current of a transistor may depend on temperature. In the present specification, off-state current may represent off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. unless otherwise specified. Alternatively, a temperature used for reliability required for a semiconductor device or the like including the transistor, or a temperature (for example, any one temperature of 5° C. to 35° C.) at which the semiconductor device or the like including the transistor is used. ), the off-state current may be expressed. The off-state current of a transistor is less than or equal to I means room temperature, 60° C., 85° C., 9
5° C., 125° C., a temperature used for reliability required for a semiconductor device including the transistor, or a temperature used for a semiconductor device including the transistor (for example, 5° C. to 35° C.) In some cases, there is a value of Vgs at which the off-state current of the transistor at one temperature) becomes less than or equal to I.

The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In the present specification, off-state currents are Vds of 0.1 V, 0.8 V, unless otherwise specified.
It may represent off current at 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, it may represent Vds used for reliability required for a semiconductor device or the like including the transistor or an off-state current at Vds used in a semiconductor device or the like including the transistor. The off-state current of the transistor is I or less means that Vds is 0.1V, 0.8V, 1V, 1.
2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds used in the reliability required for a semiconductor device including the transistor, or a semiconductor including the transistor. It may indicate that there is a value of Vgs at which the off-state current of a transistor at Vds used in a device or the like is less than or equal to I.

In the above description of the off-state current, the drain may be read as the source. That is, the off-state current may be referred to as a current flowing through the source when the transistor is off.

In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to a current flowing between a source and a drain when the transistor is off, for example.

In addition, in this specification and the like, an impurity of a semiconductor means a substance other than a main component included in a semiconductor film. For example, an element whose concentration is less than 0.1 atomic% is an impurity. Due to the inclusion of impurities, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be lowered, and crystallinity may be lowered. When the semiconductor has an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component. In particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by the mixture of impurities such as hydrogen. In the case where the semiconductor contains silicon, examples of impurities that change the characteristics of the semiconductor include a Group 1 element other than oxygen and hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.

(Embodiment 1)
In this embodiment, an example of a semiconductor device including a transistor and a method for manufacturing the semiconductor device will be described with reference to FIGS.

<1-1. Configuration example 1 of semiconductor device>
1A, 1B, and 1C illustrate an example of a semiconductor device including a transistor. Note that the transistors illustrated in FIGS. 1A, 1B, and 1C each have a top-gate structure.

1A is a top view of the transistor 150, FIG. 1B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 1A, and FIG. 1C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2. Note that in FIG. 1A, components such as the insulating film 110 are omitted for clarity. Note that in the top view of the transistor, FIG.
Similar to A), some components may be omitted in the drawing. Also, the alternate long and short dash line X1-X
The two directions may be referred to as a channel length (L) direction, and the one-dot chain line Y1-Y2 direction may be referred to as a channel width (W) direction.

A transistor 150 illustrated in FIGS. 1A, 1B, and 1C includes a conductive film 106 formed over a substrate 102, an insulating film 104 over the conductive film 106, and an oxide semiconductor film 108 over the insulating film 104.
And an insulating film 110 over the oxide semiconductor film 108 and an oxide semiconductor film 112 over the insulating film 110.
And an insulating film 116 over the oxide semiconductor film 112.
In addition, the oxide semiconductor film 108 has a channel region 108i where the oxide semiconductor film 112 overlaps.
A source region 108s provided in contact with the channel region 108i, and a channel region 10
The channel region 108i includes a layer 108_2 and a layer 108_3 which is in contact with the upper surface of the layer 108_2 and covers a side surface of the layer 108_2 in the channel width direction.

Note that the source region 108s and the drain region 108d each include an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, or a rare gas. Note that typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Source region 108s and drain region 108d
By including the above impurity element, the carrier density of the oxide semiconductor film can be increased.

The oxide semiconductor film 112 is electrically connected to the conductive film 106 through the insulating film 110, the layer 108_3, and the opening 143 provided in the insulating film 104. Therefore, the conductive film 1
The same potential is applied to 06 and the oxide semiconductor film 112. However, it is not limited to this,
Different potentials may be applied to the conductive film 106 and the oxide semiconductor film 112 without providing the opening 143.

Note that the conductive film 106 has a function as a first gate electrode (also referred to as a bottom gate electrode), and the oxide semiconductor film 112 has a function as a second gate electrode (also referred to as a top gate electrode). .. The insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.

In addition, the transistor 150 includes the insulating film 118 over the insulating film 116 and the insulating films 116 and 11
8 and the conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the layer 108_3, the insulating films 116 and 118, and the opening 141b provided in the layer 108_3. , The conductive film 120b electrically connected to the drain region 108d
And may have.

The transistor 150 may be, for example, low temperature polysilicon (LTPS (Low
(Temperature Poly-Silicon)) or hydrogenated amorphous silicon (a-Si:H) manufacturing apparatus. Therefore, there is no need to make new capital investment, or new capital investment is extremely small.

In this specification and the like, the conductive film 120a has a function as a source electrode and the conductive film 120b has a function as a drain electrode.

On the side surface of the channel region 108i in the channel width (W) direction included in the oxide semiconductor film 108 or in the vicinity thereof, defects (e.g., oxygen vacancies) are likely to be formed due to damage in processing or are easily contaminated by adhesion of impurities. .. Therefore, the channel region 1
Even if 08i is substantially intrinsic, when a stress such as an electric field is applied, the side surface of the channel region 108i in the channel width (W) direction or its vicinity is activated, and low resistance (
It tends to be an n-type) region. When the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof is an n-type region, the n-type region serves as a carrier path, so that a parasitic channel may be formed.

Therefore, in the semiconductor device of one embodiment of the present invention, the channel region 108i has a stacked structure and the side surface of the channel region 108i in the channel width (W) direction is covered with one layer of the stacked structure. With such a structure, defects on the side surface of the channel region 108i or in the vicinity thereof or adhesion of impurities can be reduced.

1A, 1B, and 1C, the layered structure of the channel region 108i corresponds to the layer 1
Although it has a two-layer structure of 08_2 and the layer 108_3, the invention is not limited to this. For example, in FIG.
) (B) (C) may have a laminated structure.

2A is a top view of the transistor 150A, FIG. 2B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 2A, and FIG. 2C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2.

The oxide semiconductor film 108 included in the transistor 150A includes the channel region 108i in which the oxide semiconductor film 112 overlaps and the source region 10 provided in contact with the channel region 108i.
8s and a drain region 108d provided in contact with the channel region 108i.
The channel region 108i is in contact with the layer 108_2 and the top surface of the layer 108_2, and the layer 1
The layer 108_3 which covers the side surface of the channel 08_2 in the channel width direction and the layer 108_1 which is in contact with the bottom surface of the layer 108_2 are included.

Thus, the transistor 150A is different in the structure of the oxide semiconductor film 108 included in the transistor 150 described above. The rest of the configuration is similar to that of the transistor 150 and has the same effect.

The layer 108_1, the layer 108_2, and the layer 108_3 in the oxide semiconductor film 108 include at least one same element. Therefore, interface scattering is unlikely to occur at the interface between the layers 108_1 and 108_2 or the interface between the layers 108_2 and 108_3. Therefore,
Since carrier movement is not hindered at the interface, field-effect mobility of the transistor 150 and the transistor 150A (sometimes referred to as mobility or μFE) is increased.

The layers 108_1, 108_2, and 108_3 each include a metal oxide, and the metal oxide preferably contains at least indium (In) or zinc (Zn).

When the oxide semiconductor film contains In, carrier mobility (electron mobility) is increased, for example.
Further, when the oxide semiconductor film contains Zn, crystallization of the oxide semiconductor film is likely to occur.

When the oxide semiconductor film contains the element M having a function as a stabilizer, the energy gap (Eg) of the oxide semiconductor film becomes large, for example. An oxide semiconductor film suitable for one embodiment of the present invention has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Thus, by using a metal oxide having a wide energy gap for the oxide semiconductor film 108, off-state current of the transistors 150 and 150A can be reduced. The element M is an element having a high binding energy with oxygen and has a binding energy with oxygen higher than that of In.

An oxide semiconductor film suitable for the semiconductor device of one embodiment of the present invention is typically In-Z
An n oxide, an In-M oxide, or an In-M-Zn oxide can be used. In-
M-Zn oxide (M is aluminum (Al), gallium (Ga), yttrium (Y),
Alternatively, tin (representing Sn) is preferably used. In particular, In-G in which M is Ga
It is preferable to use an a-Zn oxide (hereinafter sometimes referred to as IGZO).

When the layer 108_2 includes an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is preferably greater than 25 atomic% and less than 75 atomic %, more preferably less than 75 atomic %. Is greater than 34 atomic% and M is less than 66 atomic %. In particular, the layer 108_2 preferably has a region where the atomic ratio of In is greater than or equal to the atomic ratio of M.

Further, the layer 108_2 has a region in which the atomic ratio of In is greater than or equal to the atomic ratio of M, whereby the field-effect mobility of the transistor can be increased. Specifically, the transistor 1
It is possible that the field effect mobility of 50, 150 A exceeds 10 cm 2 /Vs, and more preferably the field effect mobility of the transistors 150, 150 A exceeds 30 cm 2 /Vs.

For example, a transistor having high field-effect mobility can have a small channel width. Therefore, by using the transistor for a scan line driver circuit (also referred to as a gate driver) that generates a gate signal or a demultiplexer connected to an output terminal of a shift register included in the scan line driver circuit, the scan line driver circuit A semiconductor device or a display device which can be reduced in size and has a narrow frame width (also referred to as a narrow frame) can be provided. Alternatively, since the gate voltage can be reduced, power consumption of the display device can be reduced.

In addition, the display device can have high definition by increasing the field-effect mobility of the transistor. For example, 4k×2k (horizontal pixel number=3840 pixels, vertical pixel number=216
0 pixels) or 8k x 4k (horizontal pixel number = 7680 pixel, vertical pixel number = 4320)
It can be preferably used as a pixel circuit of a high-definition display device represented by a pixel) or a transistor of a driving circuit.

On the other hand, in the case where the layer 108_2 has a region where the atomic ratio of In is greater than or equal to the atomic ratio of M, the energy gap (Eg) becomes small, so that the electrical characteristics of the transistor are easily changed at the time of light irradiation. However, in the semiconductor device of one embodiment of the present invention, the layer 108_
A layer 108_3 is formed on the second layer. Alternatively, the layer 108_2 is formed over the layer 108_1.

Further, the layers 108_1 and 108_3 each include a region in which the atomic ratio of In is lower than that of the layer 108_2. Therefore, Eg is higher than that of the layer 108_2. Therefore, layer 10
8_2 and the layer 108_3 are stacked, or the layer 108_1, the layer 108_2, and the layer 1
By stacking with 08_3, it is possible to increase the resistance of the transistor in the negative bias stress test by light.

When the layers 108_1 and 108_3 include an In-M-Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is such that In is less than 75 atomic% and M is 25 atom.
ic% is more preferable, In is less than 66 atomic%, M is more preferable.
Is greater than 34 atomic%. In particular, the layers 108_1 and 108_3 each preferably include a region in which the atomic ratio of M is greater than or equal to the atomic ratio of In.

Note that the layers 108_1 and 108_3 may have the following effects by including the element M in the atomic ratio of In or higher. (1) The energy gap becomes large. (2) The electron affinity is reduced. (3) Shield impurities from the outside. (4) Insulation becomes high. Also,
Since the element M is a metal element having a strong bonding force with oxygen, oxygen deficiency is less likely to occur when the element M has an atomic ratio of In or higher.

In addition, the number of atoms of the element M included in the layers 108_1 and 108_3 is preferably greater than or equal to the number of atoms of the element M included in the layers 108_2. Typically, the atomic ratio of the element M in the layers 108_1 and 108_3 is preferably 1.5 times or more, more preferably 2 times or more that of the element M in the layer 108_2.

In addition, the number of In atoms included in the layers 108_2 is equal to the number of In atoms included in the layers 108_1 and 108_3.
It is preferable that the number of atoms is not less than. Typically, the atomic ratio of the element In of the layer 108_2 is preferably 1.5 times or more, more preferably 2 times or more that of the element In of the layer 108_1 or the layer 108_3. At this time, the layer 108_2 includes the transistor 1
It can have a function as a channel region in 50 and 150A. In addition, the on-state current is increased in the transistors 150 and 150A by the structure, and an effect of increasing field-effect mobility can be expected. Note that a transistor with high field-effect mobility may have negative threshold voltage (i.e., normally-on characteristics) in some cases. This is because electric charge is generated due to oxygen vacancies contained in the oxide semiconductor film included in the transistor and the resistance is reduced. When the transistor has a normally-on characteristic, various problems occur such that a malfunction is likely to occur during operation and power consumption is high during non-operation. Therefore, the layer 108_2 has few impurities and defects (such as oxygen vacancies),
It is preferably a CAAC-OS described later.

<1-2. Band structure>
Next, a band structure of the oxide semiconductor film in the transistor 150 in FIG. 1 and the transistor 150A in FIG. 2 and a band structure of an insulating film in contact with the oxide semiconductor film will be described with reference to FIGS.

8A illustrates a band structure in the thickness direction of the insulating film 104, the layer 108_2, the layer 108_3, and the insulating film 110, and FIG. 8B illustrates the insulating film 104, the layer 108_1, the layer 108_2, and the band structure.
It is a band structure in the thickness direction of the layer 108_3 and the insulating film 110. The band structure is
Energy levels (Ec) at the bottoms of the conduction bands of the insulating film 104, the layers 108_1, 108_2, 108_3, and the insulating film 110 are shown for easy understanding.

Further, here, a silicon oxide film is used as the insulating film 104 and the insulating film 110, and the layer 10
8_1 is an oxide semiconductor film formed using a metal oxide target in which the atomic ratio of metal elements is In:Ga:Zn=1:1:1.2, and the atomic ratio of metal elements is expressed as layer 108_2. An oxide semiconductor film formed using a metal oxide target of In:Ga:Zn=4:2:4.1 is used, and the atomic ratio of the metal elements is In:Ga:Zn=1:1 as the layer 108_3.
An oxide semiconductor film formed by using a metal oxide target of 1.2 is used.

As shown in FIGS. 8A and 8B, in the layers 108_1, 108_2, and 108_3, the energy at the bottom of the conduction band changes smoothly without a barrier. In other words, it can be said that it continuously changes or continuously joins. Therefore, such an energy band is also referred to as a buried channel structure.

This is because the layers 108_1, 108_2, and 108_3 have a common element, and the layers 108_
This is because oxygen migrates between 1 and the layers 108_2 and 108_3 to form a mixed layer. In addition, in order to have such a band structure, the layers 108_1 and 108-1
At the interface with 08_2 or the interface between 108_2 and layer 108_3, a stacked structure is formed so that impurities such as trap centers and recombination centers that form defect levels do not exist.

Note that a continuous bond is not formed, and the interface between the layers 108_1 and 108_2 or the layer 108_1 is formed.
When impurities are mixed at the interface between the _2 and the layer 108_3, the continuity of the energy band is lost, carriers are trapped at the interface, or are recombined and disappear.

In order to form a continuous bond, it is preferable that a film is deposited in a multi-chamber system (sputtering device) equipped with a load lock chamber so that the films are continuously laminated without exposing them to the atmosphere. Each chamber in the sputtering device is
High vacuum (up to about 5×10 −7 Pa to 1×10 −4 Pa) is preferably exhausted using an adsorption type vacuum pump such as a cryopump in order to remove impurities such as water as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that gas, particularly gas having carbon or hydrogen, does not flow backward from the exhaust system into the chamber.

With the structure illustrated in FIGS. 8A and 8B, the layer 108_2 serves as a well and the transistor 150 including the layer 108_2 and the layer 108_3, the layer 108_1, and the layer 1
It can be seen that in the transistor 150A including 08_2 and the layer 108_3, a channel region is formed in the layer 108_2.

In the transistor 150, even if a trap level due to an impurity or a defect is formed in the vicinity of the interface between the layer 108_3 and the insulating film 110, the layer 108_3 is provided to form the layer 108_2 and the trap level. You can move away from the area. Also,
In the transistor 150A, the vicinity of the interface between the layer 108_1 and the insulating film 104 and the layer 1
Even if a trap level due to an impurity or a defect is formed near the interface between 08_3 and the insulating film 110, the layers 108_1 and 108_3 are provided, so that the layer 108_2 and the region where the trap level are formed are separated from each other. be able to.

However, the energy level of the trap level is the layer 108_2 functioning as a channel region.
When the energy level becomes lower than the energy level (Ec) at the lower end of the conduction band of, electrons are easily trapped in the trap level. Electrons are trapped and accumulated in the trap level, so that negative fixed charges are generated on the surface of the insulating film and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy level of the trap level be higher than the energy level (Ec) of the bottom of the conduction band of the layer 108_2. By doing so, electrons are less likely to be accumulated in the trap level, the on-current of the transistor can be increased, and the field-effect mobility can be increased. In addition, variation in the threshold voltage of the transistor is reduced and stable electrical characteristics are obtained, which is preferable.

Further, in order to prevent the layers 108_1 and 108_3 from functioning as part of the channel region, it is preferable to use a material having lower conductivity than the layers 108_2 for the layers 108_1 and 108_3. Therefore, the layers 108_1 and 108_3 can also be referred to as oxide insulating films due to their physical properties and/or functions. Further, in the layers 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is smaller than that of the layer 108_2, and the energy level at the bottom of the conduction band is at the bottom energy level of the conduction band at the layer 108_2. It is preferable to use a material having a unit and a difference (band offset). In addition, in order to suppress a difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the bottom of the conduction band of the layers 108_1 and 108_3 is set to the energy level at the bottom of the conduction band of the layer 108_2. It is preferable to apply a material closer to the vacuum level than 0.2 eV, preferably a material closer to the vacuum level than 0.5 eV.

With such a structure, the layer 108_2 serves as a main current path in the channel region 108i. That is, the layer 108_2 has a function as a channel region and the layer 10_2
8_1 and 108_3 have a function as an oxide insulating film. In addition, the layers 108_1 and 10
8_3 is an oxide semiconductor film formed of one or more kinds of metal elements included in the layer 108_2 in which the channel region is formed; therefore, 8_3 is an interface between the layers 108_1 and 108_2 or the layer 1
Interface scattering hardly occurs at the interface between 08_2 and the layer 108_3. Therefore, carrier movement is not hindered at the interface, so that the field-effect mobility of the transistor is increased.

<1-3. Oxide semiconductor film functioning as second gate electrode>
Next, the oxide semiconductor film which functions as the second gate electrode is described. The oxide semiconductor film 112 that functions as the second gate electrode has a function of supplying oxygen to the insulating film 110. Since the oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110,
The insulating film 110 has an excess oxygen region. Since the insulating film 110 has an excess oxygen region,
The excess oxygen can be supplied to the oxide semiconductor film 108, more specifically, the channel region 108i. Therefore, by supplementing the oxygen vacancies in the channel region 108i with excess oxygen, a highly reliable semiconductor device can be obtained.

Note that in order to supply excess oxygen to the oxide semiconductor film 108, the oxide semiconductor film 10
Excess oxygen may be supplied to the insulating film 104 formed below the electrode 8. In addition, the insulating film 110 formed over the oxide semiconductor film 108 has a structure including excess oxygen, and an impurity is added to the source region 108s and the drain region 108d through the insulating film 110, whereby the channel region 108i, After supplying excess oxygen to the source region 108s and the drain region 108d, the carrier density of the source region 108s and the drain region 108d can be selectively increased.

Further, the insulating film 116 contains either one or both of nitrogen and hydrogen. Insulation film 1
With the structure in which 16 contains one or both of nitrogen and hydrogen, one or both of nitrogen and hydrogen can be supplied to the oxide semiconductor film 112.

Note that the oxide semiconductor film 112 has high carrier density by supplying oxygen to the insulating film 110 and then supplying either or both of nitrogen and hydrogen from the insulating film 116. In other words, the oxide semiconductor film 112 is formed of an oxide conductor (OC: Oxide Cond).
It also has a function as an uctor). Therefore, the oxide semiconductor film 112 has a higher carrier density than the oxide semiconductor film 108 and can function as the second gate electrode.

In addition, the source region 108s and the drain region 108d included in the oxide semiconductor film 108
The oxide semiconductor film 112 may include an element that forms oxygen vacancies. Typical examples of the element that forms the oxygen deficiency include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gas. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon.

When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken and oxygen vacancies are formed. Alternatively, when the impurity element is added to the oxide semiconductor film, oxygen that is bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, oxygen is released from the metal element, and oxygen vacancies are formed. It As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

As described above, in the semiconductor device of one embodiment of the present invention, the insulating film which covers the side surface of the oxide semiconductor film to be the channel region and is formed above the channel region functions as the second gate electrode. The oxide semiconductor film contains excess oxygen. With such a structure, a highly reliable semiconductor device can be provided.

<1-4. s-channel structure>
Next, the s-channel structure will be described.

As illustrated in FIG. 1C, the oxide semiconductor film 108 is provided so as to face the conductive film 106 functioning as a first gate electrode and the oxide semiconductor film 112 functioning as a second gate electrode. It is located and sandwiched between two conductive films or oxide semiconductor films which function as gate electrodes.

The length of the oxide semiconductor film 112 in the channel width (W) direction is as follows.
Is longer than the channel width (W) direction, and the entire channel width (W) direction of the oxide semiconductor film 108 is covered with the oxide semiconductor film 112 with the insulating film 110 interposed therebetween. In addition, since the oxide semiconductor film 112 and the conductive film 106 are connected to each other in the opening 143 provided in the insulating film 104, the layer 108_3, and the insulating film 110, the channel width (W) of the oxide semiconductor film 108
One of the side surfaces in the direction faces the oxide semiconductor film 112 with the insulating film 110 interposed therebetween.

In other words, in the channel width (W) direction of the transistor 150, the conductive film 106 and the oxide semiconductor film 112 are connected to each other in the opening 143 provided in the insulating film 104, the layer 108_3, and the insulating film 110, and the insulating film is formed. 104, the layer 108_3, and the insulating film 110
The oxide semiconductor film 108 is surrounded by the oxide semiconductor film 108.

With such a structure, the oxide semiconductor film 108 included in the transistor 150 is included.
Can be electrically surrounded by the electric fields of the conductive film 106 functioning as the first gate electrode and the oxide semiconductor film 112 functioning as the second gate electrode. Transistor 15
0, a device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by the electric field of the first gate electrode and the second gate electrode is surroud.
It can be referred to as a nested channel (s-channel) structure.

Since the transistor 150 has an s-channel structure, an electric field for inducing a channel by the conductive film 106 or the oxide semiconductor film 112 can be effectively applied to the oxide semiconductor film 108; The driving ability is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 150 can be miniaturized. Further, since the transistor 150 has a structure surrounded by the conductive film 106 and the oxide semiconductor film 112, the mechanical strength of the transistor 150 can be increased.

Note that in the channel width (W) direction of the transistor 150, an opening different from the opening 143 may be formed on the side surface of the oxide semiconductor film 108 where the opening 143 is not formed. Alternatively, the opening 143 may not be provided. An example of that case is shown in FIG.
Shown in (B) and (C). 7A is a top view of the transistor 170, FIG. 7B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 7A, and FIG. 7C is FIG. 7A. It is sectional drawing between dashed-dotted line Y1-Y2.

Further, as shown in the transistor 150, when the transistor has a pair of gate electrodes which sandwich a semiconductor film therebetween, the signal A is applied to one gate electrode and the fixed potential is applied to the other gate electrode. Vb may be given. Further, the signal A may be supplied to one gate electrode and the signal B may be supplied to the other gate electrode. In addition, a fixed potential Va is applied to one of the gate electrodes.
However, the fixed potential Vb may be applied to the other gate electrode.

The signal A is, for example, a signal for controlling the conducting state or the non-conducting state. The signal A may be a digital signal that takes two types of potentials, the potential V1 or the potential V2 (V1>V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is, for example, the threshold voltage Vt seen from one gate electrode of the transistor.
It is a potential for controlling hA. The fixed potential Vb may be the potential V1 or the potential V2. In this case, a special potential generating circuit is unnecessary. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The threshold voltage VthA may be increased by decreasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of a circuit including a transistor can be reduced in some cases. For example, the fixed potential Vb may be lower than the low power supply potential. The threshold voltage VthA may be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD can be improved, and the operation speed of a circuit including a transistor can be improved in some cases. For example, the fixed potential Vb may be higher than the low power supply potential.

The signal B is, for example, a signal for controlling the conducting state or the non-conducting state. The signal B may be a digital signal that takes two types of potentials, the potential V3 and the potential V4 (V3>V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases. At this time, the potential V1 and the potential V2 in the signal A may be different from the potential V3 and the potential V4 in the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3-V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, in some cases, the influence of the signal A and the influence of the signal B on the conduction state or the non-conduction state of the transistor can be made similar to each other.

When both the signal A and the signal B are digital signals, the signal B may have a digital value different from that of the signal A. In this case, the transistors can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases. For example, if the transistor is n
In the case of a channel type, only when the signal A is the potential V1 and the signal B is the potential V3, the conductive state is obtained, or when the signal A is the potential V2 and the signal B is the potential V4. In the case where only the non-conducting state occurs, the function of the NAND circuit, the NOR circuit, or the like may be realized by one transistor. Further, the signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal whose potential is different between a period in which a circuit including a transistor is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential depending on the operation mode of the circuit. In this case, signal B is signal A
The electric potential may not switch so often.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. It may be an analog signal or the like. In this case, the on-state current of the transistor is improved and the operation speed of the circuit including the transistor can be improved in some cases. The signal B may be an analog signal different from the signal A. In this case, the transistors can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases.

The signal A may be a digital signal and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal and the signal B may be a digital signal.

When a fixed potential is applied to both gate electrodes of the transistor, the transistor can function as a resistance element in some cases. For example, in the case where the transistor is an n-channel transistor, in some cases, the effective resistance of the transistor can be reduced (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by a transistor having only one gate may be obtained.

<1-5. Components of semiconductor device>
Next, details of components of the semiconductor device illustrated in FIGS. 1A, 1B, and 1C will be described.

[substrate]
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a particular substrate. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), SO
I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate, substrate having stainless steel foil, tungsten substrate, substrate having tungsten foil, flexible substrate, laminated film, fibrous There is a paper or a base film containing the above materials. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, the base film and the like include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). Alternatively, as an example, there is a synthetic resin such as acrylic resin. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like. Alternatively, for example, polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, paper, or the like can be given. In particular, semiconductor substrates,
By manufacturing a transistor using a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, shape, high current capability, and small size can be manufactured. When a circuit is formed using such a transistor, low power consumption of the circuit or high integration of the circuit can be achieved.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. The peeling layer can be used for separating a semiconductor device over part of or the whole of the semiconductor layer, separating it from the substrate 102, and transferring to another substrate. At that time, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate. Note that, for the above-described release layer, for example, a structure having a stacked structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed over a substrate, or the like can be used.

As an example of a substrate on which a transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) (Silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon,
(Including recycled polyester)), leather substrate, or rubber substrate. By using these substrates, formation of a transistor with excellent characteristics, formation of a transistor with low power consumption, manufacture of a device that is not easily broken, heat resistance imparted, weight reduction, or thickness reduction can be achieved.

[First gate insulating film]
As the insulating film 104, sputtering method, CVD method, vapor deposition method, pulse laser deposition (
It can be formed by appropriately using a PLD) method, a printing method, a coating method, or the like. In addition, the insulating film 104
For example, the oxide insulating film or the nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region of the insulating film 104 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. By using an oxide insulating film which releases oxygen by heating as the insulating film 104, oxygen contained in the insulating film 104 can be moved to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By thickening the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 can be obtained. 1
It is possible to reduce oxygen deficiency contained in 08i.

As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used and can be provided as a single layer or a stacked layer. In this embodiment, as the insulating film 104, a stacked-layer structure of a silicon nitride film and a silicon oxynitride film is used. As described above, by using the insulating film 104 as a stacked structure and using the silicon nitride film as the lower layer side and the silicon oxynitride film as the upper layer side, oxygen can be efficiently introduced into the oxide semiconductor film 108.

[Oxide semiconductor film]
For the oxide semiconductor film 108 and the oxide semiconductor film 112, any of the above materials can be used. Further, one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 is formed using a metal oxide such as an In-M-Zn oxide (M is Al, Ga, Y, or Sn). Alternatively, an In—Ga oxide or an In—Zn oxide may be used as the oxide semiconductor film 108 and the oxide semiconductor film 112. In particular, it is preferable that the oxide semiconductor film 108 and the oxide semiconductor film 112 be formed using a metal oxide containing the same constituent element because manufacturing costs can be reduced.

Note that when the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxides, the atomic ratio of In and M is 2 when In is the sum of In and M is 100 atomic %.
Higher than 5 atomic %, M less than 75 atomic %, or In 34 atomic
It is higher than c% and M is less than 66 atomic %.

The oxide semiconductor film 108 and the oxide semiconductor film 112 each preferably have an energy gap of 2 eV or more, or 2.5 eV or more, or 3 eV or more.

The thickness of the oxide semiconductor film 108 is 3 nm or more and 200 nm or less, preferably 3 nm or more 1
00 nm or less, and more preferably 3 nm or more and 60 nm or less. The thickness of the oxide semiconductor film 112 is 5 nm or more and 500 nm or less, preferably 10 nm or more and 300 nm or less,
More preferably, it is 20 nm or more and 100 nm or less.

When the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxides, I
The atomic ratio of the metal elements of the sputtering target used for forming the n-M-Zn oxide preferably satisfies In≧M and Zn≧M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1.
1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In
:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.
1, In:M:Zn=5:1:7 and the like are preferable. Note that the oxide semiconductor film 108 to be formed
, And the atomic ratio of the oxide semiconductor film 112 may vary by about ±40% of the atomic ratio of the metal element contained in the sputtering target. For example,
When an atomic ratio of In:Ga:Zn=4:2:4.1 is used as a sputtering target, the atomic ratio of an oxide semiconductor film to be formed is near In:Ga:Zn=4:2:3. May be

Further, in the oxide semiconductor film 108 and the oxide semiconductor film 112, when silicon or carbon which is one of the Group 14 elements is contained, oxygen vacancies increase, which might result in n-type conductivity. Therefore, in the oxide semiconductor film 108, particularly in the channel region 108i, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) is set to 2×1018 atoms/c.
It can be set to m3 or less, or 2×1017 atoms/cm3 or less. As a result,
The transistor has an electrical characteristic with a positive threshold voltage (also referred to as normally-off characteristic).
) Has.

In the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1×10 18 atoms/cm 3 or less, or 2
It can be set to x1016 atoms/cm3 or less. Alkali metal and alkaline earth metal may generate carriers when combined with an oxide semiconductor, which might increase off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has electric characteristics in which the threshold voltage is positive (also referred to as normally-off characteristics).

In addition, when the channel region 108i contains nitrogen, electrons that are carriers are generated, carrier density increases, and n-type conductivity may occur. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to have normally-on characteristics. Therefore, the channel region 1
In 08i, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration obtained by the secondary ion mass spectrometry may be 5×10 18 atoms/cm 3 or less.

Further, the carrier density of the oxide semiconductor film can be reduced by reducing the impurity element in the channel region 108i. Therefore, in the channel region 108i,
The carrier density can be 1×10 17 pieces/cm 3 or less, 1×10 15 pieces/cm 3 or less, 1×10 13 pieces/cm 3 or less, or 1×10 11 pieces/cm 3 or less.

By using an oxide semiconductor film having a low impurity concentration and a low density of defect states as the channel region 108i, a transistor having further excellent electrical characteristics can be manufactured.
Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high-purity intrinsic or substantially high-purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources.
In some cases, the carrier density can be lowered. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film is likely to have positive threshold voltage (also referred to as normally-off characteristic). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.
In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have characteristics in which off-state current is extremely small. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a small variation in electric characteristics and may be a highly reliable transistor.

Further, the source region 108s and the drain region 108d contain an impurity element. Since the source region 108s and the drain region 108d contain an impurity element, carrier density is increased. The oxide semiconductor film 112 is in contact with the insulating film 116. Oxide semiconductor film 1
When 12 is in contact with the insulating film 116, one or both of hydrogen and nitrogen are added from the insulating film 116 to the oxide semiconductor film 112, so that the carrier density is increased.

Further, one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 may have a non-single-crystal structure. The non-single crystal structure has, for example, a CAAC-OS (C Ax described later).
is Aligned Crystalline Oxide Semiconductor
or), a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest defect level density and the CAAC-OS has the lowest defect level density.

Note that the oxide semiconductor film 108 is a single-layer film having two or more kinds of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Alternatively, the film may have a laminated structure. In addition, the oxide semiconductor film 112 is a single-layer film having two or more kinds of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Alternatively, the film may have a laminated structure.

Note that in the oxide semiconductor film 108, the channel region 108i and the source region 108s
And the drain region 108d may have different crystallinity. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 10 are more than the channel region 108i.
8d may have lower crystallinity. This is the source region 108s and the drain region 1.
This is because when the impurity element is added to 08d, the source region 108s and the drain region 108d are damaged and the crystallinity is lowered.

[Second gate insulating film]
The insulating film 110 can be formed as a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region of the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga is used.
-Zn oxide or the like may be used and can be provided as a single layer or a stacked layer.

Further, by providing an insulating film having a blocking effect against oxygen, hydrogen, water, and the like as the insulating film 110, diffusion of oxygen from the oxide semiconductor film 108 to the outside and hydrogen from the outside to the oxide semiconductor film 108 are performed. It is possible to prevent intrusion of water, etc. As the insulating film having a blocking effect against oxygen, hydrogen, water, and the like, aluminum oxide, aluminum oxynitride, gallium oxide,
There are gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like.

As the insulating film 110, a high-k material such as hafnium silicate (HfSiOx), nitrogen-added hafnium silicate (HfSixOyNz), nitrogen-added hafnium aluminate (HfAlxOyNz), hafnium oxide, or yttrium oxide is used. Can reduce the gate leakage of the transistor.

Further, by using an oxide insulating film which releases oxygen by heating as the insulating film 110,
By heat treatment, oxygen contained in the insulating film 110 can be moved to the oxide semiconductor film 108.

The thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.

[First insulating film]
The insulating film 116 has one or both of nitrogen and hydrogen. Examples of the insulating film 116 include a nitride insulating film. As the nitride insulating film, silicon nitride,
It can be formed using silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The hydrogen concentration in the insulating film 116 is preferably 1×10 22 atoms/cm 3 or more. The insulating film 116 is in contact with the oxide semiconductor film 112. Therefore, the hydrogen concentration in the oxide semiconductor film 112 which is in contact with the insulating film 116 is increased and the oxide semiconductor film 11 is
The carrier density of 2 can be increased.

[Second insulating film]
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or G is used.
An a-Zn oxide or the like may be used and can be provided as a single layer or a stacked layer.

The insulating film 118 is preferably a film that functions as a barrier film against hydrogen, water, and the like from the outside.

The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 n
It can be m or less.

[Conductive film]
The conductive films 120a and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In addition, the conductive film 120a
, 120b are, for example, metal elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or alloys containing the above metal elements as components, or the above metal elements. It can be formed using a combined alloy or the like. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. The conductive films 120a and 120b may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure of stacking a titanium film on an aluminum film, a two-layer structure of stacking a titanium film on a titanium nitride film, and a nitriding film. Two-layer structure in which a tungsten film is stacked on a titanium film, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, and a titanium film is formed. A two-layer structure in which a copper film is laminated on a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure is formed on the titanium film, and a copper film is laminated on a copper film containing manganese. Further, there is a three-layer structure in which a copper film containing manganese is further formed thereon. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The conductive films 120a and 120b are formed of indium tin oxide (Indium Tin O 2 ).
xide: ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon. Thing (In-Sn
A conductive material having a light-transmitting property such as —Si oxide: ITSO) can also be used. Alternatively, a stacked-layer structure of the above light-transmitting conductive material and the above metal element can be used.

The thickness of the conductive films 120a and 120b is 30 nm or more and 500 nm or less, or 10
It can be 0 nm or more and 400 nm or less.

<1-6. Configuration example 2 of semiconductor device>
Next, for a structure different from the semiconductor device illustrated in FIGS. 1A, 1B, and 1C, FIG.
This will be described using B) and (C).

3A is a top view of the transistor 150B, FIG. 3B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 3A, and FIG. 3C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2.

The transistor 150B is different from the above-described transistor 150A in the structure of the layer 108_3. The rest of the configuration is the same as that of the transistor 150A and has the same effect.

In the top view, the layer 108_3 included in the transistor 150B has the same shape as the oxide semiconductor film 112 which functions as the second gate electrode. That is, the layer 108_3 and the oxide semiconductor film 112 are formed using the same mask. For example, layer 108_
3 is formed, the layer 108_3 is processed using the same mask as the oxide semiconductor film 112, so that the structure of the transistor 150B can be obtained.

<1-7. Configuration example 3 of semiconductor device>
Next, FIG. 1(A)(B)(C), FIG. 2(A)(B)(C), and FIG. 3(A)(B)(C).
), a structure different from that of the semiconductor device illustrated in FIGS.
This will be described with reference to (C) and FIGS. 6(A), (B) and (C).

4A is a top view of the transistor 160, FIG. 4B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 4A, and FIG. 4C is FIG. It is sectional drawing between dashed-dotted line Y1-Y2. 5A is a top view of the transistor 160A, and FIG. 5B is FIG.
5C is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 5C, and FIG.
It is a sectional view between two. FIG. 6A is a top view of the transistor 160B, and FIG.
6A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 6A, and FIG. 6C is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG. 6A.

The transistors 160, 160A and 160B are the transistors 150,
150A and 150B are different from each other in that an insulating film 117 is provided. For other configurations,
It is similar to the transistor described above and has the same effect.

The insulating film 117 can be formed using the material used for the insulating film 116. For example,
By forming the insulating film 117 over the oxide semiconductor film 112, impurities diffused into the insulating film 110 located below the oxide semiconductor film 112 and the channel region 108i are suppressed during the addition treatment of the impurity element. be able to.

As described above, in the transistor of one embodiment of the present invention, the above-described transistors may be combined as appropriate.

<1-8. Manufacturing method of semiconductor device>
Next, an example of a method for manufacturing the transistor 150 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 9A to 12C are cross-sectional views illustrating a method for manufacturing the transistor 150 in a channel length (L) direction and a channel width (W) direction.

First, the conductive film 106 is formed over the substrate 102. Next, the substrate 102 and the conductive film 106
The insulating film 104 is formed thereover, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the layer 108_2 is formed (see FIG. 9A).

In this embodiment, a 100-nm-thick tungsten film is formed as the conductive film 106 by a sputtering method.

As the insulating film 104, sputtering method, CVD method, vapor deposition method, pulse laser deposition (
It can be formed by appropriately using a PLD) method, a printing method, a coating method, or the like. In this embodiment, as the insulating film 104, a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed with a PECVD apparatus.

Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Insulating film 10
The oxygen added to 4 includes oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, and the like. Moreover, as an addition method, there are an ion doping method, an ion implantation method, a plasma treatment method and the like. Alternatively, after a film which suppresses desorption of oxygen is formed over the insulating film, oxygen may be added to the insulating film 104 through the film.

As the above-mentioned film that suppresses desorption of oxygen, a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, the above-mentioned metal element is a component. A material having conductivity such as an alloy, a combination of the above metal elements, a metal nitride containing the above metal elements, a metal oxide containing the above metal elements, and a metal nitride oxide containing the above metal elements. Can be formed by using.

When oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

The layer 108_2 can be formed by a sputtering method, a coating method, a pulsed laser evaporation method, a laser ablation method, a thermal CVD method, or the like. Note that the layer 108_2 can be processed by forming a mask over the oxide semiconductor film by a lithography step and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-isolated layer 108_2 may be formed directly over the insulating film 104 by a printing method.

When the oxide semiconductor film is formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as a power supply device for generating plasma as appropriate. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Note that in forming the oxide semiconductor film, for example, when a sputtering method is used, the substrate temperature is 150° C. to 750° C., 150° C. to 450° C., or 200° C. to 350° C. It is preferable to form a film because crystallinity can be increased.

Note that in this embodiment, a sputtering apparatus is used as the layer 108_2 and an In—Ga—Zn metal oxide (In:Ga:Zn=4:2) is used as a sputtering target.
: 4.1 [atomic ratio]) is used to form an oxide semiconductor film with a thickness of 30 nm.

In addition, after the layer 108_2 is formed, heat treatment may be performed to dehydrogenate or dehydrate the layer 108_2. The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate strain point, 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

The heat treatment can be performed in an inert gas atmosphere containing a rare gas such as helium, neon, argon, xenon, or krypton, or nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, and the like. The processing time may be 3 minutes or more and 24 hours or less.

An electric furnace, an RTA device, or the like can be used for the heat treatment. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

When the oxide semiconductor film is formed with heating, or after the oxide semiconductor film is formed, heat treatment is performed so that the hydrogen concentration in the oxide semiconductor film, which is obtained by secondary ion mass spectrometry, is 5×1019 atoms. /Cm3 or less, or 1×1019 atoms/cm3 or less, 5×1018 atoms/cm3 or less, or 1×1018 atoms/cm3 or less,
Alternatively, it can be 5×10 17 atoms/cm 3 or less, or 1×10 16 atoms/cm 3 or less.

Note that in the step of forming the layer 108_2, an oxide semiconductor film having a stacked structure is formed, the oxide semiconductor film having the stacked structure is processed into an island shape, and the layers 108_1 and 108_2 are formed, The transistor 150A described above can be formed.

Next, the layer 108_3 and the insulating film 110_0 are formed over the insulating film 104, the layer 108_2 (see FIG. 9B).

The layer 108_3 is formed so as to cover the side surface of the layer 108_2. Note that the layer 108_
3 can be formed by using the same material and the same method as the layer 108_2 described above.

In this embodiment, a sputtering apparatus is used as the layer 108_3, and an In—Ga—Zn metal oxide (In:Ga:Zn=1:3:4[
The atomic number ratio]) is used to form an oxide semiconductor film with a thickness of 5 nm.

As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film is formed by PE.
It can be formed using the CVD method. In this case, it is preferable to use a deposition gas containing silicon and an oxidizing gas as the source gas. Typical examples of the deposition gas containing silicon are silane, disilane, trisilane, fluorinated silane, and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Further, as the insulating film 110_0, the oxidizing gas to the deposition gas is more than 20 times larger than the oxidizing gas.
A silicon oxynitride film with a small amount of defects can be formed by a PECVD method in which the pressure in the treatment chamber is less than 100 times, less than 40 times, less than 40 times, and less than 100 times, and less than 100 times less than 50 Pa.

As the insulating film 110_0, a substrate placed in a vacuum-evacuated processing chamber of a PECVD apparatus is held at 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa or higher. The insulating film 110_ is more preferably 100 Pa or more and 250 Pa or less depending on the condition of supplying high-frequency power to the electrodes provided in the processing chamber.
As a result, a dense silicon oxide film or a dense silicon oxynitride film can be formed.

Alternatively, the insulating film 110_0 may be formed by a plasma CVD method using a microwave. Microwave refers to a frequency range of 300 MHz to 300 GHz. In microwave, electron temperature is low and electron energy is small. Further, in the supplied electric power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of a larger number of molecules, and high density plasma (high density plasma) can be excited. .. For this reason,
The insulating film 110_0 with less defects can be formed with less plasma damage to the deposition surface and the deposit.

Further, the insulating film 110_0 can be formed by a CVD method using an organosilane gas. As the organic silane gas, ethyl silicate (TEOS: chemical formula Si(OC2H5)4
), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)). 3),
A silicon-containing compound such as trisdimethylaminosilane (SiH(N(CH3)2)3) can be used. By using the CVD method using an organic silane gas, the insulating film 110_0 with high coverage can be formed.

In this embodiment, as the insulating film 110_0, a PECVD apparatus is used to form a 100-nm-thick silicon oxynitride film.

Next, after forming a mask by lithography at a desired position on the insulating film 110_0,
The opening 143 reaching the conductive film 106 is formed by etching the insulating film 110_0, the layer 108_3, and part of the insulating film 104 (see FIG. 9C).

As a method for forming the opening 143, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment mode, a dry etching method is used,
The opening 143 is formed.

Next, the oxide semiconductor film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that when the oxide semiconductor film 112_0 is formed, the oxide semiconductor film 112_
Oxygen is added to the insulating film 110_0 from 0 (see FIG. 9D).

Note that in FIG. 9D, oxygen added to the insulating film 110_0 is schematically illustrated by an arrow. By forming the oxide semiconductor film 112_0 so as to cover the opening 143, the conductive film 106 and the oxide semiconductor film 112_0 are electrically connected to each other.

As a method for forming the oxide semiconductor film 112_0, a sputtering method is preferably used, and the oxide semiconductor film 112_0 is preferably formed in an atmosphere containing oxygen gas. By forming the oxide semiconductor film 112_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be favorably added to the insulating film 110_0.

Note that in FIG. 9D, oxygen added to the insulating film 110_0 is schematically illustrated by an arrow. For the oxide semiconductor film 112_0, a material similar to that of the layer 108_2 described above can be used.

In this embodiment, a sputtering apparatus is used as the oxide semiconductor film 112_0, and an In—Ga—Zn metal oxide (In:Ga:Zn=) is used as a sputtering target.
4:2:4.1 [atomic number ratio]) is used to form an oxide semiconductor film with a thickness of 100 nm.

Next, a mask 1 is formed at a desired position on the oxide semiconductor film 112_0 by a lithography process.
40 is formed (see FIG. 10A).

Next, the island-shaped oxide semiconductor film 112 is formed by etching the mask 140 to process the oxide semiconductor film 112_0 and then removing the mask 140 (FIG. 10).
(See (B)).

The oxide semiconductor film 112_0 may be processed by, for example, a wet etching method or a dry etching method. In this embodiment, the oxide semiconductor film 112
The processing of _0 is performed using a dry etching method.

Next, the impurity element 145 is added over the insulating film 110 and the oxide semiconductor film 112 (see FIG. 10C).

As a method for adding the impurity element 145, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. In the case of the plasma treatment method, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing plasma treatment. As a device for generating the plasma, a dry etching device, an ashing device,
A plasma CVD device, a high-density plasma CVD device, or the like can be used.

Note that B2H6, PH3, CH4, N2, NH3 are used as a source gas of the impurity element 145.
, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2 and one or more rare gases can be used. Alternatively, B2H6, PH3, N2, NH3 diluted with a rare gas,
One or more of AlH3, AlCl3, F2, HF, and H2 can be used. By adding the impurity element 145 to the layer 108_2 and the oxide semiconductor film 112 using one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with a rare gas, , Hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the layer 108_2 and the oxide semiconductor film 112.

Alternatively, after adding a rare gas, B2H6, PH3, CH4, N2, NH3, AlH3,
One or more of AlCl3, SiH4, Si2H6, F2, HF, and H2 may be added to the layer 108_2 and the oxide semiconductor film 112.

Alternatively, B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4
, Si2H6, F2, HF, and H2, and then the rare gas may be added to the layer 108_2 and the oxide semiconductor film 112.

The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose amount. For example, when argon is added by the ion implantation method, an acceleration voltage of 10 kV or more 1
00 kV or less, the dose amount is 1×1013 ions/cm2 or more and 1×1016 ions/c
m2 or less, for example, 1×1014 ions/cm2. When phosphorus ions are added by the ion implantation method, the acceleration voltage is 30 kV and the dose amount is 1×1013.
Ions/cm 2 or more and 5×10 16 ions/cm 2 or less, for example, 1×1
It may be 015ions/cm2.

In addition, although the structure in which the impurity element 145 is added after the mask 140 is removed is described in this embodiment mode, the present invention is not limited to this. For example, the impurity element 145 can be removed with the mask 140 left. You may add.

In this embodiment mode, a doping device is used as the impurity element 145,
Phosphorus ions are added to the oxide semiconductor film 108 and the oxide semiconductor film 112. However, the present invention is not limited to this, and for example, the step of adding the impurity element 145 may not be performed.

Note that the source region 108s and the drain region 108d are formed in the layers 108_2 and 108_3 by adding the impurity element 145. In addition, the oxide semiconductor film 112
A channel region 108i is formed in the layer 108_2 and the layer 108_3 which overlap with the channel region 108i. Thus, the oxide semiconductor film 108 of one embodiment of the present invention is formed (see FIG. 10C).

As described above, the oxide semiconductor film 108 includes a channel region 108i over which the oxide semiconductor film 112 overlaps, a source region 108s provided in contact with the channel region 108i, and a drain region 108d provided in contact with the channel region 108i. And has a channel region 108
i has a structure including the layer 108_2 and the layer 108_3 which is in contact with the upper surface of the layer 108_2 and covers the side surface of the layer 108_2 in the channel width direction.

Note that in the case where the impurity element 145 is added to the surface of the oxide semiconductor film 108 without providing the insulating film 110, the source region 108s is damaged due to damage at the time of adding the impurity element 145.
In some cases, the crystallinity of the drain region 108d is lowered. On the other hand, the source region 108s
By adding the impurity element 145 through the insulating film 110 when forming the drain region 108d and the drain region 108d, damage at the time of adding the impurity element 145 is suppressed, and the source region 108s is formed.
Further, deterioration of crystallinity of the drain region 108d can be suppressed.

Next, the insulating film 116 is formed over the insulating film 110 and the oxide semiconductor film 112 (FIG. 11).
(See (A)).

Note that the insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. In this embodiment mode, a PECVD apparatus is used as the insulating film 116.
A 100-nm-thick silicon nitride film is formed.

By using a silicon nitride film as the insulating film 116, hydrogen in the silicon nitride film can enter the oxide semiconductor film 112 which is in contact with the insulating film 116 and the carrier density of the oxide semiconductor film 112 can be increased.

Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 11B).

The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. In this embodiment mode, as the insulating film 118, a PECVD apparatus is used and the thickness is 3
A 00 nm silicon oxynitride film is formed.

Next, a mask is formed at a desired position of the insulating film 118 by lithography, and then the insulating film 118, the insulating film 116, the insulating film 110, and part of the layer 108_3 are etched to reach the source region 108s. A portion 141a and an opening 141b reaching the drain region 108d are formed (see FIG. 11C).

As a method for etching the insulating film 118, the insulating film 116, the insulating film 110, and the layer 108_3, a wet etching method and/or a dry etching method can be used. In this embodiment mode, the insulating film 118, the insulating film 116, and
The insulating film 110 and the layer 108_3 are processed.

Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 141a and 141b (see FIG. 12A).

The conductive film 120 can be formed by selecting a material that can be used for the conductive films 120a and 120b. In this embodiment, as the conductive film 120, a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a thickness of 100 are used with a sputtering apparatus.
A laminated film of titanium films having a thickness of nm is formed.

Next, after forming a mask at a desired position on the conductive film 120 by a lithography process,
The conductive films 120a and 120b are formed by etching part of the conductive film 120 (see FIG. 12B).

As a method for processing the conductive film 120, a wet etching method and/or a dry etching method can be used. In this embodiment mode, the conductive film 12 is formed by a dry etching method.
0 is processed to form conductive films 120a and 120b.

Through the above steps, the transistor 150 illustrated in FIG. 1 can be manufactured.

Note that a film (an insulating film, an oxide semiconductor film, a conductive film, or the like) or a layer included in the transistor 150 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, or an ALD. It can be formed using the (atomic layer deposition) method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is a MOCVD (metal organic chemical vapor deposition) method.

In the thermal CVD method, a chamber is set to atmospheric pressure or reduced pressure, a source gas and an oxidant are simultaneously sent into the chamber, and a film is formed by reacting in the vicinity of the substrate or on the substrate and depositing on the substrate. As described above, the thermal CVD method is a film forming method that does not generate plasma, and therefore has an advantage that defects are not generated due to plasma damage.

Further, in the ALD method, the inside of the chamber is set at atmospheric pressure or reduced pressure, a source gas for reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas (argon, nitrogen, etc.) may be introduced as a carrier gas together with the source gas. For example, two or more kinds of source gas may be sequentially supplied to the chamber. At that time, an inert gas is introduced and a second source gas is introduced after the reaction of the first source gas so that plural kinds of source gases are not mixed. Alternatively, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum evacuation and then the second raw material gas may be introduced. The first source gas is adsorbed/reacted on the surface of the substrate to form a first layer, and the second source gas introduced later is adsorbed/reacted to form the first layer.
To form a thin film. By repeating the gas introduction sequence a plurality of times while controlling the gas introduction sequence, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times gas is introduced repeatedly, it is possible to precisely adjust the film thickness, which is suitable for manufacturing a fine FET.

The thermal CVD method such as the MOCVD method can form films such as the above-described conductive film, insulating film, oxide semiconductor film, and metal oxide film. For example, an In-Ga-Zn-O film is formed. In this case, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)
) 3) and dimethyl zinc are used (Zn(CH3)2). Not limited to these combinations, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH3)2]4) Two kinds of gases are used: a raw material gas obtained by vaporizing a hafnium amide such as or tetrakis(ethylmethylamide) hafnium) and ozone (O3) as an oxidizing agent.

For example, when forming an aluminum oxide film by a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH3)
3) and the like) are vaporized, and two kinds of gases, H2O, are used as oxidants. Other materials include tris(dimethylamide) aluminum, triisobutyl aluminum,
Aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, in the case of forming a silicon oxide film by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface and radicals of an oxidizing gas (O2, dinitrogen monoxide) are supplied to the adsorbate. React with.

For example, when a tungsten film is formed by a film forming apparatus using ALD, WF6
Gas and B2H6 gas are sequentially introduced to form an initial tungsten film, and then a WF6 gas and H2 gas are used to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

For example, an oxide semiconductor film, for example, In-Ga-Zn-, is formed by a film formation apparatus using ALD.
When forming an O film, an In-O layer is formed using In(CH3)3 gas and O3 gas, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. , And then Z
A ZnO layer is formed using n(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. In addition, instead of O3 gas, Ar
H2O gas obtained by bubbling water with an inert gas such as H2O may be used, but O3 gas containing no H is preferably used.

As described above, the structure and the method described in this embodiment can be combined with the structures and methods described in other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a structure and the like of an oxide semiconductor will be described with reference to FIGS.

<2-1. Structure of oxide semiconductor>
The oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, CAAC-OS (c-axis-alignment) is used.
d crystalline oxide semiconductor, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
), a pseudo-amorphous oxide semiconductor (a-like OS: amorphous)
Like oxide semiconductors and amorphous oxide semiconductors.

From another viewpoint, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, CAAC
-OS, polycrystalline oxide semiconductor, nc-OS, and the like.

Amorphous structure is generally isotropic and does not have a heterogeneous structure, metastable state in which the arrangement of atoms is not fixed, bond angle is flexible, short-range order but long-range order It is said that they do not have

From the opposite viewpoint, a stable oxide semiconductor is completely amorphous.
cannot be called an oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor.
On the other hand, the a-like OS has an unstable structure having a void (also referred to as a void), although it is not isotropic. The a-like OS is physically similar to an amorphous oxide semiconductor in that it is unstable.

<2-2. CAAC-OS>
First, the CAAC-OS will be described.

The CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, InGaZnO4 classified into the space group R-3m
When the structural analysis of the CAAC-OS having the crystal of No. 3 by the out-of-plane method is performed, a peak appears at a diffraction angle (2θ) of around 31° as illustrated in FIG. Since this peak is assigned to the (009) plane of the InGaZnO 4 crystal, the CAAC-OS
In, it can be confirmed that the crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface (also referred to as a formation surface) on which the CAAC-OS film is formed or the upper surface. Note that 2θ is 31
In addition to the peak in the vicinity of °, a peak may appear in the vicinity of 2θ of 36°. 2θ is 36°
The peaks in the vicinity are due to the crystal structure classified into the space group Fd-3m. Therefore, CAA
C-OS preferably does not show the peak.

On the other hand, in-pl which makes X-rays incident on the CAAC-OS from a direction parallel to the formation surface.
When structural analysis is performed by the ane method, a peak appears at 2θ of around 56°. This peak is
It is assigned to the (110) plane of the InGaZnO4 crystal. Then, 2θ is fixed in the vicinity of 56° and analysis is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) (φ scan).
However, no clear peak appears as shown in FIG. 13(B). On the other hand, single crystal InGa
When 2θ is fixed in the vicinity of 56° with respect to ZnO 4 and φ scan is performed, as shown in FIG. 13C, six peaks belonging to a crystal plane equivalent to the (110) plane are observed. Therefore,
From structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular a-axis and b-axis orientations.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, InGa
When an electron beam having a probe diameter of 300 nm is incident on the CAAC-OS having ZnO 4 crystals in parallel to the surface where the CAAC-OS is formed, a diffraction pattern ((D) shown in FIG.
Also called a selected area electron diffraction pattern. ) May appear. In this diffraction pattern, I
A spot due to the (009) plane of the crystal of nGaZnO4 is included. Therefore, electron diffraction also reveals that the pellets included in the CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 13E shows a diffraction pattern when an electron beam with a probe diameter of 300 nm is made to enter the same sample perpendicularly to the sample surface.
). From FIG. 13E, a ring-shaped diffraction pattern is confirmed. Therefore, it is found that the a-axis and the b-axis of the pellet included in the CAAC-OS do not have orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 13E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO 4 crystal. The second ring in FIG. 13E is considered to be derived from the (110) plane and the like.

In addition, a transmission electron microscope (TEM) is used.
A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS by an electron microscope. On the other hand, even in a high-resolution TEM image, a boundary between pellets, that is, a grain boundary (also referred to as a grain boundary) may not be clearly confirmed in some cases. Therefore, CAA
It can be said that C-OS is unlikely to cause a decrease in electron mobility due to crystal grain boundaries.

FIG. 14A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of high resolution TEM images, spherical aberration correction (Spherical A
Berration Corrector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 14A, a pellet which is a region where metal atoms are arranged in layers can be confirmed. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be called a nanocrystal (nc). In addition, CAAC-OS is replaced by CANC (C-Axis Aligned na).
It can also be referred to as an oxide semiconductor having no crystals. Pellets are CAA
The C-OS film reflects unevenness on the formation surface or the top surface and is parallel to the formation surface or the top surface of the CAAC-OS.

In addition, in FIGS. 14B and 14C, CAA observed from a direction substantially perpendicular to the sample surface.
The Cs correction|amendment high resolution TEM image of the plane of C-OS is shown. FIGS. 14D and 14E are images obtained by performing image processing on FIGS. 14B and 14C, respectively. The method of image processing will be described below. First, FIG. 14B is converted into a fast Fourier transform (FFT: Fast).
An FFT image is acquired by performing a Fourier Transform) process. Next, mask processing is performed to leave a range between 2.8 nm-1 and 5.0 nm-1 in the acquired FFT image with the origin as a reference. Next, an inverse fast Fourier transform (IFFT) is applied to the masked FFT image.
: Inverse Fast Fourier Transform) processing is performed to obtain the image-processed image. The image thus obtained is called an FFT filtered image. FFT
The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and shows a lattice array.

In FIG. 14D, broken lines indicate broken grid portions. The area surrounded by the broken line is one pellet. And the part shown by the broken line is the connecting portion between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. The shape of the pellet is not limited to the regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 14E, a dotted line indicates a portion where the orientation of the lattice array is changed between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned. It is indicated by a broken line. Even in the vicinity of the dotted line, no clear grain boundary can be confirmed. A distorted hexagon can be formed by connecting the surrounding grid points around the grid point near the dotted line. That is, it is understood that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is the CAAC-OS
It is considered that the strain can be allowed due to the fact that the bond distance between atoms is not dense in the ab plane direction, the bond distance between atoms changes due to substitution with a metal element, and the like.

As described above, the CAAC-OS has a c-axis orientation and has a strained crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction. Therefore, C
AAC-OS, CAA crystal (c-axis-aligned a-b-p
It can also be called a lane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. The crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like;
It can be said that S is an oxide semiconductor with few impurities and defects (such as oxygen deficiency).

Note that the impurity is an element other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor deprives the oxide semiconductor of oxygen, which disturbs the atomic arrangement of the oxide semiconductor and reduces crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon,
Carbon dioxide or the like has a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes deterioration of crystallinity.

When the oxide semiconductor has impurities or defects, characteristics thereof may be changed by light, heat, or the like. For example, an impurity contained in the oxide semiconductor may serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor might serve as carrier traps or serve as carrier generation sources by capturing hydrogen.

The CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, the oxide has a carrier density of less than 8×10 11 pieces/cm 3, preferably less than 1×10 11/cm 3, more preferably less than 1×10 10 pieces/cm 3, and having a carrier density of 1×10 −9 pieces/cm 3 or more. It can be a semiconductor. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<2-3. nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by the out-of-plane method, no peak showing orientation is observed. That is, the nc-OS crystal has no orientation.

In addition, for example, the nc-OS having a crystal of InGaZnO4 is thinned to have a thickness of 34n.
When an electron beam with a probe diameter of 50 nm is made to enter the area m in parallel to the surface to be formed,
A ring-shaped diffraction pattern (nano-beam electron diffraction pattern) as shown in FIG. 5(A) is observed. In addition, a diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (
The nanobeam electron diffraction pattern) is shown in FIG. From FIG. 15B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS has a probe diameter of 50 nm.
The ordering is not confirmed by injecting the electron beam of, but the ordering is confirmed by injecting the electron beam having a probe diameter of 1 nm.

When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon is observed as shown in FIG. There are cases where Therefore, it is understood that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. In addition, since the crystals are oriented in various directions, there are regions where a regular electron diffraction pattern is not observed.

FIG. 15D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed in a direction substantially parallel to the formation surface. In the high-resolution TEM image, the nc-OS has a region where crystal parts can be confirmed, such as a portion indicated by an auxiliary line, and a region where clear crystal parts cannot be confirmed. The crystal part included in the nc-OS has a size of 1 nm to 10 nm, in particular, a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor whose crystal portion has a size of more than 10 nm and 100 nm or less is referred to as a microcrystalline oxide semiconductor (fine).
It may be referred to as a crystalline oxide semiconductor). In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

As described above, the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm inclusive, particularly a region of 1 nm to 3 nm inclusive). Also, nc-OS
Has no regularity in crystal orientation between different pellets. Therefore, the orientation is not seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

Since the crystal orientations between pellets (nanocrystals) do not have regularity, the nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than the a-like OS or an amorphous oxide semiconductor. However, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<2-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.

FIG. 16 shows a high-resolution cross-sectional TEM image of a-like OS. Here, FIG. 16(A)
[FIG. 4] is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. 16 (
B) is a high-resolution cross-sectional TEM image of a-like OS after electron (e-) irradiation of 4.3×10 8 e−/nm 2. From FIG. 16(A) and FIG. 16(B), a-like O
It can be seen that in S, a striped bright region extending in the longitudinal direction is observed from the start of electron irradiation. Also, it is found that the shape of the bright region changes after the electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. In the following, a-lik
Since eOS has a more unstable structure than CAAC-OS and nc-OS, the structure change due to electron irradiation is shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. All the samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, each sample has a crystal part.

The unit cell of the InGaZnO 4 crystal has three In—O layers and also has a Ga—Zn structure.
It is known that a total of 9 layers having 6 -O layers are layered in the c-axis direction. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore,
In the following, the portion where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ.
It was regarded as a crystal part of nO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

FIG. 17 is an example in which the average size of the crystal parts (22 to 30 points) of each sample was investigated. The length of the lattice fringes described above is the size of the crystal part. From FIG. 17, a-lik
It can be seen that in the eOS, the crystal part becomes larger according to the cumulative irradiation amount of electrons related to the acquisition of the TEM image. From FIG. 17, a crystal part (also referred to as an initial nucleus), which had a size of about 1.2 nm in the initial observation with TEM, had an accumulated irradiation dose of electrons (e−) of 4.2×10 8 e.
At −/nm2, it can be seen that the growth has reached a size of about 1.9 nm. On the other hand, n
In the c-OS and the CAAC-OS, the cumulative irradiation amount of electrons is 4.2×10 from the start of electron irradiation.
It can be seen that there is no change in the size of the crystal part in the range up to 8e-/nm2. FIG. 17
From this, it can be seen that the sizes of the crystal parts of the nc-OS and the CAAC-OS are about 1.3 nm and about 1.8 nm, respectively, regardless of the cumulative dose of electrons. For electron beam irradiation and TEM observation, Hitachi transmission electron microscope H-9000NAR was used. The electron beam irradiation conditions were an accelerating voltage of 300 kV, a current density of 6.7×10 5 e −/(nm 2 ·s), and a diameter of an irradiation region of 230 nm.

As described above, in the a-like OS, the growth of the crystal part may be observed by the electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, almost no crystal part growth due to electron irradiation is observed. That is, it is found that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Also, the density of nc-OS and CAA
The density of C-OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a single crystal density of less than 78%.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio],
The density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g/cm 3. Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm 3 or more and less than 5.9 g/cm 3. Further, for example, in an oxide semiconductor that satisfies In:Ga:Zn=1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g/cm 3 or more and 6.3 g/cm 3 or more.
It becomes less than 3.

When single crystals having the same composition do not exist, the density corresponding to the single crystal having the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio.
The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to a ratio of combining single crystals having different compositions. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics.
Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, a-like OS, or nc-OS.
, CAAC-OS, a stacked film including two or more kinds may be used.

As described above, the structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments or the examples.

(Embodiment 3)
In this embodiment, an example of a display device including the transistor described in any of the above embodiments will be described below with reference to FIGS.

FIG. 18 is a top view showing an example of a display device. The display device 700 shown in FIG.
The pixel portion 702 provided on the substrate 701, the source driver circuit portion 704 and the gate driver circuit portion 706 provided on the first substrate 701, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion. The sealing material 712 is provided so as to surround the substrate 706, and the second substrate 705 is provided so as to face the first substrate 701. In addition,
The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Although not shown in FIG. 18, a display element is provided between the first substrate 701 and the second substrate 705.

In the display device 700, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the gate driver circuit portion are provided in a region different from the region surrounded by the sealant 712 on the first substrate 701. 706 and an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to each other are provided. An FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. FPC
Various signals and the like supplied by 716 are given to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

Further, the display device 700 may be provided with a plurality of gate driver circuit portions 706. Further, although the display device 700 shows an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702, the present invention is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. .. Note that the method of connecting the separately formed drive circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a plurality of transistors, and the transistor which is a semiconductor device of one embodiment of the present invention can be applied. ..

In addition, the display device 700 can include various elements. As an example of the element,
For example, electroluminescence (EL) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements, LEDs, etc.), light emitting transistor elements (transistors that emit light in response to current), electron emission elements, liquid crystal elements, electrons Ink element, electrophoretic element, electrowetting element, plasma display (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (G
LV), digital micro mirror device (DMD), digital micro shutter (DMS) element, interference modulation (IMOD) element, etc.), piezoelectric ceramic display, and the like.

An example of a display device using an EL element is an EL display. A field emission display (FE) is an example of a display device using an electron-emitting device.
D) or SED type flat-panel display (SED: Surface-conductio)
n Electron-emitter Display). Examples of a display device using a liquid crystal element include a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). As an example of a display device using an electronic ink element or an electrophoretic element,
There is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have a function as a reflective electrode. For example, part or all of the pixel electrode may include aluminum, silver, or the like. Further, in that case, a memory circuit such as SRAM can be provided below the reflective electrode. Thereby, the power consumption can be further reduced.

The display system 700 may use a progressive system, an interlace system, or the like. Further, as a color element controlled by the pixel when displaying in color, R is
It is not limited to the three colors of GB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pen tile array, one color element may be configured by two colors of RGB, and two different colors may be selected and configured by the color element. Alternatively, one or more colors of yellow, cyan, magenta, etc. may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

Further, a colored layer (also referred to as a color filter) is used in order to display a display device in full color by using white light emission (W) for a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. The colored layer may be, for example, red (R), green (G), blue (B)
), yellow (Y) and the like can be used in an appropriate combination. By using the colored layer, color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, by arranging a region having a colored layer and a region not having a colored layer, white light in the region having no colored layer may be directly used for display. By arranging a region that does not have a colored layer in part, it is possible to reduce the decrease in brightness due to the colored layer during bright display, and to reduce power consumption.
In some cases, it can be reduced by about 30% to 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from the elements having respective luminescent colors. By using the self-luminous element, power consumption may be further reduced as compared with the case where the colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) of converting a part of the light emission from the above white light emission into red, green, and blue by passing through a color filter, red, green, and blue light emission A method to be used respectively (three-color method) or a method for converting a part of light emitted from blue light to red or green (color conversion method, quantum dot method) may be applied.

In this embodiment mode, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. Note that FIG. 19 is a cross-sectional view taken along alternate long and short dash line QR in FIG. 18 and has a structure in which a liquid crystal element is used as a display element. 20 is a cross-sectional view taken along alternate long and short dash line QR shown in FIG. 18, and has a structure using an EL element as a display element.

First, common parts shown in FIGS. 19 and 20 will be described first, and then different parts will be described below.

<3-1. Description of common parts of display device>
The display device 700 illustrated in FIGS. 19 and 20 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 has a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

The transistors 750 and 752 have a structure similar to that of the transistor 150 described above. Note that for the structures of the transistor 750 and the transistor 752, any of the other transistors described in the above embodiments may be used.

The transistor used in this embodiment has an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. The off-state current of the transistor can be low. Therefore, the holding time of an electric signal such as an image signal can be extended and the writing interval can be set long in the power-on state. Therefore, the frequency of refresh operations can be reduced, which leads to an effect of suppressing power consumption.

Further, the transistor used in this embodiment can have relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, in the pixel portion as well, by using a transistor which can be driven at high speed, a high-quality image can be provided.

The capacitor 790 includes a first oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, and a conductive film functioning as a source electrode and a drain electrode included in the transistor 750. A film and an upper electrode formed through a step of processing the same conductive film. In addition, a step of forming the same insulating film between the lower electrode and the upper electrode as the second insulating film included in the transistor 750 and the third insulating film An insulating film is formed after that. That is,
The capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

19 and 20, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the planarization insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed of these materials. Alternatively, the planarization insulating film 770 may be omitted.

The signal line 710 is formed through the same steps as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a step different from that of the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same step as an oxide semiconductor film functioning as a gate electrode. Membranes may be used. When a material containing a copper element, for example, is used as the signal line 710, signal delay or the like due to wiring resistance is small and display on a large screen is possible.

The FPC terminal portion 708 includes the connection electrode 760, the anisotropic conductive film 780, and the FPC 71.
Have six. Note that the connection electrode 760 is formed through the same steps as a conductive film functioning as a source electrode and a drain electrode of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, flexible substrates may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching the insulating film,
It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix,
A coloring film 736 which functions as a color filter and an insulating film 734 which is in contact with the light-blocking film 738 and the coloring film 736 are provided.

<3-2. Configuration example of display device using liquid crystal element>
The display device 700 illustrated in FIG. 19 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is formed on the second substrate 705.
It is provided on the side and has a function as a counter electrode. The display device 700 illustrated in FIG. 19 can display an image by controlling the light transmission and non-light transmission by changing the alignment state of the liquid crystal layer 776 by the voltage applied to the conductive films 772 and 774.

In addition, the conductive film 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. In addition, the conductive film 772 has a function as a reflective electrode. The display device 700 illustrated in FIG. 19 is a so-called reflective color liquid crystal display device in which light is reflected by the conductive film 772 by using external light and is displayed through the coloring film 736.

As the conductive film 772, a conductive film having a property of transmitting visible light or a conductive film having a property of reflecting visible light can be used. As a conductive film that transmits visible light,
For example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective to visible light, a material containing aluminum or silver may be used, for example. In this embodiment mode, as the conductive film 772,
A conductive film having reflectivity in visible light is used.

In addition, in the display device 700 illustrated in FIG. 19, unevenness is provided in part of the planarization insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing unevenness on the surface of the resin film. In addition, the conductive film 772 which functions as a reflective electrode is formed along the unevenness. Therefore, the external light is not reflected by the conductive film 772.
When it is incident on, it becomes possible to diffusely reflect light on the surface of the conductive film 772, and the visibility can be improved.

Note that the display device 700 illustrated in FIG. 19 is a reflective color liquid crystal display device as an example; however, the display device 700 is not limited thereto. For example, the conductive film 772 transmits visible light by using a light-transmitting conductive film. Type color liquid crystal display device may be used. In the case of a transmissive color liquid crystal display device, the unevenness provided in the planarization insulating film 770 may not be provided.

Although not shown in FIG. 19, an alignment film may be provided on each of the conductive films 772 and 774 which is in contact with the liquid crystal layer 776. Although not shown in FIG. 19, an optical member (optical substrate) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight or the like may be used as the light source.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

In the case of adopting the horizontal electric field method, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears when the temperature of the cholesteric liquid crystal is increased and immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral agent of several wt% or more is mixed is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent,
Since the response speed is short and it is optically isotropic, no alignment treatment is required. Further, since it is not necessary to provide an alignment film, rubbing treatment is not necessary, so that electrostatic breakdown caused by the rubbing treatment can be prevented and defects and damages of the liquid crystal display device during a manufacturing process can be reduced. .. A liquid crystal material exhibiting a blue phase has a small viewing angle dependence.

When a liquid crystal element is used as a display element, TN (Twisted Nematic)
) Mode, IPS (In-Plane-Switching) mode, FFS (Frin)
ge Field Switching mode, ASM (Axial Symmetry)
tric aligned Micro-cell) mode, OCB (Optical)
Compensated Birefringence mode, FLC (Ferroe)
Electric Liquid Crystal mode, AFLC (AntiFerr)
The electric liquid crystal) mode and the like can be used.

Further, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, MVA (Multi-Domain Vertical Alignment) is used.
) Mode, PVA (Patterned Vertical Alignment) mode, ASV mode and the like can be used.

<3-3. Display device using light emitting element>
The display device 700 illustrated in FIG. 20 includes a light emitting element 782. The light emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 20 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.

The conductive film 784 is connected to a conductive film which functions as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film which transmits visible light or a conductive film which reflects visible light can be used. As the conductive film having a property of transmitting visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective to visible light, a material containing aluminum or silver may be used, for example.

Further, in the display device 700 illustrated in FIG. 20, the insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers part of the conductive film 784. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and E
The light emitted from the L layer 786 is transmitted. It should be noted that although the top emission structure is illustrated in the present embodiment, the present invention is not limited to this. For example, the invention can be applied to a bottom emission structure in which light is emitted to the conductive film 784 side and a dual emission structure in which light is emitted to both the conductive film 784 and the conductive film 788.

In addition, a colored film 736 is provided in a position overlapping with the light emitting element 782, and a light shielding film 738 is provided in a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with the insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that FIG.
In the display device 700 shown in (1), the configuration in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed by coating separately, the coloring film 736 may not be provided.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 4)
In this embodiment mode, an example of a circuit structure of a semiconductor device in which stored contents can be held even when power is not supplied and the number of times of writing is not limited is described with reference to FIGS.

<4-1. Circuit configuration>
FIG. 21 is a diagram illustrating a circuit configuration of a semiconductor device. In FIG. 21, the first wiring (
1st Line) and one of the source electrode and the drain electrode of the p-type transistor 1280a are electrically connected. Further, the other of the source electrode and the drain electrode of the p-type transistor 1280a and the one of the source electrode and the drain electrode of the n-type transistor 1280b are electrically connected. Further, the other of the source and drain electrodes of the n-type transistor 1280b and one of the source and drain electrodes of the n-type transistor 1280c are electrically connected.

In addition, the second wiring (2nd Line) and one of a source electrode and a drain electrode of the transistor 1282 are electrically connected to each other. The other of the source electrode and the drain electrode of the transistor 1282 is electrically connected to one of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c.

The third wiring (3rd Line) is electrically connected to the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b. In addition, the fourth wiring (4
th Line) and the gate electrode of the transistor 1282 are electrically connected. The fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 1281 and the other of the source electrode and the drain electrode of the n-type transistor 1280c. In addition, the sixth wiring (6th Line) is electrically connected to the other of the source electrode and the drain electrode of the p-type transistor 1280a and one of the source electrode and the drain electrode of the n-type transistor 1280b.

Note that the transistor 1282 is an oxide semiconductor (OS: Oxide Semiconductor).
rector). Therefore, in FIG. 21, the symbol “OS” is added to the transistor 1282. Note that the transistor 1282 may be formed using a material other than an oxide semiconductor.

Further, in FIG. 21, a floating node (FN) is added to a connection portion between the other of the source electrode and the drain electrode of the transistor 1282, one of the electrodes of the capacitor 1281, and the gate electrode of the n-type transistor 1280c. There is. By turning off the transistor 1282, the floating node, one of the electrodes of the capacitor 1281, and n
The potential applied to the gate electrode of the type transistor 1280c can be held.

In the circuit configuration shown in FIG. 21, by utilizing the feature that the potential of the gate electrode of the n-type transistor 1280c can be held, writing, holding, and reading of information can be performed as follows.

<4-2. Writing and retaining information>
First, writing and holding of information will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, so that the transistor 1282 is turned on. Accordingly, the potential of the second wiring is the gate electrode of the n-type transistor 1280c and the capacitance element 12
81. That is, a predetermined charge is applied to the gate electrode of the n-type transistor 1280c (writing). After that, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, so that the transistor 1282 is turned off. As a result, the charge applied to the gate electrode of the n-type transistor 1280c is retained (retained).

Since the off-state current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is held for a long time.

<4-3. Read information>
Next, reading of information will be described. When the potential of the third wiring is set to the Low level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, when the potential of the third wiring is set to the High level potential, the p-type transistor 1280a is turned off and n
The type transistor 1280b is turned on. At this time, the sixth wiring has different potentials depending on the amount of charge held in the floating node (FN). Therefore, the held information can be read (reading) by observing the potential of the sixth wiring.

In addition, the transistor 1282 has a very low off-state current because an oxide semiconductor is used for the channel formation region. The off-state current of the transistor 1282 including an oxide semiconductor is less than one-hundredth of that of a transistor formed using a silicon semiconductor or the like; thus, charge accumulated in the floating node (FN) due to leakage of the transistor 1282. It is possible to ignore the disappearance of. That is, the transistor 1282 including an oxide semiconductor can realize a nonvolatile memory circuit which can hold data without being supplied with power.

In addition, by using a semiconductor device having such a circuit structure for a storage device such as a register or a cache memory, data loss in the storage device due to supply of power supply voltage can be prevented. Further, after the supply of the power supply voltage is restarted, the state before the power supply is stopped can be restored in a short time. Therefore, in the entire storage device or one or a plurality of logic circuits included in the storage device, power supply can be stopped for a short time in the standby state, so that power consumption can be suppressed.

As described above, the structure, the method, and the like described in this embodiment can be combined with the structure, the method, and the like described in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, the structure of a pixel circuit that can be used for the semiconductor device of one embodiment of the present invention will be described below with reference to FIG.

<5-1. Pixel circuit configuration>
FIG. 22A is a diagram illustrating a structure of a pixel circuit. The circuit illustrated in FIG. 22A includes a photoelectric conversion element 1360, a transistor 1351, a transistor 1352, and a transistor 13.
53 and a transistor 1354.

The photoelectric conversion element 1360 has an anode connected to the wiring 1316, and a cathode connected to one of a source electrode and a drain electrode of the transistor 1351. The other of the source electrode and the drain electrode of the transistor 1351 is connected to the charge storage portion (FD) and the gate electrode is connected to the wiring 1312 (TX). One of a source electrode and a drain electrode of the transistor 1352 is connected to the wiring 1314 (GND), the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the transistor 1354, and a gate electrode thereof is a charge storage portion (FD). ) Is connected. One of a source electrode and a drain electrode of the transistor 1353 is connected to the charge storage portion (FD), the other of the source electrode and the drain electrode is connected to the wiring 1317, and a gate electrode thereof is connected to the wiring 1311 (RS). Transistor 1
The other of the source electrode and the drain electrode of 354 is connected to the wiring 1315 (OUT), and the gate electrode is connected to the wiring 1313 (SE). Note that all the above connections are electrical connections.

Note that the wiring 1314 may be supplied with a potential such as GND, VSS, or VDD. Here, the potential and the voltage are relative. Therefore, the magnitude of the GND potential is not necessarily 0 volt.

The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current according to light incident on the pixel circuit. The transistor 1353 is a charge storage portion (F
It has a function of controlling charge accumulation in D). The transistor 1354 is a charge storage unit (FD
) Has a function of outputting a signal corresponding to the potential. The transistor 1352 is a charge storage unit (
It has a function of resetting the potential of FD). The transistor 1352 has a function of controlling selection of a pixel circuit at the time of reading.

Note that the charge storage portion (FD) is a charge holding node and holds a charge that changes depending on the amount of light received by the photoelectric conversion element 1360.

Note that the transistor 1352 and the transistor 1354 are connected to the wiring 1315 and the wiring 131.
4 may be connected in series. Therefore, the wiring 1314 and the transistor 13
52, the transistor 1354, and the wiring 1315 may be arranged in this order, or the wiring 1314, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) functions as a signal line for controlling the transistor 1351. The wiring 1313 (SE) functions as a signal line for controlling the transistor 1354. The wiring 1314 (GND) has a function as a signal line for setting a reference potential (eg GND). The wiring 1315 (OUT) is connected to the transistor 1352.
It has a function as a signal line for reading a signal output from. The wiring 1316 has a function as a signal line for outputting charges from the charge storage portion (FD) through the photoelectric conversion element 1360 and is a low potential line in the circuit in FIG. The wiring 1317 has a function as a signal line for resetting the potential of the charge storage portion (FD) and is a high-potential line in the circuit in FIG.

Next, the structure of each element illustrated in FIG. 22A will be described.

<5-2. Photoelectric conversion element>
As the photoelectric conversion element 1360, an element including selenium or a compound containing selenium (hereinafter referred to as a selenium-based material) or an element including silicon (for example, an element in which a pin-type junction is formed) can be used. It is preferable to combine a transistor including an oxide semiconductor and a photoelectric conversion element including a selenium-based material because reliability can be increased.

<5-3. Transistor>
Although the transistors 1351, 1352, 1353, and 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon, an oxide semiconductor is used. It is preferable to form the transistor used. A transistor in which a channel formation region is formed using an oxide semiconductor has a characteristic of extremely low off-state current. As the transistor in which the channel formation region is formed using an oxide semiconductor, the transistor described in Embodiment 1 can be used, for example.

In particular, when the leakage currents of the transistor 1351 and the transistor 1353 connected to the charge storage portion (FD) are large, the time when the charge stored in the charge storage portion (FD) can be held becomes insufficient. Therefore, by using a transistor including an oxide semiconductor for at least the two transistors, unnecessary charge can be prevented from flowing out from the charge storage portion (FD).

In addition, in the transistors 1352 and 1354, when the leakage current is large, unnecessary charge is output to the wiring 1314 or the wiring 1315; therefore, as these transistors, a transistor in which a channel formation region is formed using an oxide semiconductor is used. It is preferable to use.

22A illustrates the transistor having a single gate electrode, the invention is not limited to this, and the transistor may have a plurality of gate electrodes, for example. As a transistor having a plurality of gate electrodes, for example, a first gate electrode and a second gate electrode (also referred to as a back gate electrode) which overlap with a semiconductor film in which a channel formation region is formed,
It may be configured to have. As the back gate electrode, for example, the same potential as the first gate electrode, floating, or a potential different from that of the first gate electrode may be applied.

<5-4. Timing chart of circuit operation>
Next, an example of circuit operation of the circuit illustrated in FIG. 22A will be described with reference to a timing chart in FIG.

For simplification of explanation in FIG. 22B, the potential of each wiring is given as a binary-changed signal. However, since each potential is an analog signal, it may actually take various values, not just binary, depending on the situation. Note that a signal 1401 illustrated in FIG. 22B is a potential of the wiring 1311 (RS), a signal 1402 is a potential of the wiring 1312 (TX), a signal 1403 is a potential of the wiring 1313 (SE), and a signal 1404 is a charge accumulation portion (FD). ) Potential, the signal 1405 is output to the wiring 1315 (OUT
) Corresponds to the potential. Note that the potential of the wiring 1316 is always “Low” and the potential of the wiring 1317 is always “High”.

At time A, the potential of the wiring 1311 (signal 1401) is set to “High” and the wiring 1312 is
When the potential of the charge storage portion (FD) is set to “High”, the potential of the charge storage portion (FD) (the signal 14
04) is initialized to the potential (“High”) of the wiring 1317, and the reset operation is started. Note that the potential of the wiring 1315 (the signal 1405) is precharged to “High”.

At Time B, the potential of the wiring 1311 (the signal 1401) is set to “Low”, the reset operation is completed, and the accumulation operation is started. Here, since a reverse bias is applied to the photoelectric conversion element 1360, the distribution charge accumulation unit (FD) (signal 1404) starts to decrease due to the reverse current. In the photoelectric conversion element 1360, the reverse current increases when light is emitted, and thus the rate of decrease of the potential (signal 1404) of the charge storage portion (FD) changes depending on the amount of light that is emitted. That is, the channel resistance between the source and the drain of the transistor 1354 changes in accordance with the amount of light with which the photoelectric conversion element 1360 is irradiated.

At time C, the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation is completed, and the potential of the charge accumulation portion (FD) (signal 1404) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. That is, it changes according to the amount of light with which the photoelectric conversion element 1360 is irradiated. In addition, the transistor 135
1 and the transistor 1353 are transistors each having an extremely low off-state current in which a channel formation region is formed using an oxide semiconductor, and therefore, the potential of the charge storage portion (FD) is kept constant until a later selection operation (read operation) is performed. It is possible to keep it constant.

Note that when the potential of the wiring 1312 (the signal 1402) is set to “Low”, the potential of the charge storage portion (FD) may be changed due to parasitic capacitance between the wiring 1312 and the charge storage portion (FD). is there. When the amount of change in the potential is large, the photoelectric conversion element 136 is operated during the accumulation operation.
This means that the amount of charge generated by 0 cannot be acquired accurately. In order to reduce the amount of change in the potential, the gate electrode-source electrode (or gate electrode-drain electrode) capacitance of the transistor 1351 is reduced, the gate capacitance of the transistor 1352 is increased, and the charge storage portion (FD
), it is effective to take measures such as providing a storage capacitor. Note that in this embodiment, the change in the potential can be ignored by these measures.

When the potential of the wiring 1313 (the signal 1403) is set at “High” at Time D, the transistor 1354 is turned on and a selection operation is started, and the wiring 1314 and the wiring 1315 are turned on through the transistor 1352 and the transistor 1354. Then, the potential of the wiring 1315 (
The signal 1405) is decreasing. Note that the precharge of the wiring 1315 may be completed before time D. Here, the speed at which the potential of the wiring 1315 (the signal 1405) decreases is
It depends on the current between the source electrode and the drain electrode of the transistor 1352. That is, it changes according to the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation.

At Time E, when the potential of the wiring 1313 (the signal 1403) is set to “Low”, the transistor 1354 is cut off and the selection operation ends, and the potential of the wiring 1315 (the signal 1405) becomes a constant value. Here, the constant value changes depending on the amount of light with which the photoelectric conversion element 1360 is irradiated. Therefore, by acquiring the potential of the wiring 1315, the amount of light with which the photoelectric conversion element 1360 is irradiated during the accumulation operation can be known.

More specifically, when the light applied to the photoelectric conversion element 1360 is strong, the charge storage portion (F
The potential of D), that is, the gate voltage of the transistor 1352 decreases. Therefore, a current flowing between the source electrode and the drain electrode of the transistor 1352 is reduced, and the wiring 1315
Potential (signal 1405) slowly decreases. Therefore, a relatively high potential can be read from the wiring 1315.

On the contrary, when the light applied to the photoelectric conversion element 1360 is weak, the potential of the charge storage portion (FD), that is, the gate voltage of the transistor 1352 becomes high. Therefore, transistor 1
The current flowing between the source electrode and the drain electrode of 352 becomes large, and the potential of the wiring 1315 (
Signal 1405) falls off quickly. Therefore, a relatively low potential can be read from the wiring 1315.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<6. Display device circuit configuration>
The display device illustrated in FIG. 23A includes a region including a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion provided outside the pixel portion 502 and including a circuit for driving the pixel (
Hereinafter, referred to as a drive circuit portion 504) and a circuit having a function of protecting an element (hereinafter, the protection circuit 50).
6) and a terminal portion 507. Note that the protection circuit 506 may not be provided.

It is preferable that part or all of the driver circuit portion 504 be formed over the same substrate as the pixel portion 502. As a result, the number of parts and the number of terminals can be reduced. Drive circuit unit 504
When part or all of the driving circuit portion 504 is not formed on the same substrate as the pixel portion 502, a part or all of the driver circuit portion 504 is COG or TAB (Tape Automated B).
Onboarding).

The pixel portion 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) Y columns (Y is a natural number of 2 or more). The driving circuit portion 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a), a circuit for supplying a signal (data signal) for driving a display element of the pixel ( Hereinafter, the driver circuit such as the source driver 504b) is included.

The gate driver 504a includes a shift register and the like. The gate driver 504a is
A signal for driving the shift register is input through the terminal portion 507 and the signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling potentials of wirings to which scan signals are supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided and the scan lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the gate driver 50 is not limited to this.
4a can also supply another signal.

The source driver 504b includes a shift register and the like. The source driver 504b is
In addition to the signal for driving the shift register, a signal (image signal) which is a source of the data signal is input through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on an image signal. Further, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. In addition, the source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the source driver 504b is not limited to this, and can also supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches and the like.
The source driver 504b sequentially turns on a plurality of analog switches,
A signal obtained by time-sharing an image signal can be output as a data signal. Alternatively, the source driver 504b may be formed using a shift register or the like.

A pulse signal is input to each of the plurality of pixel circuits 501 through one of the plurality of scan lines GL to which a scan signal is supplied, and a data signal is received through one of the plurality of data lines DL to which a data signal is supplied. Is entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data of a data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and the n-th column, a pulse signal is input from the gate driver 504a through the scan line GL_m (m is a natural number less than or equal to X), and the data line DL_n( depending on the potential of the scan line GL_m(
A data signal is input from the source driver 504b via (n is a natural number equal to or less than Y).

The protection circuit 506 illustrated in FIG. 23A includes, for example, the gate driver 504a and the pixel circuit 5
It is connected to the scanning line GL, which is a wiring between 01. Alternatively, the protection circuit 506 is connected to the data line DL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit which, when a potential outside a certain range is applied to a wiring to which the protection circuit 506 is connected, brings the wiring and another wiring into a conductive state.

As shown in FIG. 23A, the protection circuit 50 is provided in each of the pixel portion 502 and the driver circuit portion 504.
By providing 6, ESD (Electro Static Discharge:
It is possible to increase the resistance of the display device to an overcurrent generated by (electrostatic discharge) or the like.
However, the structure of the protection circuit 506 is not limited to this, and for example, the gate driver 504a may be connected to the protection circuit 506 or the source driver 504b may be connected to the protection circuit 506. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

23A illustrates an example in which the driver circuit portion 504 is formed by the gate driver 504a and the source driver 504b, the invention is not limited to this structure. For example, a structure in which only the gate driver 504a is formed and a separately prepared substrate on which a source driver circuit is formed (eg, a driver circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

The plurality of pixel circuits 501 illustrated in FIG. 23A can have the structure illustrated in FIG. 23B, for example.

The pixel circuit 501 illustrated in FIG. 23B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in any of the above embodiments can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate in accordance with the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. Note that a common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, and an ASM (Axially Symmetric Aligned M) are used.
micro-cell) mode, OCB (optically compensated)
Birefringence mode, FLC (Ferroelectric Liquid)
id Crystal mode, AFLC (Anti Ferroelectric Li)
Quid Crystal) mode, MVA mode, PVA (Patterned Ve)
vertical alignment mode, IPS mode, FFS mode, or TBA
(Transverse Bend Alignment) mode or the like may be used.
As a driving method of the display device, in addition to the driving method described above, an ECB (Electric) is used.
all Controlled Birefringence mode, PDLC(P
Polymer Dispersed Liquid Crystal) mode, PNLC
There are (Polymer Network Liquid Crystal) mode, guest host mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 550 is electrically connected to the data line DL_n and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. It The gate electrode of the transistor 550 is connected to the scan line G
It is electrically connected to L_m. The transistor 550 has a function of controlling writing of data of a data signal by being turned on or off.

One of a pair of electrodes of the capacitor 560 has a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL).
), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Note that the value of the potential of the potential supply line VL is set as appropriate in accordance with the specifications of the pixel circuit 501. The capacitor 560 has a function as a storage capacitor that holds written data.

For example, in a display device including the pixel circuit 501 in FIG. 23B, for example, in FIG.
The pixel driver 501 of each row is sequentially selected by the gate driver 504a shown in (1), the transistor 550 is turned on, and the data of the data signal is written.

The pixel circuit 501 in which the data is written enters a holding state when the transistor 550 is turned off. An image can be displayed by sequentially performing this for each row.

The plurality of pixel circuits 501 illustrated in FIG. 23A can have the structure illustrated in FIG. 23C, for example.

The pixel circuit 501 illustrated in FIG. 23C includes transistors 552 and 554, a capacitor 562, and a light emitting element 572. Transistor 552 and transistor 554
The transistor described in any of the above embodiments can be applied to either or both of them.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is applied (hereinafter referred to as a signal line DL_n). In addition, the transistor 55
The second gate electrode is electrically connected to a wiring to which a gate signal is applied (hereinafter, referred to as a scanning line GL_m).

The transistor 552 has a function of controlling writing of data of a data signal by being turned on or off.

One of a pair of electrodes of the capacitor 562 has a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL).
_A), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

The capacitor 562 has a function as a storage capacitor which holds written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.

In a display device including the pixel circuit 501 in FIG. 23C, for example, the pixel driver 501 in each row is sequentially selected by the gate driver 504a illustrated in FIG. 23A, the transistor 552 is turned on, and data of a data signal is output. Write.

The pixel circuit 501 to which data has been written is brought into a holding state by turning off the transistor 552. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light with luminance according to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 7)
In this embodiment, an example of a circuit structure to which the transistor described in any of the above embodiments can be applied is described with reference to FIGS.

Note that in this embodiment, the transistor including an oxide semiconductor, which is described in the above embodiments, is referred to as an OS transistor in the following description.

<7. Example of inverter circuit configuration>
FIG. 24A is a circuit diagram of an inverter which can be applied to a shift register, a buffer, or the like included in a driver circuit. The inverter 800 outputs a signal obtained by inverting the logic of the input terminal IN to the output terminal OUT. The inverter 800 has a plurality of OS transistors. The signal SBG is a signal for changing the electrical characteristics of the OS transistor.

FIG. 24B is a circuit diagram showing an example of the inverter 800. The inverter 800 is
The OS transistor 810 and the OS transistor 820 are included. The inverter 800 can be manufactured as an n-channel type and can have a so-called unipolar circuit structure. Therefore, it can be manufactured at lower cost than a CMOS inverter.

The OS transistors 810 and 820 each have a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of the source and the drain. Have.

The first gate of the OS transistor 810 is connected to the second terminal. OS transistor 8
The second gate of 10 is connected to the wiring for transmitting the signal SBG. The first terminal of the OS transistor 810 is connected to a wiring which supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

The first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. The second terminal of the OS transistor 820 has a voltage VSS
Connected to the wiring that gives.

FIG. 24C is a timing chart for explaining the operation of the inverter 800. The timing chart of FIG. 24C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal SBG, and the threshold voltage of the OS transistor 810 (FET 810).

The threshold voltage (VTH) of the OS transistor 810 can be controlled by applying the signal SBG to the second gate of the OS transistor 810.

The signal SBG has a voltage VBG_A for shifting VTH in the negative direction and a voltage VBG_B for shifting the VTH in the positive direction. By applying the voltage VBG_A to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage VTH_A. Further, by applying the voltage VBG_B to the second gate, the OS transistor 810 becomes
It can be positively shifted to the threshold voltage VTH_B.

That is, the OS transistor 810 can be shifted to the curve represented by the dashed line 840 by increasing the voltage of the second gate as shown in the graph in FIG. Further, by decreasing the voltage of the second gate, it is possible to shift to the curve represented by the solid line 841.

By positively shifting to the threshold voltage VTH_B, the OS transistor 810 can be in a state in which current hardly flows. As shown in FIG. 25B, the current IB flowing at this time can be made extremely small. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in the on state (ON), the voltage at the output terminal OUT can be sharply increased. Therefore, the signal waveform 831 at the output terminal in the timing chart in FIG. 24C can be changed abruptly. Further, since the through current flowing between the wiring which supplies the voltage VDD and the wiring which supplies the voltage VSS can be reduced, operation with low power consumption can be performed.

In addition, by shifting the threshold voltage VTH_A to a negative value, the OS transistor 81
0 can be a state in which a current easily flows. As shown in FIG. 25C, the current IA flowing at this time can be made larger than at least the current IB. Therefore, when the signal applied to the input terminal IN is at a low level and the OS transistor 820 is in the off state (OFF), the voltage at the output terminal OUT can be rapidly decreased. Therefore, FIG.
The signal waveform 832 of the output terminal in the timing chart shown in FIG.

The VTH control of the OS transistor 810 by the signal SBG is performed by the OS transistor 8
It is preferable to perform it before the state of 20 is switched, that is, before the time T1 or T2.
For example, as illustrated in FIG. 24C, the threshold voltage VTH_A is changed from the threshold voltage VTH_A to the threshold voltage VTH_B before time T1 when the signal applied to the input terminal IN is switched to the high level.
It is preferable to switch the threshold voltage of the S transistor 810. In addition, FIG.
As shown in FIG. 5, it is preferable to switch the threshold voltage of the OS transistor 810 from the threshold voltage VTH_B to the threshold voltage VTH_A before time T2 when the signal applied to the input terminal IN switches to the low level.

Note that the timing chart in FIG. 24C illustrates the structure in which the signal SBG is switched in accordance with the signal supplied to the input terminal IN, but another structure may be used. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. FIG. 26 shows an example of a circuit configuration that can realize the configuration.
It shows in (A).

In FIG. 26A, in addition to the circuit configuration shown in FIG.
Have. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring which supplies the voltage VBG_B (or the voltage VBG_A). The first gate of the OS transistor 850 is connected to a wiring which gives the signal SF. The second gate of the OS transistor 850 has a voltage VBG
_B (or voltage VBG_A) is connected to the wiring.

The operation of FIG. 26A will be described with reference to the timing chart of FIG.

Similar to FIG. 24C, the voltage for controlling the threshold voltage of the OS transistor 810 is the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN is switched to the high level. To give to. A voltage VB for controlling the threshold voltage is applied to the node NBG by setting the signal SF to a high level to turn on the OS transistor 850.
G_B is given.

After the node NBG becomes the voltage VBG_B, the OS transistor 850 is turned off. Since the off-state current of the OS transistor 850 is extremely small, the threshold voltage VTH_A once held at the node can be held by continuing to be in the off state. Therefore, the number of operations of applying the voltage VBG_B to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage VBG_B can be reduced.

In the circuit configurations of FIGS. 24B and 26A, the configuration in which the voltage applied to the second gate of the OS transistor 810 is externally controlled is shown, but another configuration may be adopted. For example, the voltage for controlling the threshold voltage may be generated based on the signal applied to the input terminal IN and applied to the second gate of the OS transistor 810. FIG. 27A illustrates an example of a circuit structure which can realize the structure.

In FIG. 27A, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit structure shown in FIG. 24B. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

The operation of FIG. 27A will be described with reference to the timing chart of FIG.
In the timing chart of FIG. 27B, the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the OS transistor 810.
The change of the threshold voltage of (FET810) is shown.

The output waveform IN_B which is a signal obtained by inverting the logic of the signal applied to the input terminal IN is shown in FIG.
As in C), the threshold voltage of the OS transistor 810 can be controlled. Therefore, although the voltage is different, as described in FIGS. 25A to 25C, the OS transistor 8
A threshold voltage of 10 can be controlled. For example, at time T4 in FIG. 27B,
When the signal applied to the input terminal IN is at high level, the OS transistor 820 is turned on. At this time, the output waveform IN_B becomes low level. Therefore, the OS transistor 810 can be in a state in which a current hardly flows, and the voltage of the output terminal OUT can be rapidly increased.

Further, at time T5 in FIG. 27B, the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is off. At this time, the output waveform IN_B becomes high level. Therefore, the OS transistor 810 can be in a state where a current easily flows, and the voltage of the output terminal OUT can be rapidly increased.

As described above, in the structure of this embodiment, the voltage of the back gate in the inverter having the OS transistor is switched according to the logic of the signal of the input terminal IN. With such a structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor in accordance with the signal applied to the input terminal IN, the voltage at the output terminal OUT can be changed sharply. Further, it is possible to reduce the through current between the wirings that supplies the power supply voltage. Therefore, low power consumption can be achieved.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 8)
In this embodiment, an input/output device of one embodiment of the present invention will be described with reference to FIG.

<8. Example of I/O device configuration>
An input/output device of one embodiment of the present invention is an in-cell touch panel having a function of displaying an image and a function of a touch sensor.

There is no limitation on the display element included in the input/output device of one embodiment of the present invention. Liquid crystal element, MEMS (M
An optical element using an micro electro mechanical system, an organic EL (Electro Luminescence) element, or a light emitting diode (LE)
Various elements such as a light emitting element such as D: Light Emitting Diode, an electrophoretic element, and the like can be applied as the display element.

In the present embodiment, a transmissive liquid crystal display device using a horizontal electric field type liquid crystal element will be described as an example.

There is no limitation on a sensing element (also referred to as a sensor element) included in the input/output device of one embodiment of the present invention.
Various sensors that can detect the proximity or contact of the detected object such as finger or stylus,
It can be applied as a sensing element.

For example, as a sensor system, various systems such as a capacitance system, a resistance film system, a surface acoustic wave system, an infrared system, an optical system, and a pressure sensitive system can be used.

In this embodiment, an input/output device including a capacitance type detection element will be described as an example.

As the electrostatic capacity method, there are a surface type electrostatic capacity method, a projection type electrostatic capacity method and the like. Further, as the projection type electrostatic capacity method, there are a self capacity method, a mutual capacity method and the like. It is preferable to use the mutual capacitance method because simultaneous multipoint detection is possible.

In-cell type touch panels are typically classified into a semi-in-cell type and a full-in-cell type. The semi-in-cell type refers to a structure in which an electrode or the like forming a sensing element is provided on both the substrate supporting the display element and the counter substrate or only the counter substrate. On the other hand, the full-in cell type refers to a configuration in which an electrode or the like that constitutes a sensing element is provided only on a substrate that supports a display element. The input/output device of one embodiment of the present invention is a full-in cell touch panel. The full-in cell type touch panel is preferable because the configuration of the counter substrate can be simplified.

In the input/output device of one embodiment of the present invention, the electrode included in the display element also serves as the electrode included in the sensing element; therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced, which is preferable.

By applying one embodiment of the present invention, the input/output device can be thinner than a structure in which a display panel and a sensing element which are manufactured separately are attached to each other and a structure in which the sensing element is manufactured on the counter substrate side. Alternatively, the weight can be reduced, or the number of parts of the input/output device can be reduced.

In the input/output device of one embodiment of the present invention, both the FPC which supplies a signal for driving a pixel and the FPC which supplies a signal for driving a sensing element are arranged on one substrate side. This allows
It is easy to incorporate in electronic equipment and the number of parts can be reduced. Note that a signal for driving a pixel and a signal for driving a detection element may be supplied by one FPC.

The structure of the input/output device of one embodiment of the present invention will be described below.

[Cross-sectional configuration example 1 of input/output device]
FIG. 28A is a cross-sectional view of two adjacent subpixels of the input/output device. The two subpixels illustrated in FIG. 28A are subpixels included in different pixels.

As shown in FIG. 28A, the input/output device includes transistors 201a,
It has a transistor 203a, a liquid crystal element 207a, and the like. Insulating layers such as the insulating layer 212, the insulating layer 213, the insulating layer 215, and the insulating layer 219 are provided over the substrate 211.

For example, one pixel includes a red subpixel, a green subpixel, and a blue subpixel, whereby a full-color display can be performed in the display portion. The colors presented by the sub-pixels are not limited to red, green, and blue. For the pixel, for example, a sub-pixel which exhibits a color such as white, yellow, magenta, or cyan may be used.

The transistor illustrated in the above embodiment can be applied to the transistor 201a included in the subpixel.

The liquid crystal element 207a is a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied. The liquid crystal element 207a includes a conductive film 251, a conductive film 252, and a liquid crystal 249. The liquid crystal 2 is generated by the electric field generated between the conductive films 251 and 252.
The orientation of 49 can be controlled. The conductive film 251 can function as a pixel electrode. The conductive film 252 can function as a common electrode.

By using a conductive material that transmits visible light for the conductive films 251 and 252, the input/output device can function as a transmissive liquid crystal display device. Further, a conductive material that reflects visible light is used for the conductive film 251 and a conductive material that transmits visible light is used for the conductive film 252, so that the input/output device functions as a reflective liquid crystal display device. You can

Examples of the conductive material that transmits visible light include indium (In), zinc (Zn),
It is preferable to use a material containing one selected from tin (Sn). Specifically, indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Examples thereof include indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide, zinc oxide, and zinc oxide containing gallium. Note that a film containing graphene can also be used. The film containing graphene can be formed by reducing a film containing graphene oxide, which is formed into a film shape, for example.

It is preferable to use an oxide conductive film for the conductive film 251. Further, it is preferable to use an oxide conductive film for the conductive film 252. The oxide conductive film preferably contains one or more kinds of metal elements contained in the oxide semiconductor film 223. For example, the conductive film 251 preferably contains indium, and an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, N).
More preferably, it is a d, Sn or Hf) film. Similarly, the conductive film 252 preferably contains indium, more preferably an In-M-Zn oxide film.

Note that at least one of the conductive films 251 and 252 may be formed using an oxide semiconductor. As described above, the oxide semiconductor having the same metal element is used for two or more layers of the layers forming the input/output device, so that the manufacturing apparatus (eg, a film formation apparatus, a processing apparatus, or the like) can be performed in two or more steps. Since it can be used in common, the manufacturing cost can be suppressed.

For example, when a silicon nitride film containing hydrogen is used for the insulating film 253 and an oxide semiconductor is used for the conductive film 251, the conductivity of the oxide semiconductor can be increased by hydrogen supplied from the insulating film 253.

Examples of the conductive material that reflects visible light include aluminum, silver, and alloys containing these metal materials.

The conductive film 251 functioning as a pixel electrode is electrically connected to the source or the drain of the transistor 203a.

The conductive film 252 has a comb-like top surface shape (also referred to as a planar shape) or a top surface shape provided with a slit. An insulating film 253 is provided between the conductive films 251 and 252. The conductive film 251 has a portion overlapping with the conductive film 252 with the insulating film 253 provided therebetween. Also,
In the region where the conductive film 251 and the coloring film 241 overlap with each other, there is a portion where the conductive film 252 is not provided over the conductive film 251.

A conductive film 255 is provided over the insulating film 253. The conductive film 255 is the conductive film 252.
And can function as an auxiliary wiring of the conductive film 252. By providing the auxiliary wiring electrically connected to the common electrode, the voltage drop due to the resistance of the common electrode can be suppressed. In addition, at this time, in the case of a stacked-layer structure of a conductive film containing a metal oxide and a conductive film containing a metal, it is preferable to form by a patterning technique using a halftone mask because the process can be simplified.

The conductive film 255 may have a resistance value lower than that of the conductive film 252. The conductive film 255 is
For example, a single layer or a stacked layer can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, silver, neodymium, or scandium or an alloy material containing these elements.

The conductive film 255 is preferably provided in a position overlapping with the light-blocking film 243 or the like so that the conductive film 255 is not visible to the user of the input/output device.

The coloring film 241 has a portion overlapping with the liquid crystal element 207a. The light-blocking film 243 has a portion overlapping with at least one of the transistors 201a and 203a.

The insulating film 245 preferably has a function as an overcoat that prevents impurities contained in the coloring film 241, the light-blocking film 243, or the like from diffusing into the liquid crystal 249. The insulating film 245 is
It may not be provided if unnecessary.

Note that an alignment film may be provided on the surfaces of the substrates 211 and 261 which are in contact with the liquid crystal 249. The alignment film can control the alignment of the liquid crystal 249. For example, in FIG.
), an alignment film which covers the conductive film 252 may be formed. Further, in FIG. 28A, an alignment film may be provided between the insulating film 245 and the liquid crystal 249. Further, the insulating film 245 may have both a function as an alignment film and a function as an overcoat.

Further, the input/output device has a spacer 247. The spacer 247 has a function of preventing the distance between the substrate 211 and the substrate 261 from approaching a certain distance or more.

Although the spacer 247 is provided over the insulating film 253 and the conductive film 252 in FIG. 28A, one embodiment of the present invention is not limited to this. The spacer 247 is the substrate 211.
May be provided on the side or the substrate 261 side. For example, the insulating film 2
The spacer 247 may be formed on the 45. 28A illustrates an example in which the spacer 247 is in contact with the insulating film 253 and the insulating film 245, the spacer 247 does not need to be in contact with a structure provided on either the substrate 211 side or the substrate 261 side. ..

A granular spacer may be used as the spacer 247. A material such as silica can be used as the granular spacer, but it is preferable to use a material having elasticity such as resin or rubber. At this time, the granular spacer may be crushed in the vertical direction.

The substrate 211 and the substrate 261 are attached to each other with an adhesive layer (not shown). Board 2
Liquid crystal 249 is sealed in a region surrounded by 11, the substrate 261, and the adhesive layer.

Note that when the input/output device is made to function as a transmissive liquid crystal display device, two polarizing plates are provided so as to sandwich the display portion. The light from the backlight arranged outside the polarizing plate enters through the polarizing plate. At this time, the orientation of the liquid crystal 249 can be controlled by the voltage applied between the conductive films 251 and 252, and the optical modulation of light can be controlled. That is, the intensity of light emitted through the polarizing plate can be controlled. Further, since the incident light is absorbed by the colored film 241 except for the specific wavelength region, the emitted light is, for example, red, blue, or green light.

Further, in addition to the polarizing plate, for example, a circular polarizing plate can be used. As the circularly polarizing plate, for example, a layered product of a linearly polarizing plate and a quarter-wave retardation plate can be used. The circularly polarizing plate can reduce the viewing angle dependence of the display of the input/output device.

Note that here, an element to which the FFS mode is applied is used as the liquid crystal element 207a, but the invention is not limited to this and liquid crystal elements to which various modes are applied can be used. For example, VA(
Vertical Alignment (TN) mode, TN (Twisted Nemati)
c) mode, IPS (In-Plane-Switching) mode, ASM (Axi)
Ally Symmetric aligned Micro-cell) mode, OC
B (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, A
A liquid crystal element to which an FLC (Antiferroelectric Liquid Crystal) mode or the like is applied can be used.

Further, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be applied to the input/output device. The vertical alignment mode is MV
A (Multi-Domain Vertical Alignment) mode, PV
An A (Patterned Vertical Alignment) mode, an ASV mode, or the like can be used.

The liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Liquid crystals used for the liquid crystal element include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC:Po).
It is possible to use a liquid disperse liquid crystal), a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

Further, as the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimal liquid crystal material may be used according to the mode or design to be applied.

In the case of adopting the horizontal electric field method, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears when the temperature of the cholesteric liquid crystal is increased and immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal 249 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has small viewing angle dependence. Further, since it is not necessary to provide an alignment film, rubbing treatment is not necessary, so that electrostatic breakdown caused by the rubbing treatment can be prevented and defects and damages of the liquid crystal display device during a manufacturing process can be reduced. ..

Here, a substrate, such as a finger or a stylus, which is directly contacted with the detected object may be provided above the substrate 261. At this time, a polarizing plate or a circular polarizing plate is preferably provided between the substrate 261 and the substrate. In that case, it is preferable to provide a protective layer (ceramic coat or the like) on the substrate. The protective layer is, for example, silicon oxide, aluminum oxide, yttrium oxide,
An inorganic insulating material such as yttria-stabilized zirconia (YSZ) can be used. Further, tempered glass may be used for the substrate. The tempered glass may be one that has been subjected to a physical or chemical treatment by an ion exchange method, an air-cooling tempering method, or the like, and has its surface subjected to compressive stress.

In FIG. 28A, the conductive film 252 included in the left sub-pixel and the conductive film 2 included in the right sub-pixel.
It is possible to detect the proximity, contact, or the like of the detection target by using the capacitance formed between the detection target and the detection target 52. That is, in the input/output device of one embodiment of the present invention, the conductive film 252 serves as both a common electrode of a liquid crystal element and an electrode of a sensing element.

As described above, in the input/output device of one embodiment of the present invention, the electrode included in the liquid crystal element also serves as the electrode included in the sensing element; therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, it is possible to reduce the thickness and weight of the input/output device.

The conductive film 252 is electrically connected to the conductive film 255 which functions as an auxiliary wiring. By providing the conductive film 255, the resistance of the electrode of the sensing element can be reduced. Since the resistance of the resistance of the electrode of the sensing element decreases, the time constant of the electrode of the sensing element can be reduced. The smaller the time constant of the electrode of the detection element, the higher the detection sensitivity, and further the higher the detection accuracy.

If the capacitance between the electrode of the sensing element and the signal line is too large, the time constant of the electrode of the sensing element may increase. Therefore, it is preferable to provide an insulating film having a planarizing function between the transistor and the electrode of the sensing element to reduce the capacitance between the electrode of the sensing element and the signal line. For example, in FIG. 28A, the insulating layer 219 is provided as an insulating film having a planarization function. By providing the insulating layer 219, the capacitance between the conductive film 252 and the signal line can be reduced. Thereby, the time constant of the electrode of the sensing element can be reduced. As described above, the smaller the time constant of the electrode of the sensing element, the higher the detection sensitivity, and further the higher the detection accuracy.

For example, the time constant of the electrode of the sensing element is greater than 0 seconds and 1×10 −4 seconds or less, preferably greater than 0 seconds and 5×10 −5 seconds or less, more preferably greater than 0 seconds and 5×10 −6 seconds. Or less, more preferably greater than 0 seconds and 5×10 −7 seconds or less, and more preferably greater than 0 seconds and 2
It is good that it is ×10 −7 seconds or less. In particular, by setting the time constant to 1×10 −6 seconds or less, it is possible to realize high detection sensitivity while suppressing the influence of noise.

[Example 2 of cross-sectional configuration of input/output device]
28B is a cross-sectional view of two adjacent pixels, which is different from FIG. 28A. Figure 2
The two subpixels illustrated in FIG. 8B are subpixels included in different pixels.

28B is different from the structure example 1 illustrated in FIG. 28A in the stacking order of the conductive film 251, the conductive film 252, the insulating film 253, and the conductive film 255. Note that in Configuration Example 2, the same portions as in Configuration Example 1 can be referred to the above.

Specifically, in Structural Example 2, the conductive film 255 is provided over the insulating layer 219, the conductive film 252 is provided over the conductive film 255, the insulating film 253 is provided over the conductive film 252, and the insulating film 253 is provided. Conductive film 25
Has 1.

As in a liquid crystal element 207b illustrated in FIG. 28B, a conductive film 251 provided in an upper layer and having a comb-like or slit-like upper surface shape is used as a pixel electrode, and a conductive film 252 provided in a lower layer is used as a common electrode. You can also Even in that case, the conductive film 251 is not included in the transistor 203a.
It may be electrically connected to the source or drain of the.

In FIG. 28B, the conductive film 252 included in the left sub-pixel and the conductive film 2 included in the right sub-pixel.
It is possible to detect the proximity, contact, or the like of the detection target by using the capacitance formed between the detection target and the detection target 52. That is, in the input/output device of one embodiment of the present invention, the conductive film 252 serves as both a common electrode of a liquid crystal element and an electrode of a sensing element.

Note that in Structural Example 1 (FIG. 28A), the conductive film 25 serving as an electrode of the sensing element and a common electrode is used.
2 is located on the display surface side (the side closer to the detected body) than the conductive film 251 functioning as a pixel electrode. As a result, the detection sensitivity may be improved in the configuration example 1 as compared with the configuration example 2 in which the conductive film 251 is located on the display surface side of the conductive film 252.

(Embodiment 9)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<9-1. Display module>
A display module 8000 shown in FIG. 29 includes a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, and a printed board 801 between an upper cover 8001 and a lower cover 8002.
0, the battery 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and size of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a resistance film type or a capacitance type touch panel can be used by being superimposed on the display panel 8006. Alternatively, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, the display panel 8
It is also possible to provide an optical sensor in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008. Note that although FIG. 29 illustrates the structure in which the light source 8008 is provided over the backlight 8007, the invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007 and a light diffusion plate may be used. Note that in the case of using a self-luminous light emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function of protecting the display panel 8006 and a function of an electromagnetic shield for blocking an electromagnetic wave generated by the operation of the printed board 8010. Further, the frame 8009 may have a function as a heat dissipation plate.

The printed circuit board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply provided by a battery 8011 provided separately. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate and a prism sheet.

<9-2. Electronics>
30A to 30G are diagrams illustrating electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed,
Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared (Including a function), a microphone 9008, and the like.

The electronic devices illustrated in FIGS. 30A to 30G can have various functions.
For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, various software (
A function of controlling processing by a program), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function, and recorded in a recording medium. It can have a function of reading out the stored program or data and displaying it on the display unit. Note that the functions of the electronic devices in FIGS. 30A to 30G are not limited to these and can have various functions. Although not shown in FIGS. 30A to 30H, the electronic device includes
It may be configured to have a plurality of display portions. Further, a camera or the like is provided in the electronic device, a function of shooting a still image, a function of shooting a moving image, a function of saving a captured image in a recording medium (external or built in the camera), a captured image displayed on a display portion It may have a function to do, and the like.

Details of the electronic devices illustrated in FIGS. 30A to 30G are described below.

FIG. 30A is a perspective view showing the television device 9100. Television device 9
The display unit 9001 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

FIG. 30B is a perspective view showing the portable information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. The portable information terminal 9101 is
A speaker 9003, a connection terminal 9006, a sensor 9007, and the like may be provided. Further, the mobile information terminal 9101 can display characters and image information on its plurality of surfaces. For example, 3
One operation button 9050 (also referred to as an operation icon or simply an icon) is displayed on the display unit 9001.
Can be displayed on one side. In addition, information 9051 indicated by a dashed rectangle is displayed on the display unit 900.
It can be displayed on the other side of 1. In addition, as an example of the information 9051, a display for notifying an incoming call such as an electronic mail, an SNS (social networking service) or a telephone,
There are titles such as e-mail and SNS, names of senders such as e-mail and SNS, date and time, time, remaining battery level, and antenna reception strength. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

FIG. 30C is a perspective view showing the portable information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, information 9052,
An example in which the information 9053 and the information 9054 are displayed on different surfaces is shown. For example, the user of the mobile information terminal 9102 can confirm the display (here, information 9053) in a state where the mobile information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position that can be observed from above the mobile information terminal 9102. The user can confirm the display and determine whether to receive the call without removing the portable information terminal 9102 from the pocket.

FIG. 30D is a perspective view showing a wristwatch-type portable information terminal 9200. The mobile information terminal 9200 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and display can be performed along the curved display surface. The mobile information terminal 9200 is also capable of performing near field communication that is a communication standard. For example, by communicating with a headset capable of wireless communication, a hands-free call can be made. The mobile information terminal 9200 has a connection terminal 9006 and can directly exchange data with another information terminal through a connector. In addition, charging can be performed through the connection terminal 9006. Note that the charging operation is performed using the connection terminal 900
It may be performed by wireless power feeding without going through 6.

30E, 30F, and 30G are perspective views illustrating a portable information terminal 9201 which can be folded. 30E is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG.
FIG. 30F is a perspective view of a state where the portable information terminal 9201 is in a state where the portable information terminal 9201 is expanded or folded and is in the process of changing from one to the other, and FIG. is there. The portable information terminal 9201 is excellent in portability in a folded state, and is excellent in displayability due to a wide display area without a joint in an expanded state. Mobile information terminal 92
The display portion 9001 included in 01 includes three housings 9000 connected by a hinge 9055.
Supported by. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the unfolded state to the folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

The electronic devices described in this embodiment each include a display portion for displaying some information. However, the semiconductor device of one embodiment of the present invention can be applied to an electronic device without a display portion.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

102 substrate 104 insulating film 106 conductive film 108 oxide semiconductor film 108_1 layer 108_2 layer 108_3 layer 108d drain region 108i channel region 108s source region 110 insulating film 110_0 insulating film 112 oxide semiconductor film 112_0 oxide semiconductor film 116 insulating film 117 insulating film 118 insulating film 120 conductive film 120a conductive film 120b conductive film 140 mask 141a opening 141b opening 143 opening 145 impurity element 150 transistor 150A transistor 150B transistor 160 transistor 160A transistor 160B transistor 170 transistor 201a transistor 203a transistor 207a liquid crystal element 207b liquid crystal element 211 substrate 212 insulating layer 213 insulating layer 215 insulating layer 219 insulating layer 223 oxide semiconductor film 241 colored film 243 light shielding film 245 insulating film 247 spacer 249 liquid crystal 251 conductive film 252 conductive film 253 insulating film 255 conductive film 261 substrate 501 pixel circuit 502 Pixel portion 504 Drive circuit portion 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel portion 704 Source driver circuit portion 705 Substrate 706 Gate driver circuit portion 708 FPC terminal portion 710 Signal line 711 Wiring portion 712 Sealing material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Coloring film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure body 780 Anisotropic conductive film 782 Light emitting element 784 Conductive film 786 EL layer 788 Conductive film 790 Capacitive element 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 capacitance element 1282 transistor 1311 wiring 1312 wiring 1313 wiring 1314 wiring 1315 wiring 1316 wiring 1317 wiring 1351 transistor 1352 transistor 1353 transistor 1354 transistor 1360 photoelectric conversion element 1401 signal 1402 signal 1403 signal 1404 signal 1405 signal 8000 display module 8001 upper cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Housing 9001 Display 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television device 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal

Claims (1)

A semiconductor device having a transistor,
The transistor is
A first gate electrode,
A first gate insulating film on the first gate electrode,
A first oxide semiconductor film on the first gate insulating film,
A second oxide semiconductor film on the first oxide semiconductor film;
A second gate insulating film on the second oxide semiconductor film;
A second gate electrode on the second gate insulating film,
An insulating film on the second gate electrode,
A source electrode and a drain electrode,
The second oxide semiconductor film is in contact with an upper surface and a side surface of the first oxide semiconductor film,
The insulating film contacts the upper surface of the second gate electrode film,
The semiconductor device, wherein each of the source electrode and the drain electrode is in contact with a side surface of the insulating film, a side surface of the second gate insulating film, and a side surface of the second oxide semiconductor film.