JP2017108065A - Method of manufacturing semiconductor device, and method of manufacturing display device having the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve microfabrication, suppression of variation in electric characteristics, and improvement in reliability, of a transistor having an oxide semiconductor.SOLUTION: A transistor includes: an oxide semiconductor film on a first insulating film; a second insulating film on the oxide semiconductor film; a gate electrode on the second insulating film; and a third insulating film on the oxide semiconductor film and the gate electrode. The oxide semiconductor film has a channel region overlapped with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. A gas used for forming the second insulating film is SHand NO. A flow rate of NO to a flow rate of SHis larger than 1000 times and less than 10000 times.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

A technique for forming a transistor (also referred to as a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A semiconductor material typified by silicon is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a technique for manufacturing a transistor using an amorphous oxide containing In, Zn, Ga, Sn, or the like as an oxide semiconductor is disclosed (see Patent Document 1). In addition, a technique for manufacturing an oxide thin film transistor having a self-aligned top gate structure is disclosed (see Patent Document 2).

In addition, a semiconductor device is disclosed in which an insulating layer from which oxygen is released by heating is used as a base insulating layer of an oxide semiconductor layer that forms a channel to reduce oxygen vacancies in the oxide semiconductor layer (see Patent Document 3). ).

JP 2006-165529 A JP 2009-278115 A JP 2012-009836 A

Examples of the transistor including an oxide semiconductor film include a bottom gate structure type and a top gate structure type. When a transistor including an oxide semiconductor film is applied to a display device, a bottom-gate transistor is used because a manufacturing process is relatively simple and manufacturing cost can be reduced compared to a top-gate transistor. There are many cases. However, the screen size of the display device is increased or the image quality of the display device is increased (for example, 4k × 2k (horizontal pixel number = 3840 pixels, vertical pixel number = 2160 pixels) or 8k × 4k (horizontal pixel). When a high-definition display device represented by a number = 7680 pixels and a vertical pixel number = 4320 pixels) progresses, parasitic capacitance is generated between the gate electrode, the source electrode, and the drain electrode in the bottom-gate transistor. There is a case. Depending on the size of the parasitic capacitance, there is a problem that the signal delay or the like becomes large and the image quality of the display device is deteriorated. Thus, development of a structure having stable semiconductor characteristics and high reliability is desired for a top-gate transistor including an oxide semiconductor film.

Further, in the case where a transistor is formed using an oxide semiconductor film for a channel region, oxygen vacancies formed in the channel region of the oxide semiconductor film are problematic because they affect transistor characteristics. For example, when an oxygen vacancy is formed in the channel region of the oxide semiconductor film, carriers are generated due to the oxygen vacancy. When carriers are generated in the channel region of the oxide semiconductor film, a change in electrical characteristics of the transistor including the oxide semiconductor film in the channel region, typically, a threshold voltage shift occurs. In addition, there is a problem that electric characteristics vary from transistor to transistor. Therefore, the number of oxygen vacancies is preferably as small as possible in the channel region of the oxide semiconductor film. On the other hand, in a transistor in which an oxide semiconductor film is used for a channel region, an oxide semiconductor film in contact with a source electrode and a drain electrode has many oxygen vacancies in order to reduce contact resistance with the source electrode and the drain electrode. The lower one is preferable.

In view of the above problems, an object of one embodiment of the present invention is to suppress variation in electrical characteristics and improve reliability in a transistor including an oxide semiconductor. Another object of one embodiment of the present invention is to provide a top-gate transistor including an oxide semiconductor. Another object of one embodiment of the present invention is to provide a minute transistor. Another object of one embodiment of the present invention is to provide a transistor including an oxide semiconductor and high on-state current. Another object of one embodiment of the present invention is to provide a transistor including an oxide semiconductor and having low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of the above problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than those described above are naturally apparent from the description of the specification and the like, and it is possible to extract problems other than the above from the description of the specification and the like.

(1)
In one embodiment of the present invention, an oxide semiconductor film is formed over the first insulating film, a second insulating film is formed over the oxide semiconductor film, and a conductive film is formed over the second insulating film. A gate electrode having a conductive film and a gate insulating film having a second insulating film are formed by lithography to form a conductive film and a second insulating film, and hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur , One or more ions of chlorine, titanium, or a rare gas are implanted into the first region, and a third insulating film is formed over the first insulating film, the semiconductor film, and the gate electrode. The region has a region where the first region and the gate electrode do not overlap with each other. The second insulating film is formed using the PECVD method. The gas used for the PECVD method is silane and one gas. It is dinitrogen oxide, and the flow rate of nitrous oxide is greater than 1000 times that of silane. A method for manufacturing a semiconductor device and less than 10000 times.

(2)
Another embodiment of the present invention is the method for manufacturing a semiconductor device according to (1), in which the rare gas is one or more of helium, neon, argon, krypton, or xenon.

(3)
Another embodiment of the present invention is the method for manufacturing a semiconductor device according to (1) or (3), in which the implantation is performed using a plasma treatment method, an ion doping method, or an ion implantation method.

(4)
In one embodiment of the present invention, any one of (1) to (3) is characterized in that the third insulating film is formed using a gas containing one or more of nitrogen, hydrogen, and fluorine. A manufacturing method of the semiconductor device described.

(5)
According to one embodiment of the present invention, a first conductive film is formed over a substrate, a first insulating film is formed over the substrate and the first conductive film, and an oxide is formed over the first insulating film. A semiconductor film is formed, a second insulating film is formed over the oxide semiconductor film, a second conductive film is formed over the second insulating film, and the second conductive film and the second conductive film are formed. A gate electrode having a second conductive film and a gate insulating film having a second insulating film are formed by a lithography method, and the gate electrode and the gate insulating film are used as a mask to form hydrogen, boron, carbon, nitrogen, One or more ions of fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas are implanted into the first region, and a third insulating film is formed over the first insulating film, the semiconductor film, and the gate electrode. The first region has a region where the first region and the gate electrode do not overlap with each other, and the second insulating film is formed. Is formed using PECVD, and the gas used for PECVD is silane and dinitrogen monoxide, and the flow rate of dinitrogen monoxide is greater than 1000 times and less than 10,000 times with respect to the flow rate of silane. This is a method for manufacturing a semiconductor device.

(6)
According to one embodiment of the present invention, a first conductive film is formed over a substrate, a first insulating film is formed over the substrate and the first conductive film, and an oxide is formed over the first insulating film. A semiconductor film is formed, a second insulating film is formed over the oxide semiconductor film, and an opening reaching the first conductive film is formed in the second insulating film and the first insulating film by lithography. Then, a second conductive film is formed over the second insulating film, and the gate electrode and the second insulating film having the second conductive film are formed by lithography using the second conductive film and the second insulating film. And forming one or more ions of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas into the first region, over the first insulating film, A third insulating film is formed over the semiconductor film and the gate electrode. In the first region, the first region and the gate electrode are interchanged. The second insulating film is formed using the PECVD method, and the gas used for the PECVD method is silane and dinitrogen monoxide. The method for manufacturing a semiconductor device is characterized in that the flow rate of dinitrogen monoxide is greater than 1000 times and less than 10,000 times.

(7)
Another embodiment of the present invention is the method for manufacturing a semiconductor device according to (5) or (6), wherein the rare gas is one or more of helium, neon, argon, krypton, or xenon.

(8)
According to one embodiment of the present invention, the implantation is performed using a plasma treatment method, an ion doping method, or an ion implantation method. The manufacturing of a semiconductor device according to any one of (5) to (7) Is the method.

(9)
According to one embodiment of the present invention, the third insulating film is formed using a gas containing one or more of nitrogen, hydrogen, and fluorine. A manufacturing method of the semiconductor device described.

(10)
Another embodiment of the present invention is a method for manufacturing a display device, the display device including a semiconductor device manufactured using the method for manufacturing a semiconductor device according to any one of (1) to (9) and It is a method for manufacturing a display device including a display element.

(11)
Another embodiment of the present invention is a method for manufacturing a display module, the display module including a display device and a touch sensor manufactured using the method for manufacturing a display device according to (10). This is a method for manufacturing a display module.

(12)
Another embodiment of the present invention is a method for manufacturing an electronic device, and the electronic device includes a display module manufactured using the method for manufacturing a display module described in (11) and an operation key or a battery. This is a method for manufacturing an electronic device.

According to one embodiment of the present invention, in a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, according to one embodiment of the present invention, a top-gate transistor including an oxide semiconductor can be provided. Alternatively, according to one embodiment of the present invention, a fine transistor can be provided. Alternatively, according to one embodiment of the present invention, a transistor having an oxide semiconductor and a large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor having an oxide semiconductor and having low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. The figure explaining a band structure. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. The figure explaining the model in which oxygen deficiency is formed. The figure explaining the model in which oxygen deficiency is formed. The figure explaining the model used for calculation. The figure explaining the calculation result of the state density of a VoF model. The figure explaining the model used for calculation. The figure explaining the model used for calculation. The figure explaining the calculation result of the state density of a crystal model. The figure explaining the calculation result of the formation energy of Vo and VoF. The figure explaining the calculation result of the formation energy of Fint and Oint. The figure explaining the calculation result of the formation energy and energy difference of a reaction original system and a production | generation system. The figure explaining the model used for calculation. InGaZnO ₄ diagram illustrating a model of a stable placement of the impurities (F or H) between the cell of the crystal model. InGaZnO ₄ diagram a model describing the diffusion path for F in the crystal. The figure explaining the calculation result of the change of the energy corresponding to the diffusion path of F. InGaZnO ₄ diagram a model describing the diffusion path of H in the crystal. The figure explaining the calculation result of the change of the energy corresponding to the diffusion path of H. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 14 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. 8A and 8B are a top view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. 10A and 10B each illustrate a circuit configuration of a semiconductor device. 3A and 3B illustrate a structure of a pixel circuit and a timing chart illustrating an operation of the pixel circuit. 10A and 10B are a block diagram and a circuit diagram illustrating a display device. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. Sectional drawing which shows an example of an input / output device. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating the structure of a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating the structure of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. The figure explaining a display module. 10A and 10B each illustrate an electronic device. The perspective view of a display apparatus. The figure of the TDS analysis of an Example. The figure showing the sheet resistance of an Example. The figure of the TDS analysis of an Example. The figure of the Id-Vg characteristic of an Example. The figure of the Id-Vg characteristic of an Example. The figure of the Id-Vg characteristic of an Example. The figure of the Id-Vg characteristic of an Example. The figure of the Id-Vd characteristic of an Example.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers “first”, “second”, and “third” used in the present specification are attached to avoid confusion between components, and are not limited numerically. Appendices.

In addition, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification and the like, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. There may be a case where there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V There is a value of Vgs at which the off-state current of the transistor is less than or equal to Vds at which Vds guarantees the reliability of the semiconductor device including the transistor or Vds used in the semiconductor device or the like including the transistor. May be pointed to.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

In this specification and the like, a semiconductor impurity refers to a component other than the main components included in a semiconductor film. For example, an element having a concentration of less than 0.1 atomic% is an impurity. By including impurities, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. In the case where the semiconductor includes an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor includes silicon, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements other than oxygen and hydrogen.

(Embodiment 1)
In this embodiment, an example of a semiconductor device including a transistor and a method for manufacturing the semiconductor device will be described with reference to FIGS.

<1-1. Configuration Example 1 of Semiconductor Device>
1A, 1B, and 1C illustrate an example of a semiconductor device including a transistor. Note that the transistors illustrated in FIGS. 1A to 1C are top-gate transistors.

1A is a top view of the transistor 100, FIG. 1B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 1A, and FIG. 1C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2. Note that in FIG. 1A, components such as the insulating film 110 are omitted for clarity. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 1A. In addition, the alternate long and short dash line X1-X2 direction may be referred to as a channel length (L) direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width (W) direction.

1A, 1B, and 1C includes an insulating film 104 over a substrate 102, an oxide semiconductor film 108 over an insulating film 104, an insulating film 110 over an oxide semiconductor film 108, The conductive film 114 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 114 are included. Note that the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 114, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.

Note that the insulating film 116 contains one or more of nitrogen, hydrogen, and fluorine. When the insulating film 116 is in contact with the source region 108s and the drain region 108d, one or more of nitrogen, hydrogen, or fluorine in the insulating film 116 is added to the source region 108s and the drain region 108d. The carrier density of the source region 108s and the drain region 108d is increased by adding the above-described elements. In particular, the source region 108s and the drain region 108d preferably include fluorine. When the source region 108s and the drain region 108d have fluorine, the carrier density can be stably increased. Note that the structure in which the oxide semiconductor includes fluorine is described in detail in Embodiment 2.

Further, the transistor 100 includes an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.

Note that in this specification and the like, the insulating film 104 is a first insulating film, the insulating film 110 is a second insulating film, the insulating film 116 is a third insulating film, and the insulating film 118 is a fourth insulating film. And may be called respectively. The conductive film 114 functions as a gate electrode, the conductive film 120a functions as a source electrode, and the conductive film 120b functions as a drain electrode.

The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108 and the insulating film 104. Since the insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, oxygen can be supplied to the channel region 108 i included in the oxide semiconductor film 108. Accordingly, oxygen vacancies that can be formed in the channel region 108i can be filled with excess oxygen, so that a highly reliable semiconductor device can be provided. Further, since the insulating film 110 has a function of supplying oxygen to the insulating film 104, excess oxygen supplied to the insulating film 104 moves into the oxide semiconductor film 108 by heat treatment or the like, and the oxide semiconductor film 108. Therefore, a more reliable semiconductor device can be provided.

Note that oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108 in order to supply oxygen into the oxide semiconductor film 108. Note that in this case, excess oxygen contained in the insulating film 104 can be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When oxygen is supplied to the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d may increase.

On the other hand, when the insulating film 110 formed above the oxide semiconductor film 108 has excess oxygen, excess oxygen can be selectively supplied only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density in the source region 108s and the drain region 108d may be selectively increased.

The source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably each include an element that forms oxygen vacancies or an element that combines with oxygen vacancies. As an element that forms oxygen vacancies or an element that combines with oxygen vacancies, typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. The element that forms oxygen vacancies is added to the source region 108 s and the drain region 108 d by diffusion of the constituent elements of the insulating film 116 into the source region 108 s and the drain region 108 d, or by impurity addition treatment.

When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut, so that an oxygen vacancy is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

As described above, in the semiconductor device of one embodiment of the present invention, oxygen is selectively supplied to the channel region 108 i included in the oxide semiconductor film 108 by supplying oxygen to the insulating film 110 in contact with the oxide semiconductor film 108. Can be supplied. In addition, since the insulating film 116 includes one or more of hydrogen, nitrogen, or fluorine, the carrier density of the source region 108s and the drain region 108d that are in contact with the insulating film 116 can be selectively increased. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

Next, details of components of the semiconductor device illustrated in FIGS. 1A, 1B, and 1C will be described.

[substrate]
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a specific substrate. As an example of a substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, Examples include a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, and the base film include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Another example is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. As an example, there are polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is stacked, or a structure in which an organic resin film such as polyimide is formed over a substrate can be used for the above-described release layer.

Examples of a substrate on which a transistor is transferred include a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) in addition to the above-described substrate capable of forming a transistor. (Silk, cotton, hemp), synthetic fibers (including nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

[First insulating film]
The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating film 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 It is possible to reduce oxygen vacancies contained in 108i.

The insulating film 104 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and may be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104. In this manner, oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

[Oxide semiconductor film]
The oxide semiconductor film 108 is formed using a metal oxide such as In-M-Zn oxide (M is Al, Ga, Y, or Sn). As the oxide semiconductor film 108, an In—Ga oxide or an In—Zn oxide may be used.

Note that in the case where the oxide semiconductor film 108 is an In—M—Zn oxide, the atomic ratio of In and M excluding Zn and O is such that In is 25 atomic% when the sum of In and M is 100 atomic%. High, M is less than 75 atomic%, or In is higher than 34 atomic%, and M is less than 66 atomic%.

The oxide semiconductor film 108 preferably has an energy gap of 2 eV or more, 2.5 eV or more, or 3 eV or more.

The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.

In the case where the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide satisfies In ≧ M and Zn ≧ M. It is preferable. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, etc. are preferable. Note that the atomic ratio of the oxide semiconductor film 108 to be formed may vary by about plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 4: 2. : It may be in the vicinity of 3. In the case where an atomic ratio of In: Ga: Zn = 5: 1: 7 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 5: 1: 6. May be near.

In the case where the oxide semiconductor film 108 contains silicon or carbon which is one of Group 14 elements, oxygen vacancies increase and the oxide semiconductor film 108 may be n-type. Therefore, the silicon or carbon concentration in the oxide semiconductor film 108, particularly the channel region 108i, is preferably 2 × 10 ¹⁸ atoms / cm ³ or lower, or 2 × 10 ¹⁷ atoms / cm ³ or lower. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. Note that the concentration of silicon or carbon described above can be measured by, for example, secondary ion mass spectrometry (SIMS).

In the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁶ atoms / cm ³ or less. Can do. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In addition, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density is increased, and the n-type may be obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen is preferably reduced as much as possible in the channel region 108i. For example, the nitrogen concentration obtained by secondary ion mass spectrometry may be 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, in the channel region 108 i, the carrier density of the oxide semiconductor film can be reduced by reducing the impurity element. For this reason, in the channel region 108i, the carrier density is 1 × 10 ¹⁷ pieces / cm ³ or less, or 1 × 10 ¹⁵ pieces / cm ³ or less, or 1 × 10 ¹³ pieces / cm ³ or less, or 1 × 10 ¹¹ pieces. / Cm ³ or less.

By using an oxide semiconductor film having a low impurity concentration and a low density of defect states as the channel region 108i, a transistor having more excellent electrical characteristics can be manufactured. Here, the low impurity concentration and the low density of defect states (there are few oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. Alternatively, it is called intrinsic or substantially intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film easily has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have characteristics with extremely low off-state current. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film has a small variation in electrical characteristics and may be a highly reliable transistor.

On the other hand, the source region 108 s and the drain region 108 d are in contact with the insulating film 116. When the source region 108s and the drain region 108d are in contact with the insulating film 116, one or more of hydrogen, nitrogen, and fluorine is added from the insulating film 116 to the source region 108s and the drain region 108d, so that the carrier density is increased.

The oxide semiconductor film 108 may have a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C Axis Crystallized Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

Note that the oxide semiconductor film 108 includes a single-layer film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Or the structure where this film | membrane was laminated | stacked may be sufficient.

Note that in the oxide semiconductor film 108, the channel region 108i may differ in crystallinity from the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when the impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged, and crystallinity is lowered.

[Second insulating film]
The insulating film 110 functions as a gate insulating film of the transistor 100. The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i. For example, the insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, a region in the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using at least the oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.

The thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.

The insulating film 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) be small. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating film 110, a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less is used. Good.

In addition, in the insulating film 110, a signal due to nitrogen dioxide (NO ₂ ) may be observed in addition to the above signal. The signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003. The g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).

For example, as the insulating film 110, an insulating film whose spin density due to nitrogen dioxide (NO ₂ ) is 1 × 10 ¹⁷ spins / cm ³ or more and less than 1 × 10 ¹⁸ spins / cm ³ is preferably used.

Note that nitrogen oxide containing nitrogen dioxide (NO ₂ ) (NO _x , x is more than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO or NO ₂ ) is quasi in the insulating film 110. Form a place. The level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction.

Therefore, when the insulating film 110 is a film with a low content of nitrogen oxides, in other words, when a film with a small amount of nitrogen oxide emission is used as the insulating film 110, a shift in threshold voltage of the transistor is reduced. can do.

For example, a silicon oxynitride film can be used as the insulating film that emits less nitrogen oxide. The silicon oxynitride film is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxides in a temperature programmed desorption gas analysis (TDS), and the amount of released ammonia is typically 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. Note that the amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is in the range of 50 ° C. to 650 ° C. or 50 ° C. to 550 ° C.

Since nitrogen oxide reacts with ammonia and oxygen in heat treatment, nitrogen oxide is reduced by using an insulating film that releases a large amount of ammonia.

Note that when the insulating film 110 is measured by SIMS, the nitrogen concentration in the film is preferably 6 × 10 ²⁰ atoms / cm ³ or less.

Further, as the insulating film 110, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide, and the like By using the high-k material, the gate leakage of the transistor can be reduced.

[Third insulating film]
The insulating film 116 includes one or more of nitrogen, hydrogen, and fluorine. An example of the insulating film 116 is a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon nitride fluoride, silicon fluoronitride, or the like. The concentration of hydrogen contained in the insulating film 116 is preferably 1 × 10 ²² atoms / cm ³ or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Accordingly, the impurity (nitrogen, hydrogen, or fluorine) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.

[Fourth insulating film]
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 118 can be provided as a single layer or a stacked layer.

The insulating film 118 is preferably a film that functions as a barrier film for hydrogen, water, and the like from the outside.

The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[Conductive film]
The conductive films 114, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. In addition, as the conductive films 114, 120a, and 120b, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above-described metal elements as components. Or it can form using the alloy etc. which combined the metal element mentioned above. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. The conductive films 114, 120a, and 120b may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding Two-layer structure in which tungsten film is laminated on titanium film, two-layer structure in which tungsten film is laminated on tantalum nitride film or tungsten nitride film, two-layer structure in which copper film is laminated on copper film containing manganese, on titanium film A two-layer structure in which a copper film is laminated, a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure in which a titanium film is formed thereon, and a copper film is laminated on a copper film containing manganese Further, there is a three-layer structure on which a copper film containing manganese is formed. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The conductive films 114, 120a, and 120b are formed of indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive material such as indium tin oxide containing silicon, indium zinc oxide, or indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO) can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

Alternatively, an oxide semiconductor typified by an In—Ga—Zn oxide may be used as the conductive film 114. In this case, after supplying oxygen to the insulating film 110, the conductive film 114 is supplied with nitrogen, hydrogen, or fluorine from the insulating film 116, so that the carrier density is increased. In other words, the oxide semiconductor functions as an oxide conductor (OC). Therefore, the conductive film 114 can be used as part of the gate electrode. For example, examples of the conductive film 114 include a single-layer structure of an oxide conductor (OC), a single-layer structure of a metal film, or a stacked structure of an oxide conductor (OC) and a metal film.

Note that the conductive film 114 is formed below the conductive film 114 in the case where a single-layer structure of a light-blocking metal film or a stacked structure of an oxide conductor (OC) and a light-blocking metal film is used. This is preferable because the channel region 108i can be shielded from light.

The thickness of each of the conductive films 114, 120a, and 120b can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

<1-2. Configuration Example 2 of Semiconductor Device>
Next, a structure different from that of the semiconductor device illustrated in FIGS. 1A to 1C is described with reference to FIGS.

2A is a top view of the transistor 100A, FIG. 2B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 2A, and FIG. 2C is FIG. 2A. It is sectional drawing between dashed-dotted lines Y1-Y2.

2A, 2B, and 2C includes a conductive film 106 formed over a substrate 102, an insulating film 104 over the conductive film 106, and an oxide semiconductor film 108 over the insulating film 104. The insulating film 110 over the oxide semiconductor film 108, the conductive film 114 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 114 are included. The oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 114, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.

The transistor 100A includes a conductive film 106 and an opening 143 in addition to the structure of the transistor 100 described above.

Note that the opening 143 is provided in the insulating film 104 and the insulating film 110. In addition, the conductive film 106 is electrically connected to the conductive film 114 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 114. Note that different potentials may be applied to the conductive film 106 and the conductive film 114 without providing the opening 143. Alternatively, the conductive film 106 may be used as a light-blocking film without providing the opening 143. For example, when the conductive film 106 is formed using a light-blocking material, light from below irradiated to the channel region 108 i can be suppressed.

Note that in the structure of the transistor 100A, the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film 114 is also referred to as a second gate electrode (also referred to as a top gate electrode). ). The insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.

As described above, unlike the transistor 100 described above, the transistor 100A illustrated in FIGS. 2A, 2B, and 2C has a structure including conductive films functioning as gate electrodes above and below the oxide semiconductor film 108. . As illustrated in the transistor 100A, the semiconductor device of one embodiment of the present invention may include a plurality of gate electrodes.

Further, as illustrated in FIG. 2C, the oxide semiconductor film 108 faces the conductive film 106 functioning as the first gate electrode and the conductive film 114 functioning as the second gate electrode. And sandwiched between conductive films functioning as two gate electrodes.

The length of the conductive film 114 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire length of the oxide semiconductor film 108 in the channel width direction is interposed between the conductive film 114 and the insulating film 110. Covered with In addition, since the conductive film 114 and the conductive film 106 are connected to each other in the opening portion 143 provided in the insulating film 104 and the insulating film 110, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is the insulating film 110. Is opposed to the conductive film 114.

In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 114 are connected to each other through the insulating film 104 and the opening 143 provided in the insulating film 110, and the insulating film 104 and the insulating film 110 are interposed therebetween. The oxide semiconductor film 108 is surrounded.

With such a structure, the oxide semiconductor film 108 included in the transistor 100A is electrically connected to the conductive film 106 functioning as the first gate electrode and the conductive film 114 functioning as the second gate electrode. Can be surrounded. As in the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is a surround channel (S-channel) structure. Can be called.

Since the transistor 100A has an S-channel structure, an electric field for inducing a channel by the conductive film 106 or the conductive film 114 can be effectively applied to the oxide semiconductor film 108; thus, the current driving capability of the transistor 100A Thus, high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the transistor 100A has a structure surrounded by the conductive films 106 and 114, the mechanical strength of the transistor 100A can be increased.

Note that an opening different from the opening 143 may be formed on the side surface of the oxide semiconductor film 108 where the opening 143 is not formed in the channel width direction of the transistor 100A.

In addition, as illustrated in the transistor 100A, in the case where the transistor includes a pair of gate electrodes with a semiconductor film interposed therebetween, the signal A is supplied to one gate electrode and the fixed potential is supplied to the other gate electrode. Vb may be given.

The signal A is a signal for controlling a conduction state or a non-conduction state, for example. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor. The fixed potential Vb may be the potential V1 or the potential V2. In this case, there is no need to separately provide a potential generation circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of a circuit including a transistor can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. On the other hand, there is a case where the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is at a high power supply potential can be improved, and the operation speed of a circuit including a transistor can be improved in some cases. For example, the fixed potential Vb may be higher than the low power supply potential.

Further, a signal A may be supplied to one gate of the transistor, and a signal B may be supplied to the other gate. The signal B is a signal for controlling, for example, the conduction state or non-conduction state of the transistor. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. Further, the potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor may be approximately the same.

When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B is In the case where a non-conducting state is obtained only when the potential is V4, functions such as a NAND circuit and a NOR circuit may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including a transistor is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases. The signal B may be an analog signal different from the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.

The signal A may be a digital signal and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal and the signal B may be a digital signal.

Further, the fixed potential Va may be applied to one gate of the transistor T, and the fixed potential Vb may be applied to the other gate. In the case where a fixed potential is applied to both gate electrodes of a transistor, the transistor may function as an element equivalent to a resistance element in some cases. For example, in the case where the transistor is an n-channel transistor, the effective resistance of the transistor can be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

Note that the other structure of the transistor 100A is similar to that of the transistor 100 described above, and has the same effect.

<1-3. Configuration Example 3 of Semiconductor Device>
Next, a different structure from the semiconductor device illustrated in FIGS. 2A, 2B, and 2C is described with reference to FIGS.

3A and 3B are cross-sectional views of the transistor 100B, FIGS. 4A and 4B are cross-sectional views of the transistor 100C, and FIGS. 5A and 5B are cross-sectional views of the transistor 100D. 6A and 6B are cross-sectional views of the transistor 100E, and FIGS. 7A and 7B are cross-sectional views of the transistor 100F. Note that the top view of the transistor 100B, the transistor 100C, the transistor 100D, the transistor 100E, and the transistor 100F is similar to the transistor 100A illustrated in FIG. 2A; therefore, description thereof is omitted here.

A transistor 100B illustrated in FIGS. 3A and 3B is different from the transistor 100A described above in the shapes of the conductive film 114 and the insulating film 110. Specifically, the conductive film 114 and the insulating film 110 in the transistor 100A have a tapered shape, whereas the conductive film 114 and the insulating film 110 in the transistor 100B have a rectangular shape. Specifically, in the transistor 100A, the upper end portion of the conductive film 114 is formed inside the lower end portion of the insulating film 110 in the cross section in the channel length (L) direction of the transistor. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the conductive film 114. On the other hand, in the transistor 100B, the upper end portion of the conductive film 114 and the lower end portion of the insulating film 110 are formed at substantially the same position in a cross section in the channel length (L) direction of the transistor.

For example, the structure of the transistor 100B can be obtained by processing the conductive film 114 and the insulating film 110 with the same mask and processing them in a batch using a dry etching method.

A structure similar to that of the transistor 100A is preferable because coverage with the insulating film 116 is improved. On the other hand, a structure like the transistor 100B is preferable because end portions of the source region 108s and the drain region 108d and the conductive film 114 are formed at substantially the same position.

A transistor 100C illustrated in FIGS. 4A and 4B is different from the transistor 100A described above in the shapes of the conductive film 114 and the insulating film 110. Specifically, in the transistor 100C, the conductive film 114 and the insulating film 110 have a reverse taper shape. In other words, in the transistor 100C, the upper end portion of the conductive film 114 is formed outside the lower end portion of the insulating film 110 in the cross section of the transistor in the channel length (L) direction.

For example, the structure of the transistor 100C can be obtained by processing the conductive film 114 and the insulating film 110 with the same mask and using the wet etching method to process them in a lump.

Further, with the structure of the transistor 100C, the source region 108s and the drain region 108d are provided inside the conductive film 114 functioning as a gate electrode. Note that a region where the conductive film 114 overlaps with the source region 108s and a region where the conductive film 114 overlaps with the drain region function as a so-called overlap region (also referred to as a Lov region). Note that the Lov region is a region that overlaps with the conductive film 114 functioning as a gate electrode and has lower resistance than the channel region 108i. With the structure having the Lov region, a high-resistance region is not formed between the channel region 108i and the source region 108s and the drain region 108d, so that the on-state current of the transistor can be increased.

A transistor 100D illustrated in FIGS. 5A and 5B is different from the transistor 100A described above in the shapes of the conductive film 114 and the insulating film 110. Specifically, the position of the lower end portion of the conductive film 114 and the upper end portion of the insulating film 110 are different in the transistor 100D in the cross section in the channel length (L) direction of the transistor. The lower end portion of the conductive film 114 is formed inside the upper end portion of the insulating film 110.

For example, the structure of the transistor 100D is obtained by processing the conductive film 114 and the insulating film 110 with the same mask, and processing the conductive film 114 with a wet etching method and the insulating film 110 with a dry etching method. Can do.

In addition, with the structure of the transistor 100D, the region 108f may be formed in the oxide semiconductor film 108 in some cases. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

The region 108f functions as either a high resistance region or a low resistance region. The high resistance region is a region which has a resistance equivalent to that of the channel region 108 i and does not overlap with the conductive film 114 functioning as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100B.

The low resistance region is a region having a lower resistance than the channel region 108i and a higher resistance than the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, electric field relaxation in the drain region is possible, so that variation in threshold voltage of the transistor due to the electric field in the drain region can be reduced.

Note that in the case where the region 108f is an LDD region, for example, one or more of nitrogen, hydrogen, and fluorine is supplied from the insulating film 116 to the region 108f, or impurities are applied from above the insulating film 110 using the insulating film 110 as a mask. By adding an element, the impurity can be formed by adding the impurity to the oxide semiconductor film 108 through the insulating film 110.

A transistor 100E illustrated in FIGS. 6A and 6B is different from the transistor 110A described above in the shape of the insulating film 110. Specifically, in the transistor 100E, the lower end portion of the conductive film 114 is formed outside the upper end portion of the insulating film 110 in the cross section of the transistor in the channel length (L) direction.

For example, the conductive film 114 and the insulating film 110 are processed using the same mask, the conductive film 114 is processed by a dry etching method, and then the side surface of the insulating film 110 is etched (side etching) using an etchant or the like. The structure of the transistor 100E can be employed.

Further, with the structure like the transistor 100E, a Lov region can be provided as in the transistor 100C.

A transistor 100F illustrated in FIGS. 7A and 7B is different from the transistor 100A described above in that an insulating film 122 functioning as a planarization insulating film is provided over the insulating film 118. Other configurations are similar to those of the transistor 100A described above, and have the same effects.

The insulating film 122 has a function of planarizing unevenness caused by a transistor or the like. The insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. As this organic material, photosensitive resin materials, such as an acrylic resin or a polyimide resin, are mentioned, for example.

7A and 7B, the shape of the opening included in the insulating film 122 is smaller than the openings 141a and 141b. However, the shape is not limited to this, and for example, the openings 141a and 141b are used. The shape may be the same as or larger than the openings 141a and 141b.

7A and 7B illustrate the structure in which the conductive films 120a and 120b are provided over the insulating film 122, but the present invention is not limited thereto. For example, the conductive films 120a and 120b are provided over the insulating film 118. Alternatively, the insulating film 122 may be provided over the conductive films 120a and 120b.

<1-4. Configuration Example 4 of Semiconductor Device>
Next, a structure different from the semiconductor device illustrated in FIGS. 2A, 2B, and 2C is described with reference to FIGS.

8A and 8B are cross-sectional views of the transistor 100G, FIGS. 9A and 9B are cross-sectional views of the transistor 100H, and FIGS. 10A and 10B are cross-sectional views of the transistor 100J. 11A and 11B are cross-sectional views of the transistor 100K. Note that top views of the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K are the same as those of the transistor 100A illustrated in FIG. 2A; therefore, description thereof is omitted here.

The transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K are different from each other in the structure of the transistor 100A and the oxide semiconductor film 108 described above. Other configurations are similar to those of the transistor 100A described above, and have the same effects.

An oxide semiconductor film 108 included in the transistor 100G illustrated in FIGS. 8A and 8B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.

An oxide semiconductor film 108 included in the transistor 100H illustrated in FIGS. 9A and 9B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.

10A and 10B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i has a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3. The source region 108s and the drain region 108d each have an oxide semiconductor film. A two-layer structure of 108_1 and the oxide semiconductor film 108_2. Note that in the cross section in the channel width (W) direction of the transistor 100J, the oxide semiconductor film 108_3 covers side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.

An oxide semiconductor film 108 included in the transistor 100K illustrated in FIGS. 11A and 11B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i has a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3, and the source region 108s and the drain region 108d have a single-layer structure of the oxide semiconductor film 108_2, respectively. It is. Note that in the cross section of the transistor 100K in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.

In the side surface of the channel region 108i in the channel width (W) direction or in the vicinity thereof, defects (for example, oxygen vacancies) are likely to be formed due to damage in processing, or contamination due to adhesion of impurities. Therefore, even when the channel region 108i is substantially intrinsic, application of stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing the low resistance (n Type) area. When the side surface in the channel width (W) direction of the channel region 108i or the vicinity thereof is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.

Therefore, in the transistor 100J and the transistor 100K, the channel region 108i has a stacked structure, and the side surface in the channel width (W) direction of the channel region 108i is covered with one layer of the stacked structure. With this structure, defects on the side surface of the channel region 108i or the vicinity thereof can be suppressed, or adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof can be reduced.

<1-5. Band structure>
Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, and the band structure of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110 are described with reference to FIGS. Will be described. FIG. 12 shows a band structure in the channel region 108i.

FIG. 12A illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 12B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.

FIG. 12A illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110 and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 2 as an oxide semiconductor film 108_3 is used. It is a band diagram.

12B, a silicon oxide film is used as the insulating films 104 and 110, and an atomic ratio of metal elements is set to In: Ga: Zn = 4: 2: 4.1 as the oxide semiconductor film 108_2. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 108_3 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 1: 3: 2. FIG. 10 is a band diagram of a structure using an oxide semiconductor film.

As shown in FIG. 12A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 12B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.

In order to form a continuous bond with the oxide semiconductor films 108_1, 108_2, and 108_3, each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.

With the structure illustrated in FIGS. 12A and 12B, the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. Recognize.

Note that by providing the oxide semiconductor films 108_1 and 108_3, trap levels that can be formed in the oxide semiconductor film 108_2 can be separated from the oxide semiconductor film 108_2.

In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the trap level. . Accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, a structure in which the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 is preferable. By doing so, electrons are unlikely to accumulate in the trap level, the on-state current of the transistor can be increased, and field effect mobility can be increased.

The oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.

With such a structure, the oxide semiconductor film 108_2 serves as a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed. With such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

The oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is lower than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to apply a material closer to the vacuum level than 0.2 eV than the energy level at the lower end of the band, preferably a material closer to the vacuum level of 0.5 eV or more.

In addition, the oxide semiconductor films 108_1 and 108_3 preferably do not include a spinel crystal structure. In the case where the oxide semiconductor films 108_1 and 108c_3 include a spinel crystal structure, the constituent elements of the conductive films 120a and 120b enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse. Note that it is preferable that the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS because blocking properties of constituent elements of the conductive films 120a and 120b, for example, a copper element are increased.

In this embodiment, the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2. Although the configuration using the film is exemplified, the configuration is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 1: 1.2 [atomic ratio], In: Ga : Zn = 1: 3: 4 [atomic ratio], In: Ga: Zn = 1: 3: 6 [atomic ratio], or In: Ga: Zn = 1: 10: 1 [atomic ratio] An oxide semiconductor film formed using an oxide target may be used. Alternatively, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements Ga: Zn = 10: 1 may be used as the oxide semiconductor films 108_1 and 108_3. In this case, as the oxide semiconductor film 108_2, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of In: Ga: Zn = 1: 1: 1 is used, and the oxide semiconductor film 108_1. , 108_3, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of Ga: Zn = 10: 1 can have an energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. The oxide semiconductor films 108_1 and 108_3 are preferable because the difference from the energy level at the lower end of the conduction band can be 0.6 eV or more.

Note that in the case where a metal oxide target with In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). In the case where a metal oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target with In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.

<1-6. Manufacturing Method 1 of Semiconductor Device>
Next, an example of a method for manufacturing the transistor 100 illustrated in FIGS. 1A to 1C will be described with reference to FIGS. 13A to 15B are cross-sectional views in the channel length (L) direction and the channel width (W) direction for describing a method for manufacturing the transistor 100.

First, the insulating film 104 is formed over the substrate 102. Subsequently, an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film 107 is formed by processing the oxide semiconductor film into an island shape (see FIG. 13A).

Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions. Examples of the addition method include an ion doping method, an ion implantation method, and a plasma treatment method. Alternatively, after a film for suppressing desorption of oxygen is formed over the insulating film, oxygen may be added to the insulating film 104 through the film.

A conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten is used as the above-described film for suppressing desorption of oxygen. Can be formed.

In addition, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that the oxide semiconductor film 107 can be processed by forming a mask over the oxide semiconductor film by a lithography process and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-separated oxide semiconductor film 107 may be directly formed by a printing method.

In the case of forming an oxide semiconductor film by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Note that when the oxide semiconductor film is formed, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. to 750 ° C., 150 ° C. to 450 ° C., or 200 ° C. to 350 ° C. Forming a film is preferable because crystallinity can be improved.

Alternatively, after the oxide semiconductor film 107 is formed, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, heat treatment is performed, so that the hydrogen concentration obtained by SIMS in the oxide semiconductor film is 5 × 10 ¹⁹ atoms / cm ^3. Or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 13B).

As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD (Plasma-Enhanced Chemical Vapor Deposition) method. In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

In this embodiment, a silicon oxynitride film is formed as the insulating film 110_0 using a PECVD apparatus. The thickness of the insulating film 110_0 is greater than or equal to 10 nm and less than or equal to 100 nm. Note that when the insulating film 110_0 is formed, oxygen is added from the insulating film 110_0 to the oxide semiconductor film 107 (see FIG. 13B).

In this embodiment, the insulating film 110_0 is formed using silane as a deposition gas and dinitrogen monoxide as an oxidation gas.

Further, it is preferable to increase the flow rate of the oxidizing gas with respect to the flow rate of the deposition gas. For example, the flow rate of dinitrogen monoxide is greater than 1000 times and less than 10,000 times, preferably 2000 times or more and 6000 times or less, relative to the flow rate of silane. Further, the pressure in the processing chamber is set to 1000 Pa or lower or 500 Pa or lower, the substrate temperature in the processing chamber is maintained at 280 ° C. or higher and 400 ° C. or lower, and a silicon oxynitride film is formed using a PECVD apparatus. Oxygen can be supplied to the semiconductor film 107.

In addition, oxygen can be supplied to the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap.

Alternatively, the insulating film 110_0 may be formed using a plasma CVD apparatus using a microwave. Microwave refers to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110_0 with little plasma damage to the deposition surface and deposits and few defects can be formed.

After the insulating film 110_0 is formed, plasma treatment may be performed using a gas containing nitrogen oxide, a gas containing nitrogen or oxygen, for example, a gas containing dinitrogen monoxide. Alternatively, a gas containing oxygen may be used. For the plasma treatment, the above-described PECVD apparatus or a plasma CVD apparatus using a microwave can be used. By performing the plasma treatment, oxygen can be supplied to the oxide semiconductor film 107. In addition, oxygen can be supplied to the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap.

Next, a conductive film 114_0 is formed over the insulating film 110_0. After that, a mask 140 is formed at a desired position over the conductive film 114_0 by a lithography process (see FIG. 13C).

Next, etching is performed from above the mask 140 to process the conductive film 114_0 and the insulating film 110_0. After that, the mask 140 is removed, so that the island-shaped conductive film 114 and the island-shaped insulating film 110 are formed (see FIG. 14A).

The conductive film 114_0 and the insulating film 110_0 are processed by a wet etching method or a dry etching method.

Note that when the conductive film 114 and the insulating film 110 are processed, the oxide semiconductor film 107 in a region where the conductive film 114 is not overlapped may be thin. Alternatively, when the conductive film 114 and the insulating film 110 are processed, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap may be reduced. Further, when the conductive film 114_0 and the insulating film 110_0 are processed, an etchant or an etching gas (eg, chlorine) is added to the oxide semiconductor film 107, or the conductive film 114_0 or the constituent element of the insulating film 110_0 May be added to the oxide semiconductor film 107 in some cases.

Next, the impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114 (see FIG. 14B).

As an addition method of the impurity element 145, an ion doping method, an ion implantation method, a plasma treatment method, or the like can be given. In the case of the plasma treatment method, the impurity element can be added by performing plasma treatment by generating plasma in a gas atmosphere containing the impurity element to be added. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

Note that as source gases for the impurity element 145, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H ₂ and rare One or more of the gases can be used. Alternatively, one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. The impurity element 145 is formed in the oxide semiconductor film 107 using one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas. By addition, one or more of a rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 107.

Alternatively, after adding a rare gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ The above may be added to the oxide semiconductor film 107. Or, after adding one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ , rare A gas may be added to the oxide semiconductor film 107.

The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose. For example, when argon is added by an ion implantation method, the acceleration voltage may be 10 kV to 100 kV and the dose may be 1 × 10 ¹³ ions / cm ^{2 to} 1 × 10 ¹⁶ ions / cm ² , for example, 1 × It may be 10 ¹⁴ ions / cm ² . In addition, when phosphorus ions are added by an ion implantation method, an acceleration voltage of 30 kV and a dose amount of 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less may be used, for example, 1 × 10 ¹⁵ ions. / Cm ² is sufficient.

Further, in this embodiment mode, the structure in which the impurity element 145 is added after the mask 140 is removed is illustrated; however, the present invention is not limited to this. For example, the impurity element 145 is left in a state where the mask 140 remains. Addition may be performed.

However, the invention is not limited to this. For example, the step of adding the impurity element 145 may not be performed. In this case, since the process of adding the impurity element 145 is not performed, the manufacturing process can be simplified.

Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 14C).

The insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. As the insulating film 116, a silicon nitride fluoride film or a silicon nitride film is formed using a PECVD apparatus.

By using a silicon nitride fluoride film or a silicon nitride film as the insulating film 116, the source region 108 s and the drain region 108 d that are in contact with the insulating film 116 are formed into nitrogen, hydrogen, fluorine in the silicon nitride fluoride film or the silicon nitride film. One or more of can be supplied. In particular, fluorine is preferably supplied to the source region 108s and the drain region 108d. As a result, the carrier density of the source region 108s and the drain region 108d can be stably increased.

Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 14D).

The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. As the insulating film 118, for example, a silicon oxynitride film is formed using a PECVD apparatus.

Next, after a mask is formed by lithography at a desired position of the insulating film 118, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141a reaching the source region 108s and the drain region 108d are formed. And reaching the opening 141b (see FIG. 15A).

As a method for etching the insulating film 118 and the insulating film 116, one or both of a wet etching method and a dry etching method may be used.

Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 141a and 141b (see FIG. 15B).

The conductive film 120 can be formed by selecting a material that can be used for the conductive films 120a and 120b.

Next, after a mask is formed at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120a and 120b (see FIG. 15C). .

As a method for processing the conductive film 120, one or both of a wet etching method and a dry etching method may be used.

Through the above process, the transistor 100 illustrated in FIG. 1 can be manufactured.

Note that as a film included in the transistor 100 (an insulating film, an oxide semiconductor film, a conductive film, or the like), in addition to the above-described formation methods, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, and a pulse laser deposition It can be formed by using (PLD) method or ALD method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is an MOCVD (metal organic chemical deposition) method.

In the thermal CVD method, the inside of a chamber is set to atmospheric pressure or reduced pressure, and a source gas and an oxidant are simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. Thus, the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that no defect is generated due to plasma damage.

A thermal CVD method such as an MOCVD method can form a film such as the above-described conductive film, insulating film, oxide semiconductor film, or metal oxide film. For example, an In—Ga—Zn—O film is formed. In this case, trimethylindium (In (CH ₃ ) ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), and dimethyl zinc are used (Zn (CH ₃ ) ₂ ). Without being limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethylzinc. You can also.

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or tetrakis (ethylmethylamide) hafnium) or the like, and two gases of ozone (O ₃ ) are used as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor is used. Two types of gas, H ₂ O, are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H ₂ gas. To form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, an In—O layer is formed using In (CH ₃ ) ₃ gas and O ₃ gas. Then, a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

<1-7. Manufacturing Method 2 of Semiconductor Device>
Next, an example of a method for manufacturing the transistor 100A illustrated in FIG. 2 will be described with reference to FIGS. 16 to 18 are cross-sectional views in the channel length (L) direction and the channel width (W) direction for describing the manufacturing method of the transistor 100A.

First, the conductive film 106 is formed over the substrate 102. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film 107 is formed by processing the oxide semiconductor film into an island shape (see FIG. 16A).

The conductive film 106 can be formed using a material and a method similar to those of the conductive films 120a and 120b.

Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107. Note that when the insulating film 110_0 is formed, oxygen is supplied to the insulating film 104 in a region where the oxide semiconductor film 107 and the oxide semiconductor film 107 do not overlap with each other. In FIG. 16B, the oxygen is schematically represented by arrows (see FIG. 16B).

Next, after a mask is formed by lithography at a desired position over the insulating film 110_0, the insulating film 110_0 and part of the insulating film 104 are etched, so that an opening 143 reaching the conductive film 106 is formed (FIG. 16 (C)).

As a method for forming the opening 143, one or both of a wet etching method and a dry etching method may be used.

Next, a conductive film 114_0 is formed over the insulating film 110_0 so as to cover the opening 143 (see FIG. 16C).

Note that by forming the conductive film 114_0 so as to cover the opening 143, the conductive film 106 and the conductive film 114_0 are electrically connected to each other.

Next, a mask 140 is formed at a desired position over the conductive film 114_0 by a lithography process (see FIG. 17A).

Next, etching is performed over the mask 140 to process the conductive film 114_0 and the insulating film 110_0. By processing the conductive film 114_0 and the insulating film 110_0, the island-shaped conductive film 114 and the island-shaped insulating film 110 are formed (see FIG. 17B).

Next, after the mask 140 is removed, an impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114 (see FIG. 17C).

The above is referred to for the addition method of the impurity element 145. .

Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, and the conductive film 114. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 17D).

Next, an insulating film 118 is formed over the insulating film 116 (see FIG. 18A).

Next, after a mask is formed by lithography at a desired position of the insulating film 118, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141a reaching the source region 108s and the drain region 108d are formed. And reaching the opening 141b (see FIG. 18B).

Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 141a and 141b (see FIG. 18C).

Next, after a mask is formed at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120a and 120b (see FIG. 18D). .

Through the above steps, the transistor 100A illustrated in FIG. 2 can be manufactured.

In this embodiment, an example in which a transistor includes an oxide semiconductor film is described; however, one embodiment of the present invention is not limited thereto. In one embodiment of the present invention, a transistor does not necessarily include an oxide semiconductor film. As an example, in a channel region of a transistor, in the vicinity of the channel region, in a source region or a drain region, a material having Si (silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like is formed. May be.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 2)
In this embodiment, an oxygen vacancy (Vo) formed in an oxide semiconductor and a case where an impurity (fluorine or hydrogen) enters the oxygen vacancy will be described in detail.

<2-1. Model of oxygen deficiency (Vo) formed in oxide semiconductor>
First, a model of oxygen vacancies (Vo) formed in an oxide semiconductor is described. In an oxide semiconductor, oxygen vacancies form deep levels (also referred to as dDOS). In some cases, dDOS is a factor that degrades the electrical characteristics of a transistor including an oxide semiconductor. Here, a result of verification of a model in which an aggregate of oxygen vacancies (also referred to as a Vo cluster) is formed in an oxide semiconductor will be described.

FIG. 19A is a diagram illustrating an InGaZnO ₄ crystal model in an initial state (before oxygen vacancy is generated). FIG. 19B, FIG. 19C, FIG. 20A, and FIG. FIG. 20C is a diagram illustrating a model in which oxygen vacancies are formed in the InGaZnO ₄ crystal model. In FIG. 19B, FIG. 19C, FIG. 20A, FIG. 20B, and FIG. 20C, a white circle represents a metal atom, and an element name is described in the white circle. . A black circle represents an oxygen atom, and a dotted circle represents Vo.

[Vo formation 1]
First, from the initial state shown in FIG. 19A, Vo is formed at an oxygen site surrounded by In and Zn as shown in FIG. 19B.

[Formation 1 of Vzn]
Next, as shown in FIG. 19C, Zn in the vicinity of Vo is released from the model shown in FIG. 19B, and Zn defects (Vzn) are formed.

[Vo formation 2]
Next, from the model shown in FIG. 19C, as shown in FIG. 20A, Vo is formed at an oxygen site in the vicinity of Vzn and with a small number of coordination with Ga.

[Formation 2 of Vzn]
Next, from the model shown in FIG. 20A, as shown in FIG. 20B, Zn in the vicinity of Vo is released to form Vzn.

[Vo formation 3]
Next, from the model shown in FIG. 20B, Vo is formed in the vicinity of Vzn as shown in FIG.

As described above, when one oxygen vacancy is formed in the oxide semiconductor, an oxygen vacancy is newly formed in the vicinity of the oxygen vacancy, and a plurality of oxygen vacancies or an aggregate of oxygen vacancies (Vo cluster). ) Is formed. Therefore, when oxygen vacancies are formed, it is important to terminate the oxygen vacancies with stable bonds.

<2-2. About Vo F Termination 1>
Next, the case where fluorine enters an oxide semiconductor in order to terminate oxygen deficiency (Vo) is described. First, in order to investigate whether or not the F F termination (hereinafter referred to as VoF) is likely to occur, there are two models, namely, a model in which F exists outside Vo and a model in which F enters Vo. The calculation was made to see if it is stable.

The model diagrams used for the calculation are shown in FIGS. 21A and 21B, and the calculation conditions are shown in Table 1, respectively. 21A and 21B, large black circles represent oxygen atoms, white circles, small black circles, and gray circles represent metal atoms (In, Ga, Zn, respectively), and dotted circles represent Vo. A circle indicated by an arrow represents F.

As a model used for the calculation, an InGaZnO ₄ crystal model (112 atoms) was used. 21A shows a model in which F exists outside Vo (hereinafter referred to as Vo + Fint model), and FIG. 21B shows a model in which F enters Vo (hereinafter referred to as VoF + bulk model).

The formation site of Vo and VoF was an oxygen site of an InO ₂ layer bonded to 3 In and 1 Zn. In the case of a model in which F exists outside Vo, F is assumed to exist between lattices (Fint). Therefore, F atoms were arranged at possible interstitial sites, and the most stable site in terms of energy was selected.

Further, in the Vo + Fint model shown in FIG. 21A, it is assumed that Vo and Fint exist at positions far enough that there is no influence. In this case, in order to compare the model in which F enters Vo with the Vo + Fint model shown in FIG. Therefore, the energy of the Vo + Fint model (E _tot (Vo + Fint) is the sum of the energy of the Vo model (E (Vo)) and the energy of the Fint model (E (Fint)), and the energy of the VoF model (E _tot (VoF)) Is the sum of the energy of the VoF model (E (VoF)) and the energy of the bulk model without defects (E (bulk)).

Formulas that satisfy the above relationship are shown below.

Table 2 shows the results of the relative energy calculated by the formulas represented by the above formulas (1) and (2).

From the results shown in Table 2, it can be seen that the relative energy of VoF is lower than that of Vo + Fint. This suggests that the form of VoF is more stable than the presence of Vo and Fint apart. That is, if Vo is in the IGZO film, Fint probably fills Vo and forms VoF.

<2-3. Density of state of VoF model>
Next, the state density of the VoF model was calculated. The calculation result of the density of states of the VoF model is shown in FIG.

For the calculation of the density of states of the VoF model, GGA was used as a functional. In FIG. 22, the upper half shows up spin, the lower half shows down spin, the horizontal axis represents energy, and the position of 0 eV on the horizontal axis corresponds to the upper end of the valence band.

From the results shown in FIG. 22, when VoF is formed, one electron is emitted in the conduction band. This is probably due to the difference in ionic valence between O and F. That is, when F enters Vo, electrons are probably emitted and become n-type.

<2-4. About Vo O Termination>
Next, for comparison with the above-described Vo F-termination, calculation was performed for the Vo O-termination. Note that the Vo O-termination is Vo repair, and there is no defect after Vo O-termination. First, energy comparison was performed between a model in which O is present outside Vo and a model after Vo repair (no defect).

The model diagrams used for the calculation are shown in FIGS. The calculation conditions were the same as those for VoF described above.

As a model used for the calculation, an InGaZnO ₄ crystal model (112 atoms) was used. FIG. 23A shows a model in which O exists outside Vo (hereinafter referred to as Vo + Oint model), and FIG. 23B shows a defect-free bulk model (hereinafter referred to as bulk + bulk model). 23A and 23B, large black circles represent oxygen atoms, white circles, small black circles, and gray circles represent metal atoms (In, Ga, Zn, respectively), and dotted circles represent Vo. A circle indicated by an arrow represents Oint.

In addition, in the Vo + Oint model shown in FIG. 23A, it is assumed that Vo and Oint exist at positions far enough that there is no influence. In this case, in order to compare the model in which O enters Vo shown in FIG. 23B (model without defects) and the Vo + Oint model shown in FIG. Therefore, as the Vo + Oint model shown in FIG. 23A, the energy of the Vo + Oint model (E _tot (Vo + Oint)) is the energy of the energy of the Vo model (E (Vo)) and the energy of the Oint model (E (Oint)). The energy (E _tot (cure)) of the model after Vo repair (without defects) shown in FIG. 23B was set to twice the energy (E (bulk)) of the bulk model without defects shown in FIG.

Formulas that satisfy the above relationship are shown below.

Table 3 shows the results of the relative energy calculated by the expressions represented by the above mathematical formulas (3) and (4).

From the results shown in Table 3, it can be seen that the relative energy is lower in Vo repair than in Vo + Oint. This suggests that the form of Vo repair is more stable than the presence of Vo and Oint apart. That is, if Vo is in the IGZO film, Oint probably fills Vo and repairs Vo. Note that carriers are not generated for Vo repair.

<2-5. About Vo F Termination 2>
Next, Vo F termination by a calculation method different from the above calculation will be described. In the above calculation, a GGA functional was used, while a Hybrid functional was used below. Table 4 shows the calculation conditions.

Note that, under the calculation conditions shown in Table 4, the lattice constant and the atomic position of the crystal model without defects were first optimized, and thereafter, each defect model was formed and only the atomic arrangement was optimized.

In addition, calculation was performed in the four models shown in FIGS. 24A, 24B, C, and D here.

FIG. 24A is a model diagram showing oxygen deficiency (Vo), FIG. 24B is a model diagram showing a structure in which Vo is filled with F (VoF), and FIG. FIG. 24D is a model diagram illustrating a structure (Fint) in which F is inserted between lattices, and FIG. 24D is a model diagram illustrating a structure (Oint) in which O is inserted between lattices. 24A, 24B, 24C, and 24D, large black circles represent oxygen atoms, white circles, small black circles, and gray circles represent metal atoms (In, Ga, Zn, respectively), and dotted lines A circle represents Vo, a white circle represented by an arrow represents Fint, and a black circle represented by an arrow represents Oint.

In FIG. 24A, the position where Vo is formed is O in the InO ₂ layer, and is O in the site adjacent to Zn. That is, the formation position of Vo is a site surrounded by In3 and Zn1. In FIG. 24B, the position where VoF is formed is O in the InO ₂ layer and O in the site adjacent to Zn. That is, the formation position of VoF is a site surrounded by In3 and Zn1. In FIG. 24C, the Fint formation position is the interstitial site between the InO ₂ layer and the (Ga, Zn) O layer. That is, the position where Fint is formed is a site surrounded by In3, Ga2 and Zn1. In FIG. 24D, the Oint formation position is an interstitial site between the InO ₂ layer and the (Ga, Zn) O layer. That is, the formation position of Oint is a site surrounded by In3, Ga2 and Zn1.

In addition, with respect to the model diagrams shown in FIGS. 24A, 24B, 24C, and 24D, the formation energy (E _form (D)) of the defect model was calculated using the following mathematical formula. As the formation energy (E _form (D)) of the defect model, the smaller the value, the easier the defect is formed.

In Equation (5), E (defect, q) is the total energy of the lattice having the defect D charged to q, E (bulk) is the total energy of the crystal without defects, and Δn (X) is removed from the system. The number of atoms X (added), μ (X) is the chemical potential for atom X removed (added) from the system, q is the charge valence of the system with defects, and μ (e) is the electron Chemical potential (Fermi level from the top of the valence band), _EVBM represents the energy of the top of the valence band (VBM), and ΔV represents correction of electrostatic potential energy.

FIG. 25 shows the calculation result of the density of states of a crystal model without defects (perfect crystal).

In FIG. 25, the Fermi level represents the highest electron occupation level. In this calculation, since the calculation is performed only at the Γ point, the levels are discrete. Further, all electrons are in the valence band, and there are no in-gap levels. From the calculation result shown in FIG. 25, the band gap was 3.10 eV.

Next, the calculation result of the formation energy of Vo is shown in FIG. 26A, the calculation result of the formation energy of VoF is shown in FIG. 26B, the calculation result of the formation energy of Fint is shown in FIG. The calculation results of the formation energy are shown in FIG. Note that in FIGS. 26A and 26B and FIGS. 27A and 27B, the vertical axis indicates the formation energy calculated using Equation (5), and the horizontal axis indicates the Fermi level. Further, in the horizontal axes of FIGS. 26A and 26B and FIGS. 27A and 27B, 0.0 eV corresponds to the valence band upper end (VBM), and 3.10 eV represents the lower end of the conduction band (CBM). It corresponds to.

In FIGS. 26A and 26B and FIGS. 27A and 27B, X is the defect type (Vo, VoF, Fint, or Oint), q is the valence of the system charge, and Y Is the number of spins per unit cell (up spin electron number−down spin electron number), and is expressed in the form of X ^q (Y).

From the result shown in FIG. 26A, the charged state of Vo is +2 in the Fermi level from VBM to 2.29 eV, and 0 (neutral) in 2.29 eV or more.

From the result shown in FIG. 26B, the charged state of VoF was +1 when the Fermi level was from VBM to 2.94 eV, and -1 when the Fermi level was 2.94 eV or more. Since Fermi energy at which the charge state changes is close to 2.94 eV and CBM, VoF becomes a donor source (nation factor).

From the results shown in FIG. 27A, the charge state of Fint was +1 valence when the Fermi level was less than 0.54 eV from VBM, and -1 valence from 0.54 eV to CBM. Fint traps electrons because it easily takes a negative charge state.

From the result shown in FIG. 27B, the charge state of Oint is +1 valence when the Fermi level is VBM to 1.99 eV or less, and is 0 valence (neutral) from 1.99 eV to 2.18 eV. 2.18 eV to CBM was -2 valent.

<2-6. About Vo F Termination 3>
Next, <2-5. The reaction formula (A) and the reaction formula (B) shown below were verified using the formation energy of each defect described in 2> for the F terminal of Vo.
Reaction formula (A): Vo + F → VoF
Reaction formula (B): VoF + ex. O → F (Vo repair by + ex.O)

In the reaction formula (A), if VoF is energetically more stable than Vo + F, F termination tends to occur. In the reaction formula (B), ex. O represents excess oxygen. Further, the left side of the reaction formula (A) and the reaction formula (B) may be described below as the reaction source system and the right side as the generation system.

The following equation (6) was used for verification of the reaction formula (A), and the following equation (7) was used for verification of the reaction formula (B).

In Equation (6), ΔE _A from forming energy generating system (VOF), a value obtained by subtracting the formation energy of the reactants (Vo + Fint).

Further, in Equation (7), ΔE _B is the formation energy generating system (Fint), a value obtained by subtracting the formation energy of the reactants (VoF + Oint).

In the calculation, assuming a model that is so far away that there is no interaction between defects, the reaction system is more stable at the Fermi level where the energy difference (ΔE _A and ΔE _B ) is positive, At the Fermi level where the energy difference (ΔE _A and ΔE _B ) is negative, the production system is more stable. Moreover, <2-5. As described in 2> for the F termination of Vo, the stable charge state of the system depends on the Fermi level. Therefore, the formation energy of each defect used when calculating ΔE _A and ΔE _B is the most stable charged state at each Fermi level.

In the reaction formula (A), reactants and formation energy and the energy difference generated based a calculation result of (Delta] E _A) shown in FIG. 28 (A). From the result shown in FIG. 28 (A), it is confirmed that ΔE _A is negative in the band gap, so that when Vo and F exist, Vo is easily filled by filling F with F. It was.

Further, in the reaction formula (B), reactants and formation energy and the energy difference generated based a calculation result of (Delta] E _B) shown in FIG. 28 (B). From the result shown in FIG. 28 (B), when the Fermi level is 1.31 eV or less, F release from VoF by Oint hardly occurs (that is, the reaction system is more stable), and at 1.31 eV or more, Oint is It is more stable to release F from VoF between lattices (Fint) and repair Vo.

Therefore, if the film on which the VoF is formed has excess oxygen enough to release the F of VoF, the released F exists between the lattices, that is, becomes Fint, and the Fint traps electrons in the gap. there is a possibility.

As described above, when oxygen vacancies (Vo) formed in the oxide semiconductor film have F between lattices (Fint), VoF is formed, and the VoF generates electrons. That is, the oxide semiconductor having VoF can be n-type. In addition, when there is excess oxygen (ex.O), VoF releases F between lattices to become Vo, and the Vo receives repair of excess oxygen. That is, an oxide semiconductor having Fint is obtained. Fint traps electrons and forms a negative fixed charge.

<2-7. Regarding the stability of the structure in which impurities are contained in Vo>
Next, the stability of the structure in which impurities are contained in Vo was calculated. Here, the impurities are fluorine and hydrogen. A structure in which fluorine is contained in Vo is VoF, and a structure in which hydrogen is contained in Vo is VoH.

First, the stable arrangement of impurities released from Vo was calculated. In the calculation of the stable arrangement of impurities released from Vo, the charge of the entire model was assumed to be neutral.

FIG. 29 shows the model used for the calculation, and Table 5 shows the calculation conditions.

FIG. 29 shows an InGaZnO ₄ crystal (112 atoms) model. A model including impurities (F or H) was prepared using the model.

FIGS. 30A and 30B are model diagrams of stable arrangement of impurities (F or H) between lattices of the InGaZnO ₄ crystal model. 30A is a model diagram in which F is stably arranged between the lattices of the InGaZnO ₄ crystal model, and FIG. 30B is a model diagram in which H is stably arranged between the lattices of the InGaZnO ₄ crystal model.

In FIG. 30A, the state of F located in the center of the octahedron having six oxygen vertices was stable in terms of energy. In FIG. 30B, the state in which H is bonded to O in the InGaZnO ₄ crystal is stable in terms of energy.

Here, the relationship between the Pauling electronegativity is shown in Table 6.

As shown in Table 6, the electronegativity of H is smaller than O, and the difference in electronegativity is large. Therefore, H mixed in the InGaZnO ₄ crystal maintaining the stoichiometric ratio probably exists in an ionic bond state with O. That is, O bonded with H is negatively charged and H is positively charged.

On the other hand, since the electronegativity of F is greater than O, it tends to be negative with respect to O. However, since the difference in electronegativity is smaller than in the case of H, the contribution of the covalent bond is probably greater. Therefore, in the IGZO crystal, F tends to exist at a position (interstitial) where the bonding force with the metal of the (Ga, Zn) O layer and the repulsive force of O are balanced.

Next, in order to thermodynamically evaluate the change between a state where there is an impurity (F or H) in Vo and a state where there is an impurity (F or H) outside Vo, this is one of chemical reaction path search methods. The energy and diffusion frequency required for impurities (F or H) to enter and exit Vo were calculated using the NEB (Nudged Elastic Band) method.

Note that the NEB method was used to evaluate the diffusion barrier (Ea) necessary for estimating the diffusion frequency. A model corresponding to the start state and end state of the diffusion path was prepared. The initial state was a state in which impurities (F or H) were contained in Vo, and the final state was a state in which impurities (F or H) were released from Vo. That is, a model including an impurity (F or H) is produced using an InGaZnO ₄ crystal (112 atoms) model as shown in FIG. 29, and the impurity (F or H) is Vo relative to the crystal model including Vo. The entered models (VoF and VoH) were in the initial state, and the models (Vo + interstitial F and Vo + interstitial H) in which impurities (F or H) are located outside Vo were in the final state.

Here, the charge of the entire model is +1, and the calculation conditions are the same as those shown in Table 5 above.

[Stability of VoF]
First, the calculation result of the stability of VoF which is a structure in which F is contained in Vo will be described below. First, FIG. 31 shows a model of the F diffusion path in the InGaZnO ₄ crystal, and FIG. 32 shows calculation results of energy changes corresponding to the F diffusion path. In addition, the arrow shown in FIG. 31 shows the release route of F from VoF.

As shown in FIGS. 31 and 32, at least one diffusion barrier exists in the diffusion path of F. In FIG. 31, a state where F is in Vo is expressed as VoF, and a state where F is between the lattices is expressed as Fint. In FIG. 32, a state in which F enters Vo is expressed as VoF, and a state in which F is released from VoF is expressed as Vo + Fint. In FIG. 32, the right side from VoF corresponds to the release of F from VoF, and the left side from Vo + Fint corresponds to the entry of F into Vo (also referred to as a trap).

From the results shown in FIG. 32, the energy (diffusion barrier) required when F is released from VoF is 4.59 eV, and the energy (diffusion barrier) required when F enters Vo is 0. .90 eV. Therefore, since the energy required for F to be released from VoF is higher than the energy for F to enter into Vo, it is suggested that it is difficult to release once F enters into Vo.

[Stability of VoH]
Next, the calculation result of the stability of VoH having a structure in which H is contained in Vo will be described below. First, FIG. 33 shows a model of the H diffusion path in the InGaZnO ₄ crystal, and FIG. 34 shows calculation results of changes in energy corresponding to the H diffusion path.

As shown in FIGS. 33 and 34, at least one diffusion barrier exists in the diffusion path of H. In FIG. 33, a state where H is entered into Vo is expressed as VoH. Further, in FIG. 34, a state in which Vo enters H is expressed as VoH, and a state in which H is released from VoH is expressed as Vo + H complex. In FIG. 34, the right side from VoH corresponds to the release of H from VoH, and the left side from Vo + H complex corresponds to the entry of H into Vo (also referred to as a trap).

From the results shown in FIG. 34, the energy (diffusion barrier) required when H is released from VoH is 1.85 eV, and the energy (diffusion barrier) required for entry of H into Vo is 1 It was .01 eV. Therefore, since the energy required for H to be released from VoH is higher than the energy for H to enter into Vo, it is suggested that it is difficult to release once H enters into Vo.

[Comparison of stability between VoF and VoH]
As a result of the above calculation, when comparing the energy required when F is released from VoF (diffusion barrier) with the energy required when H is released from VoH (diffusion barrier), the following relationship is obtained. I understand that
・ F (4.59 eV)> H (1.85 eV)

Next, the diffusion frequency Γ of the impurity (F or H) was calculated from the diffusion barrier shown above using the following formula (8).

In Equation (8), ν represents a frequency factor, Ea represents a diffusion barrier, k _B represents a Boltzmann constant, and T represents an absolute temperature. Moreover, it was set as (nu) = 1.0 * 10 < ¹³ > _S- ¹ .

Table 7 shows the result of calculation using Equation (8). Table 7 shows the diffusion frequency of the impurity (F or H) at 350 ° C. and the diffusion barrier of the impurity (F or H) at 350 ° C. The route of the impurity (F or H) is emitted from Vo. And Vo and trap.

As described above, when comparing VoF that can be formed in an oxide semiconductor and VoH that can be formed in an oxide semiconductor, VoF exists more stably than VoH. Therefore, as a source region and a drain region functioning as an n-type region, an oxide semiconductor having fluorine has less change in resistance in an n-type region and a highly reliable semiconductor than an oxide semiconductor having hydrogen. It can be a device.

As described above, the structure described in this embodiment can be combined as appropriate with any of the other embodiments.

(Embodiment 3)
In this embodiment, the structure and the like of an oxide semiconductor will be described with reference to FIGS.

<3-1. Structure of oxide semiconductor>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

In other words, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<3-2. CAAC-OS>
First, the CAAC-OS will be described.

A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even if 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 35E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 35E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 35E is derived from the (010) plane and the (100) plane of the crystal of InGaZnO ₄ . Further, the second ring in FIG. 35E is attributed to the (110) plane and the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 36A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 36A shows a pellet that is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 36B and 36C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. 36D and 36E are images obtained by performing image processing on FIGS. 36B and 36C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 36 (D), the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 36E, a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. By connecting the surrounding lattice points with the lattice points near the dotted line as the center, a distorted hexagon, a distorted pentagon, or a distorted heptagon can be formed. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as a CAA crystal (c-axis-aligned ab-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm 3. An oxide semiconductor having a carrier density of ³ or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<3-3. nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm parallel to the surface to be formed, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 37B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 37B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagon is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 37D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<3-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 38 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 38A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 38B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . 38A and 38B, it can be seen that the a-like OS has a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as an InGaZnO ₄ crystal part. Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 39 is an example in which the average size of the crystal parts (from 22 to 30) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 39, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons related to the acquisition of the TEM image or the like. From FIG. 39, the crystal part (also referred to as the initial nucleus) having a size of about 1.2 nm in the initial observation by TEM has an electron (e ⁻ ) cumulative irradiation dose of 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 39 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments or examples.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described as an example in the above embodiment will be described below with reference to FIGS.

FIG. 40 is a top view illustrating an example of the display device. A display device 700 illustrated in FIG. 40 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, The sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 42, a display element is provided between the first substrate 701 and the second substrate 705.

The display device 700 includes a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion in a region different from the region surrounded by the sealant 712 over the first substrate 701. 706 and an FPC terminal portion 708 (FPC: Flexible printed circuit) that is electrically connected to each other. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. . Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a plurality of transistors, and a transistor that is a semiconductor device of one embodiment of the present invention can be used. .

In addition, the display device 700 can include various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror device (DMD), digital micro shutter (DMS) element, interference modulation (IMOD) element, etc.), piezoelectric ceramic display and the like.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat-type display (SED), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

In addition, a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like) and display a full color display device. Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed. A method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.

In this embodiment, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 41 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 40 and has a configuration using a liquid crystal element as a display element. FIG. 42 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 40, and has a configuration using an EL element as a display element.

First, common parts shown in FIGS. 43 and 44 will be described first, and then different parts will be described below.

<4-1. Explanation of common parts of display device>
The display device 700 illustrated in FIGS. 41 and 42 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.

The transistors 750 and 752 have a structure similar to that of the transistor 100 described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.

The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

The capacitor 790 includes an oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, a conductive film functioning as a source electrode and a drain electrode included in the transistor 750, And an upper electrode formed through a step of processing the same conductive film. Further, an insulating film formed through a step of forming the same insulating film as the third insulating film and the fourth insulating film included in the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

41 and 42, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Further, the planarization insulating film 770 may be omitted.

41 and 42 illustrate the structure in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are configured to have the same structure; however, the present invention is not limited to this. For example, the pixel portion 702 and the source driver circuit portion 704 may use different transistors.

Note that in the case where different transistors are used for the pixel portion 702 and the source driver circuit portion 704, the top-gate transistor and the bottom-gate transistor described in Embodiment 1 may be used in combination. Specifically, a top-gate transistor is used for the pixel portion 702 and a bottom-gate transistor is used for the source driver circuit portion 704, or a bottom-gate transistor is used for the pixel portion 702, and the source driver circuit portion 704 is used. In addition, a configuration using a top gate type transistor can be given. Note that the source driver circuit portion 704 may be replaced with a gate driver circuit portion.

Here, bottom-gate transistors that can be used for the pixel portion 702 or the source driver circuit portion 704 are illustrated in FIGS.

43A is a top view of the transistor 300A, and FIG. 43B corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 43A. Corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 in FIG. Note that in FIG. 43A, some components (such as an insulating film functioning as a gate insulating film) are omitted in order to avoid complexity. The direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 43A.

The transistor 300A includes a conductive film 304 functioning as a gate electrode over the substrate 102, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film over the insulating film 307. 308, a conductive film 312a functioning as a source electrode electrically connected to the oxide semiconductor film 308, and a conductive film 312b functioning as a drain electrode electrically connected to the oxide semiconductor film 308. Further, insulating films 314 and 316 and an insulating film 318 are provided over the transistor 300A, more specifically, over the conductive films 312a and 312b and the oxide semiconductor film 308. The insulating films 314, 316, and 318 function as protective insulating films for the transistor 300A.

FIG. 44A is a top view of the transistor 300B, and FIG. 44B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.

The transistor 300B includes a conductive film 304 functioning as a gate electrode over the substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film over the insulating film 307. 308, the insulating film 314 over the oxide semiconductor film 308, the insulating film 316 over the insulating film 314, and the opening 341a provided in the insulating film 314 and the insulating film 316 are electrically connected to the oxide semiconductor film 308. A conductive film 312a functioning as a source electrode to be connected; a conductive film 312b functioning as a drain electrode electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 314 and the insulating film 316; Have. An insulating film 318 is provided over the transistor 300B, more specifically, over the conductive films 312a and 312b and the insulating film 316. The insulating film 314 and the insulating film 316 have a function as a protective insulating film of the oxide semiconductor film 308. The insulating film 318 functions as a protective insulating film of the transistor 300B.

The transistor 300A has a channel etch type structure, whereas the transistor 300B illustrated in FIGS. 44A, 44B, and 44C has a channel protection type structure.

45A is a top view of the transistor 300C, and FIG. 45B corresponds to a cross-sectional view along a dashed-dotted line X1-X2 in FIG. 45A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.

The transistor 300C is different from the transistor 300B in FIGS. 44A, 44B, and 44C in the shapes of the insulating films 314 and 316. Specifically, the insulating films 314 and 316 of the transistor 300C are provided in an island shape over the channel region of the oxide semiconductor film 308. Other structures are similar to those of the transistor 300B.

46A is a top view of the transistor 300D, and FIG. 46B corresponds to a cross-sectional view of a cross section along the dashed-dotted line X1-X2 in FIG. 46A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.

The transistor 300D includes a conductive film 304 functioning as a first gate electrode over the substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxidation over the insulating film 307. An oxide semiconductor film 308; an insulating film 314 over the oxide semiconductor film 308; an insulating film 316 over the insulating film 314; a conductive film 312a functioning as a source electrode electrically connected to the oxide semiconductor film 308; A conductive film 312b functioning as a drain electrode electrically connected to the oxide semiconductor film 308; an insulating film 318 over the conductive films 312a and 312b and the insulating film 316; and conductive films 320a and 320b over the insulating film 318; Have

In the transistor 300D, the insulating films 314, 316, and 318 function as a second gate insulating film of the transistor 300D. In the transistor 300D, the conductive film 320a functions as a pixel electrode used for the display device. In addition, the conductive film 320a is connected to the conductive film 312b through an opening 342c provided in the insulating films 314, 316, and 318. In the transistor 300D, the conductive film 320b functions as a second gate electrode (also referred to as a back gate electrode).

As shown in FIG. 46C, the conductive film 320b is connected to the conductive film 304 functioning as the first gate electrode in the openings 342a and 342b provided in the insulating films 306, 307, 314, 316, and 318. Is done. Therefore, the same potential is applied to the conductive film 320b and the conductive film 304.

Note that in the transistor 300D, the opening portions 342a and 342b are provided and the conductive film 320b and the conductive film 304 are connected to each other, but the invention is not limited thereto. For example, a structure in which only one of the opening 342a and the opening 342b is formed and the conductive film 320b and the conductive film 304 are connected, or the conductive film 320b without the openings 342a and 342b is provided. The conductive film 304 may not be connected. Note that in the case where the conductive film 320b and the conductive film 304 are not connected to each other, different potentials can be applied to the conductive film 320b and the conductive film 304, respectively.

Note that the transistor 300D has the S-channel structure described above.

Alternatively, the oxide semiconductor film 308 included in the transistor 300A illustrated in FIGS. 43A to 43C may have a stacked structure. Examples of such cases are shown in FIGS. 47 (A), (B), (C), and (D).

47A and 47B are cross-sectional views of the transistor 300E, and FIGS. 47C and 47D are cross-sectional views of the transistor 300F. Note that top views of the transistors 300E and 300F are similar to those of the transistor 300A illustrated in FIG.

An oxide semiconductor film 308 included in the transistor 300E illustrated in FIGS. 47A and 47B includes an oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3. An oxide semiconductor film 308 included in the transistor 300F illustrated in FIGS. 47C and 47D includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.

Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the conductive film 312a, the conductive film 312b, the insulating film 314, the insulating film 316, the insulating film 318, and the conductive films 320a and 320b are respectively The conductive film 114, the insulating film 116, the insulating film 110, the oxide semiconductor film 108, the conductive film 120a, the conductive film 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 114 described in Embodiment 1 above. The material and the formation method described in the above may be used.

Further, the structures of the transistors 300A to 300F may be used in any combination.

The signal line 710 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a different process from the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same process as an oxide semiconductor film functioning as a gate electrode. A membrane may be used. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.

The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

On the second substrate 705 side, a light-blocking film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the colored film 736 are provided.

<4-2. Configuration Example of Display Device Using Liquid Crystal Element>
A display device 700 illustrated in FIG. 41 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. A display device 700 illustrated in FIG. 41 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.

The conductive film 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. The conductive film 772 functions as a reflective electrode. A display device 700 illustrated in FIG. 41 is a so-called reflective color liquid crystal display device that uses external light to reflect light through a conductive film 772 and display it through a colored film 736.

As the conductive film 772, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

In the display device 700 illustrated in FIG. 41, unevenness is provided in part of the planarization insulating film 770 in the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing the unevenness on the surface of the resin film. In addition, the conductive film 772 functioning as a reflective electrode is formed along the unevenness. Accordingly, when external light is incident on the conductive film 772, light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

Note that the display device 700 illustrated in FIG. 41 is described as an example of a reflective color liquid crystal display device; however, the present invention is not limited to this. For example, the conductive film 772 is transmitted by using a light-transmitting conductive film in visible light. Type color liquid crystal display device. In the case of a transmissive color liquid crystal display device, the unevenness provided in the planarization insulating film 770 may not be provided.

Note that although not illustrated in FIG. 41, an alignment film may be provided on each of the conductive films 772 and 774 in contact with the liquid crystal layer 776. Further, although not shown in FIG. 41, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.

When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell) mode, A Compensated Birefringence (FLC) mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, and the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

<4-3. Display device using light emitting element>
A display device 700 illustrated in FIG. 42 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 42 can display an image when the EL layer 786 included in the light-emitting element 782 emits light. Note that the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.

Examples of a material that can be used for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials. Alternatively, a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As ), A quantum dot material having an element such as aluminum (Al) may be used.

The conductive film 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.

In the display device 700 illustrated in FIG. 42, the insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers part of the conductive film 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 784 side or a dual emission structure in which light is emitted to both the conductive film 784 and the conductive film 788 can be used.

A colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 42, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a circuit configuration of a semiconductor device in which stored contents can be held even when power is not supplied and the number of writings is not limited will be described with reference to FIGS.

<5-1. Circuit configuration>
FIG. 48 illustrates a circuit configuration of the semiconductor device. In FIG. 48, the first wiring (1st Line) and one of the source electrode and the drain electrode of the p-type transistor 1280a are electrically connected. In addition, the other of the source electrode and the drain electrode of the p-type transistor 1280a and one of the source electrode and the drain electrode of the n-type transistor 1280b are electrically connected. In addition, the other of the source electrode and the drain electrode of the n-type transistor 1280b is electrically connected to one of the source electrode and the drain electrode of the n-type transistor 1280c.

The second wiring (2nd Line) and one of the source electrode and the drain electrode of the transistor 1282 are electrically connected. The other of the source electrode and the drain electrode of the transistor 1282 is electrically connected to one of the electrodes of the capacitor 1281 and the gate electrode of the n-type transistor 1280c.

The third wiring (3rd Line) and the gate electrodes of the p-type transistor 1280a and the n-type transistor 1280b are electrically connected. In addition, the fourth wiring (4th Line) and the gate electrode of the transistor 1282 are electrically connected. The fifth wiring (5th Line) is electrically connected to the other electrode of the capacitor 1281 and the other of the source electrode and the drain electrode of the n-type transistor 1280c. The sixth wiring (6th Line) is electrically connected to the other of the source and drain electrodes of the p-type transistor 1280a and one of the source and drain electrodes of the n-type transistor 1280b.

Note that the transistor 1282 can be formed using an oxide semiconductor (OS: Oxide Semiconductor). Therefore, in FIG. 48, the symbol “OS” is added to the transistor 1282. Note that the transistor 1282 may be formed using a material other than an oxide semiconductor.

In FIG. 48, a floating node (FN) is added to a connection point between the other of the source electrode and the drain electrode of the transistor 1282, one of the electrodes of the capacitor 1281, and the gate electrode of the n-type transistor 1280c. It is. When the transistor 1282 is turned off, the potential applied to one of the floating node, the electrode of the capacitor 1281, and the gate electrode of the n-type transistor 1280c can be held.

In the circuit configuration shown in FIG. 48, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the n-type transistor 1280c can be held.

<5-2. Writing and holding information>
First, writing and holding of information will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, so that the transistor 1282 is turned on. Accordingly, the potential of the second wiring is supplied to the gate electrode of the n-type transistor 1280c and the capacitor 1281. That is, a predetermined charge is given to the gate electrode of the n-type transistor 1280c (writing). After that, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, so that the transistor 1282 is turned off. Thereby, the charge given to the gate electrode of the n-type transistor 1280c is held (held).

Since the off-state current of the transistor 1282 is extremely small, the charge of the gate electrode of the n-type transistor 1280c is held for a long time.

<5-3. Reading information>
Next, reading of information will be described. When the potential of the third wiring is set to a low level potential, the p-type transistor 1280a is turned on and the n-type transistor 1280b is turned off. At this time, the potential of the first wiring is supplied to the sixth wiring. On the other hand, when the potential of the third wiring is set to a high level potential, the p-type transistor 1280a is turned off and the n-type transistor 1280b is turned on. At this time, the sixth wiring has different potentials depending on the amount of charge held in the floating node (FN). Therefore, the held information can be read (read) by looking at the potential of the sixth wiring.

The transistor 1282 is an extremely low off-state transistor because an oxide semiconductor is used for a channel formation region. Since the off-state current of the transistor 1282 including an oxide semiconductor is 1 / 100,000 or less than that of a transistor formed using a silicon semiconductor or the like, charge accumulated in the floating node (FN) due to leakage of the transistor 1282 It is possible to ignore the disappearance of In other words, the transistor 1282 including an oxide semiconductor can realize a nonvolatile memory circuit that can retain information even when power is not supplied.

In addition, by using a semiconductor device using such a circuit configuration for a storage device such as a register or a cache memory, loss of data in the storage device due to supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Therefore, power consumption can be suppressed because the entire storage device or one or a plurality of logic circuits included in the storage device can be stopped in a short time in a standby state.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, a structure of a pixel circuit of an imaging device that can be used for the semiconductor device of one embodiment of the present invention will be described below with reference to FIG.

<6-1. Configuration of pixel circuit>
FIG. 49A is a diagram illustrating a configuration of a pixel circuit. The circuit illustrated in FIG. 49A includes a photoelectric conversion element 1360, a transistor 1351, a transistor 1352, a transistor 1353, and a transistor 1354.

The anode of the photoelectric conversion element 1360 is connected to the wiring 1316 and the cathode is connected to one of the source electrode and the drain electrode of the transistor 1351. The other of the source electrode and the drain electrode of the transistor 1351 is connected to the charge accumulation portion (FD), and the gate electrode is connected to the wiring 1312 (TX). One of a source electrode and a drain electrode of the transistor 1352 is connected to the wiring 1314 (GND), the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the transistor 1354, and the gate electrode is a charge storage portion (FD). ). One of a source electrode and a drain electrode of the transistor 1353 is connected to the charge accumulation portion (FD), the other of the source electrode and the drain electrode is connected to a wiring 1317, and a gate electrode is connected to the wiring 1311 (RS). The other of the source electrode and the drain electrode of the transistor 1354 is connected to the wiring 1315 (OUT), and the gate electrode is connected to the wiring 1313 (SE). All the above connections are electrical connections.

Note that a potential such as GND, VSS, or VDD may be supplied to the wiring 1314. Here, the potential and voltage are relative. Therefore, the magnitude of the potential of GND is not necessarily 0 volts.

The photoelectric conversion element 1360 is a light receiving element and has a function of generating a current corresponding to light incident on the pixel circuit. The transistor 1353 has a function of controlling charge accumulation in the charge accumulation portion (FD) by the photoelectric conversion element 1360. The transistor 1354 has a function of outputting a signal corresponding to the potential of the charge accumulation portion (FD). The transistor 1352 has a function of resetting the potential of the charge accumulation portion (FD). The transistor 1352 has a function of controlling selection of a pixel circuit at the time of reading.

Note that the charge accumulation portion (FD) is a charge retention node and retains a charge that varies depending on the amount of light received by the photoelectric conversion element 1360.

Note that the transistor 1352 and the transistor 1354 may be connected in series between the wiring 1315 and the wiring 1314. Therefore, the wiring 1314, the transistor 1352, the transistor 1354, and the wiring 1315 may be arranged in this order, or the wiring 1314, the transistor 1354, the transistor 1352, and the wiring 1315 may be arranged in this order.

The wiring 1311 (RS) functions as a signal line for controlling the transistor 1353. The wiring 1312 (TX) functions as a signal line for controlling the transistor 1351. The wiring 1313 (SE) functions as a signal line for controlling the transistor 1354. The wiring 1314 (GND) functions as a signal line for setting a reference potential (for example, GND). The wiring 1315 (OUT) functions as a signal line for reading a signal output from the transistor 1352. The wiring 1316 functions as a signal line for outputting charge from the charge accumulation portion (FD) through the photoelectric conversion element 1360, and is a low potential line in the circuit in FIG. The wiring 1317 functions as a signal line for resetting the potential of the charge accumulation portion (FD), and is a high potential line in the circuit in FIG.

Next, the structure of each element illustrated in FIG.

<6-2. Photoelectric conversion element>
As the photoelectric conversion element 1360, an element including selenium or a compound containing selenium (hereinafter referred to as a selenium-based material) or an element including silicon (for example, an element in which a pin-type junction is formed) can be used. In addition, a combination of a transistor including an oxide semiconductor and a photoelectric conversion element including a selenium-based material is preferable because reliability can be increased.

<6-3. Transistor>
Although the transistor 1351, the transistor 1352, the transistor 1353, and the transistor 1354 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon, an oxide semiconductor is used. It is preferable to use the transistor used. A transistor in which a channel formation region is formed using an oxide semiconductor has a characteristic of extremely low off-state current. For example, the transistor described in Embodiment 1 can be used as a transistor in which a channel formation region is formed using an oxide semiconductor.

In particular, when the leakage current of the transistor 1351 and the transistor 1353 connected to the charge accumulation portion (FD) is large, the time for holding the charge accumulated in the charge accumulation portion (FD) becomes insufficient. Therefore, by using a transistor including an oxide semiconductor for at least the two transistors, unnecessary charge can be prevented from flowing out from the charge storage portion (FD).

Further, in the transistor 1352 and the transistor 1354, if the leakage current is large, unnecessary charge is output to the wiring 1314 or the wiring 1315. Therefore, a transistor in which a channel formation region is formed using an oxide semiconductor is used as these transistors. It is preferable to use it.

FIG. 49A illustrates a transistor with one gate electrode structure; however, the present invention is not limited to this, and a structure having a plurality of gate electrodes may be employed, for example. As the transistor having a plurality of gate electrodes, for example, a structure in which a first gate electrode and a second gate electrode (also referred to as a back gate electrode) overlap with a semiconductor film in which a channel formation region is formed may be used. . As the back gate electrode, for example, the same potential as that of the first gate electrode, floating, or a potential different from that of the first gate electrode may be applied.

<7-4. Circuit operation timing chart>
Next, an example of circuit operation of the circuit illustrated in FIG. 49A is described with reference to a timing chart illustrated in FIG.

For the sake of simplicity in FIG. 49B, the potential of each wiring is given as a binary change signal. However, since each potential is an analog signal, actually, it can take various values without being limited to binary values depending on the situation. 49B, the signal 1401 is the potential of the wiring 1311 (RS), the signal 1402 is the potential of the wiring 1312 (TX), the signal 1403 is the potential of the wiring 1313 (SE), and the signal 1404 is the charge storage portion (FD). ) And a signal 1405 correspond to the potential of the wiring 1315 (OUT). Note that the potential of the wiring 1316 is always “Low”, and the potential of the wiring 1317 is always “High”.

At time A, when the potential of the wiring 1311 (signal 1401) is “High” and the potential of the wiring 1312 (signal 1402) is “High”, the potential of the charge accumulation portion (FD) (signal 1404) is the potential of the wiring 1317 (signal 1404). It is initialized to “High”) and the reset operation is started. Note that the potential of the wiring 1315 (signal 1405) is precharged to “High”.

At time B, when the potential of the wiring 1311 (the signal 1401) is set to “Low”, the reset operation is completed and the accumulation operation is started. Here, since a reverse bias is applied to the photoelectric conversion element 1360, the charge distribution accumulation unit (FD) (signal 1404) starts to decrease due to the reverse current. When the photoelectric conversion element 1360 is irradiated with light, the reverse current increases, so that the rate of decrease of the potential (signal 1404) of the charge storage portion (FD) changes in accordance with the amount of light irradiated. That is, the channel resistance between the source and the drain of the transistor 1354 changes in accordance with the amount of light with which the photoelectric conversion element 1360 is irradiated.

At time C, when the potential of the wiring 1312 (signal 1402) is set to “Low”, the accumulation operation ends, and the potential of the charge accumulation portion (FD) (signal 1404) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation. That is, it changes in accordance with the amount of light applied to the photoelectric conversion element 1360. In addition, since the transistor 1351 and the transistor 1353 are formed using an oxide film semiconductor and a channel formation region is formed with a very low off-state current, the charge accumulation portion (FD) is used until a subsequent selection operation (read operation) is performed. Can be kept constant.

Note that when the potential of the wiring 1312 (the signal 1402) is set to “Low”, a change in the potential of the charge storage portion (FD) occurs due to parasitic capacitance between the wiring 1312 and the charge storage portion (FD). is there. When the amount of change in potential is large, the amount of charge generated by the photoelectric conversion element 1360 during the accumulation operation cannot be acquired accurately. In order to reduce the amount of change in the potential, the capacitance between the gate electrode and the source electrode (or the gate electrode and the drain electrode) of the transistor 1351 is reduced, the gate capacitance of the transistor 1352 is increased, and held in the charge accumulation portion (FD). Measures such as providing capacity are effective. Note that in this embodiment, the potential change can be ignored by these measures.

At the time D, when the potential of the wiring 1313 (the signal 1403) is set to “High”, the transistor 1354 is turned on to start a selection operation, and the wiring 1314 and the wiring 1315 are turned on through the transistor 1352 and the transistor 1354. Then, the potential of the wiring 1315 (signal 1405) decreases. Note that the precharge of the wiring 1315 may be completed before the time D. Here, the rate at which the potential of the wiring 1315 (the signal 1405) decreases depends on the current between the source electrode and the drain electrode of the transistor 1352. That is, it changes in accordance with the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation.

At time E, when the potential of the wiring 1313 (signal 1403) is set to “Low”, the transistor 1354 is cut off, the selection operation is finished, and the potential of the wiring 1315 (signal 1405) becomes a constant value. Here, the constant value changes in accordance with the amount of light that has been applied to the photoelectric conversion element 1360. Therefore, by acquiring the potential of the wiring 1315, the amount of light applied to the photoelectric conversion element 1360 during the accumulation operation can be known.

More specifically, when the light applied to the photoelectric conversion element 1360 is strong, the potential of the charge accumulation portion (FD), that is, the gate voltage of the transistor 1352 is decreased. Therefore, the current flowing between the source electrode and the drain electrode of the transistor 1352 is reduced, and the potential of the wiring 1315 (signal 1405) is slowly decreased. Accordingly, a relatively high potential can be read from the wiring 1315.

On the other hand, when the light applied to the photoelectric conversion element 1360 is weak, the potential of the charge accumulation portion (FD), that is, the gate voltage of the transistor 1352 increases. Therefore, a current flowing between the source electrode and the drain electrode of the transistor 1352 is increased, and the potential of the wiring 1315 (signal 1405) is quickly decreased. Accordingly, a relatively low potential can be read from the wiring 1315.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<6. Circuit configuration of display device>
A display device illustrated in FIG. 50A includes a region (hereinafter, referred to as a pixel portion 502) including a pixel of a display element, and a circuit portion (hereinafter, referred to as a pixel portion 502) that is disposed outside the pixel portion 502 and includes a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number less than or equal to X), and the data line DL_n (n) according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

The protection circuit 506 illustrated in FIG. 50A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 50A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) or the like is increased. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

FIG. 50A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 50A can have a structure illustrated in FIG. 50B, for example.

A pixel circuit 501 illustrated in FIG. 50B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, a driving method of a display device including the liquid crystal element 570 includes a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric mode). , AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Host mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

For example, in a display device including the pixel circuit 501 in FIG. 50B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. An image can be displayed by sequentially performing this for each row.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 50A can have a structure illustrated in FIG. 50C, for example.

A pixel circuit 501 illustrated in FIG. 50C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

The transistor 552 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.

The capacitor 562 functions as a storage capacitor that stores written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In the display device including the pixel circuit 501 in FIG. 50C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

The pixel circuit 501 in which data is written is brought into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, an example of a circuit configuration to which the transistor described in any of the above embodiments can be applied will be described with reference to FIGS.

Note that in this embodiment, the transistor including an oxide semiconductor described in the above embodiment is referred to as an OS transistor and is described below.

<8. Example of inverter circuit configuration>
FIG. 51A is a circuit diagram of an inverter that can be applied to a shift register, a buffer, or the like included in a driver circuit. The inverter 800 outputs a signal obtained by inverting the logic of the input terminal IN to the output terminal OUT. The inverter 800 includes a plurality of OS transistors. The signal _SBG is a signal for changing the electrical characteristics of the OS transistor.

FIG. 51B is a circuit diagram illustrating an example of the inverter 800. The inverter 800 includes an OS transistor 810 and an OS transistor 820. The inverter 800 can be manufactured in an n-channel type and can have a so-called unipolar circuit configuration. Therefore, it can be manufactured at a lower cost than a CMOS inverter.

The OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second terminal that functions as the other of a source and a drain. Have

The first gate of the OS transistor 810 is connected to the second terminal. A second gate of the OS transistor 810 is connected to a wiring that transmits the signal _SBG . A first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. A second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.

FIG. 51C is a timing chart for explaining the operation of the inverter 800. The timing chart in FIG. _51C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal SBG, and the threshold voltage of the OS transistor 810.

The signal S _BG is supplied to the second gate of the OS transistor 810, whereby the threshold voltage (V _TH ) of the OS transistor 810 can be controlled.

Signal _{S BG has} a voltage _{V BG_B} for voltage _V BG_A for causing negative shift the _{V TH,} the _{V TH} is positive shift. By applying the voltage V _{BG_A} to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V _{TH_A} . _Further, by applying the voltage _{VBG_B} to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage _{VTH_B} .

That is, the OS transistor 810 can be shifted to a curve represented by a broken line 840 by increasing the voltage of the second gate as in the graph illustrated in FIG. Further, by reducing the voltage of the second gate, the curve can be shifted to a curve represented by a solid line 841.

By positively shifting to the threshold voltage V _{TH_B} , the OS transistor 810 can be in a state in which current does not easily flow. As shown in FIG. 52 (B), it can be extremely small current I _B that flows at this time. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage of the output terminal OUT can be rapidly increased. Therefore, the signal waveform 831 at the output terminal in the timing chart shown in FIG. 51C can be changed steeply. In addition, since the through current flowing between the wiring that supplies the voltage VDD and the wiring that supplies the voltage VSS can be reduced, operation with low power consumption can be performed.

In addition, the OS transistor 810 can be in a state in which current easily flows by being negatively shifted to the threshold voltage V _{TH_A} . As shown in FIG. 52 (C), it can be larger than at least the current I _B of the current I _A flowing at this time. Therefore, when the signal applied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be sharply decreased. Therefore, the signal waveform 832 at the output terminal in the timing chart shown in FIG. 51C can be changed steeply.

Note that the V _TH control of the OS transistor 810 by the signal S _BG is preferably performed before the state of the OS transistor 820 is switched, that is, before the times T1 and T2. For example, as illustrated in FIG. _51C , the threshold voltage V _{TH_A} is _changed from the threshold voltage V _{TH_A} to the threshold voltage V _{TH_B} before the time T1 when the signal applied to the input terminal IN switches to the high level. It is preferable to switch the threshold voltage. Further, as shown in FIG. _51C , the OS transistor 810 is _switched from the threshold voltage V _{TH_B} to the threshold voltage V _{TH_A} before the time T2 when the signal applied to the input terminal IN switches to the low level. It is preferable to switch the threshold voltage.

Note that although the structure in which the signal _SBG is switched in accordance with the signal applied to the input terminal IN is illustrated in the timing chart in FIG. _51C , another structure may be employed. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is illustrated in FIG.

53A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V _{BG_B} (or voltage V _{BG_A} ). The first gate of the OS transistor 850 is connected to a wiring for providing signal _{S F.} A second gate of the OS transistor 850 is connected to a wiring that _{supplies the} voltage V _{BG_B} (or the voltage V _{BG_A} ).

The operation in FIG. 53A will be described with reference to a timing chart in FIG.

As in FIG. 51C, the voltage for controlling the threshold voltage of the OS transistor 810 is the second gate of the OS transistor 810 before the time T3 when the signal applied to the input terminal IN switches to the high level. The configuration given to The OS transistor 850 is turned on the signal _{S F} to the high level, providing a voltage _{V BG_B} for controlling a threshold voltage in the node _{N BG.}

After the node _{N BG} becomes voltage _{V BG_B} is turned off the OS transistor 850. Since the off-state current of the OS transistor 850 is extremely small, the threshold voltage V _{TH_A} once held at the node can be held by continuing the off state. Therefore, the number of operations for applying the voltage V _{BG_B} to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage V _{BG_B} can be reduced.

Note that in the circuit configurations in FIGS. 51B and 53A, a configuration is described in which the voltage supplied to the second gate of the OS transistor 810 is supplied from the outside, but another configuration may be used. For example, a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810. An example of a circuit configuration that can realize this configuration is illustrated in FIG.

54A, in the circuit configuration shown in FIG. 51B, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810. In FIG. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

The operation in FIG. 54A is described with reference to a timing chart in FIG. The timing chart in FIG. 54B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810.

An output waveform IN_B that is a signal obtained by inverting the logic of a signal supplied to the input terminal IN can control the threshold voltage of the OS transistor 810 as in FIG. Accordingly, although the voltages are different, the threshold voltage of the OS transistor 810 can be controlled as described with reference to FIGS. For example, at time T4 in FIG. 54B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be set in a state in which current does not easily flow, and the voltage of the output terminal OUT can be rapidly increased.

At time T5 in FIG. 54B, the signal supplied to the input terminal IN is low and the OS transistor 820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be sharply increased.

As described above, in the configuration of this embodiment, the voltage of the back gate in the inverter having the OS transistor is switched according to the logic of the signal at the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor together with the signal applied to the input terminal IN, the change in the voltage at the output terminal OUT can be made steep. In addition, the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 9)
In this embodiment, an input / output device of one embodiment of the present invention will be described with reference to FIGS.

<9. Configuration example of input / output device>
The input / output device of one embodiment of the present invention is an in-cell touch panel having a function of displaying an image and a function of a touch sensor.

There is no limitation on the display element included in the input / output device of one embodiment of the present invention. Various elements such as liquid crystal elements, optical elements using MEMS (Micro Electro Mechanical System), light emitting elements such as organic EL (Electro Luminescence) elements and light emitting diodes (LEDs), and electrophoretic elements, display elements Can be applied as

In this embodiment, a transmissive liquid crystal display device using a horizontal electric field liquid crystal element is described as an example.

There is no limitation on a detection element (also referred to as a sensor element) included in the input / output device of one embodiment of the present invention. Various sensors that can detect the proximity or contact of an object to be detected, such as a finger or a stylus, can be used as the detection element.

For example, various methods such as a capacitance method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used as a sensor method.

In this embodiment, an input / output device having a capacitive detection element will be described as an example.

Examples of the electrostatic capacity method include a surface electrostatic capacity method and a projection electrostatic capacity method. In addition, examples of the projected capacitance method include a self-capacitance method and a mutual capacitance method. Use of the mutual capacitance method is preferable because simultaneous multipoint detection is possible.

As an in-cell type touch panel, there are typically a hybrid in-cell type and a full-in-cell type. The hybrid in-cell type refers to a configuration in which an electrode or the like constituting a detection element is provided on both a substrate supporting a display element and a counter substrate or only on the counter substrate. On the other hand, the full-in-cell type refers to a configuration in which an electrode or the like constituting a detection element is provided only on a substrate that supports a display element. The input / output device of one embodiment of the present invention is a full-in-cell touch panel. A full-in-cell touch panel is preferable because the structure of the counter substrate can be simplified.

The input / output device of one embodiment of the present invention is preferable because the electrode included in the display element also serves as the electrode included in the detection element, so that the manufacturing process can be simplified and the manufacturing cost can be reduced.

In addition, by applying one embodiment of the present invention, the input / output device can be thinned compared to a structure in which a separately manufactured display panel and a detection element are attached to each other or a structure in which a detection element is formed on the counter substrate side. Alternatively, the weight can be reduced, or the number of parts of the input / output device can be reduced.

In the input / output device of one embodiment of the present invention, both an FPC that supplies a signal for driving a pixel and an FPC that supplies a signal for driving a detection element are arranged on one substrate side. Thereby, it becomes easy to incorporate in an electronic device, and the number of parts can be reduced. Note that a signal for driving a pixel and a signal for driving a detection element may be supplied by one FPC.

The structure of the input / output device of one embodiment of the present invention is described below.

[Cross-sectional configuration example 1 of input / output device]
FIG. 55A is a cross-sectional view of two adjacent subpixels of the input / output device. The two subpixels illustrated in FIG. 55A are subpixels included in different pixels.

As shown in FIG. 55A, the input / output device includes a transistor 201, a transistor 203, a liquid crystal element 207a, and the like over a substrate 211. In addition, an insulating film such as an insulating film 212, an insulating film 213, an insulating film 215, and an insulating film 219 is provided over the substrate 211.

For example, a single pixel includes a sub-pixel that exhibits red, a sub-pixel that exhibits green, and a sub-pixel that exhibits blue, so that a full-color display can be performed on the display unit. In addition, the color which a subpixel exhibits is not restricted to red, green, and blue. As the pixel, for example, a sub-pixel exhibiting a color such as white, yellow, magenta, or cyan may be used.

The transistors described in the above embodiments can be applied to the transistors 201 and 203 included in the subpixel.

The liquid crystal element 207a is a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied. The liquid crystal element 207 a includes a conductive film 251, a conductive film 252, and a liquid crystal 249. The alignment of the liquid crystal 249 can be controlled by an electric field generated between the conductive films 251 and 252. The conductive film 251 can function as a pixel electrode. The conductive film 252 can function as a common electrode.

By using a conductive material that transmits visible light for the conductive films 251 and 252, the input / output device can function as a transmissive liquid crystal display device. In addition, by using a conductive material that reflects visible light for the conductive film 251 and a conductive material that transmits visible light for the conductive film 252, the input / output device can function as a reflective liquid crystal display device. Can do.

As the conductive material that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. Specifically, indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Examples thereof include indium tin oxide containing titanium oxide, indium tin oxide added with silicon oxide, zinc oxide, and zinc oxide added with gallium. Note that a film containing graphene can also be used. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide formed in a film shape.

An oxide conductive film is preferably used for the conductive film 251. The conductive film 252 is preferably an oxide conductive film. The oxide conductive film preferably includes one or more metal elements contained in the oxide semiconductor film 223. For example, the conductive film 251 preferably contains indium, and more preferably is an In—M—Zn oxide (M is Al, Ga, Y, or Sn). Similarly, the conductive film 252 preferably contains indium, and more preferably an In-M-Zn oxide.

Note that at least one of the conductive film 251 and the conductive film 252 may be formed using an oxide semiconductor. As described above, a manufacturing apparatus (e.g., a film formation apparatus or a processing apparatus) can be manufactured in two or more steps by using an oxide semiconductor including the same metal element for two or more layers included in the input / output device. Therefore, the manufacturing cost can be reduced.

For example, when a silicon nitride film containing hydrogen is used for the insulating film 253 and an oxide semiconductor is used for the conductive film 251, the conductivity of the oxide semiconductor can be increased by hydrogen supplied from the insulating film 253.

Examples of the conductive material that reflects visible light include aluminum, silver, and alloys containing these metal materials.

The conductive film 251 functioning as a pixel electrode is electrically connected to the source or drain of the transistor 203.

The conductive film 252 has a comb-like upper surface shape (also referred to as a planar shape) or an upper surface shape provided with a slit. An insulating film 253 is provided between the conductive films 251 and 252. The conductive film 251 has a portion overlapping with the conductive film 252 with the insulating film 253 provided therebetween. In addition, in a region where the conductive film 251 and the coloring film 241 overlap with each other, a portion where the conductive film 252 is not provided over the conductive film 251 is included.

A conductive film 255 is provided over the insulating film 253. The conductive film 255 is electrically connected to the conductive film 252 and can function as an auxiliary wiring of the conductive film 252. By providing the auxiliary wiring electrically connected to the common electrode, a voltage drop due to the resistance of the common electrode can be suppressed. At this time, in the case where a stacked structure of a conductive film including a metal oxide and a conductive film including a metal is used, it is preferable to form by a patterning technique using a halftone mask because the process can be simplified.

The conductive film 255 may be a film having a lower resistance value than the conductive film 252. The conductive film 255 is formed with a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, silver, neodymium, or scandium, or an alloy material containing these elements, for example. can do.

The conductive film 255 is preferably provided at a position overlapping the light-shielding film 243 and the like so that the user of the input / output device cannot see the conductive film 255.

The colored film 241 has a portion overlapping with the liquid crystal element 207a. The light-shielding film 243 has a portion overlapping with at least one of the transistors 201 and 203.

The insulating film 245 preferably has a function as an overcoat that prevents impurities contained in the coloring film 241, the light-shielding film 243, and the like from diffusing into the liquid crystal 249. The insulating film 245 is not necessarily provided if not necessary.

Note that an alignment film may be provided on surfaces of the substrate 211 and the substrate 261 in contact with the liquid crystal 249. The alignment film can control the alignment of the liquid crystal 249. For example, an alignment film that covers the conductive film 252 may be formed in FIG. In FIG. 55A, an alignment film may be provided between the insulating film 245 and the liquid crystal 249. The insulating film 245 may have both a function as an alignment film and a function as an overcoat.

In addition, the input / output device includes a spacer 247. The spacer 247 has a function of preventing the distance between the substrate 211 and the substrate 261 from approaching a certain distance.

FIG. 55A illustrates an example in which the spacer 247 is provided over the insulating film 253 and the conductive film 252, but one embodiment of the present invention is not limited thereto. The spacer 247 may be provided on the substrate 211 side or may be provided on the substrate 261 side. For example, the spacer 247 may be formed over the insulating film 245. FIG. 55A illustrates an example in which the spacer 247 is in contact with the insulating film 253 and the insulating film 245; however, the spacer 247 may not be in contact with a structure provided on either the substrate 211 side or the substrate 261 side. .

A granular spacer may be used as the spacer 247. As the granular spacer, a material such as silica can be used, but an elastic material such as resin or rubber is preferably used. At this time, the granular spacer may be crushed in the vertical direction.

The board | substrate 211 and the board | substrate 261 are bonded together by the contact bonding layer which is not shown in figure. A liquid crystal 249 is sealed in a region surrounded by the substrate 211, the substrate 261, and the adhesive layer.

Note that in the case where the input / output device functions as a transmissive liquid crystal display device, two polarizing plates are arranged so as to sandwich the display portion. Light from a backlight disposed outside the polarizing plate is incident through the polarizing plate. At this time, the alignment of the liquid crystal 249 can be controlled by the voltage applied between the conductive films 251 and 252, and the optical modulation of light can be controlled. That is, the intensity of light emitted through the polarizing plate can be controlled. In addition, since the incident light is absorbed by the colored film 241 in a region other than the specific wavelength region, the emitted light is, for example, light exhibiting red, blue, or green.

In addition to the polarizing plate, for example, a circular polarizing plate can be used. As a circularly-polarizing plate, what laminated | stacked the linearly-polarizing plate and the quarter wavelength phase difference plate, for example can be used. The circularly polarizing plate can reduce the viewing angle dependency of the display of the input / output device.

Note that although an element to which the FFS mode is applied is used here as the liquid crystal element 207a, liquid crystal elements to which various modes are applied can be used without being limited thereto. For example, VA (Vertical Alignment), TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, ASM (Axially Symmetrically Aligned Micro-cell) mode, OCB (Optical Aligned Coding mode) ) Mode, an AFLC (Antiferroelectric Liquid Crystal) mode, or the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be applied to the input / output device. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, or the like can be used.

Note that the liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used in the liquid crystal element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal (PDLC), a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like is used. Can do. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Further, as the liquid crystal material, either a positive liquid crystal or a negative liquid crystal may be used, and an optimal liquid crystal material may be used depending on the mode and design to be applied.

In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed is used for the liquid crystal 249 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic. In addition, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

Here, a substrate directly touched by a detection target such as a finger or a stylus may be provided above the substrate 261. At this time, a polarizing plate or a circular polarizing plate is preferably provided between the substrate 261 and the substrate. In that case, it is preferable to provide a protective layer (ceramic coating or the like) on the substrate. For the protective layer, for example, an inorganic insulating material such as silicon oxide, aluminum oxide, yttrium oxide, and yttria-stabilized zirconia (YSZ) can be used. Further, tempered glass may be used for the substrate. As the tempered glass, it is possible to use glass that has been subjected to physical or chemical treatment by an ion exchange method, an air-cooling tempering method, or the like and to which a compressive stress is applied to the surface.

In FIG. 55A, proximity or contact of an object to be detected is detected using a capacitor formed between the conductive film 252 included in the left subpixel and the conductive film 252 included in the right subpixel. can do. That is, in the input / output device of one embodiment of the present invention, the conductive film 252 serves as both the common electrode of the liquid crystal element and the electrode of the detection element.

As described above, in the input / output device of one embodiment of the present invention, the electrode included in the liquid crystal element also serves as the electrode included in the detection element; therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. In addition, the input / output device can be reduced in thickness and weight.

The conductive film 252 is electrically connected to the conductive film 255 functioning as an auxiliary wiring. By providing the conductive film 255, the resistance of the electrode of the detection element can be reduced. By reducing the resistance of the electrode of the sensing element, the time constant of the electrode of the sensing element can be reduced. The smaller the time constant of the electrode of the sensing element, the higher the detection sensitivity, and the higher the detection accuracy.

In addition, if the capacitance between the sensing element electrode and the signal line is too large, the time constant of the sensing element electrode may increase. Therefore, it is preferable to provide an insulating film having a planarization function between the transistor and the electrode of the detection element to reduce the capacitance between the electrode of the detection element and the signal line. For example, in FIG. 55A, the insulating film 219 is provided as the insulating film having a planarization function. By providing the insulating film 219, the capacitance between the conductive film 252 and the signal line can be reduced. Thereby, the time constant of the electrode of a detection element can be made small. As described above, the smaller the time constant of the electrodes of the sensing element, the higher the detection sensitivity and the higher the detection accuracy.

For example, the time constant of the electrodes of the sensing element is greater than 0 seconds and 1 × 10 ⁻⁴ seconds or less, preferably greater than 0 seconds and 5 × 10 ⁻⁵ seconds or less, more preferably greater than 0 seconds and 5 × 10 ⁻⁶ seconds. In the following, it is more preferably greater than 0 seconds and 5 × 10 ⁻⁷ seconds or less, and more preferably greater than 0 seconds and 2 × 10 ⁻⁷ seconds or less. In particular, by setting the time constant to 1 × 10 ⁻⁶ seconds or less, high detection sensitivity can be realized while suppressing the influence of noise.

[Cross-sectional configuration example 2 of input / output device]
FIG. 55B is a cross-sectional view of two adjacent pixels, which is different from FIG. The two subpixels illustrated in FIG. 55B are subpixels included in different pixels.

In the structural example 2 illustrated in FIG. 55B, the stacking order of the conductive film 251, the conductive film 252, the insulating film 253, and the conductive film 255 is different from that in the structural example 1 illustrated in FIG. In the second configuration example, the above can be referred to for the same parts as the first configuration example.

Specifically, in Structural Example 2, the conductive film 255 is provided over the insulating film 219, the conductive film 252 is provided over the conductive film 255, the insulating film 253 is provided over the conductive film 252, and the insulating film 253 is provided over the insulating film 253. Has a conductive film 251.

As in the liquid crystal element 207b illustrated in FIG. 55B, the conductive film 251 provided in the upper layer and having a comb-shaped or slit-like upper surface shape is used as the pixel electrode, and the conductive film 252 provided in the lower layer is used as the common electrode. You can also. In that case also, the conductive film 251 only needs to be electrically connected to the source or the drain of the transistor 203.

In FIG. 55B, proximity or contact of a detection object is detected using a capacitor formed between the conductive film 252 included in the left subpixel and the conductive film 252 included in the right subpixel. can do. That is, in the input / output device of one embodiment of the present invention, the conductive film 252 serves as both the common electrode of the liquid crystal element and the electrode of the detection element.

Note that in Structural Example 1 (FIG. 55A), the conductive film 252 serving as both the electrode of the detection element and the common electrode is closer to the display surface (the side closer to the detection target) than the conductive film 251 functioning as a pixel electrode. To position. Thereby, in the configuration example 1, the detection sensitivity may be improved compared to the configuration example 2 in which the conductive film 251 is located closer to the display surface than the conductive film 252.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
(Embodiment 10)
In this embodiment, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.

<Storage device 1>
FIG. 56 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can retain stored data even in a state where power is not supplied and has no limit on the number of times of writing.

A semiconductor device illustrated in FIG. 56A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used. Here, the transistor 3200 is formed using the element layer 50, the transistor 3300 is formed using the element layer 30, and the capacitor 3400 is formed using the element layer 40, so that a circuit illustrated in FIG. The semiconductor device shown in FIGS. 58 and 59 can be used.

The transistor 3300 is preferably a transistor with low off-state current. As the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.

In FIG. 56A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been.

The semiconductor device illustrated in FIG. 56A has a characteristic that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).

Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in the case where a high-level charge is applied to the node FG in writing, the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. In order not to read data in other memory cells, the fifth wiring 3005 is _{supplied with} a potential at which the transistor 3200 is in a “non-conducting state” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H.} It is sufficient that only the information of a desired memory cell can be read by providing to the above. _{Alternatively} , only information on a desired memory cell can be obtained by applying to the fifth wiring 3005 a potential at which the transistor 3200 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L.} It may be configured to be readable.

Note that, in the above, an example in which two types of charges are held in the node FG has been described, but the semiconductor device according to the present invention is not limited to this. For example, a structure in which three or more kinds of electric charges can be held in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.

<Storage device 2>
The semiconductor device illustrated in FIG. 56B is different from the semiconductor device illustrated in FIG. 56A in that the transistor 3200 is not provided. In this case also, data can be written and held in the same manner as the semiconductor device shown in FIG. Further, a structure in which a sense amplifier or the like is provided in a lower layer of the semiconductor device illustrated in FIG.

Information reading in the semiconductor device illustrated in FIG. 56B is described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + CV) / (CB + C). Therefore, if the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. It can be seen that the potential (= (CB × VB0 + CV1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + CV0) / (CB + C)). .

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.

The semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.

<Storage device 3>
A modification of the semiconductor device (memory device) illustrated in FIG. 56A is described with reference to a circuit diagram illustrated in FIG.

The semiconductor device illustrated in FIG. 57 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 can be a transistor similar to the above-described transistor 3200, and the transistors 4200 to 4400 can be the same transistor as the above-described transistor 3300. Note that the semiconductor device illustrated in FIG. 57 is not illustrated in FIG. 57 but is provided in a matrix. The semiconductor device illustrated in FIG. 57 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.

One of a source and a drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 57, it may be an n-channel type.

The semiconductor device illustrated in FIG. 57 includes two data holding units. For example, the first data holding portion holds charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200. The second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds charge.

The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. A gate of the transistor 4400 is connected to the wiring 4005. A gate of the transistor 4200 is connected to the wiring 4006. A gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.

The transistors 4200 to 4400 function as switches for controlling writing of data voltages and holding of electric charges. Note that as the transistors 4200 to 4400, transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used. The transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor). An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon. Note that although the conductivity types of the transistors 4200 to 4400 are shown as n-channel types in FIG. 57, they may be p-channel types.

The transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even when a transistor including an oxide semiconductor is used. That is, the semiconductor device illustrated in FIG. 57 includes a first layer 4021 including a transistor 4100, a second layer 4022 including a transistor 4200 and a transistor 4300, and a third layer including a transistor 4400 as illustrated in FIG. 4023. By stacking layers including transistors, the circuit area can be reduced and the semiconductor device can be downsized.

Next, an operation of writing information to the semiconductor device illustrated in FIG. 57 is described.

First, a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V _D1, and the threshold voltage of the transistor 4100 is Vth.

In the writing operation 1, after the wiring 4003 is set to V _D1 and the wiring 4001 is set to the ground potential, the wiring 4001 is electrically floated. In addition, the wirings 4005 and 4006 are set to a high level. In addition, the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases. When the potential of the node FG2 rises and the voltage (Vgs) between the gate and the source in the transistor 4100 becomes the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the potential increase of the wiring 4001 and the nodes FG1 and FG2 stops and becomes constant at “V _D1 −Vth” which is lower than V _D1 by Vth.

That is, V _{D1 applied} to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 becomes “V _D1 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops.

Next, a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described. Incidentally, illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V _D2.

In the write operation 2, after the wiring 4001 is set to V _D2 and the wiring 4003 is set to the ground potential, the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level. The transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases. When the potential of the node FG2 rises and Vgs becomes Vth of the transistor 4100 in the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the increase in the potentials of the wirings 4003 and FG2 stops and becomes constant at “V _D2 −Vth”, which is lower than V _D2 by Vth.

That is, V _{D2 applied} to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases. When the potential of the node FG2 becomes “V _D2 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops. At this time, the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V _D1 −Vth” written in the writing operation 1 is held.

In the semiconductor device illustrated in FIG. 57, after data voltages are written in a plurality of data holding portions, the wiring 4009 is set to a high level to increase the potentials of the nodes FG1 and FG2. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.

By the data voltage writing operation to the nodes FG1 and FG2 described above, the data voltages can be held in the plurality of data holding units. Note that although “V _D1 −Vth” and “V _D2 −Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V _D1 −Vth” and “V _D2 −Vth” can be taken.

Next, an operation of reading information from the semiconductor device illustrated in FIG. 57 is described.

First, a data voltage read operation (hereinafter referred to as a read operation 1) to a data holding portion connected to the node FG2 will be described.

In the reading operation 1, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V _D2 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V _D2 ” that is a value larger by Vth than the potential “V _D2 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2. The read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.

In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V _D2 ”. In the transistor 4100, Vgs between “V _D2 −Vth” of the node FG2 becomes Vth, so that the current stops. Then, “V _D2 ” written in the writing operation 2 is read out to the wiring 4003.

When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V _D2 −Vth” of the node FG2.

Next, the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2. Here, the wirings 4001 and 4003 are set to a low level. The wiring 4006 is set to a high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to a low level. When the transistor 4200 is turned on, the charge of the node FG1 is distributed to and from the node FG2.

Here, the potential after the charge distribution is lowered from the written potential “V _D1 −Vth”. Therefore, the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500. Alternatively, the potential “V _D1 −Vth” written to the node FG1 is preferably higher than the potential “V _D2 −Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.

Next, a data voltage read operation (hereinafter referred to as read operation 2) to the data holding portion connected to the node FG1 will be described.

In the reading operation 2, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a high level at the time of precharging and then set to a low level. By setting the wiring 4009 to a low level, the node FG2 in an electrically floating state is set to a potential “V _D1 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V _D1 ” that is a value larger by Vth than the potential “V _D1 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1. The read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.

In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V _D1 ”. In the transistor 4100, the current stops because Vgs between the node FG2 and “V _D1 −Vth” becomes Vth. Then, “V _D1 ” written in the writing operation 1 is read out to the wiring 4003.

The data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in each of the nodes FG1 and FG2. In FIG. 57, the first layer 4021 to the third layer 4023 are used. However, by forming additional layers, the storage capacity can be increased without increasing the area of the semiconductor device. .

Note that the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V _D1 −Vth” or “V _D2 −Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.

<Storage device 4>
The semiconductor device illustrated in FIG. 56C is different from the semiconductor device illustrated in FIG. 57A in that the transistor 3500 and the sixth wiring 3006 are provided. In this case also, data can be written and held in the same manner as the semiconductor device shown in FIG. The transistor 3500 may be a transistor similar to the transistor 3200 described above.

The sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of the source and the drain of the transistor 3500 is electrically connected to the drain of the transistor 3200, and the other of the source and the drain of the transistor 3500 is the third It is electrically connected to the wiring 3003.
<Structure 1 of Semiconductor Device>
FIG. 58 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 58 includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are provided above the transistor 3200. Note that although an example in which the transistor illustrated in FIG. 2 is used as the transistor 3300 is described, the semiconductor device according to one embodiment of the present invention is not limited to this. Therefore, the above description of the transistor is referred to as appropriate.

The semiconductor device illustrated in FIG. 58 illustrates the case where the transistor 3200 is a Fin type. By setting the transistor 3200 to a Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 3200 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 3200 can be improved. The transistor 3200 is a transistor using the semiconductor substrate 450. The transistor 3200 includes a region 474a in the semiconductor substrate 450, a region 474b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

In the transistor 3200, the region 474a and the region 474b function as a source region and a drain region. The insulator 462 functions as a gate insulator. The conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 474a and the region 474b can be controlled by a potential applied to the conductor 454.

As the semiconductor substrate 450, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.

As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 3200. Alternatively, the semiconductor substrate 450 may be i-type.

The upper surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, the on-state characteristics of the transistor 3200 can be improved.

The region 474a and the region 474b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 3200 constitutes a p-channel transistor.

Although the case where the transistor 3200 is a p-channel transistor has been described, the transistor 3200 may be an n-channel transistor.

Note that the transistor 3200 is separated from an adjacent transistor by the region 460 or the like. The region 460 is a region having an insulating property.

58 includes an insulator 464, an insulator 466, an insulator 468, an insulator 470, an insulator 472, an insulator 475, an insulator 402, an insulator 410, and an insulator. 408, an insulator 428, an insulator 465, an insulator 467, an insulator 469, an insulator 498, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, and a conductor 478b, a conductor 478c, a conductor 476a, a conductor 476b, a conductor 476c, a conductor 479a, a conductor 479b, a conductor 479c, a conductor 477a, a conductor 477b, and a conductor 477c, a conductor 484a, a conductor 484b, a conductor 484c, a conductor 484d, a conductor 483a, a conductor 483b, a conductor 483c, a conductor 483d, a conductor, A conductor 483e, a conductor 483f, a conductor 485a, a conductor 485b, a conductor 485c, a conductor 485d, a conductor 487a, a conductor 487b, a conductor 487c, a conductor 488a, and a conductor Body 488b, conductor 488c, conductor 490a, conductor 490b, conductor 489a, conductor 489b, conductor 491a, conductor 491b, conductor 491c, conductor 492a, conductor A body 492b, a conductor 492c, a conductor 494, a conductor 496, an insulator 406a, a semiconductor 406b, and an insulator 406c are included.

The insulator 464 is provided over the transistor 3200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 470 is provided over the insulator 468. The insulator 472 is provided over the insulator 470. The insulator 475 is disposed over the insulator 472. The transistor 3300 is provided over the insulator 475. The insulator 408 is provided over the transistor 3300. The insulator 428 is provided over the insulator 408. Further, the insulator 465 is disposed over the insulator 428. In addition, the capacitor 3400 is provided over the insulator 465. The insulator 469 is provided over the capacitor 3400.

The insulator 464 includes an opening reaching the region 474a, an opening reaching the region 474b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.

The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.

The insulator 468 includes an opening reaching the conductor 478a, an opening reaching the conductor 478b, and an opening reaching the conductor 478c. In addition, a conductor 476a, a conductor 476b, or a conductor 476c is embedded in each opening.

Further, over the insulator 468, a conductor 479a in contact with the conductor 476a, a conductor 479b in contact with the conductor 476b, and a conductor 479c in contact with the conductor 476c are provided. The insulator 472 includes an opening reaching the conductor 479a through the insulator 470, an opening reaching the conductor 479b through the insulator 470, and an opening reaching the conductor 479c through the insulator 470. Have. In addition, conductors 477a, 477b, or 477c are embedded in the openings, respectively.

The insulator 475 includes an opening overlapping with the channel formation region of the transistor 3300, an opening reaching the conductor 477a, an opening reaching the conductor 477b, and an opening reaching the conductor 477c. In addition, a conductor 484d, a conductor 484a, a conductor 484b, or a conductor 484c is embedded in each opening.

The conductor 484d may function as a bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 484d. Alternatively, for example, the conductor 484d and the top gate electrode of the transistor 3300 may be electrically connected. Thus, the on-state current of the transistor 3300 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.

The insulator 402 includes an opening reaching the conductor 484a and an opening reaching the conductor 484c.

The insulator 428 includes three openings reaching the conductor 484a through the insulator 408, the insulator 410, and the insulator 402, and the source electrode or the drain electrode of the transistor 3300 through the insulator 408 and the insulator 410. And two openings reaching one of the conductors, and an opening reaching the conductor of the gate electrode of the transistor 3300 through the insulator 408. In addition, a conductor 483a, a conductor 483b, a conductor 483c, a conductor 483e, a conductor 483f, or a conductor 483d are embedded in the openings.

Further, over the insulator 428, a conductor 485a in contact with the conductors 483a and 483e, a conductor 485b in contact with the conductor 483b, a conductor 485c in contact with the conductor 483c and the conductor 483f, and a conductor in contact with the conductor 483d And a body 485d. The insulator 465 includes an opening reaching the conductor 485a, an opening reaching the conductor 485b, and an opening reaching the conductor 485c. In addition, a conductor 487a, a conductor 487b, or a conductor 487c is embedded in each opening.

Further, over the insulator 465, a conductor 488a in contact with the conductor 487a, a conductor 488b in contact with the conductor 487b, and a conductor 488c in contact with the conductor 487c are provided. The insulator 467 includes an opening reaching the conductor 488a and an opening reaching the conductor 488b. In addition, a conductor 490a or a conductor 490b is embedded in each opening. In addition, the conductor 488c is in contact with the conductor 494 of one electrode of the capacitor 3400.

Further, over the insulator 467, a conductor 489a in contact with the conductor 490a and a conductor 489b in contact with the conductor 490b are provided. The insulator 469 includes an opening reaching the conductor 489a, an opening reaching the conductor 489b, and an opening reaching the conductor 496 which is the other electrode of the capacitor 3400. In addition, a conductor 491a, a conductor 491b, or a conductor 491c is embedded in each opening.

Further, over the insulator 469, a conductor 492a in contact with the conductor 491a, a conductor 492b in contact with the conductor 491b, and a conductor 492c in contact with the conductor 491c are provided.

Insulator 464, insulator 466, insulator 468, insulator 470, insulator 472, insulator 475, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulator 467, insulator Examples of the insulating material 469 and the insulator 498 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The body may be used in a single layer or a stack. In particular, as the insulator 498, for example, an insulator formed by oxidizing the conductor 494 may be used. In addition, the insulator and metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon oxide, silicon nitride oxide, or silicon nitride It can also be a multilayer film. For example, as the insulator 401, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

Insulator 464, insulator 466, insulator 468, insulator 470, insulator 472, insulator 475, insulator 402, insulator 410, insulator 408, insulator 428, insulator 465, insulator 467, insulator One or more of 469 or the insulator 498 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 476c, conductor 479a, conductor 479b, conductor 479c, conductor Body 477a, conductor 477b, conductor 477c, conductor 484a, conductor 484b, conductor 484c, conductor 484d, conductor 483a, conductor 483b, conductor 483c, conductor 483d, conductor 483e, conductor 483f, conductor 485a, conductor 485b, conductor 485c, conductor 485d, conductor 487a, conductor 487b, conductor 487c, conductor 488a, conductor 488b, conductor 488c, conductor 490a, conductor 490b , Conductor 489a, conductor 489b, conductor 491a, conductor 491b, conductor Examples of the body 491c, the conductor 492a, the conductor 492b, the conductor 492c, the conductor 494, and the conductor 496 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, and nickel. A conductor containing one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Alternatively, a conductor containing tungsten and silicon may be used.

An oxide semiconductor is preferably used as the semiconductor 406b. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.

As the insulator 406a and the insulator 406c, an oxide including one or more elements other than oxygen included in the semiconductor 406b or two or more elements is preferably used. However, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.

The source or the drain of the transistor 3200 includes a conductor 480a, a conductor 478a, a conductor 476a, a conductor 479a, a conductor 477a, a conductor 484a, a conductor 483a, a conductor 485a, and a conductor 483e is electrically connected to a conductor which is one of a source electrode and a drain electrode of the transistor 3300. The conductor 454 that is a gate electrode of the transistor 3200 includes a conductor 480c, a conductor 478c, a conductor 476c, a conductor 479c, a conductor 477c, a conductor 484c, a conductor 483c, and a conductor 483c. It is electrically connected to a conductor which is the other of the source electrode and the drain electrode of the transistor 3300 through the body 485c and the conductor 483f.

The capacitor 3400 includes one of a source electrode and a drain electrode of the transistor 3300, a conductor 483c, a conductor 485c, a conductor 487c, and a conductor 488c, and one electrode of the capacitor 3400 A conductor 494 which is electrically connected, an insulator 498, and a conductor 496 which is the other electrode of the capacitor 3400 are included. Note that it is preferable that the capacitor 3400 be formed above or below the transistor 3300 because the size of the semiconductor device can be reduced.

Although an example of a semiconductor device including the transistor 3300 over the transistor 3200 and the capacitor 3400 over the transistor 3300 is described in this embodiment, one or more transistors including the same semiconductor as the transistor 3300 are included over the transistor 3200. It does not matter even if it has a configuration. Alternatively, the capacitor 3400 may be provided over the transistor 3200 and the transistor 3300 may be provided over the capacitor 3400. With such a structure, the degree of integration of the semiconductor device can be further increased (see FIG. 59).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 11)
In this embodiment, an example of an imaging device using a transistor or the like according to one embodiment of the present invention will be described.

<Imaging device>
The imaging device according to one embodiment of the present invention is described below.

FIG. 60A is a plan view illustrating an example of an imaging device 600 according to one embodiment of the present invention. The imaging device 600 includes a pixel portion 610, a peripheral circuit 660 for driving the pixel portion 610, a peripheral circuit 670, a peripheral circuit 680, and a peripheral circuit 690. The pixel portion 610 includes a plurality of pixels 611 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 660, the peripheral circuit 670, the peripheral circuit 680, and the peripheral circuit 690 are each connected to the plurality of pixels 611 and have a function of supplying signals for driving the plurality of pixels 611. Note that in this specification and the like, the peripheral circuit 660, the peripheral circuit 670, the peripheral circuit 680, the peripheral circuit 690, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases. For example, the peripheral circuit 660 can be said to be part of the peripheral circuit.

In addition, the imaging apparatus 600 preferably includes a light source 691. The light source 691 can emit detection light P1.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. The peripheral circuit may be formed over a substrate over which the pixel portion 610 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 660, the peripheral circuit 670, the peripheral circuit 680, and the peripheral circuit 690 may be omitted as the peripheral circuit.

In addition, as illustrated in FIG. 60B, in the pixel portion 610 included in the imaging device 600, the pixel 611 may be arranged to be inclined. By arranging the pixels 611 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 600 can be further improved.

<Pixel Configuration Example 1>
A single pixel 611 included in the imaging device 600 is configured by a plurality of subpixels 612, and a color image display is realized by combining each subpixel 612 with a filter (color filter) that transmits light in a specific wavelength range. Information can be acquired.

FIG. 61A is a plan view illustrating an example of a pixel 611 for obtaining a color image. A pixel 611 illustrated in FIG. 61A includes a subpixel 612 (hereinafter also referred to as “subpixel 612R”) provided with a color filter that transmits light in the red (R) wavelength region, and a green (G) wavelength. A subpixel 612 (hereinafter also referred to as “subpixel 612G”) provided with a color filter that transmits light in the region and a subpixel 612 (hereinafter referred to as color filter that transmits light in the blue (B) wavelength region). , Also referred to as “sub-pixel 612B”. The sub-pixel 612 can function as a photosensor.

The sub-pixel 612 (the sub-pixel 612R, the sub-pixel 612G, and the sub-pixel 612B) is electrically connected to the wiring 631, the wiring 647, the wiring 648, the wiring 649, and the wiring 650. In addition, the subpixel 612R, the subpixel 612G, and the subpixel 612B are each connected to an independent wiring 653. In this specification and the like, for example, the wiring 648 and the wiring 649 connected to the pixel 611 in the n-th row are referred to as a wiring 648 [n] and a wiring 649 [n], respectively. For example, the wiring 653 connected to the pixel 611 in the m-th column is referred to as a wiring 653 [m]. 60A, the wiring 653 connected to the subpixel 612R included in the pixel 611 in the m-th column is the wiring 653 [m] R, the wiring 653 connected to the subpixel 612G is the wiring 653 [m] G, and A wiring 653 connected to the subpixel 612B is described as a wiring 653 [m] B. The sub-pixel 612 is electrically connected to the peripheral circuit through the wiring.

In addition, the imaging device 600 has a configuration in which the sub-pixels 612 provided with color filters that transmit light in the same wavelength region of the adjacent pixels 611 are electrically connected via a switch. FIG. 61B illustrates a subpixel 612 included in a pixel 611 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q), and is adjacent to the pixel 611. An example of connection of sub-pixels 612 included in pixels 611 arranged in n + 1 rows and m columns is shown. In FIG. 61B, a subpixel 612R arranged in n rows and m columns and a subpixel 612R arranged in n + 1 rows and m columns are connected through a switch 601. Further, the sub-pixel 612G arranged in n rows and m columns and the sub-pixel 612G arranged in n + 1 rows and m columns are connected via a switch 602. In addition, a subpixel 612B arranged in n rows and m columns and a subpixel 612B arranged in n + 1 rows and m columns are connected via a switch 603.

Note that the color filter used for the sub-pixel 612 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full-color image can be acquired by providing the sub-pixel 612 that detects light of three different wavelength ranges in one pixel 611.

Alternatively, in addition to the sub-pixel 612 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 611 including the sub-pixel 612 may be used. Alternatively, in addition to the sub-pixel 612 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 611 including the sub-pixel 612 may be used. By providing the sub-pixel 612 for detecting light of four different wavelength ranges in one pixel 611, the color reproducibility of the acquired image can be further improved.

Further, for example, in FIG. 61A, a pixel number ratio (or a sub-pixel 612 that detects a red wavelength range, a sub-pixel 612 that detects a green wavelength range, and a sub-pixel 612 that detects a blue wavelength range) (or (Light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

Note that the number of subpixels 612 provided in the pixel 611 may be one, but two or more are preferable. For example, by providing two or more subpixels 612 that detect the same wavelength region, redundancy can be increased and the reliability of the imaging apparatus 600 can be increased.

In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, an imaging device 600 that detects infrared light can be realized.

Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

In addition to the filter described above, a lens may be provided in the pixel 611. Here, an arrangement example of the pixel 611, the filter 654, and the lens 655 will be described with reference to the cross-sectional view of FIG. By providing the lens 655, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 62A, the light 656 is transmitted to the photoelectric conversion element 620 through the lens 655 formed in the pixel 611, the filter 654 (filter 654R, filter 654G, and filter 654B), the pixel circuit 630, and the like. It can be set as the structure made to enter.

Note that part of the light 656 indicated by the arrow may be blocked by part of the wiring 657 as shown in the region surrounded by the alternate long and short dash line. Therefore, a structure in which a lens 655 and a filter 654 are provided on the photoelectric conversion element 620 side so that the photoelectric conversion element 620 efficiently receives the light 656 as illustrated in FIG. 62B is preferable. By making the light 656 enter the photoelectric conversion element 620 from the photoelectric conversion element 620 side, the imaging device 600 with high detection sensitivity can be provided.

As the photoelectric conversion element 620 illustrated in FIG. 62, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

Alternatively, the photoelectric conversion element 620 may be formed using a substance having a function of generating charges by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 620, the photoelectric conversion element 620 having a light absorption coefficient over a wide wavelength range such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.

Here, one pixel 611 included in the imaging device 600 may include a sub-pixel 612 including a first filter in addition to the sub-pixel 612 illustrated in FIG.

<Pixel Configuration Example 2>
Hereinafter, an example in which a pixel is formed using a transistor including silicon and a transistor including an oxide semiconductor will be described. As each transistor, a transistor similar to that described in the above embodiment can be used.

FIG. 63 is a cross-sectional view of elements constituting the imaging device. 63 includes a transistor 351 using silicon provided over a silicon substrate 300, a transistor 352 and a transistor 353 using oxide semiconductor layers stacked over the transistor 351, and the silicon substrate 300. Photodiode 360. Each transistor and photodiode 360 has electrical connection with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.

The imaging device is provided in contact with the layer 310 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371. A layer 330 including the transistor 353, and a layer 340 provided in contact with the layer 330 and including a wiring 372 and a wiring 373.

Note that in the example of the cross-sectional view of FIG. 63, the silicon substrate 300 has a light receiving surface of the photodiode 360 on the surface opposite to the surface on which the transistor 351 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.

Note that in the case where a pixel is formed using only a transistor including an oxide semiconductor, the layer 310 may be a layer including a transistor including an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.

Note that the silicon substrate 300 may be an SOI substrate. Further, instead of the silicon substrate 300, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor substrate can be used.

Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistor 352 and the transistor 353. However, the position of the insulator 380 is not limited. An insulator 379 is provided below the insulator 380, and an insulator 381 is provided on the insulator 380.

Conductors 390 a to 390 e are provided in openings provided in the insulators 379 to 380. The conductor 390a, the conductor 390b, and the conductor 390e function as a plug and a wiring. In addition, the conductor 390c functions as a back gate of the transistor 353. The conductor 390d functions as a back gate of the transistor 352.

Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 351 has an effect of terminating the dangling bond of silicon and improving the reliability of the transistor 351. On the other hand, hydrogen in the insulator provided in the vicinity of the transistor 352, the transistor 353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 352, the transistor 353, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 380, the reliability of the transistor 351 can be improved. Further, since diffusion of hydrogen from a lower layer than the insulator 380 to an upper layer than the insulator 380 can be suppressed, reliability of the transistor 352, the transistor 353, and the like can be improved. Further, since the conductor 390a, the conductor 390b, and the conductor 390e are formed, hydrogen can be prevented from diffusing into an upper layer through the via hole formed in the insulator 380, so that the reliability of the transistor 352, the transistor 353, and the like can be reduced. Can be improved.

63, the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed so as to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

Further, a part or all of the imaging device may be curved. By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to reduce the size and weight of an electronic device using an imaging device. In addition, the quality of the captured image can be improved.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 12)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

<10-1. Display module>
A display module 8000 shown in FIG. 64 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, a battery, between the upper cover 8001 and the lower cover 8002. 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

The backlight 8007 has a light source 8008. Note that although FIG. 64 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may be omitted.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

<10-2. Electronic equipment>
FIGS. 65A to 65G illustrate electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared ), A microphone 9008, and the like.

The electronic devices illustrated in FIGS. 65A to 65G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 65A to 65G are not limited to these, and can have various functions. Although not illustrated in FIGS. 65A to 65G, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.

Details of the electronic devices illustrated in FIGS. 65A to 65G are described below.

FIG. 65A is a perspective view illustrating a television device 9100. FIG. The television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.

FIG. 65B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

FIG. 65C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

FIG. 65D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

65E, 65F, and 65G are perspective views showing a foldable portable information terminal 9201. FIG. FIG. 65E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 65F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other. FIG. 65G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

66A and 66B are perspective views of a display device having a plurality of display panels. FIG. 66A is a perspective view of a form in which a plurality of display panels are wound, and FIG. 66B is a perspective view of a state in which the plurality of display panels are developed.

A display device 9500 illustrated in FIGS. 66A and 66B includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512. The plurality of display panels 9501 each include a display region 9502 and a region 9503 having a light-transmitting property.

In addition, the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, a light-transmitting region 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, a large-screen display device can be obtained. In addition, since the display panel 9501 can be taken up depending on the use state, a display device with excellent versatility can be obtained.

66A and 66B show a state in which the display area 9502 is separated by the adjacent display panel 9501, but the present invention is not limited to this. For example, the display area 9502 of the adjacent display panel 9501 is shown. The display area 9502 may be a continuous display area by overlapping them with no gap.

The electronic device described in this embodiment includes a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this embodiment, a sample in which a silicon oxynitride film is formed over an oxide semiconductor film under the deposition conditions according to the present invention is manufactured, and TDS (Thermal Depth-Ion Spectrometry) analysis and sheet resistance value of the oxide semiconductor film are performed. Was measured.

For the preparation of the sample, first, an In—Ga—Zn oxide film was formed to a thickness of 40 nm on a glass substrate by a sputtering method. Next, a silicon oxynitride film was formed over the In—Ga—Zn oxide by a CVD method. For samples 1A, 1B, and 1C, silicon oxynitride films were formed under conventional film formation conditions. That is, using a mixed gas of SiH 4 gas (flow rate 20 sccm) and N 2 O gas (flow rate 3000 sccm), the pressure was 200 Pa, the high frequency power was 100 W, the substrate temperature was 350 ° C., and the film thickness was 50 nm.

Samples 2A, 2B, 2C and Sample 3 were formed using silicon oxynitride films under the deposition conditions according to the present invention. That is, using a mixed gas of SiH ₄ gas (flow rate 6 sccm) and N ₂ O gas (flow rate 18000 sccm), the film forming pressure is 250 Pa, the high frequency power is 500 W, the substrate temperature is 350 ° C., and the samples 2A, 2B, and 2C are 50 nm. The sample 3 was formed with a film thickness of 100 nm. In this way, Samples 1A, 1B, 1C, 2A, 2B, 2C and 3 were produced.

Samples 1A, 2A and 3 were subjected to TDS analysis. In Samples 1B and 2B, the silicon oxynitride film was removed by wet etching, and then the sheet resistance value of the In—Ga—Zn oxide was measured using a sheet resistance measuring instrument. Samples 1C and 2C were subjected to a heat treatment for 1 hour at a temperature of 350 ° C. in a nitrogen atmosphere, and then the silicon oxynitride film was removed by a wet etching method. -The sheet resistance value of Zn oxide was measured.

67A, 67B, and 67C are graphs showing the results of TDS analysis of samples 1A, 2A, and 3. FIG. 67A, 67B, and 67C show the temperature dependence of the release amount of the mass-to-charge ratio M / z = 32 corresponding to oxygen molecules. As TDS analysis conditions, the temperature of the heating heater was set to 50 ° C. at the start of measurement, 1000 ° C. at the end of the measurement, and the heating rate was set to 32 ° C./min. The surface temperature of the sample film was about 50 ° C. at the start of measurement and about 540 ° C. at the end of measurement. The pressure in the sample chamber at the start of analysis was 1.2 × 10 ⁻⁷ Pa.

FIG. 67A shows a TDS analysis result of Sample 1A in which a silicon oxynitride film is formed with a film thickness of 50 nm under conventional film formation conditions, and the mass-to-charge ratio M / z = 32 corresponding to oxygen molecules is shown. Little release peak was seen. A small peak is observed around the film surface temperature of 150 ° C. of the sample, which seems to be due to adsorbed water on the sample surface. FIG. 67B shows a TDS analysis result of Sample 2A in which a silicon oxynitride film is formed with a film thickness of 50 nm under the film formation conditions according to the present invention. A slight emission peak corresponding to a mass-to-charge ratio M / z = 32 was observed. FIG. 67C shows a TDS analysis result of Sample 3 in which a silicon oxynitride film is formed to a thickness of 100 nm under the film formation conditions according to the present invention. An emission peak with a mass-to-charge ratio M / z = 32 corresponding to oxygen molecules was observed.

From these results, since the silicon oxynitride film formed under the conventional film formation conditions hardly shows an emission peak with a mass-to-charge ratio M / z = 32 corresponding to oxygen molecules, The silicon oxynitride film formed in step 1 does not contain excess oxygen, but the silicon oxynitride film formed under the film formation conditions according to the present invention was found to be a silicon oxynitride film containing excess oxygen.

Next, FIG. 68 summarizes the measurement results of the sheet resistance value of the In—Ga—Zn oxide. The measurement result of each sheet resistance value is described.

Sample 1B is a sheet resistance value of In—Ga—Zn oxide when a silicon oxynitride film is formed over an In—Ga—Zn oxide under a conventional film formation condition. Sample 1C is an In—Ga— A sheet of In—Ga—Zn oxide after a silicon oxynitride film having a conventional film formation condition is formed on the Zn oxide and then heat-treated at a temperature of 350 ° C. for 1 hour in a nitrogen atmosphere. Resistance value.

Sample 2B is a sheet resistance value of the In—Ga—Zn oxide when a silicon oxynitride film is formed over the In—Ga—Zn oxide under the film formation conditions according to the present invention. After forming a silicon oxynitride film on the In—Ga—Zn oxide under the film formation conditions according to the present invention, heat treatment was performed at a temperature of 350 ° C. for 1 hour in a nitrogen atmosphere. -Sheet resistance value of Zn oxide.

The sheet resistance value of Sample 1B and the sheet resistance value of 1C were about 4.2 × 10 ³ [Ω / □], and Sample 1C had almost the same value. On the other hand, the sheet resistance value of Sample 2B was about 3.6 × 10 ⁶ [Ω / □], which was higher than the sheet resistance value of Sample 1B. Further, the sheet resistance value of Sample 2C changed to a higher resistance value of about 9.0 × 10 ⁹ [Ω / □].

For these reasons, the silicon oxynitride film formed under the conventional film formation conditions contains almost no excess oxygen. Therefore, due to plasma damage at the time of silicon oxynitride film formation, the In—Ga—Zn oxide It is considered that carriers were generated due to the defects generated in, and the sheet resistance value of the In—Ga—Zn oxide was lowered. In addition, since the silicon oxynitride film formed under the conventional film formation conditions does not contain excess oxygen, the silicon oxynitride film can be removed from the silicon oxynitride film even if heat treatment is performed at 350 ° C. for 1 hour in a nitrogen atmosphere. Since oxygen does not diffuse into the —Ga—Zn oxide, defects in the In—Ga—Zn oxide are not repaired, and the sheet resistance value seems to remain low.

On the other hand, since the silicon oxynitride film formed under the film formation conditions according to the present invention contains excess oxygen, the plasma damage during the film formation is reduced, so that the In—Ga—Zn oxide of the sample 2B is obtained. It is considered that the sheet resistance value was higher than that of the sample 1B. Further, by performing heat treatment at 350 ° C. for 1 hour in a nitrogen atmosphere, excess oxygen contained in the silicon oxynitride film diffuses into the In—Ga—Zn oxide, and the In—Ga—Zn oxide It seems that the sheet resistance value of Sample 2C was increased because the internal defect was repaired. From this, it was found that the film formation conditions according to the present invention have a function of supplying excess oxygen to the In—Ga—Zn oxide in contact with plasma. Further, it was found that the silicon oxynitride film formed under the film forming conditions according to the present invention has excess oxygen.

In this example, a sample in which a silicon oxynitride film formed under a film formation condition according to the present invention was formed over a silicon oxynitride film formed under a conventional film formation condition was manufactured, and TDS analysis was performed.

Sample 1 was manufactured by forming a first silicon oxynitride film with a thickness of 50 nm on a glass substrate by a CVD method. Next, a second silicon oxynitride film was formed over the first silicon oxynitride film by a CVD method. The first silicon oxynitride film is a silicon oxynitride film formed under conventional film formation conditions. The second silicon oxynitride film is a silicon oxynitride film formed under the film formation conditions according to the present invention. Sample 2 was a comparative sample in which a second silicon oxynitride film was formed on a glass substrate without forming the first silicon oxynitride film. Example 1 is referred to for the conditions for forming the first silicon oxynitride film and the conditions for forming the second silicon oxynitride film.

69 (A) and 69 (B) show the TDS analysis results. The TDS analysis was performed under the same analysis conditions as the TDS analysis performed in Example 1. FIG. 69A shows the temperature dependence of the released amount of the mass-to-charge ratio M / z = 32 corresponding to the oxygen molecule of sample 1, and FIG. 69B shows the mass-to-charge ratio M corresponding to the oxygen molecule of sample 2. The temperature dependence of the discharge amount of / z = 32 is shown.

69 (A) and 69 (B), the sample 1 having the first silicon oxynitride film on the glass substrate has a mass-to-charge ratio M / corresponding to oxygen molecules at a film surface temperature of 370 ° C. of the sample. An emission peak with z = 32 is seen, but in sample 2 without the first silicon oxynitride film on the glass substrate, an emission peak with a mass-to-charge ratio M / z = 32 corresponding to oxygen molecules is hardly seen. .

From the above results, the film formation conditions according to the present invention have no function of supplying oxygen to the glass substrate in contact with plasma during film formation, but supply oxygen to the silicon oxynitride film in contact with plasma during film formation. It was found that it has a function to do.

In this example, a transistor having a second gate insulating film formed under the film formation conditions according to the present invention was manufactured, and transistor characteristics were measured.

The transistor was manufactured by first forming a first titanium film with a thickness of 10 nm on a glass substrate by a sputtering method. Next, a first copper film having a thickness of 100 nm was formed on the first titanium film.

Next, a first resist mask was formed on the first copper film using a lithography method, and unnecessary portions of the first copper film were wet-etched using the first resist mask as an etching mask. For the wet etching, a mixed solution of hydrogen peroxide and inorganic acid was used. Next, the titanium film was dry-etched using the first resist mask and the first copper film as an etching mask. Thus, the first gate electrode having the first copper film and the first titanium film was formed.

Next, a first silicon nitride film was formed to a thickness of 50 nm on the first gate electrode and the glass substrate by a CVD method. Next, a second silicon nitride film having a thickness of 300 nm was formed over the first silicon nitride film by a CVD method. Next, a third silicon nitride film was formed to a thickness of 50 nm on the second silicon nitride film by a CVD method. Next, a first silicon oxynitride film was formed to a thickness of 20 nm over the third silicon nitride film. The first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the first silicon oxynitride film were continuously formed. Thus, a first gate insulating film having a first silicon nitride film, a second silicon nitride film, a third silicon nitride film, and a first silicon oxynitride film was formed.

Next, a first In—Ga—Zn oxide was formed to a thickness of 40 nm over the first gate insulating film by a sputtering method. Next, unnecessary portions of the In—Ga—Zn oxide were etched by a lithography method, so that an oxide semiconductor film including a first In—Ga—Zn oxide was formed.

Next, a second silicon oxynitride film was formed to a thickness of 50 nm on the first gate insulating film and the semiconductor film by a CVD method. Sample 2 was formed with a film thickness of 20 nm. As the film formation conditions, the film formation conditions according to the present invention were used. Using a plasma CVD apparatus, a film was formed under conditions of SiH ₄ gas (flow rate 6 sccm), N ₂ O gas (flow rate 18000 sccm), substrate temperature (350 ° C.), and high-frequency power (500 W).

Next, a second resist mask is formed over the second silicon oxynitride film by a lithography method, and a part of the second silicon oxynitride film and the first resist mask are used as an etching mask. A part of the gate insulating film was etched to form an opening reaching the first gate electrode. The opening was formed using a dry etching method.

Next, a second In—Ga—Zn oxide was formed to a thickness of 100 nm over the second gate insulating film by a sputtering method so as to cover the opening. Next, a third resist mask is formed using a lithography method, and part of the second In—Ga—Zn oxide and the second oxidation are formed by a dry etching method using the third resist mask as an etching mask. A part of the silicon nitride film was etched to form a second gate electrode having a second In—Ga—Zn oxide and a second gate insulating film having a second silicon oxynitride film.

Next, after removing the third resist mask, plasma treatment is performed on the first gate insulating film, the oxide semiconductor film, and the second gate electrode with a mixed gas of argon and nitrogen using a CVD apparatus. Went. Next, a fourth silicon nitride film was formed to a thickness of 100 nm by a CVD method. The plasma treatment with a mixed gas of argon and nitrogen and the formation of the silicon nitride film were performed by continuous treatment.

Next, a third silicon oxide film having a thickness of 300 nm was formed over the fourth silicon nitride film by a CVD method.

Next, a fourth resist mask is formed over the third silicon oxide film by a lithography method, and the third silicon oxynitride film and the fourth silicon nitride film are formed using the fourth resist mask as an etching mask. An opening reaching the oxide semiconductor film was formed by etching part of the oxide semiconductor film. The opening was formed using a dry etching method.

Next, a second titanium film was formed to a thickness of 10 nm over the third silicon oxynitride film by a sputtering method so as to cover the opening. Next, a second copper film was formed on the second titanium film by sputtering.

Next, a fifth resist mask was formed on the second copper film using a lithography method, and unnecessary portions of the second copper film were wet etched using the fifth resist mask as an etching mask. For the wet etching, a mixed solution of hydrogen peroxide and inorganic acid was used. Next, the second titanium film was dry-etched using the fifth resist mask and the second copper film as an etching mask. As described above, the source electrode or the drain electrode having the second copper film and the second titanium film was formed.

Next, a photosensitive acrylic resin was formed to a thickness of 1.5 μm on the source or drain electrode and the third silicon oxynitride film by a coating method. Next, an unnecessary portion of the acrylic resin was removed using a lithography method. Next, the acrylic resin was baked by heat-processing using a heating apparatus, and the protective film which has an acrylic resin was formed.

As described above, a transistor including the second gate insulating film formed under the deposition conditions according to the present invention was manufactured. The thickness of the second gate insulating film of Sample 1 is 50 nm, and the thickness of the second gate insulating film of Sample 2 is 20 nm.

Next, the transistor characteristics of Sample 1 and Sample 2 were measured. First, drain current-gate voltage (Id-Vg) characteristics were measured. The measurement conditions were that the source electrode voltage (Vs) was fixed at 0V, and the drain electrode voltage (Vd) was 0.1V and 10V, respectively. The change in drain current (Id) was measured as it increased to 20V in steps of 0.25V. Sample 2 was measured for a change in drain current (Id) when it was raised from -10 V to 10 V in steps of 0.25 V.

For the Id-Vg characteristics, the channel width (W) was fixed at 50 μm, and the transistors with channel lengths (L) of 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm were measured.

70 to 73 show Id-Vg characteristics. The Id-Vg characteristics of Sample 1 (the thickness of the second gate insulating film is 50 nm) of L = 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm are shown in FIGS. B), shown in FIGS. 71 (A) and 71 (B). In addition, the Id-Vg characteristics of L = 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm of Sample 2 (the thickness of the second gate insulating film is 20 nm) are shown in FIGS. 72 (B), FIG. 73 (A) and FIG. 73 (B). Each transistor showed good Id-Vg characteristics.

Next, Id-Vd characteristics of a transistor with W = 3.0 μm and L = 3.0 μm were measured. The measurement conditions are as follows: Vs is fixed at 0V, Vg is fixed at a voltage at which Id is 100 nA / μm when 5V is applied to Vd, and Vd is increased from 0V to 12V in 0.25V steps. Changes were measured. The Vg of sample 1 (the thickness of the second gate insulating film is 50 nm) is 4.05 V, and the Vg of the sample 2 (the thickness of the second gate insulating film is 20 nm) is 3.30 V.

74 (A) and 74 (B) show the Id-Vd characteristics of each transistor. In both Sample 1 and Sample 2, the fluctuation amount of Id at Vd = 3 V or more is small, and the Id-Vd saturation characteristics are excellent Transistor characteristics could be obtained.

30 element layer 40 element layer 50 element layer 100 transistor 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 100F transistor 100G transistor 100H transistor 100J transistor 100K transistor 102 substrate 104 insulating film 106 conductive film 107 oxide semiconductor film 108 oxide semiconductor film 108_1 Oxide semiconductor film 108_2 oxide semiconductor film 108_3 oxide semiconductor film 108d drain region 108f region 108i channel region 108s source region 110 insulating film 110_0 insulating film 110A transistor 114 conductive film 114_0 conductive film 116 insulating film 118 insulating film 120 conductive film 120a conductive Film 120b Conductive film 122 Insulating film 140 Mask 141a Opening 141 b Opening 143 Opening 145 Impurity element 201 Transistor 203 Transistor 207a Liquid crystal element 207b Liquid crystal element 211 Substrate 212 Insulating film 213 Insulating film 215 Insulating film 219 Insulating film 223 Oxide semiconductor film 241 Colored film 243 Light shielding film 245 Insulating film 247 Spacer 249 Liquid crystal 250 Pa Film formation pressure 251 Conductive film 252 Conductive film 253 Insulating film 255 Conductive film 261 Substrate 300 Silicon substrate 300A Transistor 300B Transistor 300C Transistor 300D Transistor 300E Transistor 300F Transistor 302 Substrate 304 Conductive film 306 Insulating film 307 Insulating film 308 Oxide semiconductor film 308_1 Oxide semiconductor film 308_2 Oxide semiconductor film 308_3 Oxide semiconductor film 310 Layer 312a Conductive film 312b Conductive film 14 insulating film 316 insulating film 318 insulating film 320 layer 320a conductive film 320b conductive film 330 layer 340 layer 341a opening 341b opening 342a opening 342b opening 342c opening 351 transistor 352 transistor 353 transistor 360 photodiode 361 anode 363 low resistance Region 370 plug 371 wiring 372 wiring 373 wiring 379 insulator 380 insulator 381 insulator 390a conductor 390b conductor 390c conductor 390d conductor 390e conductor 401 insulator 402 insulator 406a insulator 406b semiconductor 406c insulator 408 insulator 410 insulator 428 insulator 450 semiconductor substrate 454 conductor 460 region 462 insulator 464 insulator 465 insulator 466 insulator 467 insulator 468 insulator 469 insulation 470 insulator 472 insulator 474a region 474b region 475 insulator 476a conductor 476b conductor 476c conductor 477a conductor 477b conductor 477c conductor 478a conductor 478b conductor 478c conductor 479a conductor 479c conductor 479c conductor 479c conductor 479c Conductor 480b Conductor 480c Conductor 483a Conductor 483b Conductor 483c Conductor 483c Conductor 483d Conductor 483e Conductor 483f Conductor 484a Conductor 484b Conductor 484c Conductor 484d Conductor 485a Conductor 485b Conductor 485c Conductor 485c Conductor 485c Conductor 485c 487a conductor 487b conductor 487c conductor 488a conductor 488b conductor 488c conductor 489a conductor 489b conductor 490a conductor 490b conductor 491a conductor 491b conductor 91c conductor 492a conductor 492b conductor 492c conductor 494 conductor 496 conductor 498 insulator 501 pixel circuit 502 pixel portion 504 driver circuit portion 504a gate driver 504b source driver 506 protection circuit 507 terminal portion 550 transistor 552 transistor 554 transistor 560 Capacitor 562 Capacitor 570 Liquid crystal element 572 Light emitting element 600 Imaging device 601 Switch 602 Switch 603 Switch 610 Pixel unit 611 Pixel 612 Subpixel 612B Subpixel 612G Subpixel 612R Subpixel 620 Photoelectric conversion element 630 Pixel circuit 631 Wiring 647 Wiring 648 Wiring 649 Wiring 650 Wiring 653 Wiring 654 Filter 654B Filter 654G Filter 654R Filter 655 Lens 656 Light 657 Wiring 660 Side circuit 670 peripheral circuit 680 peripheral circuit 690 peripheral circuits 691 light source 700 display device 701 substrate 702 a pixel portion 704 source driver circuit portion 705 substrate 706 gate driver circuit unit 708 FPC terminal portion 710 signal line 711 wiring portion 712 sealing material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light emitting element 784 Conductive film 786 EL layer 788 Conductive film 790 Capacitor element 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 1280a p-type transistor 1280b n-type transistor 1280c n-type transistor 1281 Capacitance element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Trans Transistor 1353 transistor 1354 transistor 1354 transistor 1360 photoelectric conversion element 1401 signal 1402 signal 1403 signal 1404 signal 1405 signal 2100 transistor 3001 wiring 3002 wiring 3003 wiring 3004 wiring 3005 wiring 3006 wiring 3200 transistor 3300 transistor 3400 capacitor element 3500 transistor 4001 wiring 4003 wiring 4005 wiring 4006 wiring 4007 wiring 4008 wiring 4009 wiring 4021 layer 4022 layer 4023 layer 4100 transistor 4200 transistor 4300 transistor 4400 transistor 4500 capacitor element 4600 capacitor element 8000 display module 8001 upper cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Back light 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television apparatus 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal 9500 display device 9501 display panel 9502 display region 9503 region 9511 shaft portion 9512 bearing portion

Claims (12)

Forming an oxide semiconductor film over the first insulating film;
Forming a second insulating film on the oxide semiconductor film;
Forming a conductive film on the second insulating film;
Forming a gate electrode having the conductive film and a gate insulating film having the second insulating film by lithography using the conductive film and the second insulating film;
Implanting one or more ions of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a noble gas into the first region;
Forming a third insulating film on the first insulating film, on the semiconductor film and on the gate electrode;
The first region has a region where the first region and the gate electrode do not overlap each other,
The second insulating film is formed using a PECVD method,
A gas used for the PECVD method is silane and dinitrogen monoxide, and the flow rate of the dinitrogen monoxide is greater than 1000 times and less than 10,000 times with respect to the flow rate of the silane. Method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the rare gas is one or more of helium, neon, argon, krypton, or xenon. The method for manufacturing a semiconductor device according to claim 1, wherein the implantation is performed using a plasma treatment method, an ion doping method, or an ion implantation method. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the third insulating film is formed using a gas containing one or more of nitrogen, hydrogen, and fluorine. Forming a first conductive film on the substrate;
Forming a first insulating film on the substrate and on the first conductive film;
Forming an oxide semiconductor film over the first insulating film;
Forming a second insulating film on the oxide semiconductor film;
Forming a second conductive film on the second insulating film;
Forming a gate electrode having the second conductive film and a gate insulating film having the second insulating film by lithography using the second conductive film and the second insulating film;
Implanting one or more ions of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a rare gas into the first region using the gate electrode and the gate insulating film as a mask;
Forming a third insulating film on the first insulating film, on the semiconductor film and on the gate electrode;
The first region has a region where the first region and the gate electrode do not overlap each other,
The second insulating film is formed using a PECVD method,
A gas used for the PECVD method is silane and dinitrogen monoxide, and the flow rate of the dinitrogen monoxide is greater than 1000 times and less than 10,000 times with respect to the flow rate of the silane. Method. Forming a first conductive film on the substrate;
Forming a first insulating film on the substrate and on the first conductive film;
Forming an oxide semiconductor film over the first insulating film;
Forming a second insulating film on the oxide semiconductor film;
Forming an opening reaching the first conductive film by lithography using the second insulating film and the first insulating film;
Forming a second conductive film on the second insulating film;
Forming a gate electrode having the second conductive film and a gate insulating film having the second insulating film by lithography using the second conductive film and the second insulating film;
Implanting one or more ions of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, or a noble gas into the first region;
Forming a third insulating film on the first insulating film, on the semiconductor film and on the gate electrode;
The first region has a region where the first region and the gate electrode do not overlap each other,
The second insulating film is formed using a PECVD method,
A gas used for the PECVD method is silane and dinitrogen monoxide, and the flow rate of the dinitrogen monoxide is greater than 1000 times and less than 10,000 times with respect to the flow rate of the silane. Method. The method for manufacturing a semiconductor device according to claim 5, wherein the rare gas is one or more of helium, neon, argon, krypton, or xenon. The method for manufacturing a semiconductor device according to claim 5, wherein the implantation is performed using a plasma treatment method, an ion doping method, or an ion implantation method. The method for manufacturing a semiconductor device according to claim 5, wherein the third insulating film is formed using a gas containing one or more of nitrogen, hydrogen, and fluorine. A method of manufacturing a display device,
A method for manufacturing a display device, comprising: a semiconductor device manufactured using the method for manufacturing a semiconductor device according to any one of claims 1 to 9; and a display element. A manufacturing method of a display module,
The display module includes a display device and a touch sensor manufactured by using the display device manufacturing method according to claim 10. A method of manufacturing an electronic device,
A method for manufacturing an electronic device, comprising: the display module manufactured using the method for manufacturing a display module according to claim 11; and an operation key or a battery.