JPWO2016035818A1 - Magnetic structure, inductance element and manufacturing method thereof, substrate with built-in electrode and manufacturing method thereof, interposer, shield substrate and module - Google Patents

Abstract

The magnetic structure (2) includes a first magnetic layer (101), a first slit (SL1) that divides the first magnetic layer (101) into a plurality, a first slit (SL1), and a first magnetic layer (101). ), A first insulating layer (12) disposed on the first insulating layer (12), a second magnetic layer (10 2) disposed on the first insulating layer (12), and a second magnetic layer (10 2) which is divided into a plurality of parts And a slit (SL2). A magnetic structure capable of reducing magnetic resistance and eddy current loss and the above magnetic structure are applied to provide an inductance element with reduced AC resistance and excellent high frequency characteristics.

Description

  The present embodiment relates to a magnetic structure, an inductance element and a manufacturing method thereof, an electrode built-in substrate and a manufacturing method thereof, an interposer, a shield substrate, and a module.

  In recent mobile devices, thinning, lightening, energy saving, and long battery life are required. For this purpose, it is particularly necessary to make the power supply circuit thinner, lighter, more energy efficient, and to extend the battery life. Among the components constituting the power supply circuit, an inductance element can be cited as one of large components.

  Wiring structures used in conventional inductance elements include a wound type, a laminated type, and a thin film type. In the winding type, a copper core is wound around a ferromagnetic core, and there are a toroidal and a solenoid depending on the shape. In addition, an inductance element having a toroidal structure formed by making a through hole in a silicon substrate is also disclosed.

JP 2004-172396 A JP 2007-214424 A JP-A-9-139313 JP-A-8-88119 JP 2009-135325 A JP 2009-135326 A

  The present embodiment is to provide a magnetic structure capable of reducing magnetic resistance and eddy current loss and the above-described magnetic structure, and to provide an inductance element with reduced AC resistance and excellent high frequency characteristics. .

  In addition, the present embodiment is to provide an inductance element with reduced magnetic resistance, eddy current loss, AC resistance, high inductance, excellent high frequency characteristics, a method for manufacturing the inductance element, and a module including the inductance element. .

  Furthermore, in this embodiment, the structure is simple and the sticking where the lines contact each other does not easily occur, and the built-in electrode substrate capable of improving the reliability and the manufacturing method thereof, and the inductance element, interposer to which the electrode built-in substrate is applied, It is to provide a shield substrate and a module.

  According to one aspect of the present embodiment, the first magnetic layer, the first slit that divides the first magnetic layer into a plurality, and the first insulation disposed on the first slit and the first magnetic layer. There is provided a magnetic structure including a layer, a second magnetic layer disposed on the first insulating layer, and a second slit dividing the second magnetic layer into a plurality of portions.

  According to another aspect of the present embodiment, the first magnetic layer, the first slit that divides the first magnetic layer into a plurality, and the first slit disposed on the first slit and the first magnetic layer. An insulating layer; a second magnetic layer disposed on the first insulating layer; a second slit that divides the second magnetic layer into a plurality of portions; and disposed on the second slit and the second magnetic layer. Provided is a magnetic structure in which a plurality of laminated structures each including a second insulating layer are laminated.

  According to another aspect of the present embodiment, an inductance coil is provided, and the magnetic structure is provided with an inductance element disposed on the front surface, the back surface, or both surfaces of the inductance coil. .

  According to another aspect of the present embodiment, the apparatus includes a core, a winding coil disposed on the core, and the magnetic structure, and the magnetic structure can be magnetically coupled to the core. An inductor is provided.

  According to another aspect of the present embodiment, the magnetic structure includes a core, a primary coil disposed in the core, a secondary coil disposed in the core, and the magnetic structure. The structure is provided with a transformer capable of magnetic coupling with the core.

  According to another aspect of the present embodiment, an electromagnetic shielding target object, a cavity surrounding the electromagnetic shielding target object, and the magnetic structure described above are provided, and the magnetic structure is interposed via the cavity. An electromagnetic shielding structure surrounding the electromagnetic shielding target object is provided.

  According to another aspect of the present embodiment, the step of forming the first magnetic layer on the substrate, the step of forming the insulating layer on the first magnetic layer, the insulating layer and the first magnetic layer Forming a first slit; filling the first slit with a buried layer; forming a second magnetic layer on the insulating layer and the buried layer; and forming a second slit in the second magnetic layer. There is provided a method of manufacturing a magnetic structure having a forming step.

  According to another aspect of the present embodiment, a step of forming a first magnetic layer on a substrate, a step of forming a first slit in the first magnetic layer, the first magnetic layer and the first slit There is provided a method for manufacturing a magnetic structure, which includes a step of forming an insulating layer thereon, a step of forming a second magnetic layer on the insulating layer, and a step of forming a second slit in the second magnetic layer. The

  According to another aspect of the present embodiment, the substrate, the upper coil disposed on the surface of the substrate, the lower coil disposed on the back surface facing the surface of the substrate, and from the surface of the substrate to the back surface An inductance element including an upper and lower coil connecting portion that penetrates and connects an end portion of the upper coil and an end portion of the lower coil is provided.

  According to another aspect of the present embodiment, the substrate, the upper coil disposed on the surface of the substrate, the lower coil disposed on the back surface facing the surface of the substrate, and from the surface of the substrate to the back surface An upper and lower coil connecting portion that penetrates and connects an end portion of the upper coil and an end portion of the lower coil, an upper core disposed on a surface of the upper coil, and the gap between the upper coil and the lower coil A lower core disposed on a substrate, and the upper coil and the lower coil sandwich the substrate to form a solenoid coil, and the upper core and the lower core are ends of the upper coil and the lower coil, respectively. There is provided an inductance element having a closed magnetic path that is magnetically coupled at the portion and penetrates the solenoid coil.

  According to another aspect of the present embodiment, the substrate, the upper coil disposed on the surface of the substrate, the lower coil disposed on the back surface facing the surface of the substrate, and from the surface of the substrate to the back surface An upper and lower coil connecting portion that penetrates and connects an end portion of the upper coil and an end portion of the lower coil, an upper core disposed on a surface of the upper coil, and the gap between the upper coil and the lower coil In a method of manufacturing an inductance element including a lower core disposed on a substrate, a step of processing the substrate, a step of forming the lower core, the lower coil, and the upper and lower coil connecting portions, and forming the upper coil There is provided a method for manufacturing an inductance element, comprising a step and a step of forming the upper core.

  According to the other aspect of this Embodiment, a module provided with said inductance element is provided.

  According to another aspect of the present embodiment, a substrate, a groove formed inside the substrate, a beam disposed on the back surface facing the front surface of the substrate, and a wiring layer embedded in the groove A substrate with a built-in electrode is provided.

  According to another aspect of the present embodiment, there is provided an inductance element including the above-described electrode-embedded substrate, wherein the groove and the wiring layer have a coil shape.

  According to another aspect of the present embodiment, an interposer including the above electrode-embedded substrate is provided.

  According to another aspect of the present embodiment, there is provided a shield substrate including the above-described electrode-embedded substrate and a back electrode disposed on the back surface facing the surface of the substrate.

  According to another aspect of the present embodiment, a module including the above electrode-embedded substrate is provided.

  According to the other aspect of this Embodiment, a module provided with said inductance element is provided.

  According to another aspect of the present embodiment, a substrate, a groove portion having a coil shape formed inside the substrate, a beam portion disposed on the back surface facing the surface of the substrate, and embedded in the groove portion. A wiring layer, a top wiring layer disposed on the surface of the substrate, a bottom wiring layer disposed on the back surface facing the surface of the substrate, and a solder layer disposed on the top wiring layer. A module comprising an integrated circuit and a capacitor is provided.

  According to another aspect of the present embodiment, a step of forming a groove portion inside the substrate, a step of forming the beam portion on the back surface opposite to the front surface of the substrate, and an embedding formation of the wiring layer in the groove portion There is provided a method of manufacturing a substrate with a built-in electrode.

  According to another aspect of the present embodiment, a step of forming a coil-shaped groove in the substrate, a step of forming a beam on the back surface facing the surface of the substrate, and a wiring layer being embedded in the groove There is provided an inductance element manufacturing method including a forming step, a step of forming an upper core on the surface of the substrate, and a step of forming a lower core on the back surface opposite to the surface of the substrate.

  According to another aspect of the present embodiment, a step of forming a groove portion having a closed circuit pattern in a plan view inside the substrate, a step of forming a beam portion on the back surface facing the surface of the substrate, There is provided a method for manufacturing a shield substrate, comprising a step of embedding a wiring layer in the groove and a step of forming a back electrode on the back surface facing the front surface of the substrate.

  According to another aspect of the present embodiment, a step of forming a coil-shaped groove in the substrate, and a step of forming a through-groove disposed in the coil shape in plan view and penetrating the substrate, A step of forming a beam portion on the back surface facing the front surface of the substrate, a step of embedding a wiring layer in the groove portion, a step of embedding a through electrode in the through groove portion, and an upper core on the surface of the substrate Forming an upper surface wiring layer connected to the through electrode on the upper core, forming a lower core on the back surface facing the surface of the substrate, and forming the lower core on the lower core. There is provided a module manufacturing method including a step of forming a lower surface wiring layer connected to a through electrode and a step of mounting an integrated circuit and a capacitor on the upper surface wiring layer via a solder layer.

  According to the present embodiment, a magnetic structure capable of reducing magnetic resistance and eddy current loss and the above-described magnetic structure are applied to provide an inductance element with reduced AC resistance and excellent high-frequency characteristics. Can do.

  In addition, according to the present embodiment, an inductance element with reduced magnetic resistance, eddy current loss, AC resistance, high inductance, and excellent high frequency characteristics, a method for manufacturing the inductance element, and a module including the inductance element are provided. Can do.

  Furthermore, according to the present embodiment, sticking in which the structure is simple and the lines do not easily stick together and the reliability of the electrode-embedded substrate and the manufacturing method thereof, and the inductance element to which the electrode-embedded substrate is applied, Interposers, shield substrates and modules can be provided.

In the magnetic structure which concerns on the comparative example 1, the schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to a perpendicular direction. In the magnetic structure which concerns on the comparative example 2, the schematic diagram of the eddy current generate | occur | produced when a magnetic flux is applied to a perpendicular direction. In the magnetic structure which concerns on the comparative example 3, the schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to a surface normal direction. In the magnetic structure which concerns on the comparative example 1, the schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to an in-plane direction. In the magnetic structure which concerns on the comparative example 2, the schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to an in-plane direction. In the magnetic structure which concerns on the comparative example 3, the schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to an in-plane direction. (A) Typical plane pattern block diagram of the magnetic structure which concerns on 1st Embodiment, (b) Typical sectional structure drawing which follows the 1A-1A line | wire of Fig.7 (a). In the magnetic structure according to the first embodiment, (a) a schematic diagram of eddy current generated when a magnetic flux is applied horizontally to the in-layer direction, and (b) a magnetic flux is applied perpendicular to the in-layer direction. The schematic diagram of the eddy current which generate | occur | produces. (A) Typical plane pattern block diagram of the magnetic structure which concerns on the modification of 1st Embodiment, (b) Typical sectional structure drawing which follows the 2A-2A line of Fig.9 (a), (c) figure FIG. 9A is a schematic cross-sectional structure diagram taken along line 3A-3A in FIG. In the first method of manufacturing a magnetic structure according to the first embodiment, (a) a schematic cross-sectional structure diagram of a step of forming a first magnetic layer on a Si substrate, (b) on the first magnetic layer Schematic cross-sectional structure diagram of the process of forming the insulating layer, (c) Schematic cross-sectional structure diagram of the process of forming the first slit in the first magnetic layer, (d) Schematic of the process of embedding the first slit by the buried layer FIG. In the first method for manufacturing a magnetic structure according to the first embodiment, (a) a schematic cross-sectional structure diagram of a step of forming a second magnetic layer on an insulating layer and a buried layer, (b) a second magnetic layer The typical cross-section figure of the process of forming the 2nd slit in a layer. In the second manufacturing method of the magnetic structure according to the first embodiment, (a) a schematic cross-sectional structure diagram of a step of forming a first slit in the first magnetic layer, (b) on the first magnetic layer and Schematic cross-sectional structure diagram of the step of forming the insulating layer in the first slit, (c) Schematic cross-sectional structure diagram of the step of forming the second magnetic layer on the insulating layer, (d) Second to the second magnetic layer The typical cross-section figure of the process of forming a slit. (A) Typical plane pattern block diagram of the magnetic structure which concerns on 2nd Embodiment, (b) Typical sectional structure drawing which follows the 4A-4A line | wire of Fig.13 (a). The typical cross-section figure of the magnetic structure which concerns on 3rd Embodiment. (A) Typical plane pattern block diagram of the inductance element which concerns on the comparative example 4, (b) Typical sectional structure drawing which follows the 5A-5A line | wire of Fig.15 (a). (A) The typical plane pattern block diagram of the inductance element which concerns on embodiment, (b) The typical cross-section figure along the 6A-6A line | wire of Fig.16 (a). (A) The typical plane pattern block diagram of the inductance element which concerns on the modification 1 of embodiment, (b) The typical cross-section figure along the 7A-7A line | wire of Fig.17 (a). (A) Circuit representation of inductance coil, (b) Schematic diagram showing relationship between _AC resistance R _AC and inductance L (comparison between slit structure WS and non-slit structure WOS). (A) The schematic diagram which shows the relationship between the inductance L and the magnetic field H, (b) The schematic diagram which shows the relationship between the magnetic flux density B and the magnetic field H. 5 is an example of a magnetic circuit for explaining that the magnetic flux Φ passes through a portion having a small magnetic resistance R _{m in} the magnetic structure and the inductance element according to the embodiment. In the magnetic structure and the inductance element according to the embodiment, examples of cylindrical sample to explain that it is possible to suppress the eddy current loss P _e by reducing the cylinder radius r _0. (A) Typical plane pattern block diagram of the inductance element which concerns on the modification 2 of embodiment, (b) The typical cross-section figure along the 8A-8A line | wire of Fig.22 (a). (A) The typical plane pattern block diagram of the experiment system which has arrange | positioned the search coil on the magnetic layer provided with the slit SL, (b) The typical bird's-eye view of the search coil. FIG. 24 is a schematic cross-sectional structure diagram taken along line 9A-9A in FIG. Explanatory drawing of the slit space | interval on the basis of the dimension of a search coil device. (A) Explanatory diagram of experimental conditions of an experimental system in which a search coil is arranged on a magnetic layer having a slit SL, (b) Explanatory diagram of an angle θ ₂ of the D _X axis of the search coil with respect to the X axis, (c) Magnetic layer Explanatory drawing of slit width (DELTA) SL and slit space | interval (slit pitch) SLP of the slit SL formed in FIG. Explanatory drawing of the experimental condition which expanded FIG. 26 using the orthogonal table, and compressed 9 ways. In the experimental system which arrange | positioned the search coil on the magnetic layer provided with the slit SL, the experimental result of the relationship between the resistance increase amount of the AC resistance and the inductance (comparison between the slit structure WS and the non-slit structure WOS). It is an inductance element which concerns on the comparative example 4, Comprising: (a) Typical bird's-eye view, (b) Typical sectional structure drawing which follows the 10A-10A line | wire of Fig.29 (a). It is an inductance element which concerns on embodiment, Comprising: (a) Typical bird's-eye view, (b) The typical cross-section figure along the 11A-11A line | wire of Fig.30 (a). Frequency characteristics of inductance (comparison between slit structure WS and slitless structure WOS). Frequency characteristics of AC resistance (comparison between slit structure WS and slitless structure WOS). BRIEF DESCRIPTION OF THE DRAWINGS It is the manufacturing method of the inductance coil applicable to the inductance element which concerns on embodiment, Comprising: (a) Typical cross-section figure of the process of preparing a magnetic metal substrate, (b) Forming a groove part by etching a magnetic metal substrate Thereafter, a schematic cross-sectional structure diagram of the step of forming the insulating layer, (c) a schematic cross-sectional structure diagram of the step of forming the metal wiring layer, (d) the metal wiring layer is polished by CMP or the like, and the metal wiring layer is formed in the groove FIG. 4 is a schematic cross-sectional structure diagram of a process of leaving a mark, and (e) a schematic cross-sectional structure diagram of a process of forming an inductance coil by etching a back surface of a magnetic metal substrate. It is typical sectional structure explaining 1 process of the manufacturing method of the inductance coil applicable to the inductance element which concerns on embodiment, Comprising: (a) The example which formed the rectangular groove part, (b) The trapezoidal groove part Example of forming, (c) Example of forming a triangular groove, (d) Example of forming a U-shaped groove. (A) In the inductance element which concerns on embodiment, the typical bird's-eye view structure figure which shows an example which formed the groove part in the magnetic metal substrate, (b) In FIG. 35 (a), a mode that the metal wiring layer was formed in the groove part is shown. FIG. (A) It is another inductance element which concerns on embodiment, Comprising: The typical plane pattern block diagram of the example which formed the circular groove part formed on the magnetic metal substrate, (b) Circle of FIG. 36 (a) (C) It is another inductance element which concerns on a mode that the metal wiring layer was formed in the shape groove part, (c) It is another inductance element which concerns on embodiment, Comprising: In the octagonal groove part formed on the magnetic metal substrate, FIG. 4D is a schematic plane pattern configuration diagram in which a metal wiring layer is arranged; and (d) is another inductance element according to the embodiment, and the metal wiring layer is formed in two opposing triangular grooves formed on the magnetic metal substrate. The typical plane pattern block diagram which has arranged. 1 is a configuration example of a power supply circuit to which an inductance element according to an embodiment is applied as a component. 1 is a schematic cross-sectional structure of an inductor (EI core) to which a magnetic structure according to an embodiment is applied, in which (a) a first configuration example, (b) a second configuration example, and (c) a third configuration. Example, (d) Fourth configuration example. It is typical sectional structure of a transformer to which a magnetic structure concerning an embodiment is applied, and (a) the 1st example of composition and (b) the 2nd example of composition. The typical cross-section figure of the electromagnetic shielding structure to which the magnetic structure which concerns on embodiment is applied. It is a detailed structure of the inductance element which concerns on 4th Embodiment, Comprising: (a) Typical bird's-eye view, (b) Typical sectional structure drawing which follows the 12A-12A line | wire of Fig.41 (a). It is an inductance element concerning a 5th embodiment, and (a) typical bird's-eye view, (b) side view seen from A direction of Drawing 42 (a), (c) partial expansion structure example 1 between upper coils (D) Partial enlarged structure example 2 between upper coils, (e) The side view seen from the B direction of Fig.42 (a). The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. 43A is a top view of FIG. 43, FIG. 43B is a side view seen from the short side direction of FIG. 43, and FIG. 43C is a bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. 45A is a top view of FIG. 45, FIG. 45B is a side view viewed from the short side direction of FIG. 45, and FIG. 45C is a bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. 47A is a top view of FIG. 47, FIG. 47B is a side view seen from the short side direction of FIG. 47, and FIG. 47C is a bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. 49A is a top view of FIG. 49, FIG. 49B is a side view seen from the short side direction of FIG. 49, and FIG. 49C is a bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. 51A is a top view of FIG. 51, FIG. 51B is a side view seen from the short side direction of FIG. 51, and FIG. 51C is a bottom view of FIG. The side view seen from the long side direction of FIG. It is an inductance element which concerns on 5th Embodiment, Comprising: The typical bird's-eye view of the structure which couple | bonded the upper core and the lower core in the inductance coil edge part. (A) An enlarged view of a portion C in FIG. 54, (b) a schematic cross-sectional structure diagram taken along line 13A-13A in FIG. 55 (a). It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Typical top view of a silicon substrate, (b) Typical sectional drawing which follows the 14A-14A line of Fig.56 (a) . It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented back surface wiring etching, (b) 15A-15A line of Fig.57 (a) FIG. It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented the penetration wiring, (b) 16A-16A line | wire of Fig.58 (a) FIG. It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented the lower core etching, (b) The 17A-17A line | wire of Fig.59 (a) FIG. FIG. 5 is a schematic plan view of a silicon substrate in which seed formation is performed in a through hole, a lower coil formation portion, and a lower core formation portion, which is a step of the inductance element manufacturing method according to the fifth embodiment; (B) Typical sectional drawing which follows the 18A-18A line | wire of Fig.60 (a). FIG. 61 shows a step of the inductance element manufacturing method according to the fifth embodiment, wherein (a) a schematic plan view of a silicon substrate on which a lower core is formed by performing photolithography and plating, and (b) FIG. Typical sectional drawing which follows the 19A-19A line of (a). FIG. 62A is a schematic plan view of a silicon substrate in which plating is performed on a through hole / lower coil forming portion, which is a step in the method of manufacturing an inductance element according to the fifth embodiment; Typical sectional drawing which follows the 20A-20A line of a). It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented the back-and-back polishing process, (b) 21A-21A line of Fig.63 (a) FIG. It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented the surface side insulating layer formation process, (b) 22A of Fig.64 (a) Typical sectional drawing which follows a -22A line. FIG. 65A is a schematic plan view of a silicon substrate in which an opening forming step for the surface-side insulating layer is performed, which is one step of the method for manufacturing an inductance element according to the fifth embodiment. Typical sectional drawing in alignment with line 23A-23A. It is one process of the manufacturing method of the inductance element which concerns on 5th Embodiment, Comprising: (a) Schematic top view of the silicon substrate which implemented the seed formation process for upper wiring, (b) 24A of Fig.66 (a) Typical sectional drawing which follows a -24A line. FIG. 67A is a schematic plan view of a silicon substrate on which a photolithography process for an upper wiring is performed, which is a process of the inductance element manufacturing method according to the fifth embodiment. Typical sectional drawing which follows the 25A-25A line. FIG. 68A is a schematic plan view of a silicon substrate on which a plating forming process for an upper wiring has been performed, which is a process of an inductance element manufacturing method according to a fifth embodiment; Typical sectional drawing which follows the 26A-26A line | wire. FIG. 69A is a schematic plan view of a silicon substrate on which a resist stripping process for an upper wiring has been performed, which is a process of an inductance element manufacturing method according to a fifth embodiment; Typical sectional drawing in alignment with line 27A-27A. FIG. 70A is a schematic plan view of a silicon substrate on which a seed removing process for an upper wiring has been performed, which is a process of an inductance element manufacturing method according to a fifth embodiment; Typical sectional drawing which follows the 28A-28A line | wire. FIG. 71A is a schematic plan view of a silicon substrate on which an insulating layer forming process for an upper core has been performed, which is a process of the inductance element manufacturing method according to the fifth embodiment. ) 29A-29A schematic sectional view taken along line. FIG. 72A is a schematic plan view of a silicon substrate on which a seed formation process for an upper core has been performed, which is a process of an inductance element manufacturing method according to a fifth embodiment. Typical sectional drawing which follows the 30A-30A line. FIG. 73A is a schematic plan view of a silicon substrate on which a photolithography process for the upper core has been performed, which is a process of the inductance element manufacturing method according to the fifth embodiment. Typical sectional drawing in alignment with line 31A-31A. FIG. 74A is a schematic plan view of a silicon substrate on which a plating process for an upper core has been performed, which is a step in the method of manufacturing an inductance element according to the fifth embodiment. Typical sectional drawing in alignment with line 32A-32A. FIG. 75A is a schematic plan view of a silicon substrate in which a resist removing process for the upper core is performed, which is a process of the inductance element manufacturing method according to the fifth embodiment. Typical sectional drawing in alignment with the 33A-33A line | wire. FIG. 76A is a schematic plan view of a silicon substrate on which a seed removing process for an upper core has been performed, which is a process of the inductance element manufacturing method according to the fifth embodiment. Typical sectional drawing which follows the 34A-34A line | wire. 76 is a schematic cross-sectional view taken along line 35A-35A in FIG. (A) In the inductance element which concerns on 5th Embodiment, the typical top view which shows the upper coil and lower coil formed in the silicon substrate, (b) The schematic which follows the 36A-36A line | wire of Fig.78 (a) Sectional drawing. FIG. 78 is a schematic cross-sectional view taken along line 37A-37A in FIG. (A) In the inductance element according to the fifth embodiment, a schematic plan view showing an upper core and a lower core formed on a silicon substrate, (b) a schematic view taken along line 38A-38A in FIG. Sectional drawing. Typical sectional drawing which follows the 39A-39A line | wire of Fig.80 (a). The frequency characteristic of the inductance L of the inductance element which concerns on 5th Embodiment (SOL: Solenoid structure which concerns on 5th Embodiment, SPI: Spiral structure which concerns on 4th Embodiment). The frequency characteristic of AC resistance ACR of the inductance element which concerns on 5th Embodiment (SOL: Solenoid structure which concerns on 5th Embodiment, SPI: Spiral structure which concerns on 4th Embodiment). The top view of the module which concerns on 4th Embodiment which has arrange | positioned the inductance element, control IC, a capacitor, etc. on the printed circuit board (PCB). The top view of the module which concerns on 5th Embodiment which has arrange | positioned IC and a capacitor | condenser etc. on the inductance element based on 5th Embodiment formed in the silicon substrate, and the silicon substrate. The top view of the module which concerns on 4th Embodiment which has arrange | positioned the inductance element, DC / DC converter IC, the capacitor, etc. on PCB. Side view of the module according to the fifth embodiment (configuration) in which the inductance element according to the fifth embodiment formed on the silicon substrate, the control IC, the DC / DC converter IC, the capacitor, etc. are arranged on the silicon substrate. Example 1). FIG. 10 is a side view of a module according to a fifth embodiment in which an inductance element according to the fifth embodiment formed on a silicon substrate and a control IC / capacitor and the like are arranged on the silicon substrate (configuration example 2). FIG. 11 is a side view of a module according to a fifth embodiment in which an inductance element according to the fifth embodiment formed on a silicon substrate and a control IC / capacitor are arranged on the silicon substrate (configuration example 3). The connection structural example of the DC / DC converter (DCDC) which applied the inductance element which concerns on 5th Embodiment to an output load circuit, and was entirely mounted in the silicon substrate, and an output load circuit. It is a typical plane pattern block diagram of the electrode built-in substrate which concerns on 6th Embodiment, (a) The example in which a beam part is orthogonal to a wiring layer in planar view, and is provided with a stripe pattern parallel to each other, (b) An example in which beam portions are provided with stripe patterns that intersect each other at a predetermined angle θ in plan view. (A) Typical cross-section diagram along line 40A-40A in FIG. 91, (b) Typical cross-section diagram along line 41A-41A in FIG. FIG. 10 is a schematic plan pattern configuration diagram of an electrode built-in substrate according to a sixth embodiment, which has a relatively long line and space formed on a silicon wafer. (A) Typical cross-sectional structure diagram along line 42A-42A in FIG. 93, (b) Typical cross-sectional structure diagram along line 43A-43A in FIG. (A) Schematic plane pattern configuration diagram of an electrode-embedded substrate according to Comparative Example 5 that has a relatively long line and space formed on a silicon wafer, (b) Sixth embodiment The typical plane pattern block diagram of the electrode built-in board | substrate which concerns on this, Comprising: The electrode built-in board | substrate which has the relatively long line and space formed in the silicon wafer. FIG. 10 is a schematic plan pattern configuration diagram of an electrode built-in substrate according to Comparative Example 5 that has a spiral-shaped inductance element formed on a silicon substrate. FIG. 9A is a diagram of a substrate with a built-in electrode according to the sixth embodiment, wherein FIG. 9A is a schematic surface pattern configuration diagram, FIG. 97B is a schematic cross-sectional structure diagram along line 44A-44A in FIG. 97 (a) is a schematic cross-sectional structure diagram taken along line 45A-45A in FIG. 97 (d), and a schematic back surface pattern configuration diagram corresponding to FIG. 97 (a). It is 1 process of the manufacturing method of the board | substrate with a built-in electrode concerning 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 46A-46A line of Fig.98 (a) FIG. 99 (c) is a schematic backside pattern configuration diagram corresponding to FIG. 98 (a). It is 1 process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 47A-47A line | wire of Fig.99 (a) FIG. 99 (c) is a schematic back surface pattern configuration diagram corresponding to FIG. 99 (a). It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 48A-48A line | wire of Fig.100 (a) FIG. 10C is a schematic backside pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 49A-49A line of Fig.101 (a) FIG. 10C is a schematic backside pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 50A-50A line of Fig.102 (a) FIG. 10C is a schematic cross-sectional structure diagram taken along line 51A-51A in FIG. 102A, and FIG. 10D is a schematic back surface pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which followed the 52A-52A line of Fig.103 (a) FIG. 10C is a schematic cross-sectional structure diagram taken along line 53A-53 in FIG. 103A, and FIG. 10D is a schematic back surface pattern configuration diagram corresponding to FIG. 103A. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 54A-54A line of Fig.104 (a) FIG. 10C is a schematic cross-sectional structure diagram taken along line 55A-55A in FIG. 104A, and FIG. 10D is a schematic back surface pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure which follows the 56A-56A line of Fig.105 (a) FIG. 105, (c) a schematic cross-sectional structure diagram taken along line 57A-57A in FIG. 105 (a), and (d) a schematic back surface pattern configuration diagram corresponding to FIG. 105 (a). It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical cross-section along the 58A-58A line | wire of Fig.106 (a) FIG. 107, (c) a schematic cross-sectional structure diagram along line 59A-59A in FIG. 106 (a), and (d) a schematic back surface pattern configuration diagram corresponding to FIG. 106 (a). The typical cross-section figure of the inductance element of the silicon substrate system formed by applying the electrode built-in substrate concerning a 6th embodiment. (A) Schematic cross-sectional structure diagram of a permalloy substrate type inductance element according to Comparative Example 6 (structure example without back surface polishing), (b) Schematic cross-sectional structure diagram of a permalloy substrate type inductance element according to Comparative Example 6 ( Example of structure with backside polishing). (A) Schematic bird's-eye view configuration diagram of inductance element formed by applying electrode built-in substrate according to sixth embodiment, (b) Schematic cross-sectional structure diagram taken along line 60A-60A in FIG. 109 (a) . (A) It is an inductance element formed by applying the electrode built-in substrate according to the sixth embodiment, and is a schematic bird's-eye view configuration diagram of a wiring layer portion, (b) a surface configuration diagram of FIG. 110 (a), (C) The back surface block diagram of Fig.110 (a). (A) Cross-sectional bird's-eye view configuration diagram along line 61A-61A in the central portion of FIG. 110 (a), (b) Cross-sectional configuration diagram viewed from arrow B1 direction in FIG. 111 (a), (c) FIG. 111 (b) The enlarged view of C1 part of. (A) Cross-sectional bird's-eye view configuration diagram along line 62A-62A in FIG. 110 (a), (b) Cross-sectional configuration diagram viewed from arrow B2 direction in FIG. 112 (a), (c) C2 portion in FIG. 112 (b) Enlarged view of. FIG. 110A is a schematic bird's-eye view configuration diagram on the front surface side of only the silicon substrate in FIG. 110A, and FIG. 113B is a schematic bird's-eye view configuration diagram on the rear surface side in FIG. It is a typical top view of the beam part structure applicable to the electrode built-in board | substrate which concerns on 6th Embodiment, Comprising: (a) Cross type structure example, (b) Lattice type structure example, (c) Diagonal cross Mold configuration example, (d) Circular / cross composite configuration example. The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the substrate with a built-in electrode according to the sixth embodiment. The simulation result of the frequency characteristic of AC resistance ACR of the inductance element formed by applying the substrate with a built-in electrode according to the sixth embodiment. 10 is a mounting configuration example of a DC / DC converter module according to Comparative Example 7; The integrated circuit block block diagram of the structural example 1 of the DC / DC converter module which concerns on 6th Embodiment. A schematic planar pattern configuration of a configuration example 1 of a DC / DC converter in which an IC and a capacitor are mounted on an inductance element formed by applying an electrode built-in substrate according to the sixth embodiment corresponding to FIG. 118 is stacked. Composite diagram. 119 is a schematic cross-sectional structure diagram taken along a line 63A-63A in FIG. The typical bird's-eye view block diagram of the structural example 1 of the DC / DC converter module which concerns on 6th Embodiment. 119 is a schematic plan view of the lower surface wiring layer of FIGS. 119 is a schematic plan view of the inductor layer of FIGS. 119 is a schematic plan view of the upper surface wiring layer of FIGS. 119 to 121 are schematic plan views of the IC / capacitor layers of FIGS. The typical cross-section figure of the structural example 2 of the DC / DC converter module which concerns on 6th Embodiment. The typical bird's-eye view block diagram of the shield board | substrate formed by applying the electrode built-in board | substrate which concerns on 6th Embodiment. FIG. 11 is a shield substrate formed by applying the electrode built-in substrate according to the sixth embodiment, wherein (a) a top view of FIG. 127 and (b) a schematic view taken along line 64A-64A of FIG. 128 (a). Sectional structure figure, (c) Typical sectional structure figure which follows the 65A-65A line | wire of Fig.128 (a). (a) A schematic bird's-eye view of a package substrate including an interposer formed by applying the electrode built-in substrate according to the sixth embodiment, (b) a schematic cross-sectional structure taken along line 66A-66A in FIG. 129 (a) (C) Enlarged view of portion E in FIG. 129 (b).

  Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  In addition, the embodiment described below exemplifies an apparatus and method for embodying the technical idea, and does not specify the material, shape, structure, arrangement, etc. of the component parts as follows. . Various modifications can be made to the embodiments within the scope of the claims.

[Comparative Examples 1-3]
The magnetic structure 2B according to Comparative Example 1 has a single-layer structure having a single magnetic layer 10 as shown in FIGS. As shown in FIGS. 2 and 5, the magnetic structure 2 </ b> B according to the comparative example 2 has a multilayer structure having an insulating layer 12 between the magnetic layers 10 ₁ and 10 ₂ . As shown in FIGS. 3 and 6, the magnetic structure 2B according to Comparative Example 3 has a multilayer structure having an insulating layer 12 between the magnetic layers 10 ₁ and 10 ₂ , and a magnetic layer 10 ₁ and insulation by slits SL. A multilayer slit structure in which the layers 12 and 10 ₂ are divided is provided.

  The magnetic structures 2B according to Comparative Examples 1 to 3 show different characteristics depending on whether the direction of the magnetic flux Φ is perpendicular or parallel to the in-layer direction of the magnetic layer.

In the magnetic structure 2B according to the comparative example 1, when the direction of the magnetic flux Φ is the in-layer direction and the perpendicular direction to the magnetic layer 10, as shown in FIG. 1, the eddy current radius of the eddy current _Ie is The eddy current loss _Pe is relatively large. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layer 10 is single.

In the magnetic structure 2B according to the comparative example 2, when the direction of the magnetic flux Φ is the in-layer direction and the perpendicular direction of the magnetic layers 10 ₁ and 10 ₂ , as shown in FIG. 2, the eddy currents I _e1 and I _e2 the eddy current radius determined by the size of the magnetic layer 10 _1, 10 _2, the relatively large eddy current loss P _e. On the other hand, the magnetoresistance R _m is generated in the insulating layer 12 between the magnetic layers 10 ₁ and 10 _2, and is relatively large as compared with the comparative example 1.

In the magnetic structure 2B according to Comparative Example 3, when the direction of the magnetic flux Φ is the in-layer direction and the perpendicular direction of the magnetic layers 10 ₁ and 10 ₂ , as shown in FIG. 3, eddy currents i _e1 and i _e2 eddy current radius, capable of controlling at intervals of the slits SL to divide the magnetic layer 10 _1, 10 _2, the eddy current loss P _e becomes relatively small. On the other hand, the magnetoresistance R _m is generated in the insulating layer 12 between the magnetic layers 10 _1, 10 _2, and since the cross-sectional area of the magnetic layer 10 _1, 10 ₂ is reduced in the slit SL moiety, relative comparison with Comparative Example 2 Big.

In the magnetic structure 2B according to Comparative Example 1, when the direction of the magnetic flux Φ is parallel to the in-layer direction of the magnetic layer 10, the eddy current radius of the eddy current I _e is as shown in FIG. The eddy current loss _Pe is relatively large. On the other hand, the magnetoresistance R _m because the magnetic layer 10 is a single layer, relatively small.

In the magnetic structure 2B according to Comparative Example 2, when the direction of the magnetic flux Φ is parallel to the in-layer direction of the magnetic layers 10 ₁ and 10 ₂ , the eddy currents I _e1 and I _e2 are eddy current radius is determined by the interval of the magnetic layer 10 _1, 10 ₂ thick-insulating layer 12, the eddy current loss P _e becomes relatively small. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layers 10 ₁ and 10 ₂ are each a single layer.

In the magnetic structure 2B according to Comparative Example 3, when the direction of the magnetic flux Φ is parallel to the in-layer direction of the magnetic layers 10 ₁ and 10 ₂ , the eddy currents i _e1 and i _e2 are eddy current radius is determined by the interval of the magnetic layer 10 _1, 10 ₂ thick-insulating layer 12, the eddy current loss P _e becomes relatively small. On the other hand, the magnetoresistance R _m is to occur at the slit SL part, relatively large.

As described above, in the magnetic structure 2B according to the comparative example, the magnetic resistance R _m is relatively small with respect to the magnetic flux Φ in two directions of the in-layer direction and the perpendicular direction / parallel direction of the magnetic layer. it is difficult to form a magnetic circuit that can achieve both a relatively small eddy current loss P _e.

[First embodiment]
(Magnetic structure)
A schematic plane pattern configuration of the magnetic structure 2 according to the first embodiment is expressed as shown in FIG. 7A, and a schematic cross-sectional structure taken along line 1A-1A in FIG. It is expressed as shown in FIG.

The magnetic structure 2 according to the first embodiment, as shown in FIG. 7 (a) and 7 (b), first dividing the first magnetic layer 10 _1, the first magnetic layer 10 ₁ in more a first slit SL1, a first insulating layer 12, second magnetic layer 10 _2, the second magnetic layer disposed on the first insulating layer 12 disposed on the first slit SL1 and the first upper magnetic layer 10 ₁ And a second slit SL2 that divides 10 ₂ into a plurality of pieces.

  Further, as shown in FIG. 7A, the first slit SL1 and the second slit SL2 have stripe patterns parallel to each other in plan view.

  Further, as shown in FIG. 7A, the first slit SL1 and the second slit SL2 have stripe patterns that are parallel to each other and do not overlap in plan view.

As shown in FIGS. 7A and 7B, the magnetic structure 2 according to the first embodiment includes an insulating layer 12 formed between the magnetic layers 10 ₁ and 10 ₂ , and the magnetic layer 10 ₁ are separated from each other through the slit SL1, the magnetic layer 10 ₂ are separated from each other through the slit SL2.

Here, the magnetic layers 10 ₁ and 10 ₂ may be formed of a ferromagnetic material.

  The insulating layer 12 may be formed of a ferromagnetic material, a paramagnetic material, or a diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, it is convenient because the magnetic resistance is reduced. Instead of the insulating layer 12, it may be formed of a semi-insulating semiconductor or a high-resistance semiconductor layer.

  The slits SL1 and SL2 may be formed by being filled with a ferromagnetic material, a paramagnetic material, or a diamagnetic material. The magnetic resistance can be reduced by using a ferromagnetic material.

  The slits SL1 and SL2 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the first embodiment, the eddy current I _e generated when the magnetic flux Φ is applied horizontally to the inner direction of the magnetic layer is schematically expressed as shown in FIG. The eddy current I _e generated when the magnetic flux Φ is applied perpendicular to the direction in the magnetic layer is schematically represented as shown in FIG.

In the magnetic structure 2 according to the first embodiment, when a magnetic flux Φ is applied horizontally to the inner direction of the magnetic layer, as shown in FIG. 8A, along the overlapping magnetic layers 10 ₁ and 10 ₂ . Thus, a magnetic circuit is formed. Compared with the comparative example 3 shown in FIG. 6, since there is no gap by the slit SL, the magnetic resistance is reduced. Further, the radius of the eddy current I _e can be controlled by the thickness of the magnetic layers 10 ₁ and 10 ₂ and the slit intervals SLP1 and SLP2 of the slits SL1 and SL2. Here, as shown in FIG. 8A, the slit interval SLP1 of the slit SL1 corresponds to the center pitch between the adjacent slits SL1, and the slit interval SLP2 of the slit SL2 is set to the center pitch between the adjacent slits SL2. Correspond. The slit widths of the slits SL1 and SL2 are represented by ΔSL1 and ΔSL2.

In the magnetic structure 2 according to the first embodiment, as shown in FIG. 8B, when the magnetic flux Φ is applied perpendicular to the magnetic layer inner direction, the slit intervals SLP1 and SLP2 of the slits SL1 and SL2 and The radius of the eddy current I _e can be controlled by the thickness of the magnetic layers 10 ₁ and 10 ₂ . Moreover, since there is no magnetic flux which passes a slit compared with the multilayer slit structure of the comparative example 3 shown in FIG. 3, magnetic resistance becomes small.

  The radius of the eddy current generated by the magnetic flux can be controlled by the slit intervals SLP1 and SLP2 and the thickness of the magnetic layer. By reducing the eddy current radius, eddy current loss (the main component of AC resistance) can be suppressed.

  In the magnetic structure 2 according to the first embodiment, the formation positions of the first slit SL1 and the second slit SL2 are arranged so as not to overlap between adjacent slits.

In the magnetic structure 2 according to the first embodiment, as shown in FIG. 8A, the amount of magnetic flux in the in-plane direction is determined by the slit intervals SLP1 and SLP2 of the slits SL1 and SL2 and the magnetic layers 10 ₁ and 10 _2. It is controllable by the thickness of.

Further, in the magnetic structure 2 according to the first embodiment, as shown in FIG. 8B, the amount of magnetic flux in the perpendicular direction is set to the thickness of the magnetic layers 10 ₁ and 10 ₂ and the slits SL 1 and SL 2. It can be controlled by the slit intervals SLP1 and SLP2.

  In the magnetic structure 2 according to the first embodiment, as shown in FIGS. 8A and 8B, the slit widths ΔSL1 and ΔSL2 of the slits SL1 and SL2 are equal to the thickness of the first insulating layer 12. It is set larger than this.

(Modification)
A schematic planar pattern configuration of the magnetic structure 2 according to the modification of the first embodiment is represented as shown in FIG. 9A, and is a schematic cross section taken along line 2A-2A in FIG. 9A. The structure is represented as shown in FIG. 9B, and the schematic cross-sectional structure taken along line 3A-3A in FIG. 9A is represented as shown in FIG. 9C.

The magnetic structure 2 according to a modification of the first embodiment, as shown in FIG. 9 (a) ~ FIG 9 (c), the plurality of first magnetic layer 10 _1, the first magnetic layer 10 ₁ a first slit SL1 that divides, first an insulation layer 12, second magnetic layer 10 ₂ that are disposed on the first insulating layer 12 disposed on the first slit SL1 and the first upper magnetic layer 10 _1, the and a second slit SL2 that divides the second magnetic layer 10 ₂ into a plurality.

  Further, as shown in FIG. 9A, the first slit SL1 and the second slit SL2 have a parallel stripe pattern in plan view.

  Further, as shown in FIG. 9A, the first slit SL1 and the second slit SL2 intersect at a predetermined angle θ in plan view. Here, the angle θ is not less than 0 degrees and not more than 90 degrees.

  When the predetermined angle θ = 0 degrees, the first slit SL1 and the second slit SL2 have stripe patterns that are parallel to each other and do not overlap in plan view.

As shown in FIGS. 9A and 9B, the magnetic structure 2 according to the modification of the first embodiment has an insulating layer 12 formed between the magnetic layers 10 ₁ and 10 ₂ , and magnetic layer 10 ₁ are separated from each other through the slit SL1, the magnetic layer 10 ₂ are separated from each other through the slit SL2.

  Further, as shown in FIG. 9C, the magnetic structure 2 according to the modification of the first embodiment has the function of the present embodiment in the portion where the first slit SL1 and the second slit SL2 overlap. Is not expressed, but does not overlap in other parts, so the functions of the embodiment are expressed. Other configurations are the same as those of the first embodiment.

The magnetic structure 2 according to the first embodiment is not limited to the stripe pattern described above, and the first magnetic layer 10 ₁ and the second magnetic layer 10 ₂ are rectangular patterns parallel to each other in plan view. , A parallel triangular pattern, a parallel hexagonal pattern, a parallel octagonal pattern, a parallel polygonal pattern, a parallel circular pattern, or a parallel elliptical pattern may be provided. . Further, the first slit SL1 and the second slit SL2 may have a configuration that does not overlap with each other in plan view.

(First manufacturing method of magnetic structure)
The first manufacturing method of the magnetic structure 2 according to the first embodiment is expressed as shown in FIGS. 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (b). .

As shown in FIGS. 10A to 10D and FIGS. 11A to 11B, the first manufacturing method of the magnetic structure 2 according to the first embodiment is performed on the substrate 8. forming a step of forming a first magnetic layer 10 ₁ above, forming an insulating layer 12 on a first magnetic layer 10 _1, the first slit SL1 in the insulating layer 12 and the first magnetic layer 10 ₁ A step of filling the first slit SL1 with the buried layer 14, a step of forming the second magnetic layer 10 ₂ on the insulating layer 12 and the buried layer 14, and a second slit SL2 in the second magnetic layer 10 ₂ . Process.
(A) First, as shown in FIG. 10 (a), for example, preparing a silicon substrate 8, on the silicon substrate 8, to form the magnetic layer 10 _1, for example made of a ferromagnetic material. Here, the thickness of the silicon substrate 8 is, for example, about 525 μm. The magnetic layer 10 _1, for example, is applicable and Co-Ta-Zr layer. Thickness of the magnetic layer 10 ₁ is, for example, about 2 [mu] m. In the formation of the magnetic layer 10 _1, sputtering techniques, chemical vapor deposition: like (CVD Chemical Vapor Deposition) technique can be used. Here, an insulating substrate made of SiO ₂ may be applied instead of the silicon substrate 8.
(B) Next, as shown in FIG. 10 (b), the insulating layer 12 is formed on the magnetic layer 10 _1. As the insulating layer 12, for example, a silicon oxide film can be applied. In forming the insulating layer 12, for example, a plasma CVD technique can be used. The insulating layer 12 may be formed of a ferromagnetic material, a paramagnetic material, or a diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, it is convenient because the magnetic resistance is reduced. Instead of the insulating layer 12, it may be formed of a semi-insulating semiconductor or a high-resistance semiconductor layer.
(C) Next, as shown in FIG. 10 (c), the patterning step, the insulating layer 12 and the magnetic layer 10 ₁ is etched to form a slit SL1. Here, the width of the slit SL1 is, for example, about 10 μm.
(D) Next, as shown in FIG. 10D, the slit SL1 is filled with the buried layer. For the buried layer 14, an insulating layer or a magnetic material can be applied. As the insulating layer, for example, a silicon oxide film, a polyimide resin, or the like can be applied. The magnetic material may be a paramagnetic material or a diamagnetic material. Specifically, ferrite plating or ferrite paste can be used. The buried layer 14 may be formed of a semiconductor. Further, a ferromagnetic material can be applied to the buried layer 14. The magnetic resistance can be reduced by using a ferromagnetic material.
(E) Next, as shown in FIG. 11 (a), on the insulating layer 12 and the buried layer 14 to form a magnetic layer 10 _2, for example made of a ferromagnetic material. Here, the magnetic layer 10 _2, for example, is applicable and Co-Ta-Zr layer. Thickness of the magnetic layer 10 ₂ is, for example, about 2 [mu] m. In the formation of the magnetic layer 10 _2, it can be used sputtering technique, and CVD techniques.
(f) Next, as shown in FIG. 11 (b), by patterning step, the magnetic layer 10 ₂ is etched to form a slit SL2. Here, the slit width of the slit SL2 is, for example, about 10 μm. The slit SL2 may be filled with the buried layer 14 in the same manner as the slit SL1.

(Second manufacturing method of magnetic structure)
The second manufacturing method of the magnetic structure according to the first embodiment is expressed as shown in FIGS. 12 (a) to 12 (d).

As shown in FIGS. 12A to 12D, the second manufacturing method of the magnetic structure according to the first embodiment includes the steps of forming the first magnetic layer on the substrate, Forming a first slit in the magnetic layer; forming an insulating layer on the first magnetic layer and the first slit; forming a second magnetic layer on the insulating layer; and forming a second slit on the second magnetic layer. Forming two slits.
(A) First, as shown in FIG. 12 (a), for example, preparing a silicon substrate 8, on the silicon substrate 8, to form the magnetic layer 10 _1, for example made of a ferromagnetic material. Here, the magnetic layer 10 _1, for example, is applicable and Co-Ta-Zr layer. In the formation of the magnetic layer 10 ₁ can be used for sputtering technique, and CVD techniques. Here, an insulating substrate made of SiO ₂ may be applied instead of the silicon substrate 8.
(B) Next, by patterning step, the magnetic layer 10 ₁ is etched to form a slit SL1.
(C) Next, as shown in FIG. 12 (b), the insulating layer 12 is formed on the magnetic layer 10 ₁ and the slit SL1. As the insulating layer 12, for example, a silicon oxide film can be applied. In forming the insulating layer 12, for example, a plasma CVD technique can be used. The insulating layer 12 may be formed of a ferromagnetic material, a paramagnetic material, or a diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, it is convenient because the magnetic resistance is reduced. Instead of the insulating layer 12, it may be formed of a semi-insulating semiconductor or a high-resistance semiconductor layer.
(D) Next, as shown in FIG. 12 (c), on the insulating layer 12 to form a magnetic layer 10 _2, for example made of a ferromagnetic material. Here, the magnetic layer 10 _2, for example, is applicable and Co-Ta-Zr layer. In the formation of the magnetic layer 10 _2, it can be used sputtering technique, and CVD techniques.
(e) Next, as shown in FIG. 12 (d), by patterning step, the magnetic layer 10 ₂ is etched to form a slit SL2. Note that the slit SL2 may be filled with a buried layer. The buried layer may be formed of a paramagnetic material or a diamagnetic material. Further, it may be formed of a semiconductor or an insulator. Further, a ferromagnetic material can be applied to the buried layer. The magnetic resistance can be reduced by using a ferromagnetic material.

  According to the first embodiment, it is possible to provide a magnetic structure capable of reducing magnetoresistance and eddy current loss.

[Second Embodiment]
(Magnetic structure)
A schematic plane pattern configuration of the magnetic structure 2 according to the second embodiment is expressed as shown in FIG. 13A, and a schematic cross-sectional structure taken along line 4A-4A in FIG. It is expressed as shown in FIG.

The magnetic structure 2 according to the second embodiment, as shown in FIG. 13 (a) and 13 (b), first dividing the first magnetic layer 10 _1, the first magnetic layer 10 ₁ in more a first slit SL1, a first insulating layer 12 ₁ disposed on the first slit SL1 and the first upper magnetic layer 10 _1, second magnetic layer 10 ₂ disposed on a first insulating layer 12 _1, second The second slit SL2 that divides the magnetic layer 10 ₂ into a plurality of parts, the second insulating layer 12 ₂ disposed on the second slit SL2 and the second magnetic layer 10 ₂ , and the second insulating layer 12 ₂ It comprises a third magnetic layer 10 _3, and a third slit SL3 that divides the third magnetic layer into a plurality.

In the second embodiment, as compared with the first embodiment, the magnetic layer in the magnetic structure 2 has a three-layer structure and is multilayered. By multilayering the magnetic structure 2, the cross-sectional area of the magnetic structure 2 can be substantially increased, so that the magnetoresistance R _m can be reduced. In addition, since the volume of the magnetic structure 2 can be substantially increased by forming the multilayer structure, the magnetic energy that can be stored increases.

  As shown in FIG. 13A and FIG. 13B, the first slit SL1 and the second slit SL2 have a lattice pattern parallel to each other in plan view, and the second slit SL2 and the third slit SL3 In a plan view, they may have lattice patterns parallel to each other.

  Further, as shown in FIGS. 13A and 13B, the first slit SL1 and the third slit SL3 have a lattice pattern that overlaps with each other in plan view, and the second slit SL2 and the third slit SL3. May have a lattice pattern parallel to each other in plan view.

In the magnetic structure 2 according to the second embodiment, as shown in FIGS. 13A and 13B, an insulating layer 12 ₁ is formed between the magnetic layers 10 ₁ and 10 ₂ , and the magnetic layer 10 _An insulating layer 12 ₂ is formed between ₂ and 10 _3, and the magnetic layer 10 ₁ is divided into each other through the slit SL1, the magnetic layer 10 ₂ is divided into each other through the slit SL2, and the magnetic layer 10 ₃ forms the slit SL3. Are separated from each other.

Here, the magnetic layers 10 ₁ , 10 _2, and 10 ₃ may be formed of a ferromagnetic material.

The insulating layers 12 ₁ and 12 ₂ may be made of a ferromagnetic material, a paramagnetic material, or a diamagnetic material. In particular, when the insulating layers 12 ₁ and 12 ₂ are formed of a ferromagnetic material, it is convenient because the magnetoresistance is reduced. Instead of the insulating layers 12 ₁ and 12 ₂ 2, a semi-insulating semiconductor or a high-resistance semiconductor layer may be used.

  The slits SL1, SL2, and SL3 may be formed by being filled with a ferromagnetic material, a paramagnetic material, or a diamagnetic material. The magnetic resistance can be reduced by using a ferromagnetic material.

  The slits SL1, SL2, and SL3 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the second embodiment, when the magnetic flux Φ is applied horizontally to the inner direction of the magnetic layer, the three-layer structure overlapped as in the two-layer structure of FIG. A magnetic circuit is formed along the magnetic layers 10 ₁ , 10 _2, and 10 ₃ . Since there is no gap due to the slit SL, the magnetic resistance is reduced. Further, the radius of the eddy current _Ie can be controlled by the thickness of the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ and the slit intervals SLP1, SLP2, SLP3 of the slits SL1, SL2, SL3. Here, the slit intervals SLP1 and SLP2 are as shown in FIG. Further, since the slit interval SLP3 is the same, the illustration is omitted.

In the magnetic structure 2 according to the second embodiment, when the magnetic flux Φ is applied perpendicular to the magnetic layer inner direction, the slit SL1 is also formed in the three-layer structure as in the two-layer structure of FIG. 8B. The radius of the eddy current _Ie can be controlled by the slit spacings SLP1, SLP2, SLP3 of SL2 and SL3 and the thickness of the magnetic layers 10 ₁ , 10 _2, and 10 ₃ . Further, since there is no magnetic flux passing through the slit, the magnetic resistance is reduced as compared with the multilayer slit structure.

In the magnetic structure 2 according to the second embodiment, the amount of magnetic flux in the in-plane direction is the thickness of the slit intervals SLP1, SLP2, and SLP3 of the slits SL1, SL2, and SL3 and the magnetic layers 10 ₁ , 10 _2, and 10 ₃ . It can be controlled by.

In the magnetic structure 2 according to the second embodiment, the amount of magnetic flux in the direction perpendicular to the plane is also the thickness of the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ and the slit spacings SLP 1, SLP 2 of the slits SL 1, SL ₂ , SL _3. -It can be controlled by SLP3.

Further, the magnetic structure 2 according to the second embodiment, the slit width ΔSL1 · ΔSL2 the first slit SL1 and the second slit SL2 is greater than the first thickness of the insulating layer 12 _1, and the second slit SL2 and the slit width ΔSL2 · ΔSL3 third slit SL3 is set to be larger than the thickness of the second insulating layer 12 _2. Here, the slit widths ΔSL1 and ΔSL2 are as shown in FIG. Further, since the slit width ΔSL3 is the same, the illustration is omitted.

  In the magnetic structure 2 according to the second embodiment, the first slit SL1 and the second slit SL2 have a stripe pattern that is parallel and intersects with each other at a predetermined angle θ in plan view, and the second slit SL2 The third slit SL3 may have a stripe pattern that is parallel and intersects with each other at a predetermined angle θ in plan view. Here, the angle θ is not less than 0 degrees and not more than 90 degrees. Further, when the predetermined angle θ = 0 degrees, the relationship between the slits includes stripe patterns that are parallel to each other and do not overlap in a plan view.

  In the magnetic structure 2 according to the second embodiment, the first slit SL1 and the third slit SL3 have a stripe pattern that overlaps with each other in plan view, and the second slit SL2 and the third slit SL3 are planar. When viewed, stripe patterns that are parallel and intersect each other at a predetermined angle θ may be provided. Here, the angle θ is not less than 0 degrees and not more than 90 degrees. When the predetermined angle θ = 0 degrees, the second slit SL2 and the third slit SL3 have stripe patterns that are parallel to each other and do not overlap in plan view.

In the magnetic structure 2 according to the second embodiment, the first magnetic layer 10 ₁ , the second magnetic layer 10 _2, and the third magnetic layer 10 ₃ are not limited to the lattice pattern described above. In the above, any of a rectangular pattern parallel to each other, a triangular pattern parallel to each other, a hexagonal pattern parallel to each other, an octagonal pattern parallel to each other, a polygonal pattern parallel to each other, a circular pattern parallel to each other, or an elliptical pattern parallel to each other You may have. Further, the first slit SL1 and the second slit SL2 and the second slit SL2 and the third slit SL2 may have a configuration that does not overlap with each other in plan view.

  According to the second embodiment, it is possible to provide a magnetic structure capable of reducing magnetoresistance and eddy current loss.

[Third embodiment]
(Magnetic structure)
A schematic cross-sectional structure of the magnetic structure 2 according to the third embodiment is expressed as shown in FIG.

The magnetic structure 2 according to the third embodiment, as shown in FIG. 14, a first slit SL1 that divides the first magnetic layer 10 _1, the first magnetic layer 10 ₁ into a plurality of first slit SL1 The first insulating layer 12 ₁ disposed on the first magnetic layer 10 ₁ , the second magnetic layer 10 ₂ disposed on the first insulating layer 12 ₁ , and the second magnetic layer 10 ₂ are divided into a plurality of parts. A second slit SL2, a second insulating layer 12 ₂ disposed on the second slit SL2 and the second magnetic layer 10 ₂ , a third magnetic layer 10 ₃ disposed on the second insulating layer 12 ₂ , A third slit SL3 that divides the three magnetic layer 10 ₃ into a plurality of pieces, a third insulating layer 12 ₃ disposed on the third slit SL3 and the third magnetic layer 10 ₃ ,..., An n−1th insulating layer 12 _n a first n magnetic layer 10 _n disposed on _-1, and the n slits SLn dividing the second n magnetic layer 10 _n in plurality, the And the n + 1 insulating layer 12 _{n + 1,} which is arranged in the slit SLn and the n magnetic layer 10 _n, and the n + 1 magnetic layer 10 _{n + 1} arranged on the (n + 1) insulating layer 12 _{n + 1,} the (n + 1) magnetic And n + 1-th slit SLn + 1 that divides the layer 10 _{n + 1} into a plurality of layers.

That is, the magnetic structure 2 according to the third embodiment, the first magnetic layer 10 _1, a first slit SL1 for dividing the first magnetic layer 10 ₁ into a plurality of first slit SL1 and the first magnetic layer A first insulating layer 12 ₁ disposed on 10 ₁ , a second magnetic layer 10 ₂ disposed on the first insulating layer 12 ₁ , and a second slit SL2 that divides the second magnetic layer 10 ₂ into a plurality of portions And a configuration in which a plurality of stacked structures including the second slit SL2 and the second insulating layer 12 ₂ disposed on the second magnetic layer 10 ₂ are stacked.

In the third embodiment, the magnetic layer in the magnetic structure 2 is multilayered. By multilayering the magnetic structure 2, the cross-sectional area of the magnetic structure 2 can be substantially increased, so that the magnetoresistance R _m can be reduced. In addition, since the volume of the magnetic structure 2 can be substantially increased by forming the multilayer structure, the magnetic energy that can be stored increases.

Here, the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ ,..., 10 _{n + 1} may be formed of a ferromagnetic material.

The insulating layers 12 ₁ , 12 ₂ ,..., 12 _n may be made of a ferromagnetic material, a paramagnetic material, or a diamagnetic material. In particular, when the insulating layer _{12 1 · 12 2 · ... ·} 12 n is formed of a ferromagnetic material, it is advantageous magnetoresistance decreases. Instead of the insulating layers 12 ₁ , 12 ₂ ,..., 12 _n , a semi-insulating semiconductor or a high resistance semiconductor layer may be used.

  In addition, the slits SL1, SL2, SL3,..., SLn + 1 may be formed by being filled with a ferromagnetic material, a paramagnetic material, or a diamagnetic material. The magnetic resistance can be reduced by using a ferromagnetic material.

  Moreover, the slits SL1, SL2, SL3,..., SLn + 1 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the third embodiment, the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ ,. _A magnetic circuit is formed along _{n + 1} . Since there is no gap due to the slit SL, the magnetic resistance is reduced. Further, the radius of the eddy current _Ie is determined based on the thickness of the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ ,... 10 _{n + 1} and the slit intervals SLP1, SLP2, SLP3, and SLn + 1. .... Controllable with SLPn + 1.

In the magnetic structure 2 according to the third embodiment, when the magnetic flux Φ is applied perpendicularly to the magnetic layer inner direction, the slit intervals SLP1 and SLP2 of the slits SL1, SL2, SL3,. .. SLPn + 1 and the magnetic layers 10 ₁ , 10 ₂ , 10 ₃ ,..., 10 _{n + 1} can control the radius of the eddy current I _e . Further, since there is no magnetic flux passing through the slit, the magnetic resistance is reduced as compared with the multilayer slit structure.

In the magnetic structure 2 according to the third embodiment, the magnetic flux amount of plane direction, the slit interval of the slit SL1 · SL2 · SL3 · ... · SLn + 1 SLP1 · SLP2 · SLP3 · ... · SLPn + 1 and the magnetic layer 10 ₁ - It can be controlled by a thickness of 10 ₂ , 10 ₃ ,..., 10 _{n + 1} .

Further, in the magnetic structure 2 according to the third embodiment, the amount of magnetic flux in the perpendicular direction is determined by the thickness of the insulating layers 12 ₁ , 12 ₂ ,... 12 _n and the slits SL1, SL2, SL3,. .. SLPn + 1 can be controlled by the slit intervals SLP1, SLP2, SLP3,.

  According to the third embodiment, it is possible to provide a magnetic structure capable of reducing magnetoresistance and eddy current loss.

[Comparative Example 4]
(Inductance element)
A schematic plane pattern configuration of the inductance element 4B according to the comparative example 4 is expressed as shown in FIG. 15A, and a schematic cross-sectional structure taken along the line 5A-5A in FIG. ).

  As shown in FIG. 15A and FIG. 15B, the inductance element 4B according to Comparative Example 4 includes an inductance coil 16, a magnetic layer 10U disposed on the surface of the inductance coil 16, and the back surface of the inductance coil 16. And a magnetic layer 10 </ b> D disposed on the surface.

  Here, the magnetic layers 10 </ b> D and 10 </ b> U have a single layer structure as in the comparative example 1 of FIGS. 1 and 4.

  The inductance coil 16 is formed by a metal wiring layer 22 formed in the magnetic metal substrate 20.

  A magnetic layer 10 </ b> U is disposed on the surface of the inductance coil 16 via an insulating layer 24, and a magnetic layer 10 </ b> D is disposed on the back surface of the inductance coil 16 via an insulating layer 24. For this reason, in the schematic planar pattern configuration shown in FIG. 15A, the inductance coil 16 should be indicated by a broken line, but is illustrated by a solid line for easy viewing of the arrangement of the inductance coil 16 on the magnetic layer 10D.

Similarly to the magnetic structure according to the comparative example 1, when the direction of the magnetic flux Φ is the in-layer direction and the perpendicular direction of the magnetic layers 10D and 10U, the eddy current radius of the eddy current I _e is that of the magnetic layers 10D and 10U. The eddy current loss _Pe is relatively large depending on the size. Meanwhile, since the magnetoresistance R _m is a single magnetism layer 10D · 10 U, relatively small.

Similarly to the magnetic structure according to Comparative Example 1, when the direction of the magnetic flux Φ is parallel to the in-layer direction of the magnetic layers 10D and 10U, the eddy current radius of the eddy current _Ie is the thickness of the magnetic layers 10D and 10U. in rule, the eddy current loss P _e becomes relatively large is. On the other hand, the magnetoresistance R _m because the magnetic layer 10 is a single layer, relatively small.

In Comparative Example 4, a relatively small magnetic resistance R _m and a relatively small eddy current loss _Pe are compatible with the magnetic flux Φ in the two directions of the in-layer direction of the magnetic layer and the perpendicular direction and the parallel direction. It is difficult to form possible magnetic circuits.

Therefore, since the inductance element 4B according to the comparative example 4 has a relatively large eddy current loss in the magnetic layers 10D and 10U, the AC resistance _RAC is also large.

[Fourth embodiment]
(Inductance element)
A schematic plane pattern configuration of the inductance element 4 according to the fourth embodiment is expressed as shown in FIG. 16A, and a schematic cross-sectional structure taken along line 6A-6A in FIG. 16 (b).

  As shown in FIGS. 16A and 16B, the inductance element 4 according to the fourth embodiment includes an inductance coil 16, a magnetic structure 2U arranged on the surface of the inductance coil 16, and an inductance. And a magnetic layer 10 </ b> D disposed on the back surface of the coil 16.

Here, the magnetic structure 2U has a configuration in which three-layer structures of magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U are laminated. That is, the magnetic structure 2U corresponds to the magnetic structure 2 according to the second embodiment.

  Further, the magnetic layer 10D has a single-layer structure like the comparative example 4 in FIG.

  The inductance coil 16 is formed by a metal wiring layer 22 formed in the magnetic metal substrate 20.

Here, the widths of the slits SL1, SL2, and SL3 are about 10 μm. The thickness of the insulating layer is about 1 μm. The thickness of each magnetic layer 10 ₁ U · 10 ₂ U · 10 ₃ U is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm.

In the inductance element 4 according to the fourth embodiment, by setting the slit width wider than the thickness of the insulating layer, the magnetic flux passes through a portion having a small gap, so that the magnetoresistance R _m is reduced. Can do.

  In the inductance element 4 according to the fourth embodiment, when the magnetic flux is parallel to the plane of the magnetic layer, the eddy current radius is controlled by the slit interval and the thickness of the magnetic layer. Even in the case of being perpendicular to the plane of the magnetic layer, it can be controlled by the thickness of the magnetic layer and the slit interval. For this reason, since the inductance element 4 according to the fourth embodiment includes the magnetic structure having a multilayer structure, the eddy current radius can be reduced, and as a result, the eddy current loss can be reduced.

In the inductance element 4 according to the fourth embodiment, as shown by the broken line of FIG. 16 (b), relatively reluctance R _m is small and relatively eddy current loss P _e is small magnetic circuit Is formed.

  Since the inductance element 4 according to the fourth embodiment can reduce the eddy current radius of the magnetic structure 2U as shown in FIGS. 16A and 16B, the eddy current loss can be reduced. it can.

As shown in FIGS. 16A and 16B, the inductance element 4 according to the fourth embodiment includes a magnetic structure 2U capable of reducing the magnetic resistance and eddy current loss on the inductance coil 16. Therefore, compared to the inductance element 4B according to the comparative example 4, the eddy current loss is relatively reduced, and the AC resistance _RAC can be reduced.

In the inductance element 4 according to the fourth embodiment, the magnetic layer 10 ₁ close to the inductor 16 is relatively narrower the slit interval SLP1 of the magnetic layer 10 _first slit SL1 since the magnetic flux Φ is relatively large and, according away from inductor 16, the magnetic flux Φ may be relatively wider slit spacing SLP2 of the magnetic layer 10 _{and second} slit SL2 from becoming relatively small. In the magnetic layer 10 ₂ , the magnetic flux density is small and the eddy current is small as compared with the magnetic layer 10 ₁ . For this reason, it is not necessary to set the slit interval SLP2 as finely as the slit interval SLP1. If the slit interval SLP2 widened than the slit intervals SLP 1, it can reduce the magnetic resistance in the magnetic layer 10 _2. On the other hand, the magnetic layer 10 ₃ may have a single-layer structure without forming the slit SL3 and may be configured to suppress a leakage magnetic field to the outside.

(Modification 1)
A schematic planar pattern configuration of the inductance element 4 according to the first modification of the fourth embodiment is expressed as shown in FIG. 17A and is a schematic cross section taken along the line 7A-7A in FIG. The structure is represented as shown in FIG.

  As shown in FIGS. 17A and 17B, the inductance element 4 according to the first modification of the fourth embodiment includes an inductance coil 16 and a magnetic structure disposed on the surface of the inductance coil 16. 2U and a magnetic structure 2D disposed on the back surface of the inductance coil 16.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U, 10 ₂ U, and 10 ₃ U is laminated, and the magnetic structure 2D includes the magnetic layers 10 ₁ D, 10 ₂ D, and It has a configuration in which 10 ₃ D three-layer structures are stacked. That is, the magnetic structures 2U and 2D correspond to the magnetic structure 2 according to the second embodiment.

An insulating layer is formed between the magnetic layers 10 ₁ U and 10 ₂ U, an insulating layer is formed between the magnetic layers 10 ₂ U and 10 ₃ U, and the magnetic layer 10 ₁ U is separated from each other through the slit SL1 and is magnetic. The layer 10 ₂ U is divided from each other through the slit SL2, and the magnetic layer 10 ₃ U is divided from each other through the slit SL3. The same applies to the magnetic layers 10 ₁ D · 10 ₂ D · 10 ₃ D.

  As shown in FIGS. 17A and 17B, the slit SL1 and the slit SL3 are provided with a lattice pattern overlapping each other in plan view, and the slit SL2 and the slit SL3 are parallel to each other in plan view. A pattern is provided.

  The inductance coil 16 is formed by a metal wiring layer 22 formed in the magnetic metal substrate 20.

Here, the slit widths ΔSL1, ΔSL2, and ΔSL3 of the slits SL1, SL2, and SL3 are about 10 μm. The thickness of the insulating layer is about 1 μm. The thickness of each magnetic layer 10 ₁ U · 10 ₂ U · 10 ₃ U · 10 ₁ D · 10 ₂ D · 10 ₃ D is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm. is there.

In the inductance element 4 according to the first modification of the fourth embodiment, by setting the slit widths ΔSL1, ΔSL2, and ΔSL3 to be wider than the thickness of the insulating layer, the magnetic flux passes through a small gap portion. reduction of the resistance R _m can be achieved.

  Further, in the inductance element 4 according to the first modification of the fourth embodiment, the eddy current radius is controlled by the slit interval and the magnetic layer thickness when the magnetic flux is parallel to the plane of the magnetic layer. Even when the magnetic flux is perpendicular to the plane of the magnetic layer, it can be controlled by the thickness of the magnetic layer and the slit interval. For this reason, since the inductance element 4 according to the first modification of the fourth embodiment includes the magnetic structure having a multilayer structure, the eddy current radius can be reduced, and as a result, the eddy current loss can be reduced. .

In the inductance element 4 according to the first modification of the fourth embodiment, as indicated by the broken line in FIG. 17B, the magnetic resistance R _m is relatively small, and the eddy current loss P _{e is} relatively small. A small magnetic circuit is formed.

  Since the inductance element 4 according to the first modification of the fourth embodiment can reduce the eddy current radius of the magnetic structures 2U and 2D as shown in FIGS. Loss can be reduced. The magnetic flux in the in-plane direction of the magnetic layer can be controlled by the slit interval of the magnetic structures 2U and 2D and the film thickness of each magnetic layer. The magnetic flux in the direction perpendicular to the magnetic layer is also the film thickness of each magnetic layer. Further, it can be controlled by the slit interval of the magnetic structures 2U and 2D.

As shown in FIGS. 17A and 17B, the inductance element 4 according to the first modification of the fourth embodiment includes magnetic structures 2U and 2D that can reduce magnetoresistance and eddy current loss. Is provided above and below the inductance coil 16, the eddy current loss is further reduced and the AC resistance R _AC can be further reduced as compared with the inductance element 4 according to the fourth embodiment.

Also in the inductance element 4 according to the first modification of the fourth embodiment, the magnetic layer 10 ₁ close to the inductance coil 16, the magnetic flux Φ is the slit spacing SLP1 of the magnetic layer 10 _first slit SL1 since relatively large relatively narrow form, according away from inductor 16, the magnetic flux Φ may be relatively wider slit spacing SLP2 of the magnetic layer 10 _{and second} slit SL2 from becoming relatively small. In the magnetic layer 10 ₂ , the magnetic flux density is small and the eddy current is small as compared with the magnetic layer 10 ₁ . For this reason, it is not necessary to set the slit interval SLP2 as finely as the slit interval SLP1. If the slit interval SLP2 widened than the slit intervals SLP 1, it can reduce the magnetic resistance in the magnetic layer 10 _2. On the other hand, the magnetic layer 10 ₃ may have a single-layer structure without forming the slit SL3 and may be configured to suppress a leakage magnetic field to the outside.

  A circuit representation of the inductance element is expressed as shown in FIG.

The inductance element is represented by a series circuit configuration of an inherent inductance L and an AC resistance R _AC having frequency characteristics.

Further, the relationship between the _AC resistance R _AC and the inductance L is schematically represented as shown in FIG. The AC resistance R _AC shows an increasing tendency as the inductance L increases. Here, in FIG. 18B, WS corresponds to the case where the inductance element has a slit structure, that is, corresponds to the fourth embodiment shown in FIGS. Corresponds to the comparative example 4 shown in FIG. 15. Although the AC resistance R _AC shows an increasing tendency as the inductance L increases, the increasing tendency is suppressed as compared with the comparative example 4 in the inductance element according to the fourth embodiment or the modification thereof. That is, the AC resistance R _AC can be reduced by providing the slit structure. The experimental results are as shown in FIG.

In the inductance element, the relationship between the inductance L and the magnetic field H is schematically expressed as shown in FIG. 19A, and the relationship between the magnetic flux density B and the magnetic field H is schematically shown in FIG. 19B. It is expressed in The magnetic field H is proportional to the current through the inductance element. The relationship between the inductance L and the magnetic field H is ideally a constant value L ₀ with respect to the increase of the current, that is, the magnetic field H, as indicated by a broken line, but in practice, it is shown in FIG. as shows the decreasing trend as shown by L _d exceeds field H ₁ threshold. This is because, as shown in FIG. 19B, in the BH curve, the gradients of the magnetic flux density B and the magnetic field H are reduced when the threshold magnetic field H _{1 is} exceeded, and as a result, the inductance L is also reduced. Here, the saturation magnetic flux density B _s and the gradient of the magnetic field H indicate the magnetic permeability μ.

(Relationship between magnetic flux and magnetoresistance)
In the magnetic structure and the inductance element according to the fourth embodiment, an example of a magnetic circuit for explaining that the magnetic flux Φ passes through a portion having a small magnetic resistance R _m is schematically shown in FIG. expressed.

The magnetic field H in the annular iron core 6 having the magnetic permeability μ is expressed by the law of ampere-round integration, where N is the number of turns and I is the conduction current.
It is represented by If S (m ² ) is the cross-sectional area at an arbitrary position of the magnetic circuit and B is the magnetic flux density, then Φ = BS = μHS. Therefore, the magnetic field H at an arbitrary point in the magnetic circuit is expressed by the following equation. The

H = Φ / (μS) (2)

Even if the cross-sectional area S in the magnetic circuit changes, the magnetic flux Φ is constant everywhere in the magnetic circuit. From the equations (1) and (2),
It is represented by Using the magnetic resistance R _m ,

NI = R _m Φ (4)

Φ = NI / R _m (5)

Is established. From equation (5), it can be seen that the smaller the magnetic resistance R _m is, the larger the magnetic flux Φ becomes, and the magnetic flux Φ easily passes through the magnetic circuit. Therefore, it can be seen that the magnetic flux Φ passes through a portion having a small magnetic resistance R _m .

(Relationship between eddy current loss and eddy current radius)
The In fourth magnetic structure and the inductance element according to the embodiment, the example of the cylindrical sample to explain that it is possible to suppress the eddy current loss P _e by reducing the cylinder radius r ₀ is schematically Is expressed as shown in FIG.

  Eddy current loss is a phenomenon in which a current flows in a sample according to the law of electromagnetic induction accompanying a change in magnetization, and the change in magnetization is therefore braked.

The eddy current loss _Pe is given by assuming that the cylinder radius is r ₀ , the resistivity is ρ, the conduction current is I, and the change with time is dI / dt.

P _e = r ₀ ² / (8ρ) · (dI / dt) ² (6)

Is established. From (6), a cylinder radius by reducing the r _0, it is possible to suppress the eddy current loss P _e.

(Modification 2)
A schematic planar pattern configuration of the inductance element 4 according to the second modification of the fourth embodiment is expressed as shown in FIG. 22A, and is a schematic cross section taken along line 8A-8A in FIG. The structure is represented as shown in FIG.

  As shown in FIGS. 22A and 22B, the inductance element 4 according to the second modification of the fourth embodiment includes an inductance coil 16 and a magnetic structure disposed on the surface of the inductance coil 16. 2U and a magnetic structure 2D disposed on the back surface of the inductance coil 16.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U, 10 ₂ U, and 10 ₃ U is laminated, and the magnetic structure 2D includes the magnetic layers 10 ₁ D, 10 ₂ D, and It has a configuration in which 10 ₃ D three-layer structures are stacked. The magnetic structures 2U and 2D correspond to the magnetic structure 2 according to the second embodiment.

An insulating layer 12 ₁ is formed between the magnetic layers 10 ₁ U and 10 ₂ U, an insulating layer 12 ₂ is formed between the magnetic layers 10 ₂ U and 10 ₃ U, and the magnetic layers 10 ₁ U are mutually connected via the slit SL1. The magnetic layer 10 ₂ U is divided from each other through the slit SL2, and the magnetic layer 10 ₃ U is divided from each other through the slit SL3. The same applies to the magnetic layers 10 ₁ D · 10 ₂ D · 10 ₃ D.

  As shown in FIGS. 22A and 22B, the slit SL1 and the slit SL3 are provided with a lattice pattern overlapping each other in plan view, and the slit SL2 and the slit SL3 are parallel to each other in plan view. A pattern is provided.

Here, the widths of the slits SL1, SL2, and SL3 are about 10 μm. The film thickness of the insulating layers 12 ₁ and 12 ₂ is about 1 μm. The thickness of each magnetic layer 10 ₁ U · 10 ₂ U · 10 ₃ U · 10 ₁ D · 10 ₂ D · 10 ₃ D is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm. is there.

In the inductance element 4 according to the second modification of the fourth embodiment, the slit width by setting wider than the thickness of the insulating layer, the magnetic flux to pass a small portion of the gap, reducing the magnetic resistance R _m Can be achieved.

Further, in the inductance element 4 according to the second modification of the fourth embodiment, the eddy current radius is controlled by the thickness of the magnetic layer and the slit interval when the magnetic flux is parallel to the plane of the magnetic layer. Even when the magnetic flux is perpendicular to the plane of the magnetic layer, it can be controlled by the slit interval and the thickness of the magnetic layer. Therefore, in the inductance element 4 according to the second modification of the fourth embodiment, since with a magnetic structure of the multilayer structure to reduce eddy current radius, the eddy current loss P _e can be reduced as a result It is.

In the inductance element 4 according to the second modification of the fourth embodiment, as shown by the broken line in FIG. 22, a relatively reluctance R _m is small and relatively eddy current loss P _e is small magnetic A circuit is formed.

  The inductance element 4 according to the second modification of the fourth embodiment is the same as the inductance element 4 according to the first modification of the fourth embodiment in that the magnetic structures 2U and 2D have a lattice pattern. .

  In the second modification of the fourth embodiment, as shown in FIG. 22A, the arrangement structure of the lattice pattern of the magnetic structures 2U and 2D is different from the first modification of the fourth embodiment. Yes. Other configurations are the same as those of the first modification of the fourth embodiment.

As shown in FIGS. 22A and 22B, the inductance element 4 according to the second modification of the fourth embodiment includes a magnetic structure that can reduce magnetoresistance and eddy current loss as an inductance coil. Since 16 are provided above and below, the eddy current loss can be further reduced and the AC resistance R _AC can be further reduced as compared with the inductance element 4 according to the fourth embodiment.

(Evaluation using search coil)
In order to verify whether or not the _AC resistance R _AC can be reduced by forming slits in the magnetic layer, the search coil 40 is mounted on the magnetic layer in which the slits SL are formed in various shapes, and impedance measurement is performed. went.

Schematic plane pattern configuration of the experimental system arranged search coil 40 on the magnetic layer 10 ₃ having the slit SL is expressed as shown in FIG. 23 (a), schematic bird's-eye view structure of the search coil 40 is schematically Is represented as shown in FIG. Further, a schematic cross-sectional structure taken along line 9A-9A in FIG. 23A is expressed as shown in FIG.

As shown in FIG. 23A, the short side direction of the magnetic layer is the X axis direction, the long side direction is the Y axis direction, the short side direction of the search coil device is the D _X axis direction, and the long side direction is the D _Y axis. The direction.

As shown in FIG. 24, the search coil 40 and the magnetic structure 2 form a closed magnetic circuit (closed magnetic circuit) as shown by a broken line. The resistance R _AC can be evaluated.

As shown in FIGS. 23A and 23B, the search coil 40 is disposed on a search coil substrate 42 and connected to the search coil electrode terminals 38 ₁ and 38 ₂ .

As shown in FIGS. 23A and 24, the search coil 40 is arranged on the magnetic layer having the slit SL so that the coil surface of the search coil 40 faces the magnetic layer surface. Therefore, the search coil electrode terminals 38 ₁ and 38 ₂ can be taken out from above.

  In this experimental system, the magnetic structure is disposed on the magnetic layer substrate 50. Here, the magnetic structure has the same structure as the magnetic structure 2 (FIG. 12) according to the second embodiment.

As shown in FIG. 23A, the slit width of the slit SL is represented by ΔSL, the slit interval in the X-axis direction (the arrangement pitch of the slit SL) is represented by W _X , and the slit interval in the Y-axis direction (slit SL arrangement pitch) is represented by W _Y.

A narrower slit width ΔSL of the slit SL is desirable because the magnetic resistance R _m decreases. A longer slit interval W _X · W _Y of the slit SL is desirable because the magnetic resistance R _m decreases.

  The description of the slit interval on the basis of the dimension DS × DL of the search coil device is schematically shown in FIG.

The experimental conditions of the experimental system in which the search coil 40 is arranged on the magnetic layer having the slit SL are expressed as shown in FIG. 26A, and the explanation of the angle θ ₂ of the D _X axis of the search coil with respect to the X axis is as follows: It is expressed as shown in FIG. The description of the slit width ΔSL and the slit interval (slit pitch) SLP of the slit SL formed in the magnetic layer 10 is expressed as shown in FIG. Furthermore, the experimental conditions in which FIG. 26A is expanded using the orthogonal table and compressed in nine ways are expressed as shown in FIG.

In FIG. 26 (a), No. 1 shows that the slit interval SLP is in the (D _X · D _Y ) direction under the condition that the angle θ ₂ is 90 ° and the slit width ΔSL is 2 μm, as shown in FIG. This corresponds to dividing the magnetic layer into a size of / 8) × (DL / 8). No. 2 is a condition where the angle θ ₂ is 45 ° and the slit width ΔSL is 6 μm, and the slit interval SLP is in the (D _X · D _Y ) direction, as shown in FIG. 25, (DS / 4) × (DL / This corresponds to dividing the magnetic layer into the size of 4). No. 3 is a condition where the angle θ ₂ is 0 ° and the slit width ΔSL is 10 μm, and the slit interval SLP is in the (D _X · D _Y ) direction, as shown in FIG. 25, (DS / 2) × (DL / This corresponds to dividing the magnetic layer into the size of 2). Since the same applies to FIG. 27, the duplicate description is omitted.

26A and 27, the angle θ ₂ between the search coil and the magnetic layer of 90 ° corresponds to an arrangement relationship in which the short side axis X of the search coil and the short side axis D _{X of the} magnetic layer are perpendicular. The angle θ ₂ between the search coil and the magnetic layer of 45 ° corresponds to an arrangement relationship in which the short side axis X of the search coil and the short side axis D _{X of the} magnetic layer have an angle of 45 °. An angle θ ₂ between the search coil and the magnetic layer of 0 ° corresponds to an arrangement relationship in which the short side axis X of the search coil and the short side axis D _{X of the} magnetic layer are parallel.

  Note that in FIG. No. 1 is a pair in which the number of magnetic layers is one. No. 2 is a pair in which the number of magnetic layers is two. 3 includes a pair in which the number of magnetic layers is three.

  Similarly, in FIG. 1-No. No. 3 is a pair in which the number of magnetic layers is one. 4-No. No. 6 is a pair in which the number of magnetic layers is two. 7-No. 9 includes a pair of three magnetic layers.

  26A and 27, the slit widths 2 μm, 6 μm, and 10 μm correspond to the conditions that the slit width ΔSL of the slit SL is 2 μm, 6 μm, and 10 μm. In FIGS. 26A and 27, the thickness of each magnetic layer is 2 μm.

In the above experimental system, the experimental result of the relationship between the resistance increase amount R _{6 MHz} -R _{100 kHz} of the AC resistance R _AC and the inductance L is expressed as shown in FIG. In FIG. 28, WS corresponds to the slit structure, and experimental data corresponding to the experimental conditions of FIGS. 26 (a) and 27 are indicated by white circle plots and broken lines. The AC resistance R _AC of the resistance increase R _6MHz -R _100kHz is the difference AC resistance R _AC at a frequency of 6MHz and 100kHz. On the other hand, WOS corresponds to a structure without slits, the magnetic layer has a single layer structure, and the thickness of the magnetic layer is changed to 0.25 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, and 14 μm. Data are shown as black circle plots and solid lines.

As shown in FIG. 28, the resistance increase amount R _{6 MHz} -R _{100 kHz} of the _AC resistance R _AC shows an increasing tendency as the inductance L increases, but the fourth embodiment in which the magnetic layer has a slit structure or a modification thereof. In the inductance element according to the above, an increase tendency is suppressed as compared with Comparative Example 4 in which the magnetic layer has a single layer structure. That is, by providing the slit structure, the resistance increase amount of the _AC resistance R _AC can be reduced. Therefore, the AC resistance R _AC can be reduced by providing the magnetic layer with a slit structure.

(Evaluation of AC loss)
In the inductance element according to the fourth embodiment and the inductance element according to Comparative Example 4, the AC loss was compared. Specifically, in the inductance element according to the fourth embodiment having a magnetic structure in which a slit is formed in the magnetic layer and the inductance element according to Comparative Example 4 in which the magnetic layer has a single-layer structure, the frequency characteristics of the inductance L and The frequency characteristic of the _AC resistance R _AC was measured.

  In the inductance element according to the comparative example 4, the schematic bird's-eye view configuration is represented as shown in FIG. 29A, and the schematic cross-sectional structure taken along the line 10A-10A in FIG. It is expressed as shown in (b). In Comparative Example 4 shown in FIG. 29, the device size of the inductance element is 1.9 mm × 1.1 mm, and the thickness of the magnetic layer having a single layer structure is 6 μm.

In the inductance element according to the fourth embodiment, a schematic bird's-eye view configuration is represented as shown in FIG. 30A, and a schematic cross-sectional structure taken along line 11A-11A in FIG. This is expressed as shown in FIG. In the example shown in FIG. 30, the device size of the inductance element is 1.9 mm × 1.1 mm, and the magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U and 10 ₁ D · 10 ₂ D · 10 have a three-layer structure. the thickness of ₃ D are each 2 [mu] m. The film thickness of the insulating layer 12 between the magnetic layers is 1 μm, and the slit widths ΔSL1, ΔSL2, and ΔSL3 are each 10 μm. The slit interval is 1/4 of the device size, (DL / 4) × (DS / 4) = 475 μm × 275 μm, and the device size is divided into 16 parts.

The experimental result of the frequency characteristic of the inductance L of the inductance element according to the fourth embodiment and the inductance element according to Comparative Example 4 is expressed as shown in FIG. 31, and the experimental result of the frequency characteristic of the _AC resistance R _AC is shown in FIG. It is expressed as shown in 31 and 32, WS corresponds to the slit structure of the fourth embodiment shown in FIG. 30, and WOS corresponds to the slitless structure of Comparative Example 4 shown in FIG.

In the inductance element according to the fourth embodiment, as the frequency characteristic of the inductance L, a flat frequency characteristic is obtained in a wide frequency band as shown in FIG. Further, in the inductance element according to the fourth embodiment, the frequency characteristic of the _AC resistance R _AC can suppress an increase in AC resistance on the high frequency side as shown in FIG. That is, the magnetic structure having the slit structure can improve the high frequency characteristics of the inductance L and can suppress an increase in AC resistance. As a result, the inductance element according to the fourth embodiment can reduce AC loss.

(Inductance coil manufacturing method)
A schematic cross-sectional structure for explaining one process of the method of manufacturing the inductance coil 16 applicable to the inductance element 4 according to the fourth embodiment is as shown in FIGS. 33 (a) to 33 (e). expressed. Moreover, it is a schematic cross-sectional structure explaining one process of the manufacturing method of the inductance coil 16 applicable to the inductance element 4 which concerns on 4th Embodiment, Comprising: Rectangle shape, trapezoid shape, triangle shape, U-shape Examples in which the groove portion 15 is formed are represented as shown in FIGS. 34 (a) to 34 (d), respectively.
(A) First, as shown in FIG. 33A, the magnetic metal film to be the magnetic metal substrate 20 is cleaned and then chemically polished. Here, for example, PC permalloy (NiFeMoCu) can be applied to the magnetic metal film.
(B) Next, as shown in FIG. 33B, after forming the U-shaped groove 15 on the surface of the magnetic metal substrate 20, the insulating layer 25 is formed. The groove 15 can be formed by, for example, wet etching (using an etching solution containing phosphoric acid), laser processing, or press processing after resist patterning. As the insulating layer 25, for example, SiO ₂ can be applied. In forming the insulating layer 25, a sputtering technique, a CVD technique, or the like can be used. By forming the insulating layer 25, the magnetic metal substrate 20 and the metal wiring layer 22 can be electrically insulated.
(C) Next, as shown in FIG. 33C, electrolytic plating is performed on the entire surface of the magnetic metal substrate 20 via the insulating layer 25 to form the metal wiring layer 22. Cu can be applied to the metal wiring layer 22. As other materials, Pt, Au, Ag, and the like are also applicable.
(D) Next, as shown in FIG. 33D, the metal wiring layer 22 and the flat insulating layer 25 are etched to leave the metal wiring layer 22 filled only in the groove 15. For the etching, for example, a dry etching technique, a chemical mechanical polishing (CMP) technique, or the like can be applied. As a result, the excess metal wiring layer 22 can be removed.
(E) Next, as shown in FIG. 33E, the magnetic metal substrate 20 on the back surface is etched and thinned. For example, wet etching technology, CMP technology, or the like can be applied to the back surface etching. As a result, the excess metal wiring layer 22 on the back surface can be removed.

  Through the above steps, the inductance coil 16 applicable to the inductance element 4 according to the fourth embodiment is completed.

  In the inductance coil applicable to the inductance element 4 according to the fourth embodiment, a schematic bird's-eye view showing a state in which the groove 15 is formed in the magnetic metal substrate 20 is expressed as shown in FIG. A schematic bird's-eye view showing a state in which the metal wiring layer 22 and the inductance coil terminal electrode 23 are formed in the groove portion 15 is expressed as shown in FIG.

  Furthermore, it is another inductance coil applicable to the inductance element 4 according to the fourth embodiment, and a schematic planar pattern configuration of the circular groove portion 15 formed on the magnetic metal substrate 20 is shown in FIG. FIG. 36B shows a schematic planar pattern configuration in which the metal wiring layer 22 and the inductance coil terminal electrode 23 are arranged in the circular groove portion 15 shown in FIG. 36A. It is expressed in

  Moreover, it is another inductance coil applicable to the inductance element 4 according to the fourth embodiment, and the metal wiring layer 22 and the terminal for the inductance coil are formed in the octagonal groove portion 15 formed on the magnetic metal substrate 20. A schematic planar pattern configuration in which the electrodes 23 are arranged is expressed as shown in FIG. 36C, and a schematic arrangement in which the metal wiring layer 22 and the inductance coil terminal electrode 23 are arranged in two opposing triangular grooves 15 is shown. The planar pattern configuration is expressed as shown in FIG.

  In the inductance coil applicable to the inductance element 4 according to the fourth embodiment, the metal wiring layer 22 is thus provided with a coil shape, which is rectangular, circular, octagonal, or triangular. Any one of the plane patterns may be provided. The coil shape may have a polygonal shape or an arbitrary plane pattern.

(Application example for power circuit)
A configuration example of a power supply circuit to which the inductance element 4 according to the fourth embodiment is applied as a component is expressed as shown in FIG. In FIG. 37, an example of a DC-DC step-down converter is shown.

The DC-DC step-down converter to which the inductance element 4 according to the fourth embodiment is applied includes a DC input voltage V _I , a MOSFET Q, a diode D, a capacitor C, and an inductor L. The inductance element 4 according to the fourth embodiment is applied to the inductor L. In the DC-DC step-down converter shown in FIG. 37, the energy stored in the inductor L is switched from the DC input voltage V _I by the switching operation of the MOSFET Q, and the DC output voltage V _O is stepped down from the DC input voltage V _I. Can be obtained from both ends of the capacitor C. The application example of the inductance element 4 according to the fourth embodiment is not limited to the above-described DC-DC step-down converter, but is used for a DC-DC step-up converter, a choke coil application for noise removal, and the like. Is also applicable.

[Application example]
(Inductor)
FIG. 38 is a schematic cross-sectional structure of an inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied, and the first configuration example is represented as shown in FIG. The configuration example of FIG. 38 is expressed as shown in FIG. 38B, the third configuration example is expressed as shown in FIG. 38C, and the fourth configuration example is expressed as shown in FIG. 38D. Is done.

  An inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied includes a core 200 and windings disposed on the core 200, as shown in FIGS. 38 (a) to 38 (d). A wire coil 220 and a magnetic structure 240 are provided, and the magnetic structure 240 can be magnetically coupled to the core 200.

  As the magnetic structure 240, as shown in FIGS. 38A to 38D, the magnetic structure according to the second embodiment having a three-layer structure is applied. The magnetic structure 240 according to the first or third embodiment can also be applied to the magnetic structure 240. As the core 200, a ferrite or metal magnetic material can be used. An Fe—Si based silicon rigid plate reactor or the like may be applied.

  In the inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied, a magnetic circuit with small magnetoresistance and eddy current loss is applied to the inductor, so that the entire inductor (EI core) can be obtained. Magnetic resistance and eddy current loss can be reduced. Also, leakage magnetic flux can be suppressed.

(Trance)
39 is a schematic cross-sectional structure of a transformer 300 to which the magnetic structure 240 according to the fourth embodiment is applied, and the first configuration example is arranged in the core 200 and the core 200 as shown in FIG. The primary side coil L1, the secondary side coil L2 disposed on the core 200, and the magnetic structure 240 are provided. The magnetic structure 240 can be magnetically coupled to the core 200.

FIG. 39B is a schematic cross-sectional structure of a transformer 300 to which the magnetic structures 240 ₁ and 240 _{2 according} to the fourth embodiment are applied, and a second configuration example includes a core 200 and a core as shown in FIG. a primary coil L1 placed in 200, the secondary coil L2 disposed in the core 200, and a magnetic structure 240 _{1-240 2,} the magnetic structure 240 ₁ - 240 ₂ includes a core 200 Magnetic coupling is possible.

As the magnetic structures 240, 240 _1, and 240 _2, as shown in FIGS. 39A and 39B, the magnetic structure according to the second embodiment having a three-layer structure is applied. The magnetic structure 240, 240 _1, 240 _2, the magnetic structure according to the first or third embodiment can also be applied. As the core 200, a ferrite or metal magnetic material can be used. An Fe—Si based silicon rigid plate reactor or the like may be applied.

  In the transformer 300 to which the magnetic structure 240 according to the fourth embodiment is applied, the magnetic resistance and eddy current loss of the entire transformer are reduced by applying a magnetic circuit with small magnetoresistance and eddy current loss to the transformer 300. Can be realized. Also, leakage magnetic flux can be suppressed.

(Electromagnetic shielding structure)
As shown in FIG. 40, a schematic cross-sectional structure of an electromagnetic shielding structure 400 to which the magnetic structure 240 according to the fourth embodiment is applied includes an electromagnetic shielding target object 250 and a hollow portion surrounding the electromagnetic shielding target object 250. 260 and a magnetic structure 240, and the magnetic structure 240 surrounds the electromagnetic shielding target object 250 through the cavity 260. The electromagnetic shielding target object 250 is an object that does not want to give an electromagnetic field (E, H) such as a sensor component.

  In the electromagnetic shielding structure 400 to which the magnetic structure 240 according to the fourth embodiment is applied, the electromagnetic shielding structure 400 is applied by applying a magnetic circuit with small magnetic resistance and eddy current loss to the electromagnetic shielding structure 400. The overall magnetic resistance and eddy current loss can be reduced. Also, leakage magnetic flux can be suppressed.

  As described above, according to the first to fourth embodiments, the magnetic structure capable of reducing the magnetic resistance and eddy current loss and the above magnetic structure are applied, the AC resistance is reduced, and the high frequency An inductance element having excellent characteristics can be provided.

  According to the first to fourth embodiments, it is possible to provide an inductor, a transformer, and an electromagnetic shielding structure to which the above magnetic structure can be applied.

(Detailed configuration of inductance element)
FIG. 41A is a detailed configuration of the inductance element 4B according to the fourth embodiment, and a schematic bird's-eye view configuration is represented as shown in FIG. 41A, and is a schematic diagram taken along line 12A-12A in FIG. A typical cross-sectional structure is represented as shown in FIG.

  As shown in FIGS. 41A and 41B, the inductance element 4B according to the fourth embodiment includes an inductance coil 160, a magnetic structure 2U disposed on the surface of the inductance coil 160, and an inductance. A magnetic structure 2D disposed on the back surface of the coil 160.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U, 10 ₂ U, and 10 ₃ U is laminated, and the magnetic structure 2D includes the magnetic layers 10 ₁ D, 10 ₂ D, and It has a configuration in which 10 ₃ D three-layer structures are stacked.

An insulating layer 122 ₁ is formed between the magnetic layers 10 ₁ U and 10 ₂ U, an insulating layer 122 ₂ is formed between the magnetic layers 10 ₂ U and 10 ₃ U, and the magnetic layers 10 ₁ U are mutually connected via the slit SL. The magnetic layer 10 ₂ U is also divided from each other through the slit SL, and the magnetic layer 10 ₃ U is also divided from each other through the slit SL. The same applies to the magnetic layers 10 ₁ D · 10 ₂ D · 10 ₃ D.

  The magnetic metal substrate 290 is formed by permalloy, for example.

  The inductance coil 160 is formed by a metal wiring layer formed in the magnetic metal substrate 290. For example, it is formed by embedding a metal wiring layer in a spiral groove formed by etching permalloy.

  In the inductance element 4B according to the fourth embodiment, the magnetic structures 2U and 2D having slits are formed as a core to form a closed magnetic circuit structure.

  As shown in FIGS. 41 (a) and 41 (b), an inductance element 4B according to the fourth embodiment includes magnetic structures 2U and 2D that can reduce magnetoresistance and eddy current loss. Since it is provided at the top and bottom, eddy current loss is reduced, and AC resistance can also be reduced.

[Fifth embodiment]
(Configuration of inductance element)
In the inductance element 4 according to the fifth embodiment, a schematic bird's-eye view configuration is represented as shown in FIG. 42A, and a side configuration viewed from the direction A in FIG. It is expressed as shown in (b). Partially enlarged structure example 1 between the upper coils is represented as shown in FIG. 42C, and partially enlarged structure example 2 between the upper coils is represented as shown in FIG. Moreover, the side structure seen from the B direction of Fig.42 (a) is represented as shown in FIG.42 (e).

  The inductance element 4 according to the fifth embodiment includes a substrate 112, an upper coil 126 disposed on the surface of the substrate 112, a lower coil 122 disposed on the back surface facing the surface of the substrate 112, and the substrate 112. An upper and lower coil connecting portion 120 that penetrates from the front surface to the back surface and connects the upper coil 126 and the lower coil 122 is provided.

  As shown in FIGS. 42B and 42D, a relatively thick insulating layer 128B may be embedded between the upper coils 126 with the insulating layer 128 interposed therebetween. Alternatively, as shown in FIG. 42C, the magnetic layer of the upper core 130 may be embedded between the upper coils 126 via the insulating layer 128.

  As shown in FIG. 42D, the structural example 2 including the relatively thick insulating layer 128B between the upper coils 126 has a width W2 between the coils that is twice or more the thickness D of the magnetic layer of the upper core 130. Applicable to the case. On the other hand, in Structural Example 1 in which the magnetic layer of the upper core 130 is provided between the upper coils 126, the width W1 between the coils is more than twice the thickness D of the magnetic layer of the upper core 130, as shown in FIG. Applicable when it is small.

  In the inductance element 4 according to the fifth embodiment, the upper coil 126 and the lower coil 122 sandwich the substrate 112 and constitute a solenoid coil.

  Further, a lower core 124 disposed on the substrate 112 between the upper coil 126 and the lower coil 122 may be provided.

  The upper core 130 includes an upper core 130 disposed on the surface of the upper coil 126, and a lower core 124 disposed on the substrate 112 between the upper coil 126 and the lower coil 122. 126 and the end of the lower coil 122 may be magnetically coupled.

  The inductance element 4 according to the fifth embodiment includes a substrate 112, an upper coil 126 disposed on the surface of the substrate 112, a lower coil 122 disposed on the back surface facing the surface of the substrate 112, and a substrate. 112, the upper and lower coil connecting portions 120 that penetrate from the front surface to the back surface and connect the upper coil 126 and the lower coil 122, the upper core 130 disposed on the surface of the upper coil 126, and between the upper coil 126 and the lower coil 122 The lower core 124 disposed on the substrate 112 may be provided. Here, the upper coil 126 and the lower coil 122 sandwich the substrate 112 to form a solenoid coil, and the upper core 130 and the lower core 124 are magnetically coupled at the end portions of the upper coil 126 and the lower coil 122 to provide a solenoid. You may provide the closed magnetic circuit which penetrates a coil.

  Further, the substrate may be provided with either a silicon substrate or an insulating substrate such as a glass substrate or a ferrite substrate.

  As shown in FIGS. 42A to 42E, the inductance element 4 according to the fifth embodiment performs deep etching on the silicon substrate 112, the front and back surfaces of the silicon substrate, and the silicon substrate 112. An upper coil 126 and a lower coil 122 formed of a metal wiring layer disposed in a solenoid-shaped groove portion formed in practice are provided.

  Further, the inductance element 4 according to the fifth embodiment may include an upper core 130 disposed on the surface of the upper coil 126 as shown in FIGS. 42 (a) to 42 (e). The upper core 130 may have a multilayer structure of a magnetic layer and an insulating layer. Here, the magnetic layer constituting the upper core 130 can be formed by a plating technique, a sputtering technique, a vacuum deposition technique, or the like.

Further, the inductance element 4 according to the fifth embodiment is arranged on the surface of the silicon substrate 112 as shown in FIGS. 42A to 42E, and is a solenoid composed of an upper coil 126 and a lower coil 122. A lower core 124 built in the coil may be provided. The lower core 124 may have a multilayer structure of a magnetic layer and an insulating layer. Here, the magnetic layer constituting the lower core 124 can also be formed by a plating technique, a sputtering technique, a vacuum deposition technique, or the like.

  Here, the magnetic layers constituting the upper core 130 and the lower core 124 may include a ferromagnetic material.

  The insulating layers constituting the upper core 130 and the lower core 124 may include any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material, and may have a resistivity of 10 Ω · cm or more.

  Further, the eddy current radius in the magnetic layer can be controlled by the thickness of the magnetic layer constituting the upper core 130 and the lower core 124. By forming the magnetic layer thin, the eddy current radius can be reduced, and eddy current loss can be reduced.

  In addition, the inductance element 4 according to the fifth embodiment includes an upper core 130 and a lower core 124 at the ends of the upper coil 126 and the lower coil 122, as shown in FIGS. 42 (a) to 42 (e). May be provided.

  Since the upper core 130 and the lower core 124 have a multilayer structure of a magnetic layer and an insulating layer, an eddy current radius can be reduced, eddy current loss can be reduced, and magnetic resistance can be reduced.

  In addition, by connecting the upper core 130 and the lower core 124 at the ends of the upper coil 126 and the lower coil 122, a closed magnetic circuit that penetrates the solenoid structure including the upper coil 126 and the lower coil 122 can be formed. The inductance value can be made relatively high.

  In the inductance element according to the fifth embodiment, as a simple configuration, the upper core and the lower core may be omitted, and the solenoid structure described above may be provided.

  Further, in the inductance element according to the fifth embodiment, as a simple configuration, the lower core may be omitted, and a combined structure of the upper core and the solenoid structure may be provided.

  Further, in the inductance element according to the fifth embodiment, as a simple configuration, the upper core may be omitted and a combined structure of the lower core and the solenoid structure may be provided.

  The fifth embodiment can provide an inductance element with reduced magnetic resistance, eddy current loss, and AC resistance, high inductance, and excellent high frequency characteristics.

  According to the fifth embodiment, it is possible to provide an inductance element having a high inductance while maintaining an AC resistance equivalent to that of the inductance element according to the fourth embodiment.

(Processed structure of silicon substrate)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 43, and a top view of FIG. 43 is represented as shown in FIG. A side view in the short side direction is represented as shown in FIG. 44 (b), and a bottom view of FIG. 43 is represented as shown in FIG. 44 (c).

  As shown in FIGS. 43 and 44 (a) to 44 (c), the inductance element 4 according to the fifth embodiment performs deep etching on the silicon substrate 112 from the surface of the silicon substrate 112. A through hole 114 penetrating the back surface, a lower core forming portion 116 formed on the surface of the silicon substrate 112, and a lower coil forming portion 118 formed on the back surface of the silicon substrate are provided.

(Structure of lower coil and upper / lower coil connection part)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 45, and a top view of FIG. 45 is represented as shown in FIG. 46 (a). A side view in the short side direction is represented as shown in FIG. 46B, and a bottom view of FIG. 45 is represented as shown in FIG.

  As shown in FIGS. 45 and 46A to 46C, the inductance element 4 according to the fifth embodiment performs a plating process on the through hole 114 and the lower coil forming portion 118. The upper and lower coil connecting portions 120 and the lower coil 122 are formed.

(Lower core structure)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 47, and a top view of FIG. 47 is represented as shown in FIG. 48 (a). A side view in the short side direction is represented as shown in FIG. 48B, and a bottom view of FIG. 47 is represented as shown in FIG.

  As shown in FIGS. 47 and 48 (a) to 48 (c), the inductance element 4 according to the fifth embodiment is formed by performing a plating process on the lower core forming portion 116. A core 124 is provided.

(Upper coil structure)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 49, and a top view of FIG. 49 is represented as shown in FIG. A side view in the short side direction is represented as shown in FIG. 50B, and a bottom view of FIG. 49 is represented as shown in FIG.

  As shown in FIG. 49 and FIGS. 50 (a) to 50 (c), the inductance element 4 according to the fifth embodiment includes upper and lower coils at both ends of the long side via an insulating layer 128 on the lower core 124. An upper coil 126 for connecting the connection parts 120 is provided. In the process of forming the upper coil 126, a photolithography and plating process of a thick film resist can be applied.

(Upper core structure)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 51, and a top view of FIG. 51 is represented as shown in FIG. 52 (a). The side view in the short side direction is represented as shown in FIG. 52 (b), and the bottom view of FIG. 51 is represented as shown in FIG. 52 (c). A side view seen from the long side direction of FIG. 51 is expressed as shown in FIG.

  The inductance element 4 according to the fifth embodiment includes an upper core 130 disposed on the upper coil 126 as shown in FIGS. 51, 52 (a) to 52 (c), and FIG. 53.

(Connection structure of upper core and lower core)
A configuration in which the upper core 130 and the lower core 124 are coupled to each other at the end of the upper coil 126 in the inductance element 4 according to the fifth embodiment is expressed as shown in FIG.

  In the inductance element 4 according to the fifth embodiment, a closed magnetic circuit 32R is formed between the upper core 130 and the lower core 124 by coupling the upper core 130 and the lower core 124 as shown in FIG. Is done.

  An enlarged view of a portion C in FIG. 54 is expressed as shown in FIG. As shown in FIG. 55 (a), the upper core 130 has a multilayer structure of, for example, 3 pairs (3P) of magnetic layers and insulating layers, and the lower core 124 has, for example, 8 pairs of (8P) magnetic layers and insulating layers. It has a multilayer structure.

  A schematic cross-sectional structure taken along line 13A-13A in FIG. 55A is represented as shown in FIG. The upper core 130 and the lower core 124 may have a multilayer structure of a magnetic layer and an insulating layer.

  The inductance element 4 according to the fifth embodiment may include an insulating layer 128 disposed on the surface of the substrate 112, and the lower core 124 and the upper core 130 may be stacked with the insulating layer 128 interposed therebetween. .

  As shown in FIG. 55B, the coupling structure of the upper core and the lower core is disposed in the lower core forming portion 116 of the substrate 112, and the lower core 124 having a multilayer structure of a magnetic layer and an insulating layer, and the lower core 124. An insulating layer 128 disposed thereon, an upper coil 126 disposed on the insulating layer 128, an upper surface and a side surface of the upper coil 126, an upper portion disposed on the insulating layer 128, and having a multilayer structure of a magnetic layer and an insulating layer A core 130.

(Production method)
The inductance element manufacturing method according to the fifth embodiment includes a substrate 112, an upper coil 126 disposed on the surface of the substrate 112, a lower coil 122 disposed on the back surface facing the surface of the substrate 112, and a substrate. 112, the upper and lower coil connecting portions 120 that penetrate from the front surface to the back surface and connect the upper coil 126 and the lower coil 122, the upper core 130 disposed on the surface of the upper coil 126, and between the upper coil 126 and the lower coil 122 In the inductance element including the lower core 124 disposed on the substrate 112, the step of processing the substrate 112, the step of forming the lower core 124, the lower coil 126 and the upper and lower coil connecting portions 120, and the upper coil 126 are formed. And a step of forming the upper core 130.

(Silicon substrate processing process)
With reference to FIGS. 56 to 59, the processing steps of the silicon substrate 112 will be described.

  In the silicon substrate processing step, the back surface wiring etching is performed on the back surface of the substrate 112, the lower coil forming portion 118 and a part of the through hole 114 are formed, and the through wiring etching is performed on the surface of the substrate 112. The step of forming the through hole 114 and the step of performing lower core etching on the surface of the substrate 112 to form the lower core forming portion 116 are included.

  FIG. 56A is a schematic plan view of the silicon substrate 112, which is one step of the method for manufacturing the inductance element 4 according to the fifth embodiment, and is represented by 14A in FIG. 56A. A schematic cross-sectional view along the line -14A is expressed as shown in FIG.

  Further, a schematic plan view of the silicon substrate 112 subjected to the back surface wiring etching is represented as shown in FIG. 57A, and a schematic cross-sectional view taken along the line 15A-15A in FIG. It is expressed as shown in (b).

  Further, a schematic plan view of the silicon substrate 112 subjected to the through wiring etching is expressed as shown in FIG. 58A, and a schematic cross-sectional view taken along the line 16A-16A in FIG. It is expressed as shown in (b).

Further, a schematic plan view of the silicon substrate 112 subjected to the lower core etching is represented as shown in FIG. 59A, and a schematic cross-sectional view taken along the line 17A-17A in FIG. It is expressed as shown in (b).
(A1) First, as shown in FIGS. 56A and 56B, a silicon substrate 112 is prepared.
(A2) Next, as shown in FIGS. 57 (a) and 57 (b), the back surface wiring etching is performed on the back surface of the silicon substrate 112 to form a part of the lower coil forming portion 118 and the through hole 114. To do.
(A3) Next, as shown in FIGS. 58A and 58B, through-hole etching is performed on the surface of the silicon substrate 112 to form through-holes 114.
(A4) Next, as shown in FIGS. 59 (a) and 59 (b), lower core etching is performed on the surface of the silicon substrate 112 to form a lower core forming portion 116.

  Here, in the case where a silicon substrate 112 of 10 Ω · cm or more or an insulating substrate such as glass or ferrite is applied as the substrate, the above steps may be used, but a silicon substrate 112 of 10 Ω · cm or less is applied as the substrate. In this case, it is necessary to form an insulating layer by thermal oxidation or CVD after forming the lower coil forming portion 118, the through hole 114, and the lower core forming portion 116.

(Manufacturing process of lower core, lower coil, and upper and lower coil connecting parts)
A manufacturing process of the lower core, the lower coil, and the upper and lower coil connecting portions will be described with reference to FIGS.

  The process of forming the lower core 124, the lower coil 122, and the upper and lower coil connecting portions 120 is performed for the plating process on the through hole 114, the lower coil forming portion 118, and the lower core forming portion 116 after the substrate 112 is processed. A step of forming the first seed 113, a first resist 125 is applied to the surface of the substrate 112 or a dry film is laminated, patterning is performed by photolithography, a plating formation step is performed on the lower core formation portion 116, and a lower core 124 is formed. And forming the upper and lower coil connecting portions 120 and the lower coil 122 by plating the through holes 114 and the lower coil forming portion 118 after removing the first resist 125 or the dry film.

  Schematic plan view of a silicon substrate 112 in which a seed is formed in the through hole 114, the lower coil forming portion 118, and the lower core forming portion 116, which is one step of the method for manufacturing an inductance element according to the fifth embodiment. Is represented as shown in FIG. 60 (a), and a schematic cross-sectional view taken along line 18A-18A in FIG. 60 (a) is represented as shown in FIG. 60 (b).

  Further, a schematic plan view of the silicon substrate on which the lower core 124 is formed by performing photolithography and plating is represented as shown in FIG. 61A, and is along the line 19A-19A in FIG. A schematic cross-sectional view is represented as shown in FIG.

Further, a schematic plan view of a silicon substrate on which plating is formed for the through hole 114 and the lower coil forming portion 118 is represented as shown in FIG. 62A, and is taken along the line 20A-20A in FIG. A schematic cross-sectional view is represented as shown in FIG.
(B1) After the processing step of the silicon substrate 112, first, as shown in FIGS. 60A and 60B, the through hole 114, the lower coil forming portion 118, and the lower core forming portion 116 are A step of forming a seed 113 for the plating step is performed.
(B2) Next, as shown in FIGS. 61 (a) and 61 (b), a first resist 125 is applied or a dry film is laminated on the surface of the silicon substrate, and patterned by photolithography to form a lower core forming portion. A plating process is performed on 116 to form the lower core 124. In forming the lower core 124, a multilayer structure of a magnetic layer and an insulating layer may be formed. Here, the magnetic layer can be formed by a sputtering technique, a vacuum deposition technique or the like in addition to the plating formation technique.
(B3) Next, as shown in FIGS. 62A and 62B, after removing the resist 125 or the dry film, plating is performed on the through hole 114 and the lower coil forming portion 118 to connect the upper and lower coils. The part 120 and the lower coil 122 are formed.

  Further, the step of forming the lower core 124 may include a step of forming a multilayer structure of a magnetic layer and an insulating layer.

(Upper coil manufacturing process)
The manufacturing process of the upper coil will be described with reference to FIGS.

  The step of forming the upper coil 126 includes a step of forming the first insulating layer 128 on the surface side of the substrate 112, a step of forming the first opening 128A for the first insulating layer 128, and the first opening 128A. A step of forming a second seed 129 on the entire surface of the substrate 112; a step of applying a second resist 131 to the second seed 129; and patterning by photolithography to form a second opening; And performing a plating process to form the upper coil 126.

  A schematic plan view of the silicon substrate, which is one step of the method of manufacturing an inductance element according to the fifth embodiment and has been subjected to the front and back polishing steps, is represented as shown in FIG. A schematic cross-sectional view taken along line 21A-21A in a) is expressed as shown in FIG.

  In addition, a schematic plan view of a silicon substrate that has been subjected to the surface-side insulating layer forming step is represented as shown in FIG. 64A, and a schematic cross-sectional view taken along the line 22A-22A in FIG. It is expressed as shown in FIG.

  Further, a schematic plan view of the silicon substrate that has been subjected to the opening forming step for the surface-side insulating layer is represented as shown in FIG. 65A, and is a schematic cross-sectional view taken along line 23A-23A in FIG. Is expressed as shown in FIG.

  A schematic plan view of the silicon substrate subjected to the upper coil seed formation step is represented as shown in FIG. 66 (a), and a schematic cross-sectional view taken along line 24A-24A in FIG. 66 (a) is shown in FIG. It is expressed as shown in (b).

  In addition, a schematic plan view of a silicon substrate subjected to a photolithography process for the upper coil is represented as shown in FIG. 67 (a), and is a schematic cross-sectional view taken along line 25A-25A in FIG. 67 (a). Is expressed as shown in FIG.

  Further, a schematic plan view of the silicon substrate subjected to the plating forming process for the upper coil is represented as shown in FIG. 68A, and is a schematic cross-sectional view taken along the line 26A-26A in FIG. Is expressed as shown in FIG.

  A schematic plan view of the silicon substrate on which the resist stripping process for the upper coil has been performed is expressed as shown in FIG. 69A, and is a schematic cross-sectional view taken along line 27A-27A in FIG. Is expressed as shown in FIG.

Further, a schematic plan view of the silicon substrate subjected to the seed removing process for the upper coil is represented as shown in FIG. 70 (a), and is a schematic cross-sectional view taken along the line 28A-28A in FIG. 70 (a). Is expressed as shown in FIG.
(C1) After the manufacturing process of the lower core 124, the lower coil 122, and the upper and lower coil connecting portions 120, as shown in FIG. 63 (a) and FIG. Layer 22M is removed.
(C2) Next, as shown in FIGS. 64A and 64B, an insulating layer 128 is formed on the surface side of the silicon substrate 112.
(C3) Next, as shown in FIGS. 65A and 65B, a step of forming an opening 128A for the insulating layer 128 is performed.
(C4) Next, as shown in FIGS. 66 (a) and 66 (b), a step of forming a seed 129 for the plating process for the upper coil is performed. Here, the seed 129 is formed on the entire surface of the silicon substrate including the opening 128 </ b> A with respect to the insulating layer 128.
(C5) Next, as shown in FIGS. 67 (a) and 67 (b), a resist 131 is applied on the seed 129 and patterned by photolithography to open an opening for plating the upper coil 126. Form.
(C6) Next, as shown in FIGS. 68A and 68B, a plating process is performed on the seed 129 to form the upper coil 126.
(C7) Next, as shown in FIGS. 69A and 69B, the resist 131 is removed.
(C8) Next, as shown in FIGS. 70A and 70B, the seed 129 used in the plating process of the upper coil 126 is removed, and the insulating layer 128 is exposed.

(Upper core manufacturing process)
The manufacturing process of the upper coil will be described with reference to FIGS.

  In the formation process of the upper core 130, after the formation process of the upper coil 126, a process of forming the second insulating layer 128C on the surfaces of the upper coil 126 and the substrate 112, and a third seed 130S on the second insulating layer 128C. Forming a third resist 133 on the third seed 130S, patterning by photolithography, forming a third opening, and performing a plating process on the third seed 130S, Forming a core 130.

  As shown in FIG. 71 (a), a schematic plan view of a silicon substrate, which is one step of the method of manufacturing an inductance element according to the fifth embodiment and has performed the insulating layer forming step for the upper core, is shown. A schematic cross-sectional view taken along line 29A-29A in FIG. 71 (a) is represented as shown in FIG. 71 (b).

  In addition, a schematic plan view of a silicon substrate that has been subjected to the seed formation process for the upper core is represented as shown in FIG. 72A, and is a schematic cross-sectional view taken along the line 30A-30A in FIG. Is expressed as shown in FIG.

  Further, a schematic plan view of a silicon substrate subjected to a photolithography process for the upper core is represented as shown in FIG. 73A, and is a schematic cross-sectional view taken along line 31A-31A in FIG. Is expressed as shown in FIG.

  Further, a schematic plan view of the silicon substrate subjected to the plating formation process for the upper core is represented as shown in FIG. 74A, and is a schematic cross-sectional view taken along the line 32A-32A in FIG. Is represented as shown in FIG.

  Further, a schematic plan view of the silicon substrate that has been subjected to the resist removal process for the upper core is represented as shown in FIG. 75A, and is a schematic cross-sectional view taken along line 33A-33A in FIG. Is represented as shown in FIG.

In addition, a schematic plan view of the silicon substrate that has been subjected to the seed removal process for the upper core is represented as shown in FIG. 76 (a), and is a schematic cross-sectional view taken along the line 34A-34A in FIG. 76 (a). Is represented as shown in FIG. 76 (b), and a schematic cross-sectional view taken along line 35A-35A of FIG. 76 (a) is represented as shown in FIG.
(D1) After the manufacturing process of the upper coil 126, as shown in FIGS. 71 (a) and 71 (b), insulation for the upper core (130) is formed on the surface of the upper coil 126 and the silicon substrate 112. Layer 128C is formed. Here, the insulating layer 128C is the same as the relatively thick insulating layer 128B embedded between the upper coils 126 shown in FIG.
(D2) Next, as shown in FIGS. 72A and 72B, a seed 130S for the upper core (130) is formed on the insulating layer 128C.
(D3) Next, as shown in FIGS. 73 (a) and 73 (b), a resist 133 is applied on the seed 130S and patterned by photolithography to open an opening for the plating process of the upper core 130. Form.
(D4) Next, as shown in FIGS. 74A and 74B, a plating process is performed on the seed 130 </ b> S to form the upper core 130. In forming the upper core 130, a multilayer structure of a magnetic layer and an insulating layer may be formed.
(D5) Next, as shown in FIGS. 75A and 75B, the resist 133 is removed.
(D6) Next, as shown in FIGS. 76 (a), 76 (b), and 77, the seed 130S used in the plating process of the upper core 130 is removed, and the insulating layer 128C is exposed. As a result of the above steps, a solenoid structure embedded in the silicon substrate 112 is formed.

  Further, the step of forming the upper core 130 may include a step of forming a multilayer structure of a magnetic layer and an insulating layer.

(Coil configuration)
In the inductance element according to the fifth embodiment, a schematic plan view showing the upper coil 126 and the lower coil 122 formed on the silicon substrate is expressed as shown in FIG. 78 (a), and FIG. 78 (a). A schematic cross-sectional view taken along line 36A-36A is represented as shown in FIG. 78 (b), and a schematic cross-sectional view taken along line 37A-37A in FIG. 78 (a) is represented as shown in FIG. Is done.

  As shown in FIGS. 78A, 78B and 79, the upper coil 126 and the lower coil 122 disposed on the front and back surfaces of the silicon substrate 112 are upper and lower coils formed at the end of the silicon substrate. The connection is made through the connection unit 120. For this reason, the inductance element according to the fifth embodiment has a solenoid structure.

(Core configuration)
In the inductance element according to the fifth embodiment, a schematic plan view showing the upper core 130 and the lower core 124 formed on the silicon substrate 112 is expressed as shown in FIG. ) Is a schematic cross-sectional view taken along line 38A-38A as shown in FIG. 80B, and a schematic cross-sectional view taken along line 39A-39A in FIG. 80A is shown in FIG. expressed.

  Since the lower core 124 arranged on the surface of the silicon substrate 112 and the upper core 130 arranged on the upper coil 126 are magnetically coupled at the end of the silicon substrate 112, a closed magnetic circuit is formed. For this reason, the inductance of the inductance element according to the fifth embodiment shows a relatively high value.

(Inductance frequency characteristics)
The frequency characteristic of the inductance L of the inductance element according to the fifth embodiment is expressed as shown in FIG. In FIG. 82, a curve SOL corresponds to the solenoid structure according to the fifth embodiment, and a curve SPI corresponds to the spiral structure according to the fourth embodiment.

  The frequency characteristic of the inductance L of the inductance element according to the fifth embodiment shows a substantially constant value in the measurement range of 100 kHz to 10 MHz, and the inductance value is compared with the spiral structure according to the fourth embodiment. The value is about double.

  The inductance L is proportional to the square of the number of coil turns N. For this reason, a solenoid structure having a large number of coil turns per unit area is advantageous in increasing the inductance value.

(Frequency characteristics of AC resistance)
The frequency characteristic of the AC resistance ACR of the inductance element according to the fifth embodiment is expressed as shown in FIG. In FIG. 83, the curve SOL corresponds to the solenoid structure according to the fifth embodiment, and the curve SPI corresponds to the spiral structure according to the fourth embodiment.

  The frequency characteristic of the AC resistance ACR of the inductance element according to the fifth embodiment shows substantially the same characteristics as the spiral structure according to the fourth embodiment in the measurement range of 100 kHz to 10 MHz.

  Most of the AC resistance is caused by eddy current loss that occurs when high-frequency magnetic flux enters the core. Eddy current loss can be reduced by narrowing the eddy current radius. In the solenoid structure, the eddy current radius can be controlled by making the core multi-layered, which is advantageous in suppressing the AC resistance ACR.

  In the inductance element according to the fifth embodiment, the inductance value can be increased with the AC resistance ACR substantially equivalent to the spiral structure according to the fourth embodiment.

(module)
A fourth in which an inductance element (L1) 130, an integrated circuit for control (IC: 140A), a load capacitor (C1) 150, and a snubber capacitor (CB) 180 are arranged on a printed circuit board (PCB) 100. The module according to the embodiment is schematically represented as shown in FIG.

  On the other hand, the inductance element L1 according to the fifth embodiment and the module according to the fifth embodiment in which the control IC 140A, the load capacitor (C1) 150, the snubber capacitor (CB) 180, etc. are arranged on the silicon substrate 110. Is schematically represented as shown in FIG. Here, the inductance element L1 according to the fifth embodiment is formed on the silicon substrate 110 (Si) and has a solenoid structure.

  A module according to the fourth embodiment in which an inductance element (L1) 130, a DC / DC converter IC 140B, a load capacitor (C1) 150, and a snubber capacitor (CB) 180 are arranged on the PCB 100 is schematically shown in FIG. It is expressed in

  On the other hand, a fifth embodiment in which an inductance element L1 according to the fifth embodiment formed on a silicon substrate, and a DC / DC converter IC 140B, a load capacitor (C1) 150, and a snubber capacitor (CB) 180 are arranged on the silicon substrate 110. A schematic side view (configuration example 1) of the module according to the embodiment is expressed as shown in FIG.

  An inductance element L1 according to the fifth embodiment is formed on a silicon substrate 110 (Si) and has a solenoid structure. As shown in FIG. 87, the inductance element L1 according to the fifth embodiment is formed in a silicon substrate 110 having a substrate thickness T1, and includes a DC / DC converter IC 140B, a load capacitor (C1) 150, and a snubber capacitor. (CB) 180 is disposed on a relatively thin silicon substrate 110 having a substrate thickness T2. For this reason, the module to which the inductance element according to the fifth embodiment is applied has a configuration advantageous for reducing the height.

  A fifth embodiment in which an inductance element L1 according to the fifth embodiment formed on the silicon substrate 110 and a control IC 140A, a load capacitor (C1) 150, and a snubber capacitor (CB) 180 are arranged on the silicon substrate 110. A schematic side view (configuration example 2) of the module according to FIG. 8 is expressed as shown in FIG. The configuration example 2 in FIG. 88 uses a relatively thin silicon substrate 110 and has a configuration advantageous for reducing the height. In the configuration example 2 of FIG. 88, since the inductance element L1 is built in the silicon substrate 110, the area can be reduced in addition to the reduction in the height of the module.

  Also, a schematic diagram of a module according to the fifth embodiment in which the inductance element L1 according to the fifth embodiment formed on the silicon substrate 110 and the control IC 140A and the load capacitor (C1) 150 are arranged on the silicon substrate 110. A schematic side view (Configuration Example 3) is expressed as shown in FIG. In the configuration example 3 in FIG. 89, the snubber capacitor (CB) is omitted. Similarly, the configuration example 3 in FIG. 89 also has a configuration that is advantageous in reducing the height by applying the relatively thin silicon substrate 110. In the configuration example 3 of FIG. 89, since the inductance element L1 is built in the silicon substrate 110, the area can be reduced in addition to the reduction in the height of the module.

(DC / DC converter and output load circuit)
Further, the connection configuration between the DC / DC converter (DCDC) in which the inductance element according to the fifth embodiment is applied to the output load circuit and the whole is mounted on the silicon substrate 110 and the output load circuit is as shown in FIG. Represented.

As shown in FIG. 90, an example of an output circuit of the DC / DC converter (DCDC) has a complementary circuit configuration including a p-channel MOSFET Q _p 1 and an n-channel MOSFET Q _n 1. The source of the p-channel MOSFET Q _p 1 is connected to the power supply pin P, and the source of the n-channel MOSFET Q _n 1 is connected to the GND pin N. The output of the DC / DC converter is taken out from the drain of the p-channel MOSFET Q _p 1 and the drain of the n-channel MOSFET Q _n 1.

The output of the DC / DC converter is connected to the external lead pin P1, and the external lead pin P1 is further connected to one electrode of the inductance L1 via the power wiring LX1. Further, the load capacitor C1 is connected between the other electrode of the inductance L1 and the ground potential, and the output voltage _Vout1 is taken _out from both ends of the load capacitor C1.

As shown in FIG. 90, a snubber capacitor CB1 is connected between the power supply pin P and the GND pin N of the DC / DC converter. As shown in FIG. 90, the power wiring LX1 connected to the external lead pin P1 has a parasitic wiring inductance L _p1 and a wiring resistance R _p1 . Therefore, as shown in FIG. 90, the output load circuit connected to the external lead pin P1 of the DC / DC converter is composed of a wiring inductance L _p 1, a wiring resistance R _p 1, an inductance L 1, and a load capacitor C 1.

  The inductance element according to the fifth embodiment can be applied to the inductance L1 constituting the output load circuit, and is formed on the silicon substrate 110.

  Also, the DC / DC converter (DCDC) can be mounted on the silicon substrate 110 as shown in FIG.

  The load capacitor C1 and the snubber capacitor CB1 can also be mounted on the silicon substrate 110 as shown in FIG.

  According to the fifth embodiment, an inductance element with reduced magnetic resistance, eddy current loss, AC resistance, high inductance, and excellent high frequency characteristics, a method for manufacturing the inductance element, and a module to which the inductance element is applied are provided. Can be provided.

[Sixth embodiment]
(Configuration of substrate with built-in electrode)
FIG. 91A is a schematic plane pattern configuration diagram of the electrode built-in substrate according to the sixth embodiment, and an example in which the beam portions include stripe patterns parallel to each other in plan view is represented as shown in FIG. An example in which the beam portions are provided with stripe patterns intersecting each other at a predetermined angle θ in plan view is represented as shown in FIG.

  In addition, a schematic cross-sectional structure taken along line 40A-40A in FIG. 91A is represented as shown in FIG. 92A, and a schematic cross-sectional structure taken along line 41A-41A in FIG. It is expressed as shown in FIG.

As shown in FIGS. 91 to 92, the electrode built-in substrate 1 according to the sixth embodiment includes a substrate 212, grooves 225 ₁ , 225 ₂ , 225 ₃ formed inside the substrate 212, and Beam portions 228 ₁ , 228 _2, and 228 ₃ disposed on the back surface facing the front surface, and wiring layers 226 ₁ , 226 _2, and 226 ₃ embedded in the groove portions 225 ₁ , 225 _2, and 225 ₃ are provided. Here, wiring layers 226 ₁ , 226 _2, and 226 ₃ are formed in the grooves 225 ₁ , 225 _2, and 225 ₃ formed inside the substrate 212 by embedding a metal such as copper (Cu).

Further, as shown in FIG. 91A, the beam portions 228 ₁ , 228 _2, and 228 ₃ have stripe patterns that are orthogonal to the wiring layers 226 ₁ , 226 _2, and 226 ₃ in a plan view and are parallel to each other. .

Further, as shown in FIG. 91B, the beam portions 228 ₁ and 228 ₂ may be provided with a stripe pattern that intersects with each other at a predetermined angle θ in plan view.

Further, as shown in FIG. 92A, the thickness TB of the beam portions 228 ₁ , 228 _2, and 228 ₃ is formed thinner than the depth TD of the groove portion. Further, the beam portions 228 ₁ , 228 _2, and 228 ₃ have widths W 1, W 2, and W 3, respectively, as shown in FIGS.

Further, the groove portions 225 ₁ , 225 ₂ , 225 ₃ , the beam portions 228 ₁ , 228 ₂ , 228 ₃ or the wiring layers 226 ₁ , 226 ₂ , 226 ₃ are rectangular, circular, elliptical, octagonal, triangular in plan view. Or may have a polygonal pattern.

  Further, for example, when the trench and the wiring layer have stripe patterns that are parallel to each other and intersect each other at 90 ° in plan view, an electrode-embedded substrate for an inductance element as shown in FIG. Can do.

  In the electrode built-in substrate 1 according to the sixth embodiment, the substrate 212 may include a silicon substrate or a glass substrate.

  Further, a schematic planar pattern of the electrode built-in substrate 1 according to the sixth embodiment, which has a relatively long line and space (L & S) formed on the silicon wafer 222. The structure is represented as shown in FIG. 93, and the schematic cross-sectional structure taken along line 42A-42A in FIG. 93 is represented as shown in FIG. 94A, and schematically shown along line 43A-43A in FIG. The cross-sectional structure is expressed as shown in FIG.

As shown in FIGS. 93 to 94, the electrode built-in substrate 1 according to the sixth embodiment includes a silicon wafer 222 and grooves 225 ₁ , 225 ₂ , 225 ₃ ,... Formed in the silicon wafer 222. 225 _n , wiring portions 226 ₁ , 226 embedded in the grooves 225 ₁ , 225 ₂ , 225 ₃ ,... 225 _n and the beam portions 228 ₁ , 228 ₂ disposed on the back surface facing the front surface of the silicon wafer 222. and a _{2 · 226 3 · ... · 226} n. Here, the trenches 225 ₁ , 225 ₂ , 225 ₃ ,..., 225 _n formed inside the silicon wafer 222 are filled with a metal such as copper (Cu) to thereby form the wiring layers 226 ₁ , 226 ₂ , 226. ₃ ... 226 _n are formed.

Further, as shown in FIG. 93, the beam portions 228 ₁ and 228 ₂ have a parallel stripe pattern in plan view.

Further, as shown in FIG. 94 (a), the thickness TB of the beam portion 228 ₁ is formed thinner than the depth TD of the groove.

  A schematic planar pattern configuration of an electrode built-in substrate 1B according to the fourth embodiment, which is an electrode built-in substrate 1B having a relatively long line and space (L & S) formed on a silicon wafer 222, is as follows. 95 is represented as shown in FIG.

The electrode-embedded substrate 1B according to Comparative Example 5 includes a silicon wafer 222 and wiring layers 226 ₁ 226 ₂ 226 ₃ ... 226 _n embedded in through holes formed in the silicon wafer 222. since having no beam portion structure, as shown in broken line ST portion of FIG. 95 (a), sticking tends to occur where the line between the wiring layers _{226 1 · 226 2 · 226 3} · ... · 226 n are in contact.

  On the other hand, a schematic planar pattern configuration of the electrode built-in substrate 1 according to the sixth embodiment and having a relatively long line and space formed on the silicon wafer 222 is shown in FIG. ).

The electrode-embedded substrate 1 according to the sixth embodiment includes a silicon wafer 222 and wiring layers 226 ₁ , 226 ₂ , 226 ₃ ,... 226 _n embedded in through holes formed inside the silicon wafer 222. 95. As shown in FIG. 95 (b), the wiring layers 226 ₁ , 226 ₂ , 226 ₃ ... Are provided with the beam portions 228 ₁ and 228 ₂ having stripe patterns that intersect each other at a predetermined angle θ in plan view. -It is possible to suppress the occurrence of sticking where 226 _n lines contact each other.

  Further, a schematic planar pattern configuration of the electrode built-in substrate 1B according to the comparative example 5 and having the spiral-shaped inductance element formed on the silicon substrate 212 is expressed as shown in FIG. .

  As shown in FIG. 96, in the electrode built-in substrate 1B according to Comparative Example 5, since the wiring layer 226 embedded in the through hole is formed in a coil shape, the silicon substrate 212 is formed in the state where the groove portion of the through hole is formed. Since only the A portion of the circle indicated by the broken line in FIG. 96 is supported, the manufacturing reliability tends to be lowered.

  The electrode built-in substrate according to the sixth embodiment can be formed, for example, by forming a groove portion in a silicon substrate and embedding copper in the groove portion, so that a spiral coil structure can be easily realized inside the silicon substrate. is there.

  The electrode-embedded substrate according to the sixth embodiment can be applied to LSI stacked modules, interposers, inductance elements, shield substrates, and the like, as will be described later.

  The electrode built-in substrate according to the sixth embodiment can form the electrode built-in substrate structure by two-step etching of the substrate. In addition, since the back surface has, for example, a lattice-like beam structure, sticking in which lines come into contact with each other is difficult to occur even if the line and space (L & S) of the electrode wiring layer is increased.

  Moreover, since the electrode built-in substrate according to the sixth embodiment has a penetrating structure other than the beam portion, it is easy to fill with metal plating such as copper.

  In the sixth embodiment, it is possible to provide a substrate with a built-in electrode that has a simple structure and is unlikely to cause sticking in which lines come into contact with each other and can improve reliability.

(Method for manufacturing electrode-embedded substrate)
In the electrode built-in substrate 1 according to the sixth embodiment, a schematic surface pattern configuration is expressed as shown in FIG. 97A, and is a schematic cross section taken along line 44A-44A in FIG. 97A. The structure is represented as shown in FIG. 97 (b), and the schematic cross-sectional structure diagram taken along the line 45A-45A in FIG. 97 (a) is represented as shown in FIG. 97 (c). ) Is represented as shown in FIG. 97 (d). FIG. 97 (b) also corresponds to the schematic cross-sectional structure along the line 44A-44A in FIG. 97 (d). FIG. 97C also corresponds to a schematic cross-sectional structure along the line 45A-45A in FIG.

As shown in FIGS. 97A to 97D, the electrode built-in substrate 1 according to the sixth embodiment includes a substrate 212 and groove portions 225 ₁ 225 ₂ 225 formed inside the substrate 212. and _{3-225 4-225 5,} the beam portions 228 _1, 228 _2, 228 ₃ that is disposed on the rear surface opposite to the surface of the substrate 212, embedded in the groove portion 225 _1, 225 _2, 225 _3, 225 _4, 225 ₅ Wiring layers 226 ₁ 226 ₂ 226 ₃ 226 ₄ 226 ₅ are provided. Here, the trenches 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ formed inside the substrate 212 are filled with a metal such as copper (Cu) to thereby form the wiring layers 226 ₁ , 226 _2, and 226. ₃ · 226 ₄ · 226 ₅ are formed.

Further, as shown in FIGS. 97 (a) and 97 (d), the beam portions 228 ₁ , 228 ₂ and 228 ₃ are connected to the wiring layers 226 ₁ , 226 ₂ , 226 ₃ , 226 ₄ and 226 ₅ in a plan view. The stripe pattern is orthogonal and parallel to each other. Although not shown, the beam portion may be provided with a stripe pattern that intersects with each other at a predetermined angle θ in plan view, as in FIG. 91 (b).

As shown in FIG. 97 (b), the thickness TB of the beam portions 228 ₁ , 228 ₂ and 228 ₃ is formed thinner than the depth TD of the groove portion. Further, the thickness T of the substrate 212 is equal to TB + TD.

97D, the line widths of the wiring layers 226 ₁ 226 ₂ 226 ₃ 226 ₄ 226 ₅ are equal to Y, and the space width is equal to X.

  A manufacturing method of the electrode built-in substrate according to the sixth embodiment shown in FIG. 97 will be described with reference to FIGS.

The manufacturing method of the electrode built-in substrate according to the sixth embodiment includes the step of forming the grooves 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ inside the substrate 212 and the back surface facing the surface of the substrate 212. in forming a beam portion 228 _1, 228 _2, 228 _3, a wiring layer 226 _1, 226 _2, 226 _3, 226 _4, 226 ₅ to the groove 225 _{1-225 2-225 3-225 4-225 5} Embedding and forming.

  FIG. 98A shows a schematic surface pattern configuration at the start of the process, which is one step in the method of manufacturing the electrode built-in substrate according to the sixth embodiment. A schematic cross-sectional structure along the line 46A-46A is expressed as shown in FIG. 98 (b), and a schematic back surface pattern configuration corresponding to FIG. 98 (a) is expressed as shown in FIG. 98 (c). The FIG. 98 (b) also corresponds to the schematic cross-sectional structure along the line 46A-46A in FIG. 98 (c).

  FIG. 99 (a) shows a schematic surface pattern configuration in one step of the method of manufacturing the electrode built-in substrate according to the sixth embodiment, in the photolithography process on the upper surface. ) Of 47A-47A is represented by a schematic cross-sectional structure as shown in FIG. 99 (b), and a schematic back surface pattern configuration corresponding to FIG. 99 (a) is shown in FIG. 99 (c). expressed. FIG. 99 (b) also corresponds to a schematic cross-sectional structure taken along the line 47A-47A in FIG. 99 (c).

  FIG. 100 (a) shows a schematic surface pattern configuration in the upper surface etching process, which is one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment. A schematic cross-sectional structure taken along line 48A-48A is represented as shown in FIG. 100 (b), and a schematic back surface pattern configuration corresponding to FIG. 100 (a) is represented as shown in FIG. 100 (c). Is done. FIG. 100B also corresponds to a schematic cross-sectional structure along the line 48A-48A in FIG.

  FIG. 101 (a) shows a schematic surface pattern configuration in one step of the method of manufacturing the electrode built-in substrate according to the sixth embodiment in the resist stripping process on the upper surface. ) In FIG. 101 (b), and a schematic back surface pattern configuration corresponding to FIG. 101 (a) is shown in FIG. 101 (c). expressed. FIG. 101 (b) also corresponds to a schematic cross-sectional structure along the line 49A-49A in FIG. 101 (c).

(Groove formation process)
(A1) First, as shown in FIGS. 98A to 98C, a substrate 212 is prepared. The substrate 212 may include a silicon substrate or a glass substrate.
(A2) Next, as shown in FIGS. 99 (a) to 99 (c), a resist 214 is applied on the surface of the silicon substrate 212 and patterned by a photolithography process.
(A3) Next, as shown in FIGS. 100A to 100C, etching is performed on the surface of the silicon substrate 212 to form grooves 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ . To do.
(A4) Next, as shown in FIGS. 101A to 101C, the resist 214 on the surface of the substrate 212 is removed. Here, as shown in FIGS. 100 (b) and 101 (b), the width of the grooves 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ is represented by Y, and the grooves 225 ₁ , 225 _2, and 225 are displayed. The width between ₃ · 225 ₄ · 225 ₅ is represented by X. The depths of the groove portions 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ are represented by TD. Further, the thickness of the substrate 212 to be a thinned beam portion is represented by TB. The thickness TB is formed thinner than the depth TD of the groove.

Here, when an insulating substrate such as a glass substrate is applied as the substrate 212, the above steps may be performed. However, when a silicon substrate is applied as the substrate 212, the grooves 225 ₁ , 225 ₂ , 225 ₃ , After forming 225 ₄ 225 ₅ , it is necessary to form an insulating layer by thermal oxidation or chemical vapor deposition (CVD).

(Beam formation process)
FIG. 102A shows a schematic surface pattern configuration in a lower surface photolithography process, which is one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment. ) Is represented as shown in FIG. 102 (b), and the schematic sectional structure taken along line 51A-51A in FIG. 102 (a) is shown in FIG. 102 (c). A schematic back surface pattern configuration corresponding to FIG. 102 (a) is represented as shown in FIG. 102 (d). FIG. 102 (b) also corresponds to a schematic cross-sectional structure along the line 50A-50A in FIG. 102 (d). FIG. 102 (c) also corresponds to a schematic cross-sectional structure along the line 51A-51A in FIG. 102 (d).

  FIG. 103 (a) shows a schematic surface pattern configuration in the bottom surface etching step, which is one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment. A schematic cross-sectional structure taken along line 52A-52A is represented as shown in FIG. 103 (b), and a schematic cross-sectional structure taken along line 53A-53 in FIG. 103 (a) is shown in FIG. 103 (c). A schematic back surface pattern configuration corresponding to FIG. 103A is represented as shown in FIG. 103D. FIG. 103 (b) also corresponds to a schematic cross-sectional structure along the line 52A-52A in FIG. 103 (d). FIG. 103 (c) also corresponds to the schematic cross-sectional structure along the line 53A-53 in FIG. 103 (d).

FIG. 104 (a) shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment, in the resist removing process on the lower surface. ) Is a schematic cross-sectional structure taken along line 54A-54A as shown in FIG. 104 (b), and a schematic cross-sectional structure taken along line 55A-55A in FIG. 104 (a) is shown in FIG. 104 (c). A schematic back surface pattern configuration corresponding to FIG. 104 (a) is represented as shown in FIG. 104 (d). FIG. 104 (b) also corresponds to the schematic cross-sectional structure along the line 54A-54A in FIG. 104 (d). FIG. 104C also corresponds to a schematic cross-sectional structure along the line 55A-55A in FIG.
(B1) Next, as shown in FIGS. 102A to 102D, a resist 216 is applied on the back surface of the substrate 212 and patterned by a photolithography process. Here, as shown in FIG. 102C, the opening width Y ₂ of the lower resist 216 is relatively smaller than the opening width of the upper resist 214 (corresponding to Y ₁ in FIG. 102C). It is desirable to set it narrowly. For example, the opening widths Y ₁ and Y ₂ are 50 μm and 30 μm. This is to suppress the occurrence of a step due to the misalignment.
(B2) Next, as shown in FIGS. 103A to 103D, etching is performed on the back surface of the substrate 212 to form through-grooves 227 ₁ 227 ₂ 227 ₃ 227 ₄ 227 ₅ Thus, the beam portions 228 ₁ 228 ₂ 228 ₃ are formed. By setting a relatively narrow opening width Y ₂ of the lower part of the resist 216, the substrate 212, the stepped structure as shown in FIG. 103 (c) it is formed. In the following steps, the same structure is maintained.
(B3) Next, as shown in FIGS. 104A to 104D, the resist 216 on the back surface of the substrate 212 is removed. Here, as shown in FIGS. 104 (b) and 104 (c), the widths of the groove portions 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ are represented by Y, and the groove portions 225 ₁ , 225 _2, and 225 are displayed. The width between ₃ · 225 ₄ · 225 ₅ is represented by X. The depths of the groove portions 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ are represented by TD. Moreover, the thickness of the silicon substrate 212 part used as the beam parts 228 ₁ 228 ₂ 228 ₃ is represented by TB. The thickness TB is formed thinner than the depth TD of the groove. In the case of a silicon substrate, an insulating layer can be formed on the entire substrate by performing a thermal oxidation process.

(Wiring layer embedding process)
A schematic surface pattern configuration in the metal (Cu) plating embedding step, which is one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment, is expressed as shown in FIG. A schematic cross-sectional structure taken along line 56A-56A in (a) is represented as shown in FIG. 105 (b), and a schematic cross-sectional structure taken along line 57A-57A in FIG. 105 (a) is shown in FIG. ) And a schematic back surface pattern configuration corresponding to FIG. 105 (a) is represented as shown in FIG. 105 (d). FIG. 105 (b) also corresponds to the schematic cross-sectional structure along the line 56A-56A in FIG. 105 (d). FIG. 105C also corresponds to a schematic cross-sectional structure taken along line 57A-57A in FIG.

FIG. 106 (a) shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode built-in substrate according to the sixth embodiment, in the metal (Cu) plating polishing step on the upper surface and the lower surface. A schematic cross-sectional structure taken along line 58A-58A in FIG. 106 (a) is represented as shown in FIG. 106 (b), and a schematic cross-sectional structure taken along line 59A-59A in FIG. A schematic back surface pattern configuration represented as shown in FIG. 106 (c) and corresponding to FIG. 106 (a) is represented as shown in FIG. 106 (d). FIG. 106 (b) also corresponds to a schematic cross-sectional structure along the line 58A-58A in FIG. 106 (d). FIG. 106C also corresponds to a schematic cross-sectional structure taken along the line 59A-59A in FIG.
(C1) Next, as shown in FIGS. 105 (a) to 105 (d), a metal plating layer 226U is formed from the surface side of the substrate 212 with respect to the grooves 225 ₁ , 225 ₂ , 225 ₃ , 225 _4, and 225 ₅ . The metal plating layers 226U and 226D are formed on the through-groove portions 227 ₁ , 227 ₂ , 227 ₃ , 227 _4, and 227 ₅ from the front surface side and the back surface side of the substrate 212. The metal plating layers 226U and 226D may include, for example, a Cu plating layer. In addition, although illustration is abbreviate | omitted, all perform the process of forming the seed layer for formation of a plating layer as a pre-process of the process of forming metal plating layer 226U * 226D. In the seed layer forming process, a CVD technique, a sputtering technique, a vapor deposition technique, an electroless plating technique, or the like can be applied.

Here, when an insulating substrate such as a glass substrate is applied as the substrate 212, the above steps may be performed. However, when a silicon substrate is applied as the substrate 212, the grooves 225 ₁ , 225 ₂ , 225 ₃ , 225 ₄ 225 ₅ and through-grooves 227 ₁ 227 ₂ 227 ₃ 227 ₄ 227 ₅ are formed, an insulating layer is formed by thermal oxidation or CVD, and then the metal plating layers 226U 226D are formed. To implement.
(C2) Next, as shown in FIGS. 106 (a) to 106 (d), the polishing process of the metal plating layers 226U and 226D is performed on the front surface and the back surface of the substrate 212, so that the grooves 225 ₁ 225 _2. The wiring layers 226 ₁ , 226 ₂ , 226 ₃ , 226 _4, and 226 ₅ embedded in the 225 ₃ , 225 ₄ , 225 ₅ and the through-groove portions 227 ₁ , 227 ₂ , 227 ₃ , 227 _4, and 227 ₅ are formed. Here, as the polishing process, a chemical mechanical polishing (CMP) technique may be applied.

(Comparison between inductance element of silicon substrate method and permalloy substrate method)
A schematic cross-sectional structure of a silicon substrate type inductance element formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG. A schematic cross-sectional structure (structure example without back surface polishing) of a permalloy substrate type inductance element according to Comparative Example 6 is represented as shown in FIG. 108 (a), and a structure example with back surface polishing is shown in FIG. It can be expressed as shown in (b). In FIG. 107, the beam structure will be described later with reference to FIG.

  A silicon substrate type inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment is embedded in a substrate 212 and a groove formed in the substrate 212 as shown in FIG. Wiring layer 226, insulating layer 230S disposed on the side surface of wiring layer 226, insulating layer 230U disposed on the surface of wiring layer 226, insulating layer 230D disposed on the back surface of wiring layer 226, and insulating layer 230U And a magnetic layer 10D disposed under the insulating layer 230D. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element 232.

  In the silicon substrate method, a coil having a high density and a large cross-sectional area can be formed by deep etching and through silicon via (TSV) technology. Since the silicon substrate is a non-magnetic substrate, the magnetic resistance is large and the inductance value is relatively small compared to the permalloy method, but magnetic saturation is less likely to occur, which is advantageous for increasing the current.

  As shown in FIG. 108 (a), a schematic cross-sectional structure of the permalloy substrate type inductance element according to Comparative Example 6 (structure example without back surface polishing) was formed inside the permalloy substrate 120P and the permalloy substrate 120P. The wiring layer 262 embedded in the groove, the insulating layer 320S disposed on the side surface / bottom surface of the wiring layer 262, the insulating layer 320U disposed on the surface of the wiring layer 262, and the magnetic layer 102U disposed on the insulating layer 320U With. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element 232.

  As shown in FIG. 108B, a schematic cross-sectional structure of the permalloy substrate type inductance element according to Comparative Example 6 (structure example with backside polishing) was formed inside the permalloy substrate 120P and the permalloy substrate 120P. A wiring layer 262 embedded in the groove, an insulating layer 320S disposed on the side surface of the wiring layer 262; an insulating layer 320D disposed on the bottom surface of the wiring layer 262; an insulating layer 320U disposed on the surface of the wiring layer 262; A magnetic layer 102U disposed on the layer 320U and a magnetic layer 102D disposed on the insulating layer 320D. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element.

  In the permalloy substrate system, wet etching is applied to process the permalloy, which is disadvantageous for increasing the density and the cross-sectional area of the coil. On the other hand, since the permalloy substrate is a magnetic substrate, the magnetic resistance is small and the inductance value is large.

(Configuration of inductance element)
A schematic bird's-eye view configuration of the inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG. 109 (a), and 60A-60A in FIG. 109 (a). A schematic cross-sectional structure along the line is represented as shown in FIG.

  As shown in FIG. 109, an inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment includes a substrate 212 and a wiring layer 226 embedded in a groove formed inside the substrate 212. The insulating layer 230S disposed on the side surface of the wiring layer 226, the insulating layer 230U disposed on the front surface of the wiring layer 226, the insulating layer 230D disposed on the back surface of the wiring layer 226, and the insulating layer 230U. The magnetic layer 10 </ b> U and the magnetic layer 10 </ b> D disposed under the insulating layer 230 </ b> D are provided.

  In the inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment, the wiring layer 226 embedded in the groove may have a coil shape as shown in FIG.

  Also, as shown in FIG. 109, an upper core (230U · 10U) disposed on the surface of the substrate 212 may be provided.

  Further, as shown in FIG. 109, a lower core (230D / 10D) disposed on the back surface of the substrate 212 may be provided.

  Further, the upper core (230U · 10U) and the lower core (230D · 10D) may have a multilayer structure of the magnetic layers 10U · 10D and the insulating layers 230U · 230D.

  Furthermore, as shown in FIG. 109, the slit SL which divides | segments an upper core (230U * 10U) and a lower core (230D * 10D) into plurality may be provided. With this slit structure, eddy current loss can be reduced. The magnetic layers 10U and 10D may include a ferromagnetic material such as permalloy or ferrite.

  The insulating layers 230U and 230D may include any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material. Further, the eddy current radius in the magnetic layers 10U and 10D can be controlled by dividing the magnetic layers 10U and 10D by the thickness of the magnetic layers 10U and 10D and the slit SL.

(Inductance element manufacturing method: upper core / lower core formation process)
In addition to the manufacturing process of the electrode-embedded substrate 1 according to the sixth embodiment described above, the method for manufacturing an inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment is described with reference to FIG. 109 (b), a process of forming an upper core (230U · 10U) on the surface of the substrate 212, and a process of forming a lower core (230D · 10D) on the back surface facing the surface of the substrate 212; You may have.
(D1) As shown in FIGS. 107 and 109 (b), the substrate 212 is formed on the electrode built-in substrate 1 formed by performing the manufacturing process of the electrode built-in substrate 1 according to the sixth embodiment. Insulating layers 230U and 230D are formed on the front surface and back surface.
(D2) Next, as shown in FIGS. 107 and 109 (b), the magnetic layer 10U is formed on the insulating layer 230U, and the upper core (230U · 10U) is formed.
(D3) Next, as shown in FIGS. 107 and 109 (b), the magnetic layer 10D is formed under the insulating layer 230D to form the lower core (230D and 10D).

  In forming the upper core (230U · 10U) and the lower core (230D · 10D), a multilayer structure of a magnetic layer and an insulating layer may be formed. Here, the magnetic layer can be formed by a plating technique, a sputtering technique, a vacuum deposition technique, or the like.

  An inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment, and a schematic bird's-eye view configuration of the wiring layer portion is expressed as shown in FIG. The front surface configuration of (a) is represented as shown in FIG. 110 (b), and the back surface configuration of FIG. 110 (a) is represented as shown in FIG. 110 (c).

  Furthermore, the cross-sectional bird's-eye view configuration along the 61A-61A line in the central portion of FIG. 110 (a) is represented as shown in FIG. 111 (a), and the cross-sectional configuration viewed from the direction of arrow B1 in FIG. 21 (b), and an enlarged view of the portion C1 in FIG. 111 (b) is represented as shown in FIG. 111 (c).

  Moreover, the cross-sectional bird's-eye view configuration along line 62A-62A in FIG. 110 (a) is represented as shown in FIG. 112 (a), and the cross-sectional configuration viewed from the direction of arrow B2 in FIG. b), and an enlarged view of a portion C2 in FIG. 112 (b) is represented as shown in FIG. 112 (c).

  Further, the front-side schematic bird's-eye view configuration of only the silicon substrate of FIG. 110 (a) is represented as shown in FIG. 113 (a), and the rear-side schematic bird's-eye view configuration of FIG. ).

  The inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment is formed by performing two-step etching and Cu plating technology on the silicon substrate 212. As shown in FIGS. 110 (a) and 113 (a), the size of the silicon substrate 212 is represented by LX · LY. As a specific numerical example, LX and LY are both about 4.2 mm.

  In addition, the inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment has a lattice structure beam on the back surface of the silicon substrate 212 as shown in FIGS. 110 (c) and 113 (b). Part 228. Here, the width of the cross portion of the lattice of the beam portion 228 is represented by ΔB, and the width of the frame portion of the lattice is represented by ΔEX · ΔEY. As specific numerical examples, ΔB, ΔEX, and ΔEY are all about 100 μm.

  In addition, as shown in FIG. 111C, the line and space of the wiring layer 226 pattern is represented by Y and X, the depth of the wiring layer 226 is represented by TD, and the thickness of the beam portion 228 is represented by TB. Is done. As a specific numerical example, the line width Y of the wiring layer 226 is about 50 μm, the interval X is about 15 μm, the depth TD of the wiring layer 226 is about 300 μm, and the thickness TB of the beam portion 228 is about 50 μm.

  In addition, as shown in FIG. 112 (c), the width of the beam portion 228 at the center of the substrate 212 is represented by WB. This WB is equal to ΔB in FIGS. 110 (c) and 113 (b) and is about 100 μm.

  In the inductance element 232 formed by applying the electrode built-in substrate according to the sixth embodiment, an inductance element built in the silicon substrate is formed. Therefore, a DC / DC in which an IC or a capacitor is arranged on the electrode built-in substrate. It can be applied to converters. Further, by forming the magnetic layers 10U and 10D above and below the electrode-embedded substrate, it is possible to reduce the influence of noise on the IC and the capacitor.

(Beam structure)
FIG. 14 is a schematic plan view of a structure of a beam portion 228 applicable to an electrode built-in substrate according to a sixth embodiment, and a cross-shaped configuration example is represented as shown in FIG. An example is represented as shown in FIG. 114 (b), a diagonal cross type configuration example is represented as shown in FIG. 114 (c), and a circular / cross composite configuration example is shown in FIG. 114 (d). It is expressed as shown in

  As shown in FIG. 114, the structure of the beam portion 228 applicable to the electrode built-in substrate according to the sixth embodiment has a cross shape, a lattice type, a diagonal cross type, and a circular / cross composite type in plan view. Any of these patterns may be provided. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  Further, in the electrode built-in substrate according to the sixth embodiment, the groove portion or the wiring layer also has a cross shape, a lattice shape, a diagonal cross shape, a circular / cross composite shape, a rectangular shape, a circular shape, and a beam shape. You may have any pattern, such as an ellipse, an octagon, a triangle, or a polygon.

(Inductance frequency characteristics)
The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG.

  In addition, the simulation result of the frequency characteristic of the AC resistance ACR of the inductance element formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG.

  115 and 116, the “air core” curve represented by the plot corresponds to the structure including the insulating layers 230U and 230D above and below the electrode-embedded substrate, and the “magnetic layer” represented by the plot ▲. The curve corresponds to the structure having the magnetic layers 10U and 10D above and below the insulating layers 230U and 230D, and the “magnetic layer & slit” curve represented by the plot ■ further forms a slit SL in the magnetic layers 10U and 10D. It corresponds to the structure.

  The frequency characteristic of the inductance L of the inductance element according to the sixth embodiment shows a substantially constant value in the measurement range of 100 kHz to 10 MHz. The inductance L can be increased by forming the magnetic layers 10U and 10D.

  The frequency characteristic of the AC resistance ACR of the inductance element according to the sixth embodiment shows a relatively low AC resistance ACR value in the measurement range of 100 kHz to 10 MHz. In particular, by forming the slit SL, a relatively low AC resistance ACR can be obtained as compared with the case of only the magnetic layers 10U and 10D.

(module)
-Comparative Example 7-
A mounting configuration example of the DC / DC converter module according to Comparative Example 7 is expressed as shown in FIG. In the DC / DC converter module according to Comparative Example 7, since the inductance element 234, the IC 236, and the capacitors 340 ₁ and 340 ₂ are mounted on the printed circuit board 238, it is difficult to reduce the mounting area.

-Configuration example 1-
The integrated circuit block configuration of Configuration Example 1 of the DC / DC converter module 3 according to the sixth embodiment is expressed as shown in FIG. In FIG. 118, a terminal A1: VIN is a power supply terminal to which the DC / DC converter input voltage VIN of the voltage E is input, a terminal A2: EN is an enable terminal, and a terminal A3: GND is a ground terminal. Terminal B1: LX represents an inductor connection terminal, terminal B2: FB represents an output voltage feedback input terminal, and terminal B3: MODE represents a DE / PFM-PWM mode switching terminal. An input capacitor Ci is connected to the voltage E in parallel. An output capacitor Co is connected to the terminal B1: LX via a reactor L, and a DC / DC converter output voltage VOUT can be obtained from both ends of the output capacitor Co.

  In addition, a stacked composite diagram of the schematic planar pattern configuration of the configuration example 1 of the DC / DC converter module 3 corresponding to FIG. 118 is represented as shown in FIG. 119 and is a schematic diagram taken along the line 63A-63A in FIG. The cross-sectional structure is expressed as shown in FIG.

As shown in FIG. 120, the DC / DC converter module 3 according to the sixth embodiment includes a substrate 212, a wiring layer 226 embedded in a groove formed inside the substrate 212, and the surface of the wiring layer 226. Insulating layer 230U ₁ / magnetic layer 10U / insulating layer 230U ₂ disposed on the upper surface, insulating layer 230D ₁ / magnetic layer 10D / insulating layer 230D ₂ disposed on the back surface of wiring layer 226, and upper surface on insulating layer 230U ₂ It comprises a IC236-capacitor 340 disposed over the wiring layer 244, a solder layer 245, and a lower surface wiring layer 246, a solder layer 247 disposed on the lower surface of the insulating layer 230D _2. Here, the insulating layer 230S disposed on the side surface of the wiring layer 226, the slit SL formed in the magnetic layers 10U and 10D and the beam portion 228 formed in the substrate 212 are not shown.

  In the configuration example 1 of the DC / DC converter module 3 according to the sixth embodiment, an IC 236 and a capacitor 340 can be mounted as shown in FIGS. For this reason, the mounting area can be reduced by the lamination technique.

  A bird's-eye view configuration of the configuration example 1 of the DC / DC converter module 3 according to the sixth embodiment corresponding to FIGS. 119 and 120 is expressed as shown in FIG.

  As shown in FIG. 121, an IC 236 and a capacitor 340 can be mounted on an inductance element 232 formed by applying an electrode built-in substrate. For this reason, the mounting area can be reduced as compared with Comparative Example 7 by the lamination technique.

  A schematic plan configuration of the lower surface wiring layer 246 of FIGS. 119 to 121 is expressed as shown in FIG. 122. On the lower wiring layer 246, a VIN electrode pattern for the terminal A1, an EN electrode pattern for the terminal A2, a GND electrode pattern for the terminal A3, a VOUT electrode pattern for the terminal B1, a MODE electrode pattern for the terminal B3, and the like are arranged. ing.

  A schematic plan configuration of the inductor layer in FIGS. 119 to 121 is expressed as shown in FIG. As shown in FIG. 123, the wiring layer 226 embedded in the groove formed inside the substrate 212 is arranged in a coil shape. A through electrode 226T for extracting the electrode of the wiring layer 226 is formed at the center of FIG. Here, the through electrode 226 </ b> T connects the upper surface wiring layer 244 and the lower surface wiring layer 246.

  A schematic plan configuration of the upper surface wiring layer 244 in FIGS. 119 to 121 is expressed as shown in FIG. 124. As shown in FIG. 124, power source terminal A1: VIN electrode pattern to which DC / DC converter input voltage VIN of voltage E is input, enable terminal A2: EN electrode pattern, ground terminal A3: GND electrode pattern, inductor connection Terminal B1: LX electrode pattern, output voltage feedback input terminal B2: FB electrode pattern, DE / PFM-PWM mode switching terminal B3: MODE electrode pattern, and the like are arranged.

  A schematic plan configuration of the IC / capacitor layer in FIGS. 119 to 121 is expressed as shown in FIG. 125. As shown in FIG. 125, an IC 236, an input capacitor Ci, and an output capacitor Co are arranged.

-Configuration example 2-
A schematic cross-sectional structure of Configuration Example 2 of the DC / DC converter module 3 according to the sixth embodiment is expressed as shown in FIG.

As shown in FIG. 126, the configuration example 2 of the DC / DC converter module 3 according to the sixth embodiment includes a substrate 212, a wiring layer 226 embedded in a groove formed inside the substrate 212, and wiring. Insulating layer 230U ₁ / magnetic layer 10U / insulating layer 230U ₂ disposed on the surface of layer 226, insulating layer 230D ₁ / magnetic layer 10D / insulating layer 230D ₂ disposed on the back surface of wiring layer 226, and insulating layer 230U It comprises a IC236-capacitor 340 disposed over the top interconnect layer 244, a solder layer 245 on _2, and a lower surface wiring layer 246, a solder layer 247 disposed on the lower surface of the insulating layer 230D _2. Here, the insulating layer 230S disposed on the side surface of the wiring layer 226, the slit SL formed in the magnetic layers 10U and 10D and the beam portion 228 formed in the substrate 212 are not shown.

  In the configuration example 2 of the DC / DC converter module 3 according to the sixth embodiment, as shown in FIG. 126, the substrate 212 is processed into a ship shape. Similar to the configuration example 1, the IC 236 and the capacitor 340 can be mounted on the bottom of the substrate 212 processed into a ship shape. For this reason, the mounting area can be reduced and the height can be reduced by the lamination technique.

  The area of the DC / DC converter module 3 according to the sixth embodiment can be reduced by the laminated structure. Further, since no IC built-in substrate or ferrite substrate is used, it can be formed at low cost.

  The DC / DC converter module 3 according to the sixth embodiment can be formed by using the deep etching of the silicon substrate and the copper plating technique as described in the method for manufacturing the electrode built-in substrate.

(Shield board)
A schematic bird's-eye view configuration of the shield substrate 202 formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG. The top view of FIG. 127 is represented as shown in FIG. 128 (a), and the schematic cross-sectional structure along the line 64A-64A of FIG. 128 (a) is represented as shown in FIG. 128 (b). A schematic cross-sectional structure taken along the line 65A-65A in FIG. 128A is expressed as shown in FIG. 128C.

  The shield substrate 202 formed by applying the electrode built-in substrate according to the sixth embodiment includes a substrate 212 and an interior of the substrate 212 as shown in FIGS. A wiring layer 226C embedded in a groove having a rectangular stripe pattern in plan view, a beam portion 228 disposed on the back surface facing the surface of the substrate 212, and a back surface facing the surface of the substrate 212. And a rear surface electrode 226B arranged. Here, a wiring layer 226 </ b> C is formed by embedding a metal such as copper (Cu) in a groove formed in the substrate 212.

  Moreover, the beam part 228 is provided with the cross-shaped pattern in planar view of FIG. 128 (a)-FIG.128 (c).

  In the above configuration, the structure of the wiring layer 226C embedded in the groove portion having a rectangular pattern in plan view is shown, but the present invention is not limited to this, and the shape is not limited to this, but a circle, an ellipse, an octagon, a triangle, Or you may have any pattern, such as a polygon. Any shape may be used as long as it can exhibit a shielding effect, and any shape pattern may be provided as long as a closed circuit is formed.

  Similarly to FIG. 114, the structure of the beam portion 228 may have a pattern of a cross shape, a lattice shape, a diagonal cross shape, or a circular / cross composite shape in plan view. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  Of the substrate 212, the substrate 212I surrounded by the wiring layer 226C embedded in the groove portion having a rectangular stripe pattern in plan view is surrounded by the wiring layer 226C and the back electrode 226B. Even if it is placed in the environment of the electromagnetic field EM as shown in c), the influence of noise can be suppressed. For example, the electromagnetic shielding effect can be obtained by digging the substrate 212I and arranging the components. Furthermore, if metal is formed on the upper surface of the wiring layer 226C and the substrate 212I, the influence of noise from the upper surface can be suppressed.

(Interposer)
A schematic bird's-eye view configuration in which the silicon interposer 251 formed by applying the electrode built-in substrate according to the sixth embodiment is arranged on the package substrate 252 is expressed as shown in FIG. 129 (a), and FIG. A schematic cross-sectional structure taken along line 66A-66A in a) is represented as shown in FIG. 129 (b), and an enlarged view of portion E in FIG. 129 (b) is represented as shown in FIG. 129 (c). Is done.

When mounting a plurality of semiconductor integrated circuit chips 248 ₁ , 248 ₂ , 248 _3, and 248 ₄ on the package substrate 252, a silicon interposer 251 is used as an intermediate layer.

  As the silicon interposer 251, the electrode built-in substrate according to the sixth embodiment can be applied.

  A silicon interposer 251 formed by applying the electrode built-in substrate according to the sixth embodiment includes a silicon substrate and a wiring layer embedded in a groove formed in the silicon substrate. Moreover, the beam part is provided similarly to the electrode built-in board | substrate which concerns on 6th Embodiment. As described above, an insulating layer may be formed at the boundary between the silicon substrate and the wiring layer.

The BGA solder balls 254 disposed on the back surface of the package substrate 252 can be connected to the bumps 261 disposed on the surface of the package substrate 252 through through vias. Further, the bump 261 can be connected to a micro bump 256 arranged on the silicon interposer 251 through a through silicon via (CUTSV) 258 and an interposer built-in electrode 226I. The micro bumps 256 are connected to the semiconductor integrated circuit chips 248 ₁ , 248 ₂ , 248 _3, and 248 ₄ .

  Similar to the electrode-embedded substrate according to the sixth embodiment, by providing the beam portion to the silicon substrate, a through groove can also be formed, so that the silicon interposer 251 has a higher degree of design freedom.

  According to the silicon interposer to which the electrode-embedded substrate according to the sixth embodiment is applied, it is possible to provide a highly reliable interposer with a simple structure that hardly causes sticking between the lines.

  As described above, according to the sixth embodiment, an electrode-embedded substrate that has a simple structure, is less likely to cause sticking in which lines come into contact with each other, can be improved in reliability, and a method for manufacturing the same, and this electrode-embedded substrate It is possible to provide an inductance element, an interposer, a shield substrate, and a module to which is applied.

(Other embodiments)
As described above, the embodiments have been described. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, this embodiment includes various embodiments not described here.

  The magnetic structures of the first to fourth embodiments can be applied to all elements using magnetic flux, and can be applied to inductors, transformer cores, magnetic flux shields, sensors using eddy currents, and the like. In addition, the inductance elements to which the magnetic structures of the first to fourth embodiments are applied include all electronic parts using inductance such as inductors, transformers, noise filters, and isolators, sensor parts such as magnetic sensors and position sensors, and other wireless devices. The present invention can be applied to a power supply coil and the like, and in particular, can be applied to an electronic device such as an inductor for a mobile device and a DC-DC converter incorporating the inductor.

  The inductance element according to the fifth embodiment can be applied to all electronic parts using inductance such as inductors, transformers, noise filters, and isolators, sensor parts such as magnetic sensors and position sensors, and other coils for wireless power feeding. In particular, the present invention is applicable to electronic devices such as an inductor for mobile devices and a DC-DC converter with a built-in inductor.

  The electrode-embedded substrate according to the sixth embodiment can be applied to all electronic parts using inductance such as inductors, transformers, noise filters, and isolators, sensor parts such as magnetic sensors and position sensors, and other coils for wireless power feeding. Furthermore, the present invention can be applied to an interposer, a shield substrate, and the like, and particularly applicable to electronic devices such as an inductor for mobile devices and a DC / DC converter module incorporating the inductor.

1 ... electrode-containing substrate 2 and 2b, 2U, 2D, 240, 240 _1, 240 ₂ ... magnetic structure 3 ... module 4, 4b ... inductance element 6 ... core 10, 10 _1, 10 _2, 10 _3, ..., 10 _n , 10 _{n + 1} , 10 ₁ U, 10 ₂ U, 10 ₃ U, 10 ₁ D, 10 ₂ D, 10 ₃ D, 10U, 10D, 102U, 102D... Magnetic layers 12, 12 ₁ , 12 ₂ ,. , 12 _n , 24, 25 ... insulating layer 14 ... buried layer 15 ... groove 16 ... inductance coil 20 ... magnetic metal substrate 22 ... metal wiring layer 23 ... inductance coil terminal electrodes 38 ₁ , 38 ₂ ... search coil electrode terminals 40 ... Search coil 42 ... Search coil substrate 50 ... Magnetic layer substrate 100 ... Printed circuit board (PCB)
112 ... Substrate 113, 129, 130S ... Seed 114 ... Through hole 116 ... Lower core forming part 118 ... Lower coil forming part 120 ... Upper and lower coil connecting part 120P ... Permalloy substrate 122 ... Lower coil 124 ... Lower core 125, 131, 133 ... Resist 126 ... upper coils 128, 128B, 128C, 122 ₁ , 122 ₂ , 242 ... insulating layer 128A ... opening 130 ... upper core 140A ... control integrated circuit (control IC)
140B ... DC / DC converter IC
150 ... Load capacitor (C1)
160 ... Inductance coil 180 ... Snubber capacitor (CB)
200 ... Core 202 ... Shield substrate 220 ... Winding coils 212, 212I, 120 ... Substrate (silicon substrate, silicon wafer)
214, 216... Resists 225 ₁ , 225 ₂ , 225 ₃ ,..., 225 _n ... grooves 226, 226 ₁ , 226 ₂ , 226 ₃ ,... 226 _n , 262 ... electrode layers (wiring layers)
226B ... back electrode 226C ... shield electrode 226I ... interposer built electrodes 226T ... through electrodes 226U, 226D ... Cu plating layer _{227 1, 227 2, 227 3} , ..., 227 n ... through grooves 228, 228 _1, 228 _2, 228 ₃ , ..., 228 ... beam portion _{230,230U, 230U 1, 230U 2,} 230S, 230D, 230D 1, 230D 2, 320U, 320S, 320D ... insulating layer 232 and 234 ... inductor 236 ... IC (integrated circuit)
238 ... Printed circuit board (PCB)
244 ... upper surface wiring layers 245, 247 ... solder layer 246 ... lower surface wiring layers 248 _1, 248 _2, 248 _3, 248 ₄ ... semiconductor integrated circuit chip 251 ... silicon interposer 252 ... package substrate 254 ... BGA solder balls 256 ... micro bumps 258 ... CUTSV (through silicon via)
261: bump 250 ... electromagnetic shielding object 260 ... cavity 290 ... magnetic metal substrate 300 ... transformer (transformer)
340, 340 ₁ , 340 ₂ ... capacitor 400 ... electromagnetic field shield structure L1 ... primary side inductance L2 ... secondary side inductance B ... magnetic flux density H ... magnetic field SL, SL1, SL2, SL3 ... slit ΔSL ... slit width SLP ... slit spacing (Slit pitch)
I _e , I _e1 , I _e2, i _e1 , i _e2 ... Eddy current Φ ... Magnetic flux θ ... Angle

Claims (98)

A first magnetic layer;
A first slit for dividing the first magnetic layer into a plurality of portions;
A first insulating layer disposed on the first slit and the first magnetic layer;
A second magnetic layer disposed on the first insulating layer;
And a second slit for dividing the second magnetic layer into a plurality of magnetic structures.   2. The magnetic structure according to claim 1, wherein the first slit and the second slit have a stripe pattern that is parallel and intersects with each other at a predetermined angle in a plan view.   2. The magnetic structure according to claim 1, wherein the first slit and the second slit have a lattice pattern parallel to each other in a plan view.   The first magnetic layer and the second magnetic layer are, in plan view, a rectangular pattern parallel to each other, a triangular pattern parallel to each other, a hexagonal pattern parallel to each other, an octagonal pattern parallel to each other, a polygonal pattern parallel to each other, The magnetic structure according to claim 1, comprising either a parallel circular pattern or an elliptical pattern parallel to each other.   5. The magnetic structure according to claim 2, wherein the first slit and the second slit do not overlap each other in plan view.   2. The magnetism according to claim 1, wherein a radius of an eddy current flowing in a plane of the first magnetic layer and the second magnetic layer can be controlled by a slit interval of the first slit and the second slit. Structure.   The radius of the eddy current flowing in the plane perpendicular to the planes of the first magnetic layer and the second magnetic layer, and the magnetic flux in the perpendicular direction can be controlled by the thicknesses of the first magnetic layer and the second magnetic layer. The magnetic structure according to claim 1.   The magnetic structure according to any one of claims 1 to 7, wherein a slit width of the first slit and the second slit is larger than a thickness of the first insulating layer.   The magnetic structure according to claim 1, wherein the first magnetic layer and the second magnetic layer include a ferromagnetic material.   The magnetic structure according to claim 1, wherein the first insulating layer includes a ferromagnetic material, a paramagnetic material, or a diamagnetic material.   The magnetic structure according to any one of claims 1 to 10, wherein the first slit and the second slit include a filled ferromagnetic material, paramagnetic material, or diamagnetic material.   The magnetic structure according to claim 1, wherein the first slit and the second slit include a semiconductor or an insulator to be filled.   The magnetic structure according to claim 1, wherein the insulating layer includes a semi-insulating semiconductor or a high-resistance semiconductor. A second insulating layer disposed on the second slit and the second magnetic layer;
A third magnetic layer disposed on the second insulating layer;
The magnetic structure according to claim 1, further comprising a third slit that divides the third magnetic layer into a plurality of pieces. The first slit and the second slit have a stripe pattern that is parallel and intersects with each other at a predetermined angle in plan view,
The magnetic structure according to claim 14, wherein the second slit and the third slit have a stripe pattern that is parallel and intersects with each other at a predetermined angle in a plan view. The first slit and the second slit have a lattice pattern parallel to each other in plan view,
The magnetic structure according to claim 14, wherein the second slit and the third slit have a lattice pattern parallel to each other in plan view. The first slit and the third slit have a stripe pattern overlapping each other in plan view,
The magnetic structure according to claim 14, wherein the second slit and the third slit have a stripe pattern that is parallel and intersects with each other at a predetermined angle in a plan view. The first slit and the third slit have a lattice pattern overlapping each other in plan view,
The magnetic structure according to claim 14, wherein the second slit and the third slit have a lattice pattern parallel to each other in plan view.   The first magnetic layer, the second magnetic layer, and the third magnetic layer have a rectangular pattern parallel to each other, a triangular pattern parallel to each other, a hexagonal pattern parallel to each other, an octagonal pattern parallel to each other, and parallel to each other in plan view. The magnetic structure according to claim 14, wherein the magnetic structure has any one of a polygonal pattern, a circular pattern parallel to each other, and an elliptical pattern parallel to each other.   The magnetic structure according to claim 19, wherein the first slit, the second slit, and the second slit and the third slit do not overlap each other in a plan view.   The radius of eddy current flowing in the planes of the first magnetic layer, the second magnetic layer, and the third magnetic layer can be controlled by the slit spacing of the first slit, the second slit, and the third slit. The magnetic structure according to claim 14.   The radius of the eddy current flowing in the plane perpendicular to the planes of the first magnetic layer, the second magnetic layer, and the third magnetic layer is defined as the thickness of the first magnetic layer, the second magnetic layer, and the third magnetic layer. The magnetic structure according to claim 14, wherein the magnetic structure is controllable by:   The slit width of the first slit and the second slit is larger than the thickness of the first insulating layer, and the slit width of the second slit and the third slit is larger than the thickness of the second insulating layer. The magnetic structure according to claim 7, wherein the magnetic structure is a magnetic structure.   The magnetic structure according to any one of claims 14 to 23, wherein the first magnetic layer, the second magnetic layer, and the third magnetic layer include a ferromagnetic material.   25. The magnetic structure according to claim 14, wherein the first insulating layer and the second insulating layer include a ferromagnetic material, a paramagnetic material, or a diamagnetic material.   The said 1st slit, the said 2nd slit, and the said 3rd slit are provided with the ferromagnetic body, paramagnetic body, or diamagnetic body with which it fills, The any one of Claims 14-25 characterized by the above-mentioned. Magnetic structure.   The magnetic structure according to any one of claims 14 to 25, wherein the first slit, the second slit, and the third slit include a semiconductor or an insulator to be filled.   The magnetic structure according to claim 14, wherein the insulating layer includes a semi-insulating semiconductor or a semiconductor. A first magnetic layer;
A first slit for dividing the first magnetic layer into a plurality of portions;
A first insulating layer disposed on the first slit and the first magnetic layer;
A second magnetic layer disposed on the first insulating layer;
A second slit for dividing the second magnetic layer into a plurality of portions;
A magnetic structure comprising a plurality of laminated structures each including the second slit and a second insulating layer disposed on the second magnetic layer. An inductance coil;
An inductance element comprising: the magnetic structure according to claim 1, wherein the magnetic structure is disposed on a front surface, a back surface, or both surfaces of the inductance coil.   The inductance element according to claim 30, wherein the inductance coil has a planar pattern of any one of a rectangle, a circle, an octagon, a triangle, and a polygon. The core,
A winding coil disposed in the core;
An inductor comprising: the magnetic structure according to claim 1, wherein the magnetic structure is capable of magnetic coupling with the core. The core,
A primary coil disposed in the core;
A secondary coil disposed in the core;
A transformer comprising: the magnetic structure according to any one of claims 1 to 29, wherein the magnetic structure is capable of magnetic coupling with the core. Electromagnetic shielding target object,
A cavity surrounding the electromagnetic shielding target object;
An electromagnetic shielding structure comprising: the magnetic structure according to any one of claims 1 to 29, wherein the magnetic structure surrounds the object to be electromagnetically shielded via the cavity. Forming a first magnetic layer on a substrate;
Forming an insulating layer on the first magnetic layer;
Forming a first slit in the insulating layer and the first magnetic layer;
Filling the first slit with a buried layer;
Forming a second magnetic layer on the insulating layer and the buried layer;
Forming a second slit in the second magnetic layer. A method for manufacturing a magnetic structure, comprising: Forming a first magnetic layer on a substrate;
Forming a first slit in the first magnetic layer;
Forming an insulating layer on the first magnetic layer and the first slit;
Forming a second magnetic layer on the insulating layer;
Forming a second slit in the second magnetic layer. A method for manufacturing a magnetic structure, comprising: A substrate,
An upper coil disposed on the surface of the substrate;
A lower coil disposed on the back surface facing the front surface of the substrate;
An inductance element comprising: an upper and lower coil connecting portion that penetrates from the front surface to the back surface of the substrate and connects the upper coil and the lower coil.   38. The inductance element according to claim 37, wherein the upper coil and the lower coil sandwich the substrate and constitute a solenoid coil.   The inductance element according to claim 37 or 38, further comprising an upper core disposed on a surface of the upper coil.   40. The inductance element according to claim 39, wherein the upper core has a multilayer structure of a magnetic layer and an insulating layer.   41. The inductance element according to any one of claims 37 to 40, further comprising a lower core disposed on the substrate between the upper coil and the lower coil.   42. The inductance element according to claim 41, wherein the lower core has a multilayer structure of a magnetic layer and an insulating layer. An upper core disposed on a surface of the upper coil;
A lower core disposed on the substrate between the upper coil and the lower coil, wherein the upper core and the lower core are magnetically coupled at ends of the upper coil and the lower coil. The inductance element according to claim 37 or 38. A substrate,
An upper coil disposed on the surface of the substrate;
A lower coil disposed on the back surface facing the front surface of the substrate;
An upper and lower coil connecting portion that penetrates from the front surface to the back surface of the substrate and connects the upper coil and the lower coil;
An upper core disposed on a surface of the upper coil;
A lower core disposed on the substrate between the upper coil and the lower coil,
The upper coil and the lower coil sandwich the substrate, constitute a solenoid coil,
The inductance element, wherein the upper core and the lower core include a closed magnetic path that is magnetically coupled at an end portion of the upper coil and the lower coil and penetrates the solenoid coil.   45. The inductance element according to claim 43, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   46. The inductance element according to claim 45, wherein the magnetic layer includes a ferromagnetic material.   47. The inductance element according to claim 45 or 46, wherein the insulating layer includes any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material, and has a resistivity of 10 Ω · cm or more.   The inductance element according to any one of claims 45 to 47, wherein an eddy current radius in the magnetic layer can be controlled by a thickness of the magnetic layer. Comprising an insulating layer disposed on the surface of the substrate;
43. The inductance element according to claim 42, wherein the lower core and the upper core are stacked via the insulating layer.   50. The inductance element according to claim 37, wherein the substrate includes any one of a silicon substrate, a glass substrate, and a ferrite substrate. A substrate, an upper coil disposed on the surface of the substrate, a lower coil disposed on the back surface facing the surface of the substrate, and penetrating from the surface of the substrate to the back surface, the upper coil and the lower coil An inductance element manufacturing method comprising: an upper and lower coil connecting portion to be connected; an upper core disposed on a surface of the upper coil; and a lower core disposed on the substrate between the upper coil and the lower coil. ,
Processing the substrate;
Forming the lower core, the lower coil, and the upper and lower coil connecting portions;
Forming the upper coil;
And a step of forming the upper core. The substrate processing step includes:
On the back surface of the substrate, performing a back surface wiring etching, forming a part of the lower coil forming portion and the through hole,
On the surface of the substrate, performing a through wiring etching to form the through hole;
52. The method of manufacturing an inductance element according to claim 51, further comprising: performing a lower core etching on the surface of the substrate to form a lower core forming portion. Forming the lower core, the lower coil, and the upper and lower coil connecting portions,
Forming a first seed for a plating process on the through hole, the lower coil forming portion, and the lower core forming portion;
Applying a first resist on the substrate surface or laminating a dry film, patterning by photolithography, performing a plating process on the lower core forming part, and forming the lower core;
The method further comprises the step of, after removing the first resist or the dry film, performing plating on the through hole and the lower coil forming portion to form the upper and lower coil connecting portions and the lower coil. Item 53. The method for manufacturing an inductance element according to Item 52. The step of forming the upper coil includes:
Forming a first insulating layer on the surface side of the substrate;
Forming a first opening for the first insulating layer;
Forming a second seed on the entire surface of the substrate including the first opening;
Applying a second resist to the second seed and patterning by photolithography to form a second opening;
54. A method of manufacturing an inductance element according to claim 53, further comprising: performing a plating process on the second seed to form the upper coil. The upper core forming step includes:
Forming a second insulating layer on the upper coil and the substrate surface;
Forming a third seed on the second insulating layer;
Applying a third resist on the third seed and patterning by photolithography to form a third opening;
55. A method of manufacturing an inductance element according to claim 54, further comprising: performing a plating process on the third seed to form the upper core.   56. The method for manufacturing an inductance element according to claim 53, wherein the step of forming the lower core includes a step of forming a multilayer structure of a magnetic layer and an insulating layer.   57. The method of manufacturing an inductance element according to claim 55, wherein the step of forming the upper core includes a step of forming a multilayer structure of a magnetic layer and an insulating layer.   51. A module comprising the inductance element according to claim 37. An integrated circuit mounted on the substrate;
59. The module of claim 58, wherein the integrated circuit comprises a DC / DC converter. A substrate,
A groove formed in the substrate;
A beam portion disposed on the back surface facing the front surface of the substrate;
And a wiring layer embedded in the groove.   61. The electrode-embedded substrate according to claim 60, wherein the beam portion includes a stripe pattern that is orthogonal to the wiring layer in a plan view and parallel to each other.   61. The electrode built-in substrate according to claim 60, wherein the beam portion includes a stripe pattern that intersects with each other at a predetermined angle in a plan view.   61. The electrode according to claim 60, wherein the groove, the beam, or the wiring layer has a rectangular, circular, elliptical, octagonal, triangular, or polygonal pattern in plan view. Built-in board.   64. The electrode built-in substrate according to claim 60, wherein a thickness of the beam portion is thinner than a depth of the groove portion.   The substrate with built-in electrodes according to any one of claims 60 to 64, wherein the substrate comprises a silicon substrate or a glass substrate. An electrode-embedded substrate according to any one of claims 60 to 65,
The groove and the wiring layer have a coil shape.   The inductance device according to claim 66, further comprising an upper core disposed on a surface of the substrate.   68. The inductance element according to claim 67, further comprising a lower core disposed on a back surface facing the front surface of the substrate.   69. The inductance element according to claim 68, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   70. The inductance element according to claim 69, further comprising a slit that divides the upper core and the lower core into a plurality of portions.   The inductance element according to claim 69 or 70, wherein the magnetic layer includes a ferromagnetic material.   72. The inductance element according to claim 69, wherein the insulating layer includes any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material.   The inductance element according to claim 70 or 71, wherein an eddy current radius in the magnetic layer can be controlled by dividing the magnetic layer by the thickness of the magnetic layer and the slit.   An interposer comprising the electrode-embedded substrate according to any one of claims 60 to 65. An electrode built-in substrate according to any one of claims 60 to 65,
A shield substrate comprising: a back electrode disposed on a back surface facing the surface of the substrate.   The shield substrate according to claim 75, further comprising an upper core disposed on a surface of the substrate.   77. The shield substrate according to claim 76, further comprising a lower core disposed on a back surface facing the front surface of the substrate.   78. The shield substrate according to claim 77, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   The shield substrate according to claim 78, further comprising a slit that divides the upper core and the lower core into a plurality of portions.   The shield substrate according to claim 78 or 79, wherein the magnetic layer comprises a ferromagnetic material.   The shield substrate according to any one of claims 78 to 80, wherein the insulating layer includes any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material.   The shield substrate according to any one of claims 78 to 81, wherein an eddy current radius in the magnetic layer can be controlled by a width of the magnetic layer.   A module comprising the inductance element according to any one of claims 66 to 73. A substrate,
A groove having a coil shape formed inside the substrate;
A beam portion disposed on the back surface facing the front surface of the substrate;
A wiring layer embedded in the groove,
An upper surface wiring layer disposed on the surface of the substrate;
A lower surface wiring layer disposed on the back surface facing the surface of the substrate;
A module comprising: an integrated circuit disposed on the upper wiring layer via a solder layer; and a capacitor. An upper core disposed on a surface of the substrate;
A lower core disposed on the back surface opposite to the front surface of the substrate, wherein the upper surface wiring layer is disposed on the upper core and the lower surface wiring layer is disposed on the lower core. 85. The module of claim 84, wherein   86. The module according to claim 84 or 85, further comprising a through electrode disposed inside the coil shape in plan view, penetrating the substrate and connecting the upper surface wiring layer and the lower surface wiring layer.   The module of claim 85, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   88. The module according to claim 87, comprising a slit that divides the upper core and the lower core into a plurality of pieces.   The module according to claim 87 or 88, wherein the magnetic layer comprises a ferromagnetic material.   The module according to any one of claims 87 to 89, wherein the insulating layer includes any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material.   90. The module according to claim 88 or 89, wherein an eddy current radius in the magnetic layer can be controlled by dividing the magnetic layer by the thickness of the magnetic layer and the slit. Forming a groove in the substrate;
Forming the beam portion on the back surface facing the front surface of the substrate;
And a step of embedding and forming the wiring layer in the groove. Forming a coil-shaped groove inside the substrate;
Forming a beam portion on the back surface facing the front surface of the substrate;
A step of embedding a wiring layer in the groove,
Forming an upper core on the surface of the substrate;
Forming a lower core on the back surface facing the front surface of the substrate. Forming a groove provided with a closed circuit-shaped pattern in a plan view inside the substrate;
Forming a beam portion on the back surface facing the front surface of the substrate;
A step of embedding a wiring layer in the groove,
And a step of forming a back electrode on the back surface facing the surface of the substrate. Forming an upper core on the surface of the substrate;
The method of manufacturing a shield substrate according to claim 94, further comprising: forming a lower core on a back surface facing the front surface of the substrate. Forming a coil-shaped groove inside the substrate;
A step of forming a through-groove portion disposed inside the coil shape in plan view and penetrating the substrate;
Forming a beam portion on the back surface facing the front surface of the substrate;
A step of embedding a wiring layer in the groove,
Embedding and forming a through electrode in the through groove,
Forming an upper core on the surface of the substrate;
Forming an upper surface wiring layer connected to the through electrode on the upper core;
Forming a lower core on the back surface facing the surface of the substrate;
Forming a lower surface wiring layer connected to the through electrode on the lower core;
And a step of mounting an integrated circuit and a capacitor on the upper wiring layer via a solder layer.   99. The module manufacturing method according to claim 96, wherein the step of forming the groove and the step of forming the through groove can be performed simultaneously. 98. The module manufacturing method according to claim 97, wherein the step of embedding the wiring layer and the step of embedding the through electrode can be performed simultaneously.