JP6514708B2 - Wiring built-in substrate, method of manufacturing the same, and module and method of manufacturing the same - Google Patents

Description

The present embodiment relates to a wiring built-in substrate and a method of manufacturing the same , and a module and a method of manufacturing the module.

  In recent mobile devices, reduction in thickness, weight, energy saving, and battery life have been required. For this purpose, in particular, it is necessary to make the power supply circuit thinner, lighter, save energy, and extend the life of the battery. Among components constituting a power supply circuit, an inductance element can be mentioned as one having a large size.

  The wiring structure used for the conventional inductance element includes a winding type, a laminated type, and a thin film type. The wire-wound type is one in which a copper wire is wound around a core of a ferromagnetic material, and there are toroidal, solenoid and the like depending on the shape. Also disclosed is an inductance element having a toroidal structure formed by forming a through hole in a silicon substrate.

JP 2004-172396 A JP 2007-214424 A JP-A-9-139313 JP-A-8-88119 JP, 2009-135325, A JP, 2009-135326, A

The present embodiment provides a wiring-embedded substrate having a simple structure, in which sticking between lines is unlikely to occur, and the reliability can be improved, a method of manufacturing the same, a module to which the wiring-embedded substrate is applied, and a method of manufacturing the same. It is.

According to the aspect of the present embodiment, the wiring built-in substrate is provided, and the groove portion and the wiring layer have a coil shape.

According to the aspect of the present embodiment, a module using the above-described wiring built-in substrate as an interposer is provided.

According to an aspect of the present embodiment, an interposer provided with the above electrode-embedded substrate is provided.

According to an aspect of the present embodiment, a substrate having a front surface and a rear surface, a groove having a coil shape formed to partially penetrate the inside of the substrate, and a groove formed on the rear surface of the substrate or A beam portion which is disposed and partially intersects the groove portion, a wiring layer embedded in the groove portion, a top surface wiring layer disposed on the front surface side of the substrate, and the back surface side of the substrate There is provided a module comprising a lower surface wiring layer, an integrated circuit and a capacitor disposed on the upper surface wiring layer via a solder layer.

According to the aspect of the present embodiment, the step of forming a groove so as to partially penetrate the inside of the substrate having the front surface and the back surface, and the step of partially crossing the groove on the back surface side of the substrate A method of manufacturing a wiring-embedded substrate is provided, including the steps of forming a beam portion and embedding a wiring layer in the groove portion.

According to an aspect of the present embodiment, a step of forming a coil-shaped groove portion so as to partially penetrate the inside of the substrate having the front surface and the back surface, and partially forming the groove portion on the back surface side of the substrate. Forming a cross beam portion, embedding a wiring layer in the groove, forming or arranging an upper core on the surface of the substrate, and forming or arranging a lower core on the back side of the substrate A method of manufacturing a wiring built-in substrate is provided.

According to an aspect of the present embodiment, a step of forming a coil-shaped groove portion so as to partially penetrate the inside of a substrate having a front surface and a back surface, and being disposed at a central portion of the coil shape in plan view A step of forming a through groove portion penetrating the substrate, a step of forming a beam portion partially intersecting the groove portion on the back surface side of the substrate, embedding a wiring layer in the groove portion, and penetrating the through groove portion A step of embedding an electrode, a step of forming or arranging an upper core on the surface of the substrate, a step of forming an upper surface wiring layer connected to the through electrode on the upper core, and a lower portion on the back surface of the substrate A step of forming or arranging a core, a step of forming a lower surface wiring layer connected to the through electrode on the lower core, and mounting an integrated circuit and a capacitor on the upper surface wiring layer via a solder layer Method of manufacturing a module having a degree is provided.

Furthermore, according to the present embodiment, a wiring built-in substrate having a simple structure, in which sticking between lines is unlikely to occur, and reliability can be improved, a method of manufacturing the same, and a module to which the wiring built-in substrate is applied A manufacturing method can be provided.

The magnetic structure which concerns on the comparative example 1, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces, when a magnetic flux is applied to surface orthogonal direction. The magnetic structure which concerns on the comparative example 2, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to a surface orthogonal direction. The magnetic structure which concerns on the comparative example 3, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to a surface orthogonal direction. The magnetic structure which concerns on the comparative example 1, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces when magnetic flux is applied to in-plane direction. The magnetic structure which concerns on the comparative example 2, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to in-plane direction. The magnetic structure which concerns on the comparative example 3, WHEREIN: The schematic diagram of the eddy current which generate | occur | produces when a magnetic flux is applied to in-plane direction. (A) A schematic plane pattern block diagram of the magnetic structure according to the first embodiment, (b) a schematic sectional view taken along line 1A-1A of FIG. 7 (a). In the magnetic structure according to the first embodiment, (a) a schematic view of an eddy current generated when a magnetic flux is applied horizontally to the in-layer direction, (b) a magnetic flux applied perpendicularly to the in-layer direction Schematic of the eddy current generated in (A) A schematic plan pattern configuration view of a magnetic structure according to a modification of the first embodiment, (b) a schematic sectional view taken along line 2A-2A in FIG. 9 (a), (c) a view The typical cross-section figure in alignment with the 3A-3A line of 9 (a). In the first method of manufacturing a magnetic structure according to the first embodiment, (a) a schematic cross-sectional view of the step of forming the first magnetic layer on the Si substrate, (b) on the first magnetic layer A schematic sectional view of the step of forming the insulating layer, (c) a schematic sectional view of the step of forming the first slit in the first magnetic layer, (d) a schematic view of the step of embedding the first slit by the embedded layer Cross sectional view. In the first method of manufacturing a magnetic structure according to the first embodiment, (a) a schematic cross-sectional view of the step of forming a second magnetic layer on the insulating layer and the buried layer, (b) a second magnetic layer Typical cross-section figure of the process of forming the 2nd slit in a layer. In the second method of manufacturing a magnetic structure according to the first embodiment, (a) a schematic cross-sectional structure view of a step of forming a first slit in the first magnetic layer, (b) on the first magnetic layer and A schematic sectional view of the step of forming the insulating layer in the first slit, (c) A schematic sectional view of the step of forming the second magnetic layer on the insulating layer, and (d) the second magnetic layer Typical cross-section figure of the process of forming a slit. (A) A schematic plane pattern block diagram of a magnetic structure according to a second embodiment, (b) A schematic sectional view taken along line 4A-4A in FIG. The typical cross-section figure of the magnetic structure concerning a 3rd embodiment. (A) A schematic plane pattern block diagram of an inductance element according to comparative example 4, (b) A schematic sectional structural view taken along line 5A-5A of FIG. (A) A schematic plane pattern configuration diagram of an inductance element according to an embodiment, (b) A schematic cross-sectional structure diagram along line 6A-6A in FIG. (A) A schematic plane pattern block diagram of an inductance element according to a first modification of the embodiment, (b) a schematic sectional view taken along line 7A-7A of FIG. (A) Circuit representation of an inductance coil, (b) Schematic view showing the relationship between _AC resistance R _AC and inductance L (comparison of slit structure WS and non-slit structure WOS). (A) A schematic view showing a relationship between an inductance L and a magnetic field H, (b) a schematic view showing a relationship between a magnetic flux density B and a magnetic field H. Examples of the magnetic circuit for the magnetic structure and the inductance element according to the embodiment, the magnetic flux Φ is for explaining that passes a small portion of the magneto-resistance R _m. In the magnetic structure and the inductance element according to the embodiment, examples of cylindrical sample to explain that it is possible to suppress the eddy current loss P _e by reducing the cylinder radius r _0. (A) A typical plane pattern lineblock diagram of an inductance element concerning modification 2 of an embodiment, (b) A typical section construction figure which meets 8A-8A line of Drawing 22 (a). (A) A schematic plan pattern configuration diagram of an experimental system in which a search coil is disposed on a magnetic layer provided with slits SL, (b) a schematic bird's-eye view of the search coil. FIG. 23 is a schematic cross-sectional structure view taken along line 9A-9A of FIG. Explanatory drawing of the slit space | interval on the basis of the dimension of the search coil device. (A) Explanatory drawing of the experimental condition of the experimental system which has arranged the search coil on the magnetic layer provided with the slit SL, (b) explanatory drawing of the angle θ ₂ of the D _X axis of the search coil with respect to the X axis, (c) magnetic layer Explanatory drawing of slit width (DELTA) SL and slit space | interval (slit pitch) SLP of slit SL formed in FIG. FIG. 27 is an explanatory view of experimental conditions in which FIG. 26 is expanded using an orthogonal array and compressed nine ways. In the experimental system in which the search coil is disposed on the magnetic layer provided with the slit SL, the experimental result of the relationship between the increase in resistance of the AC resistance and the inductance (comparison of the slit structure WS and the non-slit structure WOS). It is an inductance element which concerns on the comparative example 4, Comprising: (a) Typical bird's-eye view, (b) Typical cross-section figure in alignment with the 10A-10A line of Fig.29 (a). It is an inductance element which concerns on embodiment, Comprising: (a) typical bird's-eye view, (b) Typical cross-section figure in alignment with the 11A-11A line of Fig.30 (a). Frequency characteristics of inductance (comparison of slit structure WS and non-slit structure WOS). Frequency characteristics of AC resistance (comparison of slit structure WS and non-slit structure WOS). It is a manufacturing method of the inductance coil applicable to the inductance element concerning an embodiment, and is a typical section construction drawing of the process of preparing (a) magnetic metal substrate, (b) etching a magnetic metal substrate and forming a slot After that, a schematic sectional view of the step of forming the insulating layer, (c) A schematic sectional view of the step of forming the metal wiring layer, (d) The metal wiring layer is polished by CMP or the like, and the metal wiring layer is formed in the groove portion. Typical cross-section figure of the process of leaving (e) Typical cross-section figure of the process of carrying out back surface etching of a magnetic metal substrate, and forming an inductance coil. It is a typical cross-sectional structure explaining 1 process of the manufacturing method of the inductance coil applicable to the inductance element which concerns on embodiment, Comprising: The example which formed the (a) rectangular-shaped groove part, (b) trapezoidal groove part The example which formed, (c) the example which formed the triangular-shaped groove part, the example which formed the (d) U-shaped groove part. (A) In the inductance element according to the embodiment, a schematic bird's-eye view showing an example in which a groove is formed on a magnetic metal substrate, (b) FIG. 35 (a) shows a metal wiring layer formed in the groove Schematic bird's-eye view of the structure. (A) Another inductance element according to the embodiment, which is a schematic plane pattern configuration diagram of an example in which a circular groove portion formed on a magnetic metal substrate is formed, (b) A circle of FIG. (C) Another inductance element according to the embodiment, which is an octagonal groove formed on a magnetic metal substrate, showing a metal wiring layer formed in the groove of the shape. (D) Another inductance element according to the embodiment, wherein the metal wiring layer is formed in two opposing triangular grooves formed on a magnetic metal substrate. The typical plane pattern block diagram which arranged the. The structural example of the power supply circuit which applies the inductance element which concerns on embodiment as a component. It is typical sectional structure of the inductor (EI core) to which the magnetic structure concerning embodiment is applied, Comprising: (a) 1st structural example, (b) 2nd structural example, (c) 3rd structure Example, (d) Fourth configuration example. It is a typical cross-section of the transformer to which the magnetic structure which concerns on embodiment is applied, Comprising: (a) 1st structural example, (b) 2nd structural example. BRIEF DESCRIPTION OF THE DRAWINGS The typical cross-section figure of the electromagnetic shielding structure to which the magnetic structure which concerns on embodiment is applied. It is a detailed structure of the inductance element which concerns on 4th Embodiment, Comprising: (a) typical bird's-eye view, (b) Typical cross-section figure in alignment with 12A-12A line of Fig.41 (a). It is an inductance element concerning a 5th embodiment, and (a) a typical bird's-eye view, (b) the side view seen from the A direction of Drawing 42 (a), (c) partial expansion structure example 1 between upper coils (D) A partially enlarged structural example 2 between upper coils, (e) A side view as viewed from the B direction in FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. (A) Top view of FIG. 43, (b) Side view seen from the short side direction of FIG. 43, (c) Bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. (A) Top view of FIG. 45, (b) Side view seen from the short side direction of FIG. 45, (c) Bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. (A) Top view of FIG. 47, (b) Side view seen from the short side direction of FIG. 47, (c) Bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. (A) Top view of FIG. 49, (b) Side view seen from the short side direction of FIG. 49, (c) Bottom view of FIG. The typical bird's-eye view which shows the internal structure of the inductance element which concerns on 5th Embodiment. (A) Top view of FIG. 51, (b) Side view seen from the short side direction of FIG. 51, (c) Bottom view of FIG. The side view seen from the long side direction of FIG. It is an inductance element which concerns on 5th Embodiment, Comprising: The typical bird's-eye view of the structure which couple | bonded the upper core and the lower core in the inductance coil edge part. (A) An enlarged view of C part of FIG. 54, (b) Typical cross-section figure in alignment with the 13A-13A line of FIG. 55 (a). It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) a typical top view of a silicon substrate, (b) a typical sectional view which meets 14A-14A line of Drawing 56 (a) . It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and is a typical top view of a silicon substrate which performed (a) back wiring etching, (b) 15A-15A line of Drawing 57 (a) Sectional view along the. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) Typical top view of a silicon substrate which carried out penetration wiring etching, (b) 16A-16A line of Drawing 58 (a) Sectional view along the. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) Typical top view of a silicon substrate which carried out lower core etching, (b) 17A-17A line of Drawing 59 (a) Sectional view along the. A step of a method of manufacturing an inductance element according to a fifth embodiment, which is a schematic plan view of a silicon substrate in which (a) seed formation is performed to a through hole, a lower coil formation portion, and a lower core formation portion; (B) A schematic sectional view taken along the line 18A-18A in FIG. FIG. 61A is a step view of a method of manufacturing an inductance element according to a fifth embodiment, and is (a) a schematic plan view of a silicon substrate on which a lower core is formed by performing photolithography and plating formation; The typical sectional view which meets the 19A-19A line of (a). FIG. 62 (a) is a schematic plan view of a silicon substrate on which plating formation is performed on a through hole / lower coil formation portion, which is one process of a method of manufacturing an inductance element according to a fifth embodiment; Typical sectional drawing which follows 20A-20A line of a). It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and is a typical top view of a silicon substrate which implemented a (a) front and back polishing process, (b) 21A-21A line of Drawing 63 (a) Sectional view along the. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and is a typical top view of a silicon substrate which implemented a (a) surface side insulating layer formation process, (b) 22A of Drawing 64 (a) Typical sectional drawing in alignment with a -22A line. FIG. 65 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and (a) a step of forming an opening for the front side insulating layer is performed; 23A is a schematic sectional view taken along the line 23A-23A. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) a typical top view of a silicon substrate which carried out a seed formation process for upper wiring, (b) 24A of Drawing 66 (a) Typical sectional drawing in alignment with a -24A line. FIG. 67 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment and is (a) a photolithography step for upper wiring; FIG. FIG. 25A is a schematic sectional view taken along the line 25A-25A. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) Typical top view of a silicon substrate which carried out plating formation process for upper wiring, (b) Drawing 68 (a) FIG. 26A is a schematic sectional view taken along the line 26A-26A of FIG. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) A typical top view of a silicon substrate which carried out a resist exfoliation process for upper wiring, (b) Drawing 69 (a) 27A is a schematic sectional view taken along the line 27A-27A. FIG. 70 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and (a) a seed removing step for upper wiring is performed; Typical sectional drawing in alignment with line 28A-28A. FIG. 71 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment and in which (a) a step of forming an insulating layer for the upper core is performed; FIG. 29 is a schematic sectional view taken along the line 29A-29A of FIG. FIG. 72 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and which includes (a) a seed forming step for an upper core; Typical sectional drawing in alignment with line 30A-30A. FIG. 73 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and is (a) subjected to a photolithography step for the upper core; 31A is a schematic sectional view taken along line 31A-31A. FIG. 74 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and (a) a plating formation step for an upper core is performed; 32A-32A is a schematic cross-sectional view of FIG. It is one process of a manufacturing method of an inductance element concerning a 5th embodiment, and (a) A typical top view of a silicon substrate which implemented a resist removal process for upper cores, (b) Drawing 75 (a) 33A-33A of FIG. FIG. 76 (a) is a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and (a) a seed removing step for the upper core is performed; 34A-34A line of FIG. The typical sectional view which meets 35A-35A line of Drawing 76 (a). (A) In the inductance element according to the fifth embodiment, a schematic plan view showing an upper coil and a lower coil formed on a silicon substrate, (b) a schematic view along line 36A-36A in FIG. Cross section. FIG. 78 is a schematic cross-sectional view along the line 37A-37A of FIG. 78 (a). (A) In the inductance element according to the fifth embodiment, a schematic plan view showing an upper core and a lower core formed on a silicon substrate, (b) a schematic view along line 38A-38A in FIG. Cross section. The typical sectional view which meets the 39A-39A line of Drawing 80 (a). Frequency characteristics of inductance L of the inductance element according to the fifth embodiment (SOL: solenoid structure according to the fifth embodiment, SPI: spiral structure according to the fourth embodiment). Frequency characteristics of AC resistance ACR of the inductance element according to the fifth embodiment (SOL: solenoid structure according to the fifth embodiment, SPI: spiral structure according to the fourth embodiment). FIG. 14 is a plan view of a module according to a fourth embodiment in which an inductance element, a control IC, a capacitor and the like are arranged on a printed circuit board (PCB). FIG. 21 is a plan view of an inductance element according to the fifth embodiment formed on a silicon substrate and a module according to the fifth embodiment in which an IC, a capacitor, and the like are arranged on the silicon substrate. The top view of the module concerning a 4th embodiment which arranged inductance element, DC / DC converter IC, a capacitor, etc. on PCB. A side view of a module according to a fifth embodiment in which an inductance element according to the fifth embodiment formed on a silicon substrate and an IC, a DC / DC converter IC, a capacitor, etc. for control are disposed on the silicon substrate Example 1). FIG. 21 is a side view of a module according to the fifth embodiment in which an inductance element according to the fifth embodiment formed on a silicon substrate and an IC for control, a capacitor and the like are arranged on the silicon substrate (configuration example 2). FIG. 31 is a side view of an inductance element according to the fifth embodiment formed on a silicon substrate, and a module according to the fifth embodiment in which a control IC and a capacitor are disposed on the silicon substrate (Configuration Example 3). The connection structural example of the DC / DC converter (DCDC) which applies the inductance element which concerns on 5th Embodiment to an output load circuit, and is mounted in the whole silicon substrate, and an output load circuit. It is a typical plane pattern lineblock diagram of an electrode built-in board concerning a 6th embodiment, and (a) beam example is orthogonal to a wiring layer in plane view, and is provided with a stripe pattern parallel to each other, (b) The example provided with the stripe pattern which a beam part cross | intersects by predetermined angle (theta) mutually in planar view. (A) A schematic sectional view taken along line 40A-40A in FIG. 91. (b) A schematic sectional view taken along line 41A-41A in FIG. It is an electrode built-in board concerning a 6th embodiment, and is a typical plane pattern lineblock diagram of an electrode built-in board which has a relatively long line and space formed in a silicon wafer. (A) A schematic sectional structure view taken along the line 42A-42A of FIG. 93, (b) A schematic sectional structure view taken along the line 43A-43A of FIG. (A) A schematic plan pattern configuration diagram of an electrode-embedded substrate according to Comparative Example 5 having a relatively long line and space formed on a silicon wafer, (b) Sixth embodiment The electrode built-in board which concerns on, Comprising: The typical plane pattern block diagram of the electrode built-in board | substrate which has the relatively long line and space formed in the silicon wafer. The electrode built-in board | substrate which concerns on the comparative example 5, Comprising: The typical plane pattern block diagram of the electrode built-in board | substrate which has a spiral-shaped inductance element formed in the silicon substrate. It is an electrode-incorporated substrate according to the sixth embodiment, and is (a) a schematic surface pattern configuration, (b) a schematic sectional view taken along line 44A-44A in FIG. 97 (a), (c) a diagram. Fig. 97 is a schematic sectional view taken along the line 45A-45A of Fig. 97 (a), and Fig. 97 (d) is a schematic rear surface pattern block diagram corresponding to Fig. 97 (a). It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) Typical surface pattern lineblock diagram, (b) Typical section structure which meets 46A-46A line of Drawing 98 (a) FIG. 98 (c) is a schematic rear surface pattern block diagram corresponding to FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) typical surface pattern lineblock diagram, (b) typical section structure which meets 47A-47A line of Drawing 99 (a). FIG. 99 (c) is a schematic rear surface pattern block diagram corresponding to FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) typical surface pattern lineblock diagram, (b) typical section structure which meets 48A-48A line of Drawing 100 (a). FIG. 100C is a schematic rear surface pattern block diagram corresponding to FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) Typical surface pattern lineblock diagram, (b) Typical section structure which meets 49A-49A line of Drawing 101 (a) FIG. 101C is a schematic rear surface pattern block diagram corresponding to FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) typical surface pattern lineblock diagram, (b) typical section structure which meets 50A-50A line of Drawing 102 (a) FIG. 102C is a schematic sectional structural view taken along the line 51A-51A in FIG. 102A, and FIG. 102D is a schematic rear surface pattern block diagram corresponding to FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) Typical surface pattern lineblock diagram, (b) Typical section structure which meets 52A-52A line of Drawing 103 (a) (C) A schematic sectional structure view taken along line 53A-53 in FIG. 103 (a), (d) A schematic rear surface pattern block diagram corresponding to FIG. 103 (a). It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) Typical surface pattern lineblock diagram, (b) Typical section structure which meets 54A-54A line of Drawing 104 (a) (C) A schematic cross-sectional structure view taken along line 55A-55A in (a) of FIG. 104 (d) A schematic rear surface pattern configuration view corresponding to (d) in (a) of FIG. It is 1 process of the manufacturing method of an electrode built-in substrate concerning a 6th embodiment, and (a) Typical surface pattern lineblock diagram, (b) Typical section structure which meets 56A-56A line of Drawing 105 (a) (C) A schematic cross-sectional structure view taken along line 57A-57A in (a) of FIG. 105 (d) A schematic back surface pattern configuration view corresponding to (d) FIG. 105 (a). It is 1 process of the manufacturing method of an electrode built-in board concerning a 6th embodiment, and (a) typical surface pattern lineblock diagram, (b) typical section structure which meets 58A-58A line of Drawing 106 (a). (C) A schematic cross-sectional structure view taken along line 59A-59A in (a) of FIG. 106 (d) A schematic rear surface pattern block diagram corresponding to (d) FIG. 106 (a). The typical cross-section figure of the inductance element of the silicon substrate system formed by applying the electrode built-in board concerning a 6th embodiment. (A) A schematic cross-sectional view of the inductance element of the permalloy substrate system according to the comparative example 6 (example of the structure without polishing on the back surface), (b) a schematic cross-sectional view of the inductance element of the permalloy substrate system according to the comparative example 6 Example of structure with backside grinding). (A) A schematic bird's-eye view of an inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment, (b) A schematic sectional view taken along line 60A-60A in FIG. 109 (a) . (A) An inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment, which is a schematic bird's-eye view of the wiring layer, (b) A surface view of FIG. 110 (a) (C) Back side block diagram of Fig. 110 (a). (A) A cross-sectional view along the line 61A-61A of the central portion of FIG. 110 (a), (b) A cross-sectional view as viewed in the direction of arrow B1 in FIG. 111 (a), (c) FIG. 111 (b) Enlarged view of C1 part of. (A) A sectional bird's-eye view along line 62A-62A in FIG. 110 (a), (b) A sectional view as seen in the direction of arrow B2 in FIG. 112 (a), (c) Part C2 in FIG. 112 (b) Enlarged view of. (A) Typical surface side bird's-eye view block diagram of only the silicon substrate of FIG. 110 (a), (b) Back surface side typical bird's-eye block diagram of FIG. 113 (a). It is a schematic plan view of the beam part structure applicable to the electrode built-in board concerning a 6th embodiment, and (a) cross type composition example, (b) lattice type composition example, (c) diagonal direction cross Example of mold configuration, (d) Example of circular / cross combined type configuration. The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the electrode built-in board concerning a 6th embodiment. The simulation result of the frequency characteristic of alternating current resistance ACR of the inductance element formed by applying the electrode built-in board concerning a 6th embodiment. 7 shows an example of a mounting configuration of a DC / DC converter module according to Comparative Example 7; The integrated circuit block block diagram of the structural example 1 of the DC / DC converter module which concerns on 6th Embodiment. Stacking of a schematic plane pattern configuration of a DC / DC converter configuration example 1 in which an IC and a capacitor are mounted on an inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment corresponding to FIG. 118 Composite diagram. FIG. 120 is a schematic cross-sectional structure view taken along line 63A-63A of FIG. 119. The typical bird's-eye view block diagram of example 1 of composition of the DC / DC converter module concerning a 6th embodiment. FIG. 120 is a schematic plan view of the lower surface wiring layer of FIGS. 119 to 121. FIG. FIG. 120 is a schematic plan view of the inductor layer of FIGS. 119 to 121. FIG. 120 is a schematic plan view of the upper surface wiring layer of FIGS. 119 to 121. FIG. FIG. 120 is a schematic plan view of the IC / capacitor layer of FIGS. 119 to 121. FIG. FIG. 18 is a schematic cross-sectional structure view of Configuration example 2 of the DC / DC converter module according to the sixth embodiment. The typical bird's-eye view block diagram of the shield board | substrate formed by applying the electrode built-in board | substrate which concerns on 6th Embodiment. A shield substrate formed by applying the electrode-embedded substrate according to the sixth embodiment, wherein (a) is a top view of FIG. 127, (b) a schematic view along line 64A-64A of FIG. 128 (a). Sectional structural drawing, (c) A schematic sectional structural view taken along the line 65A-65A in FIG. 128 (a). (a) A schematic bird's-eye view of a package substrate provided with an interposer formed by applying the electrode-embedded substrate according to the sixth embodiment, (b) A schematic sectional structure along line 66A-66A in FIG. 129 (a) FIG. 129 (c) is an enlarged view of a part E of FIG. 129 (b).

  Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that parts having different dimensional relationships and ratios among the drawings are included.

  In addition, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the materials, shapes, structures, arrangements and the like of the components to the following ones. . The embodiments can be variously modified within the scope of the claims.

Comparative Examples 1 to 3
The magnetic structure 2B according to Comparative Example 1 has a single layer structure having a single magnetic layer 10 as shown in FIGS. 1 and 4. The magnetic structure 2B according to the comparative example 2 has a multilayer structure having the insulating layer 12 between the magnetic layers 10 ₁ and 10 ₂ as shown in FIG. 2 and FIG. As shown in FIGS. 3 and 6, in addition to the multi-layer structure having the insulating layer 12 between the magnetic layers 10 ₁ and 10 ₂ , the magnetic structure 2 B according to the comparative example 3 includes the magnetic layer 10 ₁ · insulation comprising a multilayer slit structure divided layers 12, 10 _2.

  The magnetic structure 2B according to Comparative Examples 1 to 3 shows different characteristics depending on whether the direction of the magnetic flux Φ is perpendicular or parallel to the in-layer direction of the magnetic layer.

In magnetic structure 2B according to Comparative Example 1, if the direction of the magnetic flux Φ is the layer in the direction and the orthogonal direction of the magnetic layer 10, as shown in FIG. 1, the eddy current radius of the eddy current I _e is the magnetic layer The eddy current loss P _e is relatively large, which is determined by the size of ten. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layer 10 is single.

In magnetic structure 2B according to Comparative Example 2, when the direction of the magnetic flux Φ is the layer in the direction and the orthogonal direction of the magnetic layer 10 _1, 10 _2, as shown in FIG. 2, the eddy current I _e1, I _e2 The eddy current radius is determined by the size of the magnetic layers 10 ₁ and 10 ₂ , and the eddy current loss P _e becomes relatively large. On the other hand, the magnetoresistance R _m is generated in the insulating layer 12 between the magnetic layers 10 ₁ and 10 ₂ and is relatively larger than that of the first comparative example.

In the magnetic structure 2B according to Comparative Example 3, when the direction of the magnetic flux が is the in-plane direction and the perpendicular direction of the magnetic layers 10 ₁ and 10 ₂ , as shown in FIG. 3, the eddy currents i _e1 · i _e2 The eddy current loss _Pe can be relatively reduced because the eddy current radius can be controlled by the distance between the slits SL dividing the magnetic layers 10 ₁ and 10 ₂ . On the other hand, the magnetoresistance R _m is generated in the insulating layer 12 between the magnetic layers 10 _1, 10 _2, and since the cross-sectional area of the magnetic layer 10 _1, 10 ₂ is reduced in the slit SL moiety, relative comparison with Comparative Example 2 Great.

In the magnetic structure 2B according to Comparative Example 1, when the direction of the magnetic flux Φ is parallel to the in-layer direction of the magnetic layer 10, the eddy current radius of the eddy current _Ie is the magnetic layer 10 as shown in FIG. The eddy current loss P _e is relatively large. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layer 10 is a single layer.

In magnetic structure 2B according to Comparative Example 2, when the direction of the magnetic flux Φ is a direction parallel to the layer in the direction of the magnetic layer 10 _1, 10 _2, as shown in FIG. 5, the eddy current I _e1, I _e2 eddy current radius is determined by the interval of the magnetic layer 10 _1, 10 ₂ thick-insulating layer 12, the eddy current loss P _e becomes relatively small. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layers 10 ₁ and 10 ₂ are respectively single layers.

In magnetic structure 2B according to Comparative Example 3, if the direction of the magnetic flux Φ is a direction parallel to the layer in the direction of the magnetic layer 10 _1, 10 _2, as shown in FIG. 6, the eddy current i _e1 - i _e2 eddy current radius is determined by the interval of the magnetic layer 10 _1, 10 ₂ thick-insulating layer 12, the eddy current loss P _e becomes relatively small. On the other hand, the magnetic resistance R _m is relatively large because it occurs at the slit SL portion.

As described above, in the magnetic structure 2B according to the comparative example, the magnetic resistance R _m and the magnetic resistance R relatively smaller than the magnetic flux Φ in two directions, ie, the in-plane direction of the magnetic layer and the in-plane and parallel directions it is difficult to form a magnetic circuit that can achieve both a relatively small eddy current loss P _e.

First Embodiment
(Magnetic structure)
The schematic plane pattern configuration of the magnetic structure 2 according to the first embodiment is expressed as shown in FIG. 7A, and the schematic cross-sectional structure along line 1A-1A in FIG. It shows as shown in FIG.7 (b).

The magnetic structure 2 according to the first embodiment, as shown in FIG. 7 (a) and 7 (b), first dividing the first magnetic layer 10 _1, the first magnetic layer 10 ₁ in more a first slit SL1, a first insulating layer 12, second magnetic layer 10 _2, the second magnetic layer disposed on the first insulating layer 12 disposed on the first slit SL1 and the first upper magnetic layer 10 ₁ and a second slit SL2 that divides the 10 ₂ into a plurality.

  Further, as shown in FIG. 7A, the first slit SL1 and the second slit SL2 have stripe patterns parallel to each other in a plan view.

  Further, as shown in FIG. 7A, the first slits SL1 and the second slits SL2 have stripe patterns which are parallel to each other and do not overlap each other in plan view.

In the magnetic structure 2 according to the first embodiment, as shown in FIGS. 7A and 7B, the insulating layer 12 is formed between the magnetic layers 10 ₁ and 10 ₂ , and the magnetic layer 10 is formed. ₁ are separated from each other through the slit SL1, the magnetic layer 10 ₂ are separated from each other through the slit SL2.

Here, the magnetic layers 10 ₁ and 10 ₂ may be formed of a ferromagnetic material.

  Also, the insulating layer 12 may be formed of a ferromagnetic, paramagnetic or diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, the magnetic resistance is advantageously reduced. Instead of the insulating layer 12, a semi-insulating semiconductor or a high resistance semiconductor layer may be formed.

  The slits SL1 and SL2 may be formed by being filled with a ferromagnetic, paramagnetic or diamagnetic material. The magnetic resistance can be reduced by forming the magnetic body.

  Further, the slits SL1 and SL2 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the first embodiment, the eddy current I _e generated when the magnetic flux Φ is applied in the horizontal direction to the inside of the magnetic layer is represented schematically as shown in FIG. The eddy current I _e generated when the magnetic flux Φ is applied perpendicularly to the direction in the magnetic layer is schematically represented as shown in FIG. 8 (b).

In the magnetic structure 2 according to the first embodiment, when the magnetic flux Φ is applied horizontally to the direction in the magnetic layer, as shown in FIG. 8A, along the overlapping magnetic layers 10 ₁ and 10 ₂ A magnetic circuit is formed. Compared with Comparative Example 3 shown in FIG. 6, the magnetic resistance is reduced because there is no gap due to the slit SL. Further, the radius of the eddy current I _e can be controlled by the thickness of the magnetic layers 10 ₁ · 10 ₂ and the slit spacing SLP 1 · SLP ₂ of the slits SL 1 · SL ₂ . Here, as shown in FIG. 8A, the slit spacing SLP1 of the slits SL1 corresponds to the center pitch between the adjacent slits SL1, and the slit spacing SLP2 of the slits SL2 is the center pitch between the adjacent slits SL2. It corresponds. The slit width of the slits SL1 and SL2 is represented by ΔSL1 and ΔSL2.

In the magnetic structure 2 according to the first embodiment, as shown in FIG. 8B, when the magnetic flux Φ is applied perpendicular to the direction in the magnetic layer, the slit spacings SLP 1 and SLP 2 of the slits SL 1 and SL 2 and The radius of the eddy current _Ie can be controlled by the thickness of the magnetic layers 10 ₁ and 10 ₂ . Further, compared with the multilayer slit structure of Comparative Example 3 shown in FIG. 3, the magnetic resistance is reduced because there is no magnetic flux passing through the slit.

  The radius of the eddy current generated by the magnetic flux can be controlled by the slit spacing SLP1 and SLP2 or the thickness of the magnetic layer. By reducing the eddy current radius, it is possible to suppress the eddy current loss (main component of AC resistance).

  In the magnetic structure 2 according to the first embodiment, the formation positions of the first slit SL1 and the second slit SL2 are arranged so as not to overlap between the adjacent slits.

In the magnetic structure 2 according to the first embodiment, as shown in FIG. 8A, the amount of magnetic flux in the in-plane direction can be divided into slit spacings SLP1 and SLP2 of the slits SL1 and SL2 and the magnetic layers 10 ₁ and 10 _2. It can be controlled by the thickness of

In the magnetic structure 2 according to the first embodiment, as shown in FIG. 8 (b), the magnetic flux amount of the orthogonal directions of the magnetic layers 10 _1, 10 ₂ of the thickness and slit SL1-SL2 It can be controlled by the slit intervals SLP1 and SLP2.

  In the magnetic structure 2 according to the first embodiment, as shown in FIGS. 8A and 8B, the slit widths ΔSL1 and ΔSL2 of the slits SL1 and SL2 have the thickness of the first insulating layer 12 Is set larger than the

(Modification)
A schematic plane pattern configuration of the magnetic structure 2 according to the modification of the first embodiment is expressed as shown in FIG. 9A, and is a schematic cross section along line 2A-2A in FIG. 9A. The structure is represented as shown in FIG. 9 (b), and a schematic cross-sectional structure taken along line 3A-3A of FIG. 9 (a) is represented as shown in FIG. 9 (c).

The magnetic structure 2 according to a modification of the first embodiment, as shown in FIG. 9 (a) ~ FIG 9 (c), the plurality of first magnetic layer 10 _1, the first magnetic layer 10 ₁ a first slit SL1 that divides, first an insulation layer 12, second magnetic layer 10 ₂ that are disposed on the first insulating layer 12 disposed on the first slit SL1 and the first upper magnetic layer 10 _1, the and a second slit SL2 that divides the second magnetic layer 10 ₂ into a plurality.

  Further, as shown in FIG. 9A, the first slits SL1 and the second slits SL2 have parallel stripe patterns in plan view.

  Further, as shown in FIG. 9A, the first slit SL1 and the second slit SL2 intersect at a predetermined angle θ in plan view. Here, the angle θ is 0 degrees or more and 90 degrees or less.

  Further, in the case of the predetermined angle θ = 0 degree, the first slit SL1 and the second slit SL2 have stripe patterns which are parallel to each other and do not overlap in a plan view.

The magnetic structure 2 according to a modification of the first embodiment, as shown in FIG. 9 (a) and FIG. 9 (b), the insulating layer 12 is formed between the magnetic layer 10 _1, 10 _2, and magnetic layer 10 ₁ are separated from each other through the slit SL1, the magnetic layer 10 ₂ are separated from each other through the slit SL2.

  Further, as shown in FIG. 9C, the magnetic structure 2 according to the modification of the first embodiment has the function of the present embodiment in the portion where the first slit SL1 and the second slit SL2 overlap. Since they do not express but do not overlap in other parts, the function of the embodiment is expressed. The other configuration is the same as that of the first embodiment.

In the magnetic structure 2 according to the first embodiment is not limited to the above stripe pattern, the first magnetic layer 10 _1, the second magnetic layer 10 _2, in plan view, parallel to each other rectangular pattern It may have any of triangular patterns parallel to one another, hexagonal patterns parallel to one another, octagonal patterns parallel to one another, polygonal patterns parallel to one another, circular patterns parallel to one another, or elliptical patterns parallel to one another . In addition, the first slit SL1 and the second slit SL2 may have a configuration in which they do not overlap with each other in plan view.

(First Method of Manufacturing Magnetic Structure)
The first method of manufacturing the magnetic structure 2 according to the first embodiment is expressed as shown in FIGS. 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (b). .

As shown in FIGS. 10A to 10D and FIGS. 11A to 11B, the first manufacturing method of the magnetic structure 2 according to the first embodiment is a substrate 8. forming a step of forming a first magnetic layer 10 ₁ above, forming an insulating layer 12 on a first magnetic layer 10 _1, the first slit SL1 in the insulating layer 12 and the first magnetic layer 10 ₁ When, formed burying the buried layer 14 of the first slit SL1, a step of forming a second magnetic layer 10 ₂ on the insulating layer 12 and the buried layer 14, the second slit SL2 to the second magnetic layer 10 ₂ And a process.
(A) First, as shown in FIG. 10 (a), for example, preparing a silicon substrate 8, on the silicon substrate 8, to form the magnetic layer 10 _1, for example made of a ferromagnetic material. Here, the thickness of the silicon substrate 8 is, for example, about 525 μm. The magnetic layer 10 _1, for example, is applicable and Co-Ta-Zr layer. Thickness of the magnetic layer 10 ₁ is, for example, about 2 [mu] m. In the formation of the magnetic layer 10 _1, sputtering techniques, chemical vapor deposition: like (CVD Chemical Vapor Deposition) technique can be used. Here, instead of the silicon substrate 8, an insulating substrate made of SiO ₂ may be applied.
(B) Next, as shown in FIG. 10 (b), the insulating layer 12 is formed on the magnetic layer 10 _1. For example, a silicon oxide film or the like can be applied as the insulating layer 12. In the formation of the insulating layer 12, for example, plasma CVD technology can be used. The insulating layer 12 may be formed of a ferromagnetic, paramagnetic or diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, the magnetic resistance is advantageously reduced. Instead of the insulating layer 12, a semi-insulating semiconductor or a high resistance semiconductor layer may be formed.
(C) Next, as shown in FIG. 10 (c), the patterning step, the insulating layer 12 and the magnetic layer 10 ₁ is etched to form a slit SL1. Here, the width of the slit SL1 is, for example, about 10 μm.
(D) Next, as shown in FIG. 10D, the slits SL1 are filled with the embedded layer 14. An insulating layer or a magnetic material can be applied to the buried layer 14. As the insulating layer, for example, a silicon oxide film, a polyimide resin or the like can be applied. The magnetic body may be formed of a paramagnetic body or a diamagnetic body. Specifically, ferrite plating or ferrite paste can be used. The buried layer 14 may be formed of a semiconductor. Furthermore, a ferromagnetic material is also applicable to the buried layer 14. The magnetic resistance can be reduced by forming the magnetic body.
(E) Next, as shown in FIG. 11 (a), on the insulating layer 12 and the buried layer 14 to form a magnetic layer 10 _2, for example made of a ferromagnetic material. Here, the magnetic layer 10 _2, for example, is applicable and Co-Ta-Zr layer. Thickness of the magnetic layer 10 ₂ is, for example, about 2 [mu] m. In the formation of the magnetic layer 10 _2, it can be used sputtering technique, and CVD techniques.
(f) Next, as shown in FIG. 11 (b), by patterning step, the magnetic layer 10 ₂ is etched to form a slit SL2. Here, the slit width of the slit SL2 is about 10 μm, for example. The slit SL2 may be filled with the embedded layer 14 similarly to the slit SL1.

(Second method of manufacturing magnetic structure)
The second method of manufacturing the magnetic structure according to the first embodiment is expressed as shown in FIGS. 12 (a) to 12 (d).

According to a second method of manufacturing a magnetic structure according to the first embodiment, as shown in FIGS. 12A to 12D, a step of forming a first magnetic layer on a substrate; A process of forming a first slit in the magnetic layer, a process of forming an insulating layer on the first magnetic layer and the first slit, a process of forming a second magnetic layer on the insulating layer, and a second magnetic layer And 2) forming a slit.
(A) First, as shown in FIG. 12 (a), for example, preparing a silicon substrate 8, on the silicon substrate 8, to form the magnetic layer 10 _1, for example made of a ferromagnetic material. Here, the magnetic layer 10 _1, for example, is applicable and Co-Ta-Zr layer. In the formation of the magnetic layer 10 ₁ can be used for sputtering technique, and CVD techniques. Here, instead of the silicon substrate 8, an insulating substrate made of SiO ₂ may be applied.
(B) Next, by patterning step, the magnetic layer 10 ₁ is etched to form a slit SL1.
(C) Next, as shown in FIG. 12 (b), the insulating layer 12 is formed on the magnetic layer 10 ₁ and the slit SL1. For example, a silicon oxide film or the like can be applied as the insulating layer 12. In the formation of the insulating layer 12, for example, plasma CVD technology can be used. The insulating layer 12 may be formed of a ferromagnetic, paramagnetic or diamagnetic material. In particular, when the insulating layer 12 is formed of a ferromagnetic material, the magnetic resistance is advantageously reduced. Instead of the insulating layer 12, a semi-insulating semiconductor or a high resistance semiconductor layer may be formed.
(D) Next, as shown in FIG. 12 (c), on the insulating layer 12 to form a magnetic layer 10 _2, for example made of a ferromagnetic material. Here, the magnetic layer 10 _2, for example, is applicable and Co-Ta-Zr layer. In the formation of the magnetic layer 10 _2, it can be used sputtering technique, and CVD techniques.
(e) Next, as shown in FIG. 12 (d), by patterning step, the magnetic layer 10 ₂ is etched to form a slit SL2. The slit SL2 may be filled with a buried layer. The buried layer may be formed of a paramagnetic material or a diamagnetic material. In addition, it may be formed of a semiconductor or an insulator. Furthermore, a ferromagnetic material is also applicable to the buried layer. The magnetic resistance can be reduced by forming the magnetic body.

  According to the first embodiment, it is possible to provide a magnetic structure capable of reducing the magnetoresistance and the eddy current loss.

Second Embodiment
(Magnetic structure)
The schematic plane pattern configuration of the magnetic structure 2 according to the second embodiment is represented as shown in FIG. 13A, and the schematic cross-sectional structure along line 4A-4A in FIG. It is expressed as shown in FIG.

The magnetic structure 2 according to the second embodiment, as shown in FIG. 13 (a) and 13 (b), first dividing the first magnetic layer 10 _1, the first magnetic layer 10 ₁ in more a first slit SL1, a first insulating layer 12 ₁ disposed on the first slit SL1 and the first upper magnetic layer 10 _1, second magnetic layer 10 ₂ disposed on a first insulating layer 12 _1, second a second slit SL2 for dividing the magnetic layer 10 ₂ to a plurality, a second insulating layer 12 ₂ disposed on the second slit SL2 and the second upper magnetic layer 10 _2, which is disposed on the second insulating layer 12 ₂ It comprises a third magnetic layer 10 _3, and a third slit SL3 that divides the third magnetic layer into a plurality.

In the second embodiment, compared to the first embodiment, the magnetic layer in the magnetic structure 2 is multilayered as a three-layer structure. By forming the magnetic structure 2 in multiple layers, the cross-sectional area of the magnetic structure 2 can be substantially increased, so that the magnetic resistance R _m can be reduced. Moreover, since the volume of the magnetic structure 2 can be substantially increased by making it multilayer, the magnetic energy which can be stored increases.

  As shown in FIGS. 13A and 13B, the first slit SL1 and the second slit SL2 have lattice-like patterns parallel to each other in plan view, and the second slit SL2 and the third slit SL3 are formed. In plan view, lattice patterns parallel to one another may be provided.

  Further, as shown in FIGS. 13A and 13B, the first slit SL1 and the third slit SL3 have lattice-like patterns overlapping each other in plan view, and the second slit SL2 and the third slit SL3 May have lattice-like patterns parallel to one another in plan view.

The magnetic structure 2 according to the second embodiment, as shown in FIG. 13 (a) and 13 (b), the insulating layer 12 ₁ is formed between the magnetic layer 10 _1, 10 _2, the magnetic layer 10 ₂ · 10 insulating layer 12 ₂ between ₃ is formed and the magnetic layer 10 ₁ are separated from each other through the slit SL1, the magnetic layer 10 ₂ is divided from each other through the slit SL2, the magnetic layer ₁₀₃ is slit SL3 Are separated from each other.

Here, the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ may be formed of a ferromagnetic material.

Also, the insulating layers 12 ₁ and 12 ₂ may be formed of a ferromagnetic, paramagnetic or diamagnetic material. In particular, when the insulating layers 12 ₁ and 12 ₂ are formed of a ferromagnetic material, the magnetic resistance is advantageously reduced. Instead of the insulating layers 12 ₁ and 12 ₂ 2, semi-insulating semiconductors or high-resistance semiconductor layers may be used.

  The slits SL1, SL2, and SL3 may be filled with a ferromagnetic, paramagnetic or diamagnetic material. The magnetic resistance can be reduced by forming the magnetic body.

  The slits SL1, SL2, and SL3 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the second embodiment, when the magnetic flux Φ is applied horizontally to the direction in the magnetic layer, the three-layer structure is overlapped as in the two-layer structure of FIG. 8A. A magnetic circuit is formed along the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ . Since there is no gap due to the slit SL, the magnetic resistance is reduced. Further, the radius of the eddy current I _e can be controlled by the thickness of the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ and the slit spacing SLP 1 · SLP 2 · SLP ₃ of the slits SL 1 · SL ₂ · SL ₃ . Here, the slit intervals SLP1 and SLP2 are as shown in FIG. Further, since the slit spacing SLP3 is the same, the illustration is omitted.

In the magnetic structure 2 according to the second embodiment, when the magnetic flux Φ is applied perpendicular to the direction in the magnetic layer, the slit SL1 is formed also in the three-layer structure as in the two-layer structure of FIG. The radius of the eddy current I _e can be controlled by the slit spacing SLP 1 · SLP 2 · SLP ₃ of SL 2 · SL _{3 and} the thickness of the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ . Further, compared to the multilayer slit structure, the magnetic resistance is reduced because there is no magnetic flux passing through the slit.

In the magnetic structure 2 according to the second embodiment, the amount of magnetic flux in the in-plane direction is the thickness of the slit spacing SLP 1 · SLP 2 · SLP ₃ of the slits SL 1 · SL 2 · SL _{3 and} the thickness of the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ It is controllable by.

Further, in the magnetic structure 2 according to the second embodiment, the amount of magnetic flux in the direction perpendicular to the surface also depends on the thickness of the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ and the slit spacing SLP 1 · SLP 2 of the slits SL 1 · SL ₂ · SL _3. Controllable by SLP3.

Further, the magnetic structure 2 according to the second embodiment, the slit width ΔSL1 · ΔSL2 the first slit SL1 and the second slit SL2 is greater than the first thickness of the insulating layer 12 _1, and the second slit SL2 and the slit width ΔSL2 · ΔSL3 third slit SL3 is set to be larger than the thickness of the second insulating layer 12 _2. Here, the slit widths ΔSL1 and ΔSL2 are as shown in FIG. Further, since the slit width ΔSL3 is the same, the illustration is omitted.

  In the magnetic structure 2 according to the second embodiment, the first slit SL1 and the second slit SL2 have stripe patterns parallel to each other at a predetermined angle θ in plan view, and the second slit SL2 The third slit SL3 may have a stripe pattern which is parallel and intersects with each other at a predetermined angle θ in plan view. Here, the angle θ is 0 degrees or more and 90 degrees or less. Further, in the case of the predetermined angle θ = 0 degrees, the relationship between the respective slits comprises stripe patterns which are parallel to each other and do not overlap in plan view.

  In the magnetic structure 2 according to the second embodiment, the first slit SL1 and the third slit SL3 have stripe patterns overlapping each other in plan view, and the second slit SL2 and the third slit SL3 are planar It may have stripe patterns parallel to each other and intersect with each other at a predetermined angle θ. Here, the angle θ is 0 degrees or more and 90 degrees or less. Further, in the case of the predetermined angle θ = 0 degree, the second slit SL2 and the third slit SL3 have stripe patterns which are parallel to each other and do not overlap in plan view.

Incidentally, in the magnetic structure 2 according to the second embodiment is not limited to the aforementioned grid pattern, the first magnetic layer 10 _1, the second magnetic layer 10, _second and third magnetic layer 10 ₃ is a plan view In the above, rectangular patterns parallel to one another, triangular patterns parallel to one another, hexagonal patterns parallel to one another, octagonal patterns parallel to one another, polygonal patterns parallel to one another, circular patterns parallel to one another, or elliptical patterns parallel to one another It may be equipped with The first slit SL1 and the second slit SL2 and the second slit SL2 and the third slit SL2 may have a configuration in which they do not overlap with each other in plan view.

  According to the second embodiment, it is possible to provide a magnetic structure capable of reducing the magnetoresistance and the eddy current loss.

Third Embodiment
(Magnetic structure)
A schematic cross-sectional structure of the magnetic structure 2 according to the third embodiment is represented as shown in FIG.

The magnetic structure 2 according to the third embodiment, as shown in FIG. 14, a first slit SL1 that divides the first magnetic layer 10 _1, the first magnetic layer 10 ₁ into a plurality of first slit SL1 and the first insulating layer 12 ₁ disposed on a first magnetic layer 10 _1, divides the second magnetic layer 10 ₂ disposed on a first insulating layer 12 _1, a second magnetic layer 10 ₂ to the plurality a second slit SL2, a second insulating layer 12 ₂ disposed on the second slit SL2 and the second upper magnetic layer 10 _2, and the third magnetic layer 10 ₃ disposed on the second insulating layer 12, _second 3 and the third slit SL3 to divide the magnetic layer 10 ₃ in a plurality, the third insulating layer 12 ₃ disposed on the third slit SL3 and the third magnetic layer 10 _3, ..., the (n-1) insulating layer 12 _n a first n magnetic layer 10 _n disposed on _-1, and the n slits SLn dividing the second n magnetic layer 10 _n in plurality, the And the n + 1 insulating layer 12 _{n + 1,} which is arranged in the slit SLn and the n magnetic layer 10 _n, and the n + 1 magnetic layer 10 _{n + 1} arranged on the (n + 1) insulating layer 12 _{n + 1,} the (n + 1) magnetic And an n + 1th slit SLn + 1 which divides the layer 10 _{n + 1} into a plurality of layers.

That is, the magnetic structure 2 according to the third embodiment, the first magnetic layer 10 _1, a first slit SL1 for dividing the first magnetic layer 10 ₁ into a plurality of first slit SL1 and the first magnetic layer 10 ₁ and the first insulating layer 12 ₁ disposed on the second magnetic layer 10 ₂ disposed on a first insulating layer 12 _1, and the second slit SL2 that divides the second magnetic layer 10 ₂ to the plurality comprises a structure in which a laminated structure comprising a second insulating layer 12 ₂ disposed on the second slit SL2 and the second upper magnetic layer 10 ₂ stacking a plurality.

In the third embodiment, the magnetic layer in the magnetic structure 2 is multilayered. By forming the magnetic structure 2 in multiple layers, the cross-sectional area of the magnetic structure 2 can be substantially increased, so that the magnetic resistance R _m can be reduced. Moreover, since the volume of the magnetic structure 2 can be substantially increased by making it multilayer, the magnetic energy which can be stored increases.

Here, the magnetic layers 10 ₁ · 10 ₂ · 10 ₃ · · · · 10 _{n +1} may be formed of a ferromagnetic material.

Further, the insulating layers 12 ₁ , 12 ₂ ,... 12 _n may be formed of a ferromagnetic material, a paramagnetic material or a diamagnetic material. In particular, when the insulating layers 12 ₁ , 12 ₂ ,... 12 _n are formed of a ferromagnetic material, the magnetic resistance is advantageously reduced. Instead of the insulating layers 12 ₁ , 12 ₂ ,... 12 _n , they may be formed of a semi-insulating semiconductor or a high-resistance semiconductor layer.

  Further, the slits SL1, SL2, SL3,..., SLn + 1 may be formed filled with a ferromagnetic, paramagnetic or diamagnetic material. The magnetic resistance can be reduced by forming the magnetic body.

  Further, the slits SL1, SL2, SL3,..., SLn + 1 may be formed by being filled with a semiconductor or an insulator.

In the magnetic structure 2 according to the third embodiment, when the magnetic flux Φ is applied horizontally to the direction in the magnetic layer, the overlapping magnetic layers 10 ₁ · 10 ₂ · 10 ₃ ········ 10 also in the multilayer structure _A magnetic circuit is formed along _{n + 1} . Since there is no gap due to the slit SL, the magnetic resistance decreases. Further, the radius of the eddy current I _e is the thickness of the magnetic layer 10 ₁ · 10 ₂ · 10 ₃ ··· · · · 10 _{n +1} and the slit spacing of the slits SL 1 · SL 2 · SL 3 · · · SL _{n +1} SLP 1 · SLP 2 · SLP 3 · .. Can be controlled by SLP n + 1.

In the magnetic structure 2 according to the third embodiment, when the magnetic flux Φ is applied perpendicular to the direction in the magnetic layer, the slit spacing SLP1 and SLP2 of the slits SL1, SL2, SL3,. The radius of the eddy current I _e can be controlled by the thickness of SLP3... SLPn + 1 and the magnetic layer 10 ₁ · 10 ₂ · 10 ₃ ··· 10 _{n +1} . Further, compared to the multilayer slit structure, the magnetic resistance is reduced because there is no magnetic flux passing through the slit.

In the magnetic structure 2 according to the third embodiment, the magnetic flux amount of plane direction, the slit interval of the slit SL1 · SL2 · SL3 · ... · SLn + 1 SLP1 · SLP2 · SLP3 · ... · SLPn + 1 and the magnetic layer 10 ₁ - It is controllable by the thickness of 10 ₂ · 10 ₃ ... 10 _{n + 1} .

Further, in the magnetic structure 2 according to the third embodiment, the amount of magnetic flux in the direction perpendicular to the surface is the thickness of the insulating layers 12 ₁ 12 ₂ ... 12 _n and the slits SL 1 SL 2 SL 3 ... SL _n + 1 It is controllable by the slit space | interval of SLP1 * SLP2 * SLP3 * ... SLPn + 1.

  According to the third embodiment, it is possible to provide a magnetic structure capable of reducing the magnetoresistance and the eddy current loss.

Comparative Example 4
(Inductance element)
A schematic plane pattern configuration of an inductance element 4B according to Comparative Example 4 is expressed as shown in FIG. 15A, and a schematic cross-sectional structure along line 5A-5A of FIG. It is expressed as shown in).

  As shown in FIGS. 15A and 15B, the inductance element 4B according to the comparative example 4 includes the inductance coil 16, the magnetic layer 10U disposed on the front surface of the inductance coil 16, and the back surface of the inductance coil 16. And a magnetic layer 10D disposed on the

  Here, the magnetic layers 10D and 10U have a single-layer structure as in the first comparative example shown in FIGS.

  Further, the inductance coil 16 is formed by the metal wiring layer 22 formed in the magnetic metal substrate 20.

  The magnetic layer 10U is disposed on the surface of the inductance coil 16 via the insulating layer 24, and the magnetic layer 10D is disposed on the back surface of the inductance coil 16 via the insulating layer 24. Therefore, although the inductance coil 16 should be shown by a broken line in the schematic planar pattern configuration shown in FIG. 15A, it is shown by a solid line to make the arrangement of the inductance coil 16 on the magnetic layer 10D more visible.

Similarly to the magnetic structure according to Comparative Example 1, when the direction of the magnetic flux が is the in-plane direction and the perpendicular direction of the magnetic layers 10D and 10U, the eddy current radius of the eddy current _Ie is that of the magnetic layers 10D and 10U. Depending on the size, the eddy current loss P _e becomes relatively large. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layers 10D and 10U are single.

Similarly to the magnetic structure according to Comparative Example 1, when the direction of the magnetic flux 平行 is parallel to the in-layer direction of the magnetic layers 10D and 10U, the eddy current radius of the eddy current _Ie is the thickness of the magnetic layers 10D and 10U. The eddy current loss P _e is relatively large. On the other hand, the magnetic resistance R _m is relatively small because the magnetic layer 10 is a single layer.

In Comparative Example 4, relatively small magnetic resistance R _m and relatively small eddy current loss P _e are compatible with magnetic flux Φ in two directions of in-layer direction and in-plane direction / parallel direction of the magnetic layer. It is difficult to form a possible magnetic circuit.

Therefore, in the inductance element 4B according to the comparative example 4, since the eddy current loss in the magnetic layers 10D and 10U is relatively large, the AC resistance R _AC also becomes large.

Fourth Embodiment
(Inductance element)
The schematic plane pattern configuration of the inductance element 4 according to the fourth embodiment is expressed as shown in FIG. 16A, and the schematic cross-sectional structure along line 6A-6A in FIG. It is expressed as shown in 16 (b).

  As shown in FIGS. 16A and 16B, the inductance element 4 according to the fourth embodiment includes an inductance coil 16, a magnetic structure 2U disposed on the surface of the inductance coil 16, and an inductance And a magnetic layer 10D disposed on the back surface of the coil 16.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U is stacked. That is, the magnetic structure 2U corresponds to the magnetic structure 2 according to the second embodiment.

  Further, the magnetic layer 10D has a single-layer structure as in Comparative Example 4 of FIG.

  Further, the inductance coil 16 is formed by the metal wiring layer 22 formed in the magnetic metal substrate 20.

Here, the width of the slits SL1, SL2, and SL3 is about 10 μm. The thickness of the insulating layer is about 1 μm. The film thickness of each of the magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm.

In the inductance element 4 according to the fourth embodiment, by setting the slit width wider than the thickness of the insulating layer, the magnetic flux passes through the portion with a small gap, so that the reduction of the magnetic resistance R _m can be achieved. Can.

  Further, in the inductance element 4 according to the fourth embodiment, the eddy current radius is controlled by the slit spacing and the thickness of the magnetic layer when the magnetic flux is parallel to the surface of the magnetic layer, and the magnetic flux Also in the case of the perpendicular direction in the plane of the magnetic layer, the thickness of the magnetic layer and the slit spacing can be controlled. For this reason, in the inductance element 4 according to the fourth embodiment, since the magnetic structure having a multilayer structure is provided, the eddy current radius can be reduced, and as a result, the eddy current loss can be reduced.

In the inductance element 4 according to the fourth embodiment, as shown by the broken line in FIG. 16B, a magnetic circuit having a relatively small magnetic resistance R _m and a relatively small eddy current loss P _e Is formed.

  Since the inductance element 4 according to the fourth embodiment can reduce the eddy current radius of the magnetic structure 2U as shown in FIGS. 16 (a) and 16 (b), the eddy current loss can be reduced. it can.

As shown in FIGS. 16A and 16B, in the inductance element 4 according to the fourth embodiment, the magnetic structure 2U capable of reducing the magnetic resistance and the eddy current loss is placed on the inductance coil 16. Because of the provision, the eddy current loss is relatively reduced as compared to the inductance element 4B according to the comparative example 4, and the AC resistance R _AC can also be reduced.

In the inductance element 4 according to the fourth embodiment, the magnetic layer 10 ₁ close to the inductor 16 is relatively narrower the slit interval SLP1 of the magnetic layer 10 _first slit SL1 since the magnetic flux Φ is relatively large and, according away from inductor 16, the magnetic flux Φ may be relatively wider slit spacing SLP2 of the magnetic layer 10 _{and second} slit SL2 from becoming relatively small. In the magnetic layer 10 _2, as compared to the magnetic layer 10 _1, the magnetic flux density is small, the eddy current is also small. Therefore, it is not necessary to set the slit spacing SLP2 as finely as the slit spacing SLP1. If the slit interval SLP2 widened than the slit intervals SLP 1, it can reduce the magnetic resistance in the magnetic layer 10 _2. On the other hand, the magnetic layer ₁₀₃ is a single-layer structure without particularly forming a slit SL3, may be applied thereby suppressing the leakage magnetic field to the outside.

(Modification 1)
The schematic plane pattern configuration of the inductance element 4 according to the first modification of the fourth embodiment is expressed as shown in FIG. 17A, and is a schematic cross section taken along line 7A-7A of FIG. The structure is represented as shown in FIG. 17 (b).

  As shown in FIGS. 17A and 17B, the inductance element 4 according to the first modification of the fourth embodiment includes an inductance coil 16 and a magnetic structure disposed on the surface of the inductance coil 16. 2 U and a magnetic structure 2 D disposed on the back surface of the inductance coil 16.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U is stacked, and the magnetic structure 2D is a magnetic layer 10 ₁ D · 10 ₂ D ··· It has a configuration in which a 3-layer structure of 10 ₃ D is stacked. That is, the magnetic structures 2U and 2D correspond to the magnetic structure 2 according to the second embodiment.

An insulating layer is formed between the magnetic layers 10 ₁ U and 10 ₂ U, an insulating layer is formed between the magnetic layers 10 ₂ U and 10 ₃ U, and the magnetic layers 10 ₁ U are mutually divided via the slits SL ₁ The layers 10 ₂ U are divided into one another through the slits SL ₂ , and the magnetic layers 10 ₃ U are divided into one another through the slits SL ₃ . The same applies to the magnetic layers 10 ₁ D, 10 ₂ D, and 10 ₃ D.

  As shown in FIGS. 17A and 17B, the slits SL1 and SL3 have lattice patterns overlapping each other in plan view, and the slits SL2 and SL3 are lattices parallel to each other in plan view. It has a letter pattern.

  Further, the inductance coil 16 is formed by the metal wiring layer 22 formed in the magnetic metal substrate 20.

Here, the slit widths ΔSL1 · ΔSL2 · ΔSL3 of the slits SL1 · SL2 · SL3 are approximately 10 μm. The thickness of the insulating layer is about 1 μm. The film thickness of each of the magnetic layers 10 ₁ U, 10 ₂ U, 10 ₃ U, 10 ₁ D, 10 ₂ D, 10 ₃ D is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm. is there.

In the inductance element 4 according to the first modification of the fourth embodiment, the magnetic flux passes through the small gap by setting the slit widths ΔSL1, ΔSL2, and ΔSL3 wider than the thickness of the insulating layer. The resistance R _m can be reduced.

  Further, in the inductance element 4 according to the first modification of the fourth embodiment, the eddy current radius is controlled by the slit spacing and the thickness of the magnetic layer when the magnetic flux is in a direction parallel to the surface of the magnetic layer. It is possible to control the thickness of the magnetic layer and the slit spacing even when the magnetic flux is in the direction perpendicular to the plane of the magnetic layer. Therefore, in the inductance element 4 according to the first modification of the fourth embodiment, since the magnetic structure having a multilayer structure is provided, the eddy current radius can be reduced, and as a result, the eddy current loss can be reduced. .

In the inductance element 4 according to the first modification of the fourth embodiment, as shown by the broken line in FIG. 17B, the magnetic resistance R _m is relatively small and the eddy current loss P _{e is} relatively small. Form a small magnetic circuit.

  The inductance element 4 according to the first modification of the fourth embodiment can reduce the eddy current radius of the magnetic structures 2U and 2D as shown in FIGS. Loss can be reduced. The magnetic flux in the in-plane direction of the magnetic layer can be controlled by the slit spacing of the magnetic structures 2U and 2D and the film thickness of each magnetic layer, and the magnetic flux in the direction perpendicular to the surface of the magnetic layer is also the film thickness of each magnetic layer And the slit spacing of the magnetic structures 2U and 2D.

As shown in FIGS. 17A and 17B, the inductance element 4 according to the first modification of the fourth embodiment can reduce the magnetic resistance and the eddy current loss as a magnetic structure 2U · 2D. Since the inductance coil 16 is provided above and below the inductance coil 16, the eddy current loss is further reduced and the AC resistance R _AC can be further reduced as compared with the inductance element 4 according to the fourth embodiment.

Also in the inductance element 4 according to the first modification of the fourth embodiment, the magnetic layer 10 ₁ close to the inductance coil 16, the magnetic flux Φ is the slit spacing SLP1 of the magnetic layer 10 _first slit SL1 since relatively large relatively narrow form, according away from inductor 16, the magnetic flux Φ may be relatively wider slit spacing SLP2 of the magnetic layer 10 _{and second} slit SL2 from becoming relatively small. In the magnetic layer 10 _2, as compared to the magnetic layer 10 _1, the magnetic flux density is small, the eddy current is also small. Therefore, it is not necessary to set the slit spacing SLP2 as finely as the slit spacing SLP1. If the slit interval SLP2 widened than the slit intervals SLP 1, it can reduce the magnetic resistance in the magnetic layer 10 _2. On the other hand, the magnetic layer ₁₀₃ is a single-layer structure without particularly forming a slit SL3, may be applied thereby suppressing the leakage magnetic field to the outside.

  The circuit representation of the inductance element is represented as shown in FIG.

The inductance element is represented by a series circuit configuration of an inherent inductance L and an AC resistance R _AC having frequency characteristics.

The relationship between the _AC resistance R _AC and the inductance L is schematically represented as shown in FIG. 18 (b). The AC resistance R _AC tends to increase as the inductance L increases. Here, in FIG. 18 (b), WS corresponds to the case where the inductance element has a slit structure, that is, corresponds to the fourth embodiment shown in FIG. 15 and FIG. Corresponds to the comparative example 4 shown in FIG. 15 when it does not have a slit structure. The AC resistance R _AC tends to increase with the increase of the inductance L, but in the inductance element according to the fourth embodiment or the modification thereof, the increase tendency is suppressed as compared with the comparative example 4. That is, by providing the slit structure, the AC resistance R _AC can be reduced. The experimental results are as shown in FIG.

In the inductance element, the relationship between the inductance L and the magnetic field H is represented schematically as shown in FIG. 19 (a), and the relationship between the magnetic flux density B and the magnetic field H is represented schematically as shown in FIG. 19 (b). Is represented by The magnetic field H is proportional to the current conducting the inductance element. The relationship between the inductance L and the magnetic field H is ideally a constant value L ₀ with respect to the increase of the current or the magnetic field H, as shown by the broken line, but in practice it is shown in FIG. Thus, when the threshold magnetic field H ₁ is exceeded, it shows a decreasing tendency as shown by L _d . This is because, as shown in FIG. 19 (b), the BH curve, because the inclination of the magnetic flux density B and a magnetic field H is decreased by the threshold value of the magnetic field H ₁ or more, as a result the inductance L is also reduced. Here, the gradients of the saturation magnetic flux density B _s and the magnetic field H indicate the magnetic permeability μ.

(Relation between magnetic flux and magnetic resistance)
In the magnetic structure and the inductance element according to the fourth embodiment, an example of a magnetic circuit for illustrating that the magnetic flux Φ passes through the small portion of the magnetic resistance R _m is schematically shown in FIG. expressed.

Assuming that N is the number of turns and I is the conduction current, the magnetic field H in the annular core 6 having the permeability μ is given by the law of circuit integration of amps,
Is represented by Assuming that the cross-sectional area of an arbitrary position of the magnetic circuit is S (m ² ) and the magnetic flux density is B, since Φ = BS = μHS, the magnetic field H at any point in the magnetic circuit is expressed by the following equation Ru.

H = Φ / (μS) (2)

Since the magnetic flux Φ is constant anywhere in the magnetic circuit even if the cross-sectional area S in the magnetic circuit changes, from the equations (1) and (2),
Is represented by Using the magnetoresistance R _m

NI = R _m ((4)

== NI / R _m (5)

Is established. From the equation (5), it can be understood that the smaller the magnetic resistance R _{m, the} larger the magnetic flux 、, and the easier the magnetic flux 磁 束 passes through the magnetic circuit. Therefore, it can be seen that the magnetic flux Φ passes through the small portion of the magnetic reluctance R _m .

(Relationship between eddy current loss and eddy current radius)
In the magnetic structure and the inductance element according to the fourth embodiment, an example of a cylindrical sample for explaining that the eddy current loss P _e can be suppressed by reducing the cylindrical radius r ₀ is schematically As shown in FIG.

  Eddy current loss is a phenomenon in which a current flows in a sample according to the law of electromagnetic induction along with a change in magnetization, so that the change in magnetization is damped.

Assuming that the cylinder radius is r ₀ , the resistivity is ρ, the conduction current is I, and the time change is dI / dt, the eddy current loss P _e is

P _e = r ₀ ² / (8ρ) · (dI / dt) ² (6)

Is established. From the equation (6), the eddy current loss P _e can be suppressed by reducing the cylinder radius r ₀ .

(Modification 2)
A schematic plane pattern configuration of the inductance element 4 according to the second modification of the fourth embodiment is expressed as shown in FIG. 22 (a), and is a schematic cross section along line 8A-8A in FIG. 22 (a). The structure is represented as shown in FIG.

  As shown in FIGS. 22A and 22B, the inductance element 4 according to the second modification of the fourth embodiment includes an inductance coil 16 and a magnetic structure disposed on the surface of the inductance coil 16. 2 U and a magnetic structure 2 D disposed on the back surface of the inductance coil 16.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U is stacked, and the magnetic structure 2D is a magnetic layer 10 ₁ D · 10 ₂ D ··· It has a configuration in which a 3-layer structure of 10 ₃ D is stacked. The magnetic structures 2U and 2D correspond to the magnetic structure 2 according to the second embodiment.

Insulating layer 12 ₁ between the magnetic layer 10 ₁ U · 10 ₂ U is formed, and the magnetic layer 10 ₁ U insulating layer 12 ₂ is formed between the magnetic layer 10 ₂ U · 10 ₃ U each other via the slit SL1 The magnetic layers 10 ₂ U are divided into each other through the slits SL ₂ , and the magnetic layers 10 ₃ U are divided into each other through the slits SL ₃ . The same applies to the magnetic layers 10 ₁ D, 10 ₂ D, and 10 ₃ D.

  As shown in FIGS. 22A and 22B, the slits SL1 and SL3 have lattice patterns overlapping each other in plan view, and the slits SL2 and SL3 are gratings parallel to each other in plan view. It has a letter pattern.

Here, the width of the slits SL1, SL2, and SL3 is about 10 μm. The film thickness of the insulating layers 12 ₁ and 12 ₂ is about 1 μm. The film thickness of each of the magnetic layers 10 ₁ U, 10 ₂ U, 10 ₃ U, 10 ₁ D, 10 ₂ D, 10 ₃ D is about 2 μm, and the thickness of the magnetic metal substrate 20 is about 60 μm. is there.

In the inductance element 4 according to the second modification of the fourth embodiment, by setting the slit width to be wider than the thickness of the insulating layer, the magnetic flux passes through the portion with a small gap, so reduction of the magnetic resistance R _m Can be implemented.

Further, in the inductance element 4 according to the second modification of the fourth embodiment, the eddy current radius is controlled by the film thickness of the magnetic layer and the slit spacing when the magnetic flux is in a direction parallel to the surface of the magnetic layer. Even in the case where the magnetic flux is in the direction perpendicular to the surface of the magnetic layer, it can be controlled by the slit spacing and the thickness of the magnetic layer. For this reason, in the inductance element 4 according to the second modification of the fourth embodiment, since the magnetic structure having a multilayer structure is provided, the eddy current radius can be reduced, and as a result, the eddy current loss P _e can be reduced. It is.

In the inductance element 4 according to the second modification of the fourth embodiment, as shown by the broken line in FIG. 22, the magnetic resistance R _m is relatively small, and the eddy current loss P _e is relatively small. A circuit is formed.

  The inductance element 4 according to the second modification of the fourth embodiment is the same as the inductance element 4 according to the first modification of the fourth embodiment in that the magnetic structures 2U and 2D have lattice patterns. .

  In the second modification of the fourth embodiment, as shown in FIG. 22A, the arrangement structure of the lattice pattern of the magnetic structures 2U and 2D is different from that of the first modification of the fourth embodiment. There is. The other configuration is the same as that of the first modification of the fourth embodiment.

As shown in FIGS. 22 (a) and 22 (b), the inductance element 4 according to the second modification of the fourth embodiment includes a magnetic structure capable of reducing magnetic resistance and eddy current loss. Since the upper and lower electrodes 16 are provided above and below, the eddy current loss is further reduced and the AC resistance R _AC can be further reduced as compared with the inductance element 4 according to the fourth embodiment.

(Evaluation using search coil)
In order to verify whether the _AC resistance R _AC can be reduced by forming slits in the magnetic layer, the search coil 40 is mounted on the magnetic layer in which the slits SL are formed in various shapes, and impedance measurement is performed. went.

Schematic plane pattern configuration of the experimental system arranged search coil 40 on the magnetic layer 10 ₃ having the slit SL is expressed as shown in FIG. 23 (a), schematic bird's-eye view structure of the search coil 40 is schematically As shown in FIG. 23 (b). In addition, a schematic cross-sectional structure taken along line 9A-9A in FIG. 23A is expressed as shown in FIG.

As shown in FIG. 23A, the short side direction of the magnetic layer is the X axis direction, the long side direction is the Y axis direction, the short side direction of the search coil device is the D _X axis direction, and the long side direction is the D _Y axis It was the direction.

As shown in FIG. 24, a closed magnetic circuit (closed magnetic circuit) is formed by the search coil 40 and the magnetic structure 2 as shown by a broken line. The resistance R _AC can be evaluated.

Search coil 40, as shown in FIG. 23 (a), FIG. 23 (b), the arranged on the search coil board 42 is connected to the electrode terminals for search coil 38 _1, 38 _2.

As shown in FIGS. 23A and 24, the search coil 40 is disposed on the magnetic layer provided with the slit SL so that the coil surface of the search coil 40 faces the magnetic layer surface. Thus, the electrode terminals 38 _1, 38 ₂ for search coil can be taken out from the top.

  Further, in this experimental system, the magnetic structure is disposed on the magnetic layer substrate 50. Here, the magnetic structure has the same structure as the magnetic structure 2 (FIG. 12) according to the second embodiment.

As shown in FIG. 23A, the slit width of the slit SL is represented by ΔSL, and the slit spacing in the X-axis direction (arrangement pitch of the slits SL) is represented by W _X , and the slit spacing in the Y-axis direction (slit The arrangement pitch of SL is represented by W _Y.

It is desirable that the slit width ΔSL of the slit SL be smaller because the magnetic resistance R _m is reduced. Further, it is desirable that the slit spacing W _X · W _Y of the slits SL be longer as the magnetic resistance R _m decreases.

  The description of the slit spacing based on the dimension DS × DL of the search coil device is schematically represented as shown in FIG.

The experimental conditions of the experimental system in which the search coil 40 is disposed on the magnetic layer provided with the slit SL are expressed as shown in FIG. 26A, and the explanation of the angle θ ₂ of the D _X axis of the search coil with respect to the X axis is It is expressed as shown in FIG. Further, the description of the slit width ΔSL of the slits SL formed in the magnetic layer 10 and the slit spacing (slit pitch) SLP is expressed as shown in FIG. Furthermore, the experimental conditions which expanded FIG. 26 (a) using an orthogonal array, and compressed nine ways are represented as shown in FIG.

In FIG. 26 (a), No. 1 is as shown in FIG. 25 with the slit spacing SLP in the (D _X · D _Y ) direction under the condition that the angle θ ₂ is 90 ° and the slit width ΔSL is 2 μm (DS It corresponds to dividing a magnetic layer into the size of / 8) x (DL / 8). No.2, the angle theta ₂ is 45 ° · slit width ΔSL is the condition of 6 [mu] m, in the slit spacing SLP is (D _X · D _Y) direction, as shown in FIG. 25 (DS / 4) × ( DL / It corresponds to dividing the magnetic layer into the size of 4). No. 3 is (DS / 2) × (DL /) as shown in FIG. 25 in the slit spacing SLP in the (D _X · D _Y ) direction under the condition that the angle θ ₂ is 0 ° and the slit width ΔSL is 10 μm. It corresponds to dividing the magnetic layer into the size of 2). The same applies to FIG.

In FIGS. 26 (a) and 27, when the angle θ ₂ of the search coil and the magnetic layer is 90 °, this corresponds to an arrangement relationship in which the short side axis X of the search coil and the short side axis D _{X of the} magnetic layer are perpendicular. Search coil and the angle theta ₂ is 45 ° of the magnetic layer, the short side axis D _X of the short side axis X and the magnetic layer of the search coil corresponds to the arrangement relationship with an angle of 45 °. The angle θ ₂ of the search coil and the magnetic layer of 0 ° corresponds to an arrangement relationship in which the short side axis X of the search coil and the short side axis D _{X of the} magnetic layer are parallel.

  Note that in FIG. No. 1 is a pair of one magnetic layer. No. 2 is a pair of two magnetic layers. The number 3 of magnetic layers is provided with a pair of three layers.

  Similarly, in FIG. 1 to No. No. 3 is a pair of one magnetic layer. 4-No. No. 6 is a pair of two magnetic layers. 7-No. 9 is provided with a pair of three magnetic layers.

  In FIGS. 26 (a) and 27, the slit widths of 2 μm, 6 μm and 10 μm correspond to the condition that the slit width ΔSL of the slit SL is 2 μm, 6 μm and 10 μm. Further, in FIGS. 26A and 27, the film thickness of each magnetic layer is 2 μm.

In the above-described experimental system, the experimental result of the relationship between the increase in resistance R _{6 MHz} −R _{100 kHz} of the AC resistance R _AC and the inductance L is expressed as shown in FIG. In FIG. 28, WS corresponds to the slit structure, and experimental data corresponding to the experimental conditions of FIG. 26 (a) and FIG. 27 are shown by white circle plots and broken lines. The AC resistance R _AC of the resistance increase R _6MHz -R _100kHz is the difference AC resistance R _AC at a frequency of 6MHz and 100kHz. On the other hand, WOS corresponds to a structure without a slit, and the magnetic layer has a single layer structure, and the thickness of the magnetic layer is changed to 0.25 μm, 2 μm, 4 μm, 6 μm, 8 μm, 8 μm, 10 μm, 14 μm. Data are shown as black circle plots and solid lines.

As shown in FIG. 28, the resistance increase amount R _{6 MHz} −R _{100 kHz} of the _AC resistance R _AC tends to increase with the increase of the inductance L, but the fourth embodiment having the slit structure in the magnetic layer or its modification In the inductance element according to the present invention, the increase tendency of the magnetic layer is suppressed as compared with Comparative Example 4 of the single layer structure. That is, by providing the slit structure, the amount of increase in resistance of the _AC resistance R _AC can be reduced. Therefore, the alternating current resistance R _AC can be reduced by providing the magnetic layer with the slit structure.

(Evaluation of AC loss)
In the inductance element according to the fourth embodiment and the inductance element according to comparative example 4, the AC loss was compared. Specifically, in the inductance element according to the fourth embodiment having a magnetic structure in which slits are formed in the magnetic layer and the inductance element according to the comparative example 4 in which the magnetic layer has a single-layer structure, frequency characteristics of the inductance L and The frequency characteristics of _AC resistance R _AC were measured.

  29 is an inductance element according to Comparative Example 4, and a schematic bird's-eye view configuration is represented as shown in FIG. 29A, and a schematic cross-sectional structure along line 10A-10A in FIG. It is represented as shown in (b). In Comparative Example 4 shown in FIG. 29, the device size of the inductance element is 1.9 mm × 1.1 mm, and the thickness of the magnetic layer of the single layer structure is 6 μm.

30 is an inductance element according to a fourth embodiment, and a schematic bird's-eye view configuration is represented as shown in FIG. 30A, and a schematic cross-sectional structure along line 11A-11A in FIG. , As shown in FIG. 30 (b). In the example shown in FIG. 30, the device size of the inductance element is 1.9 mm × 1.1 mm, and the magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U and 10 ₁ D · 10 ₂ D · 10 of the three-layer structure. the thickness of ₃ D are each 2 [mu] m. The film thickness of the insulating layer 12 between the magnetic layers is 1 μm, and the slit widths ΔSL1, ΔSL2, and ΔSL3 are 10 μm each. The slit spacing is 1⁄4 of the device size, (DL / 4) × (DS / 4) = 475 μm × 275 μm, and the device size is divided by 16.

The experimental results of the frequency characteristics of the inductance L according to the fourth embodiment and the inductance L according to the comparative example 4 are expressed as shown in FIG. 31, and the experimental results of the frequency characteristics of the _AC resistance R _AC are shown in FIG. It is represented as shown in. 31 and 32, WS corresponds to the slit structure of the fourth embodiment shown in FIG. 30, and WOS corresponds to the non-slit structure of Comparative Example 4 shown in FIG.

In the inductance element according to the fourth embodiment, as shown in FIG. 31, the frequency characteristic of the inductance L is flat in the wide frequency band. Further, in the inductance element according to the fourth embodiment, as shown in FIG. 32, the frequency characteristic of the _AC resistance R _AC can suppress an increase in the AC resistance on the high frequency side. That is, the magnetic structure having a slit structure can improve the high frequency characteristics of the inductance L and can suppress an increase in AC resistance. As a result, the inductance element according to the fourth embodiment can reduce AC loss.

(Method of manufacturing inductance coil)
In addition, a schematic cross-sectional structure for explaining one step of a method of manufacturing the inductance coil 16 applicable to the inductance element 4 according to the fourth embodiment is as shown in FIGS. 33 (a) to 33 (e). expressed. In addition, a schematic cross-sectional structure for explaining one step of a method of manufacturing the inductance coil 16 applicable to the inductance element 4 according to the fourth embodiment, which is rectangular, trapezoidal, triangular or U-shaped The example which formed the groove part 15 is expressed as shown to FIG. 34 (a)-FIG.34 (d), respectively.
(A) First, as shown in FIG. 33A, the magnetic metal film to be the magnetic metal substrate 20 is cleaned and then chemically polished. Here, for example, PC permalloy (NiFeMoCu) can be applied to the magnetic metal film.
(B) Next, as shown in FIG. 33 (b), a groove 15 having a U-shaped structure is formed on the surface of the magnetic metal substrate 20, and then an insulating layer 25 is formed. The groove portion 15 can be formed by, for example, wet etching (using an etching solution containing phosphoric acid), laser processing, or pressing after resist patterning. For example, SiO ₂ can be applied as the insulating layer 25. In the formation of the insulating layer 25, a sputtering technique, a CVD technique, or the like can be used. By forming the insulating layer 25, electrical insulation between the magnetic metal substrate 20 and the metal wiring layer 22 can be obtained.
(C) Next, as shown in FIG. 33C, electrolytic plating is performed on the entire surface of the magnetic metal substrate 20 via the insulating layer 25 to form a metal wiring layer 22. Cu can be applied to the metal wiring layer 22. Other materials such as Pt, Au and Ag are also applicable.
(D) Next, as shown in FIG. 33D, the metal wiring layer 22 and the insulating layer 25 in the flat portion are etched to leave the metal wiring layer 22 filled only in the groove portion 15. For the etching, for example, dry etching technology, chemical mechanical polishing (CMP) technology, etc. can be applied. As a result, the excess metal wiring layer 22 can be removed.
(E) Next, as shown in FIG. 33 (e), the magnetic metal substrate 20 on the back surface is etched and thinned. For example, a wet etching technique, a CMP technique or the like can be applied to the back surface etching. As a result, the excess metal wiring layer 22 on the back surface can be removed.

  The inductance coil 16 applicable to the inductance element 4 according to the fourth embodiment is completed by the above steps.

  In the inductance coil applicable to the inductance element 4 according to the fourth embodiment, a schematic bird's-eye view structure showing a state in which the groove portion 15 is formed in the magnetic metal substrate 20 is represented as shown in FIG. A schematic bird's-eye view structure showing a metal wiring layer 22 and a terminal electrode 23 for an inductance coil formed in the groove portion 15 is expressed as shown in FIG.

  Furthermore, another inductance coil applicable to the inductance element 4 according to the fourth embodiment, and the schematic plane pattern configuration of the circular groove portion 15 formed on the magnetic metal substrate 20 is shown in FIG. The schematic plan pattern configuration in which the metal wiring layer 22 and the terminal electrode 23 for inductance coil are arranged in the circular groove portion 15 of FIG. 36 (a) is represented as shown in FIG. 36 (b). Is represented by

  Furthermore, another inductance coil applicable to the inductance element 4 according to the fourth embodiment, in which the octagonal groove portion 15 formed on the magnetic metal substrate 20 has a metal wiring layer 22 and a terminal for an inductance coil A schematic planar pattern configuration in which the electrode 23 is disposed is represented as shown in FIG. 36C, and is a schematic configuration in which the metal wiring layer 22 and the terminal electrode 23 for inductance coil are disposed in two opposing triangular grooves 15. The planar pattern configuration is represented as shown in FIG.

  Thus, in the inductance coil applicable to the inductance element 4 according to the fourth embodiment, the metal wiring layer 22 has a coil shape, and the coil shape is rectangular, circular, octagonal or triangular. It may have any of the plane patterns. Moreover, this coil shape may have a polygon or any plane pattern.

(Example of application to power supply circuit)
A configuration example of a power supply circuit to which the inductance element 4 according to the fourth embodiment is applied as a component is represented as shown in FIG. In FIG. 37, an example of a DC-DC step-down converter is shown.

DC-DC buck converter to apply the inductance element 4 according to the fourth embodiment includes a DC input voltage V _I, the MOSFET Q, a diode D, a capacitor C, and an inductor L. The inductor L according to the fourth embodiment is applied to the inductor L. FIG The DC-DC buck converter illustrated in 37, by the switching operation of the MOSFET Q, by switching the energy accumulated from the DC input voltage V _I to the inductor L, the DC input voltage V _I DC output voltage V _O which is stepped down from the Can be obtained from both ends of the capacitor C. The application example of the inductance element 4 according to the fourth embodiment is not limited to the DC-DC step-down converter described above, but is used for DC-DC step-up converter, choke coil application for noise removal, etc. Is also applicable.

[Application example]
(Inductor)
A schematic cross-sectional structure of an inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied, wherein a first configuration example is represented as shown in FIG. An example of the configuration is represented as shown in FIG. 38 (b), a third example of the configuration is represented as shown in FIG. 38 (c), and a fourth example of the configuration is shown in FIG. Be done.

  An inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied has a core 200 and a winding disposed on the core 200 as shown in FIGS. 38 (a) to 38 (d). A wire coil 220 and a magnetic structure 240 are provided, and the magnetic structure 240 can be magnetically coupled to the core 200.

  As the magnetic structure 240, as shown in FIGS. 38 (a) to 38 (d), the magnetic structure according to the second embodiment of the three-layer structure is applied. The magnetic structure according to the first or third embodiment is also applicable to the magnetic structure 240. As the core 200, a ferrite or metal magnetic material can be used. An Fe-Si based silicon rigid plate reactor or the like may be applied.

  In the inductor (EI core) 300 to which the magnetic structure 240 according to the fourth embodiment is applied, the magnetic circuit having a small magnetic resistance and eddy current loss is applied to the inductor to obtain the entire inductor (EI core). Magnetic resistance and eddy current loss can be reduced. In addition, leakage flux can be suppressed.

(Trance)
It is a schematic cross-sectional structure of the transformer 300 to which the magnetic structure 240 according to the fourth embodiment is applied, and the first configuration example is disposed in the core 200 and the core 200 as shown in FIG. 39 (a). The magnetic structure 240 can be magnetically coupled to the core 200. The magnetic structure 240 is provided with the primary side coil L1 and the secondary side coil L2 disposed in the core 200, and the magnetic structure 240.

The fourth magnetic structure 240 ₁ - 240 ₂ according to the embodiment a schematic sectional structure of a transformer 300 which is applied in the example the second configuration, as shown in FIG. 39 (b), the core 200, the core a primary coil L1 placed in 200, the secondary coil L2 disposed in the core 200, and a magnetic structure 240 _{1-240 2,} the magnetic structure 240 ₁ - 240 ₂ includes a core 200 Magnetic coupling is possible.

As shown in FIGS. 39 (a) and 39 (b), magnetic structures according to the second embodiment of the three-layer structure are applied as the magnetic structures 240 · 240 ₁ · 240 ₂ . The magnetic structures according to the first or third embodiment can also be applied to the magnetic structures 240, 240 ₁ , 240 ₂ . As the core 200, a ferrite or metal magnetic material can be used. An Fe-Si based silicon rigid plate reactor or the like may be applied.

  In the transformer 300 to which the magnetic structure 240 according to the fourth embodiment is applied, the application of a magnetic circuit with small magnetoresistance and eddy current loss to the transformer 300 reduces the magnetoresistance and eddy current loss of the entire transformer. Can be In addition, leakage flux can be suppressed.

(Electromagnetic shielding structure)
The schematic cross-sectional structure of the electromagnetic shielding structure 400 to which the magnetic structure 240 according to the fourth embodiment is applied is, as shown in FIG. 40, an electromagnetic shielding target object 250 and a hollow portion surrounding the electromagnetic shielding target object 250. The magnetic structure 240 surrounds the electromagnetic shielding target object 250 through the cavity 260. The electromagnetic shielding target object 250 is an object that does not want to give an electromagnetic field (E, H) such as a sensor component.

  In the electromagnetic shielding structure 400 to which the magnetic structure 240 according to the fourth embodiment is applied, the electromagnetic shielding structure 400 can be obtained by applying a magnetic circuit having a small magnetic resistance and an eddy current loss to the electromagnetic shielding structure 400. It is possible to reduce the overall reluctance and eddy current loss. In addition, leakage flux can be suppressed.

  As described above, according to the first to fourth embodiments, the magnetic structure capable of reducing the magnetoresistance and the eddy current loss, and the magnetic structure described above are applied to reduce the alternating current resistance, and the high frequency An inductance element excellent in characteristics can be provided.

  According to the first to fourth embodiments, an inductor, a transformer, and an electromagnetic shielding structure to which the above magnetic structure can be applied can be provided.

(Detailed configuration of inductance element)
FIG. 41B is a detailed configuration of the inductance element 4B according to the fourth embodiment, and a schematic bird's-eye view configuration is represented as shown in FIG. 41A, and is a schematic diagram along line 12A-12A in FIG. The target cross-sectional structure is represented as shown in FIG. 41 (b).

  As shown in FIGS. 41 (a) and 41 (b), the inductance element 4B according to the fourth embodiment includes an inductance coil 160, a magnetic structure 2U disposed on the surface of the inductance coil 160, and an inductance And a magnetic structure 2D disposed on the back surface of the coil 160.

Here, the magnetic structure 2U has a configuration in which a three-layer structure of magnetic layers 10 ₁ U · 10 ₂ U · 10 ₃ U is stacked, and the magnetic structure 2D is a magnetic layer 10 ₁ D · 10 ₂ D ··· It has a configuration in which a 3-layer structure of 10 ₃ D is stacked.

Insulating layer 122 ₁ between the magnetic layer 10 ₁ U · 10 ₂ U is formed, and the magnetic layer 10 ₁ U insulating layer 122 ₂ is formed between the magnetic layer 10 ₂ U · 10 ₃ U each other through the slit SL The magnetic layers 10 ₂ U are also divided into one another through the slits SL, and the magnetic layers 10 ₃ U are also divided into one another through the slits SL. The same applies to the magnetic layers 10 ₁ D, 10 ₂ D, and 10 ₃ D.

  The magnetic metal substrate 290 is made of, for example, permalloy.

  Further, the inductance coil 160 is formed of a metal wiring layer formed in the magnetic metal substrate 290. For example, it is formed by embedding a metal wiring layer in a spiral-shaped groove portion formed by performing etching on permalloy.

  In the inductance element 4B according to the fourth embodiment, a magnetic structure 2U · 2D having a slit is formed as a core to form a closed magnetic path structure.

  As shown in FIGS. 41 (a) and 41 (b), the inductance element 4B according to the fourth embodiment includes a magnetic structure 2U · 2D capable of reducing magnetic resistance and eddy current loss as an inductance coil 160. Because of the provision at the top and bottom, the eddy current loss can be reduced and the AC resistance can also be reduced.

Fifth Embodiment
(Configuration of inductance element)
42 is an inductance element 4 according to the fifth embodiment, and a schematic bird's-eye view configuration is represented as shown in FIG. 42 (a), and a side view viewed from the A direction of FIG. 42 (a) is FIG. It is expressed as shown in (b). A partially enlarged structural example 1 between the upper coils is represented as shown in FIG. 42 (c), and a partially expanded structural example 2 between the upper coils is represented as shown in FIG. 42 (d). Moreover, the side surface structure seen from the B direction of Fig.42 (a) is represented as shown in FIG.42 (e).

  The inductance element 4 according to the fifth embodiment includes a substrate 112, an upper coil 126 disposed on the front surface of the substrate 112, a lower coil 122 disposed on the back surface opposite to the front surface of the substrate 112, and An upper and lower coil connection portion 120 is provided which penetrates from the front surface to the rear surface and connects the upper coil 126 and the lower coil 122.

  As shown in FIGS. 42 (b) and 42 (d), a relatively thick insulating layer 128B may be embedded between the upper coils 126 via the insulating layer 128. Alternatively, as shown in FIG. 42 (c), the magnetic layer of the upper core 130 may be embedded between the upper coils 126 via the insulating layer 128.

  In Structural Example 2 in which the relatively thick insulating layer 128B is provided between the upper coils 126, the width W2 between the coils is twice or more the thickness D of the magnetic layer of the upper core 130, as shown in FIG. If applicable. On the other hand, in the structural example 1 including the magnetic layer of the upper core 130 between the upper coils 126, the width W1 between the coils is twice the thickness D of the magnetic layer of the upper core 130, as shown in FIG. It is applicable when it is small.

  In the inductance element 4 according to the fifth embodiment, the upper coil 126 and the lower coil 122 sandwich the substrate 112 to form a solenoid coil.

  Also, the lower core 124 may be provided on the substrate 112 between the upper coil 126 and the lower coil 122.

  The upper core 130 disposed on the surface of the upper coil 126, and the lower core 124 disposed on the substrate 112 between the upper coil 126 and the lower coil 122, wherein the upper core 130 and the lower core 124 are the upper coil A configuration may be provided in which magnetic coupling is performed at the end of the lower coil 122 and the lower coil 122.

  The inductance element 4 according to the fifth embodiment includes the substrate 112, the upper coil 126 disposed on the surface of the substrate 112, the lower coil 122 disposed on the back surface facing the surface of the substrate 112, and the substrate The upper and lower coil connection portions 120 penetrating from the surface to the back surface 112 and connecting the upper coil 126 and the lower coil 122, the upper core 130 disposed on the surface of the upper coil 126, and between the upper coil 126 and the lower coil 122 And the lower core 124 disposed on the substrate 112 of FIG. Here, the upper coil 126 and the lower coil 122 sandwich the substrate 112 to form a solenoid coil, and the upper core 130 and the lower core 124 are magnetically coupled at the end of the upper coil 126 and the lower coil 122 to form a solenoid You may provide the closed magnetic circuit which penetrates a coil.

  In addition, the substrate may be provided with either a silicon substrate or an insulating substrate such as a glass substrate or a ferrite substrate.

  As shown in FIGS. 42A to 42E, the inductance element 4 according to the fifth embodiment performs deep etching on the silicon substrate 112, the front and back surfaces of the silicon substrate, and the silicon substrate 112. It has an upper coil 126 and a lower coil 122 formed of a metal wiring layer disposed in a solenoid-shaped groove formed by implementation.

  Further, as shown in FIGS. 42A to 42E, the inductance element 4 according to the fifth embodiment may include an upper core 130 disposed on the surface of the upper coil 126. The upper core 130 may have a multilayer structure of a magnetic layer and an insulating layer. Here, the magnetic layer constituting the upper core 130 can be formed by plating, sputtering, vacuum evaporation, or the like.

Further, as shown in FIGS. 42A to 42E, the inductance element 4 according to the fifth embodiment is disposed on the surface of the silicon substrate 112, and is a solenoid formed of an upper coil 126 and a lower coil 122. You may provide the lower core 124 incorporated in a coil. The lower core 124 may have a multilayer structure of a magnetic layer and an insulating layer. Here, the magnetic layer constituting the lower core 124 can also be formed by plating, sputtering, vacuum evaporation, or the like.

  Here, the magnetic layer constituting the upper core 130 and the lower core 124 may be provided with a ferromagnetic material.

  The insulating layer constituting the upper core 130 and the lower core 124 may be any of ferromagnetic, paramagnetic or diamagnetic material, and may have a resistivity of 10 Ω · cm or more.

  In addition, the thickness of the magnetic layer constituting the upper core 130 and the lower core 124 can control the eddy current radius in the magnetic layer. By reducing the thickness of the magnetic layer, the eddy current radius can be reduced and eddy current loss can be reduced.

  Further, as shown in FIGS. 42A to 42E, the inductance element 4 according to the fifth embodiment has the upper core 130 and the lower core 124 at the end of the upper coil 126 and the lower coil 122. And may be combined.

  The upper core 130 and the lower core 124 can have a smaller eddy current radius, a reduced eddy current loss, and a reduced reluctance by forming a multilayer structure of a magnetic layer and an insulating layer.

  Further, by connecting the upper core 130 and the lower core 124 at the end of the upper coil 126 and the lower coil 122, a closed magnetic circuit can be formed which penetrates the solenoid structure including the upper coil 126 and the lower coil 122. The inductance value can be made relatively high.

  In the inductance element according to the fifth embodiment, as a simple configuration, the upper core and the lower core may be omitted, and the above-described solenoid structure may be provided.

  Further, in the inductance element according to the fifth embodiment, the lower core may be omitted and a combined structure of the upper core and the solenoid structure may be provided as a simple configuration.

  Moreover, in the inductance element according to the fifth embodiment, the upper core may be omitted and a combination structure of the lower core and the solenoid structure may be provided as a simple configuration.

  According to the fifth embodiment, it is possible to provide an inductance element which has reduced magnetic resistance, eddy current loss, alternating current resistance, high inductance, and excellent high frequency characteristics.

  According to the fifth embodiment, it is possible to provide an inductance element having a high inductance while maintaining the same AC resistance as the inductance element according to the fourth embodiment.

(Processing structure of silicon substrate)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 43, and the top view of FIG. 43 is represented as shown in FIG. The side view in the direction of the short side is represented as shown in FIG. 44 (b), and the bottom view of FIG. 43 is represented as shown in FIG. 44 (c).

  As shown in FIGS. 43 and 44 (a) to 44 (c), the inductance element 4 according to the fifth embodiment performs deep etching on the silicon substrate 112 so as to process the surface of the silicon substrate 112. It has a through hole 114 penetrating to the back surface, a lower core forming portion 116 formed on the front surface of the silicon substrate 112, and a lower coil forming portion 118 formed on the back surface of the silicon substrate.

(Structure of lower coil and upper and lower coil connections)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 45, and the top view of FIG. 45 is represented as shown in FIG. The side view in the direction of the short side is represented as shown in FIG. 46 (b), and the bottom view of FIG. 45 is represented as shown in FIG. 46 (c).

  As shown in FIGS. 45 and 46 (a) to 46 (c), the inductance element 4 according to the fifth embodiment performs a plating process on the through hole 114 and the lower coil forming portion 118. The upper and lower coil connection portions 120 and the lower coil 122 are formed.

(Structure of lower core)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 47, and the top view of FIG. 47 is represented as shown in FIG. The side view in the direction of the short side is represented as shown in FIG. 48 (b), and the bottom view of FIG. 47 is represented as shown in FIG. 48 (c).

  As shown in FIGS. 47 and 48 (a) to 48 (c), the inductance element 4 according to the fifth embodiment is formed by performing a plating process on the lower core forming portion 116. A core 124 is provided.

(Structure of upper coil)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 49, and the top view of FIG. 49 is represented as shown in FIG. 50 (a). The side view in the direction of the short side is represented as shown in FIG. 50 (b), and the bottom view of FIG. 49 is represented as shown in FIG. 50 (c).

  In the inductance element 4 according to the fifth embodiment, as shown in FIGS. 49 and 50 (a) to 50 (c), upper and lower coils on both ends of the long side with the insulating layer 128 on the lower core 124. The upper coil 126 connecting between the connection parts 120 is provided. In the process of forming the upper coil 126, photolithography and plating processes of a thick film resist can be applied.

(Structure of upper core)
A schematic bird's-eye view showing the internal structure of the inductance element 4 according to the fifth embodiment is represented as shown in FIG. 51, and the top view of FIG. 51 is represented as shown in FIG. 52 (a). The side view in the direction of the short side is represented as shown in FIG. 52 (b), and the bottom view of FIG. 51 is represented as shown in FIG. 52 (c). Further, a side view viewed from the long side direction of FIG. 51 is represented as shown in FIG.

  The inductance element 4 according to the fifth embodiment includes an upper core 130 disposed on the upper coil 126, as shown in FIGS. 51, 52 (a) to 52 (c) and 53.

(Connection structure of upper core and lower core)
A configuration in which the upper core 130 and the lower core 124 are coupled at the end of the upper coil 126, which is the inductance element 4 according to the fifth embodiment, is represented as shown in FIG.

  In the inductance element 4 according to the fifth embodiment, a closed magnetic path 32R is formed between the upper core 130 and the lower core 124 by coupling the upper core 130 and the lower core 124 as shown in FIG. Be done.

  An enlarged view of a portion C of FIG. 54 is expressed as shown in FIG. 55 (a). As shown in FIG. 55 (a), the upper core 130 has a multilayer structure of, for example, three pairs (3P) of magnetic layer and insulating layer, and the lower core 124 has, for example, eight pairs (8P) of magnetic layer and insulating layer The multi-layered structure of

  A schematic cross-sectional structure taken along line 13A-13A of FIG. 55 (a) is expressed as shown in FIG. 55 (b). The upper core 130 and the lower core 124 may have a multilayer structure of a magnetic layer and an insulating layer.

  The inductance element 4 according to the fifth embodiment may include the insulating layer 128 disposed on the surface of the substrate 112, and the lower core 124 and the upper core 130 may be stacked via the insulating layer 128. .

  The connection structure of the upper core and the lower core is disposed in the lower core forming portion 116 of the substrate 112, as shown in FIG. 55 (b), and includes the lower core 124 having a multilayer structure of the magnetic layer and the insulating layer; An insulating layer 128 disposed thereon, an upper coil 126 disposed on the insulating layer 128, an upper surface and a side surface of the upper coil 126 and an insulating layer 128 disposed on the upper surface and a multilayer structure of a magnetic layer and an insulating layer And a core 130.

(Production method)
In the method of manufacturing an inductance element according to the fifth embodiment, a substrate 112, an upper coil 126 disposed on the surface of the substrate 112, a lower coil 122 disposed on the back surface facing the surface of the substrate 112, and the substrate The upper and lower coil connection portions 120 penetrating from the surface to the back surface 112 and connecting the upper coil 126 and the lower coil 122, the upper core 130 disposed on the surface of the upper coil 126, and between the upper coil 126 and the lower coil 122 Forming the lower core 124, the lower coil 124, the lower coil 126, and the upper and lower coil connection portion 120, and forming the upper coil 126. And a step of forming the upper core 130.

(Processing process of silicon substrate)
The processing steps of the silicon substrate 112 will be described with reference to FIGS.

  In the processing step of the silicon substrate, back wiring etching is performed on the back surface of the substrate 112 to form a part of the lower coil forming portion 118 and the through hole 114, and through wiring etching is performed on the surface of the substrate 112. And forming the lower core forming portion 116 by performing lower core etching on the surface of the substrate 112.

  56A, which is a process of the method of manufacturing the inductance element 4 according to the fifth embodiment, and is represented as shown in FIG. 56A, and a schematic plan view of the silicon substrate 112 is shown. A schematic cross-sectional view along the -14A line is expressed as shown in FIG. 56 (b).

  In addition, a schematic plan view of the silicon substrate 112 subjected to the back surface wiring etching is represented as shown in FIG. 57A, and a schematic sectional view taken along line 15A-15A of FIG. It is expressed as shown in (b).

  In addition, a schematic plan view of the silicon substrate 112 subjected to the through wiring etching is represented as shown in FIG. 58A, and a schematic sectional view taken along line 16A-16A of FIG. It is expressed as shown in (b).

Further, a schematic plan view of the silicon substrate 112 subjected to the lower core etching is represented as shown in FIG. 59A, and a schematic sectional view taken along line 17A-17A of FIG. 59A is FIG. It is expressed as shown in (b).
(A1) First, as shown in FIGS. 56 (a) and 56 (b), a silicon substrate 112 is prepared.
(A2) Next, as shown in FIGS. 57 (a) and 57 (b), back surface wiring etching is performed on the back surface of silicon substrate 112 to form lower coil formation portion 118 and a part of through hole 114. Do.
(A3) Next, as shown in FIGS. 58A and 58B, through wiring etching is performed on the surface of the silicon substrate 112 to form through holes 114.
(A4) Next, as shown in FIGS. 59A and 59B, lower core etching is performed on the surface of the silicon substrate 112 to form a lower core forming portion 116.

  Here, in the case where a silicon substrate 112 of 10 Ω · cm or more or an insulating substrate such as glass or ferrite is applied as a substrate, the above steps may be used as it is, but a silicon substrate 112 of 10 Ω · cm or less is applied as a substrate. In this case, after forming the lower coil formation portion 118, the through hole 114, and the lower core formation portion 116, it is necessary to form an insulating layer by thermal oxidation or CVD.

(Manufacturing process of lower core, lower coil and upper and lower coil connection parts)
The manufacturing process of the lower core, the lower coil, and the upper and lower coil connection portions will be described with reference to FIGS.

  The step of forming lower core 124 and lower coil 122 and upper and lower coil connection portion 120 is performed for the plating step for through hole 114, lower coil formation portion 118 and lower core formation portion 116 after the processing step of substrate 112. A step of forming a first seed 113, a first resist 125 is coated on the surface of the substrate 112 or a dry film is laminated, and patterned by photolithography to carry out a plating formation step on the lower core forming portion 116. And forming the upper and lower coil connection portions 120 and the lower coil 122 by plating the through holes 114 and the lower coil formation portion 118 after removing the first resist 125 or the dry film.

  A schematic plan view of a silicon substrate 112 which is a step of a method of manufacturing an inductance element according to a fifth embodiment, and on which seed formation is performed on through holes 114, lower coil formation portion 118 and lower core formation portion 116. Is represented as shown in FIG. 60 (a), and a schematic cross-sectional view taken along line 18A-18A in FIG. 60 (a) is represented as shown in FIG. 60 (b).

  In addition, a schematic plan view of the silicon substrate on which the lower core 124 is formed by performing photolithography and plating formation is represented as shown in FIG. 61A, and is taken along line 19A-19A in FIG. A schematic cross-sectional view is expressed as shown in FIG. 61 (b).

Further, a schematic plan view of the silicon substrate on which the plating formation is performed on the through hole 114 and the lower coil forming portion 118 is represented as shown in FIG. 62 (a), and is along the 20A-20A line of FIG. 62 (a). A schematic cross-sectional view is expressed as shown in FIG. 62 (b).
(B1) After the above processing step of the silicon substrate 112, first, as shown in FIGS. 60 (a) and 60 (b), the through hole 114, the lower coil forming portion 118, and the lower core forming portion 116 are The step of forming the seed 113 for the plating step is carried out.
(B2) Next, as shown in FIGS. 61 (a) and 61 (b), the first resist 125 is coated on the surface of the silicon substrate or a dry film is laminated and patterned by photolithography to form the lower core forming portion A plating process is performed at 116 to form the lower core 124. In the formation of the lower core 124, a multilayer structure of a magnetic layer and an insulating layer may be formed. Here, the magnetic layer can be formed by sputtering technology, vacuum evaporation technology or the like in addition to plating technology.
(B3) Next, as shown in FIGS. 62 (a) and 62 (b), after removing the resist 125 or dry film, plating is performed on the through hole 114 / lower coil forming portion 118 to connect the upper and lower coils The portion 120 and the lower coil 122 are formed.

  Further, the step of forming the lower core 124 may have the step of forming a multilayer structure of the magnetic layer and the insulating layer.

(Manufacturing process of upper coil)
The manufacturing process of the upper coil will be described with reference to FIGS. 63 to 70.

  The process of forming the upper coil 126 includes a process of forming a first insulating layer 128 on the surface side of the substrate 112, a process of forming a first opening 128A to the first insulating layer 128, and a first opening 128A. A step of forming a second seed 129 on the entire surface of the substrate 112, a step of applying a second resist 131 to the second seed 129, patterning it by photolithography, and forming a second opening, and And performing a plating process to form the upper coil 126.

  A schematic plan view of a silicon substrate which is a process of a method of manufacturing an inductance element according to the fifth embodiment and on which front and back polishing steps have been carried out is represented as shown in FIG. A schematic cross-sectional view taken along line 21A-21A of a) is expressed as shown in FIG.

  In addition, a schematic plan view of the silicon substrate on which the surface-side insulating layer forming step has been performed is represented as shown in FIG. 64 (a), and a schematic cross-sectional view taken along line 22A-22A in FIG. It is expressed as shown in FIG.

  In addition, a schematic plan view of the silicon substrate subjected to the step of forming the opening to the surface-side insulating layer is represented as shown in FIG. 65A, and is a schematic sectional view taken along line 23A-23A in FIG. Is expressed as shown in FIG.

  A schematic plan view of the silicon substrate subjected to the upper coil seed forming step is represented as shown in FIG. 66 (a), and a schematic sectional view taken along line 24A-24A of FIG. 66 (a) is FIG. It is expressed as shown in (b).

  In addition, a schematic plan view of a silicon substrate subjected to a photolithography process for the upper coil is represented as shown in FIG. 67 (a), and is a schematic sectional view taken along line 25A-25A of FIG. 67 (a). Is expressed as shown in FIG. 67 (b).

  Also, a schematic plan view of the silicon substrate subjected to the plating formation step for the upper coil is represented as shown in FIG. 68 (a), and is a schematic sectional view taken along line 26A-26A of FIG. 68 (a). Is expressed as shown in FIG. 68 (b).

  In addition, a schematic plan view of the silicon substrate subjected to the resist peeling process for the upper coil is represented as shown in FIG. 69 (a), and is a schematic sectional view taken along line 27A-27A in FIG. 69 (a). Is expressed as shown in FIG. 69 (b).

Also, a schematic plan view of the silicon substrate subjected to the seed removal step for the upper coil is represented as shown in FIG. 70 (a), and is a schematic cross-sectional view along line 28A-28A in FIG. 70 (a). Is expressed as shown in FIG. 70 (b).
(C1) After the manufacturing steps of the lower core 124, the lower coil 122 and the upper and lower coil connection portion 120, as shown in FIGS. 63 (a) and 63 (b), the front and back polishing step is carried out to remove excess plating. Remove layer 22M.
(C2) Next, as shown in FIGS. 64A and 64B, the insulating layer 128 is formed on the surface side of the silicon substrate 112.
(C3) Next, as shown in FIGS. 65 (a) and 65 (b), the step of forming an opening 128A in the insulating layer 128 is performed.
(C4) Next, as shown in FIGS. 66 (a) and 66 (b), the step of forming the seed 129 for the plating step for the upper coil is carried out. Here, the seed 129 is formed on the entire surface of the silicon substrate including the opening 128 A for the insulating layer 128.
(C5) Next, as shown in FIGS. 67 (a) and 67 (b), a resist 131 is applied on the seed 129, patterned by photolithography, and an opening for the plating process of the upper coil 126. Form
(C6) Next, as shown in FIGS. 68 (a) and 68 (b), a plating process is performed on the seed 129 to form the upper coil 126.
(C7) Next, as shown in FIGS. 69 (a) and 69 (b), the resist 131 is peeled off.
(C8) Next, as shown in FIGS. 70A and 70B, the seed 129 used in the plating process of the upper coil 126 is removed to expose the insulating layer 128.

(Upper core manufacturing process)
The manufacturing process of the upper coil will be described with reference to FIGS.

  In the step of forming the upper core 130, the step of forming the second insulating layer 128C on the surface of the upper coil 126 and the substrate 112 after the step of forming the upper coil 126, and the third seed 130S on the second insulating layer 128C. A step of forming, a step of forming a third opening by applying a third resist 133 on the third seed 130S, patterning by photolithography, and performing a plating step on the third seed 130S And forming the core 130.

  As shown in FIG. 71A, a schematic plan view of a silicon substrate which is a step of a method of manufacturing an inductance element according to the fifth embodiment and on which an insulating layer forming step for the upper core is performed is shown. A schematic cross-sectional view taken along line 29A-29A of FIG. 71 (a) is shown as shown in FIG. 71 (b).

  Also, a schematic plan view of the silicon substrate subjected to the seed formation process for the upper core is represented as shown in FIG. 72 (a), and is a schematic sectional view taken along line 30A-30A of FIG. 72 (a). Is expressed as shown in FIG. 72 (b).

  Further, a schematic plan view of the silicon substrate subjected to the photolithography process for the upper core is represented as shown in FIG. 73 (a), and is a schematic sectional view taken along line 31A-31A of FIG. 73 (a). Is expressed as shown in FIG. 73 (b).

  Further, a schematic plan view of the silicon substrate subjected to the plating formation step for the upper core is represented as shown in FIG. 74 (a), and is a schematic sectional view taken along line 32A-32A of FIG. 74 (a). Is expressed as shown in FIG. 74 (b).

  In addition, a schematic plan view of the silicon substrate subjected to the resist removing step for the upper core is expressed as shown in FIG. 75 (a), and is a schematic sectional view taken along line 33A-33A in FIG. 75 (a). Is represented as shown in FIG. 75 (b).

Also, a schematic plan view of the silicon substrate subjected to the seed removal step for the upper core is represented as shown in FIG. 76 (a), and is a schematic sectional view taken along line 34A-34A in FIG. 76 (a). Is represented as shown in FIG. 76 (b), and a schematic cross-sectional view taken along line 35A-35A of FIG. 76 (a) is represented as shown in FIG.
(D1) As shown in FIGS. 71 (a) and 71 (b), after the above manufacturing process of upper coil 126, insulation for upper core (130) on upper coil 126 and silicon substrate 112 surfaces. Form layer 128C. Here, the insulating layer 128C is the same as the relatively thick insulating layer 128B embedded between the upper coils 126 shown in FIG. 42 (b).
(D2) Next, as shown in FIGS. 72 (a) and 72 (b), a seed 130S for the upper core (130) is formed on the insulating layer 128C.
(D3) Next, as shown in FIGS. 73 (a) and 73 (b), a resist 133 is applied on the seed 130S, patterned by photolithography, and an opening for the plating process of the upper core 130. Form
(D4) Next, as shown in FIG. 74 (a) and FIG. 74 (b), a plating process is performed on the seed 130S to form the upper core 130. In the formation of the upper core 130, a multilayer structure of a magnetic layer and an insulating layer may be formed.
(D5) Next, as shown in FIGS. 75 (a) and 75 (b), the resist 133 is peeled off.
(D6) Next, as shown in FIGS. 76A, 76B and 77, the seed 130S used in the plating process of the upper core 130 is removed to expose the insulating layer 128C. The above steps result in the formation of a solenoid structure embedded in the silicon substrate 112.

  Further, the step of forming the upper core 130 may include the step of forming a multilayer structure of the magnetic layer and the insulating layer.

(Coil configuration)
In the inductance element according to the fifth embodiment, a schematic plan view showing the upper coil 126 and the lower coil 122 formed on the silicon substrate is represented as shown in FIG. 78 (a), and FIG. 78 (a) A schematic cross sectional view taken along the line 36A-36A of FIG. 78 is expressed as shown in FIG. 78 (b), and a schematic cross sectional view taken along the line 37A-37A of FIG. 78 (a) is shown in FIG. Be done.

  The upper coil 126 and the lower coil 122 disposed on the front and back surfaces of the silicon substrate 112 are upper and lower coils formed at the end of the silicon substrate as shown in FIGS. 78 (a), 78 (b) and 79. It is connected via the connection unit 120. Therefore, the inductance element according to the fifth embodiment has a solenoid structure.

(Core configuration)
In the inductance element according to the fifth embodiment, a schematic plan view showing the upper core 130 and the lower core 124 formed on the silicon substrate 112 is represented as shown in FIG. 80 (a), and FIG. A schematic cross sectional view taken along the line 38A-38A) is shown as shown in FIG. 80 (b), and a schematic cross sectional view taken along the line 39A-39A shown in FIG. 80 (a) shown in FIG. expressed.

  The lower core 124 disposed on the surface of the silicon substrate 112 and the upper core 130 disposed on the upper coil 126 are magnetically coupled at the end of the silicon substrate 112, so that a closed magnetic path is formed. For this reason, the inductance of the inductance element according to the fifth embodiment exhibits a relatively high value.

(Inductance frequency characteristics)
The frequency characteristic of the inductance L of the inductance element according to the fifth embodiment is expressed as shown in FIG. In FIG. 82, the curve SOL corresponds to the solenoid structure according to the fifth embodiment, and the curve SPI corresponds to the spiral structure according to the fourth embodiment.

  The frequency characteristic of the inductance L of the inductance element according to the fifth embodiment exhibits a substantially constant value in the measurement range of 100 kHz to 10 MHz, and the inductance value is smaller than that of the spiral structure according to the fourth embodiment. It shows about twice the value.

  The inductance L is proportional to the square of the number of turns N of the coil. Therefore, a solenoid structure having a large number of coil turns per unit area is advantageous for increasing the inductance value.

(Frequency characteristics of AC resistance)
The frequency characteristic of the AC resistance ACR of the inductance element according to the fifth embodiment is expressed as shown in FIG. In FIG. 83, the curve SOL corresponds to the solenoid structure according to the fifth embodiment, and the curve SPI corresponds to the spiral structure according to the fourth embodiment.

  The frequency characteristic of the alternating current resistance ACR of the inductance element according to the fifth embodiment exhibits substantially the same characteristic as the spiral structure according to the fourth embodiment in a measurement range of 100 kHz to 10 MHz.

  Most of the AC resistance is caused by the eddy current loss generated by the high frequency magnetic flux entering the core. Eddy current loss can be reduced by narrowing the eddy current radius. The solenoid structure is advantageous in suppressing the alternating current resistance ACR because the eddy current radius can be controlled by forming the core in multiple layers.

  In the inductance element according to the fifth embodiment, the inductance value can be increased while maintaining the AC resistance ACR substantially equivalent to the spiral structure according to the fourth embodiment.

(module)
The inductance element (L1) 130, integrated circuit for control (IC: Integrated circuit) 140A, load capacitor (C1) 150, snubber capacitor (CB) 180 is arranged on a printed circuit board (PCB) 100. The module according to the embodiment of is schematically represented as shown in FIG.

  On the other hand, a module according to the fifth embodiment in which the inductance element L1 according to the fifth embodiment and the IC 140A for control, the load capacitor (C1) 150, the snubber capacitor (CB) 180, etc. Is schematically represented as shown in FIG. Here, the inductance element L1 according to the fifth embodiment is formed on a silicon substrate 110 (Si) and has a solenoid structure.

  A module according to the fourth embodiment in which an inductance element (L1) 130, a DC / DC converter IC 140B, a load capacitor (C1) 150, a snubber capacitor (CB) 180 is disposed on the PCB 100 is schematically shown in FIG. Is represented by

  On the other hand, an inductance element L1 according to the fifth embodiment formed on a silicon substrate, and a fifth in which a DC / DC converter IC 140B, a load capacitor (C1) 150 and a snubber capacitor (CB) 180 are disposed on the silicon substrate 110. A schematic side view (configuration example 1) of the module according to the embodiment is represented as shown in FIG.

  The inductance element L1 according to the fifth embodiment is formed on a silicon substrate 110 (Si) and has a solenoid structure. Further, as shown in FIG. 87, an inductance element L1 according to the fifth embodiment is formed in a silicon substrate 110 having a substrate thickness T1, and a DC / DC converter IC 140B. Load capacitor (C1) 150 snubber capacitor. (CB) 180 is disposed on a relatively thin silicon substrate 110 having a substrate thickness T2. For this reason, the module to which the inductance element according to the fifth embodiment is applied has a configuration advantageous for reducing the height.

  A fifth embodiment in which an inductance element L1 according to the fifth embodiment formed on a silicon substrate 110 and a control IC 140A, a load capacitor (C1) 150 and a snubber capacitor (CB) 180 are disposed on the silicon substrate 110. A schematic side view (configuration example 2) of the module according to is represented as shown in FIG. Configuration example 2 of FIG. 88 applies a relatively thin silicon substrate 110 and has a configuration advantageous for reducing the height. In the configuration example 2 of FIG. 88, since the inductance element L1 is built in the silicon substrate 110, the area can be reduced in addition to the reduction in height of the module.

  In addition, a model of a module according to the fifth embodiment in which the control IC 140A and the load capacitor (C1) 150 are disposed on the inductance element L1 according to the fifth embodiment formed on the silicon substrate 110 and the silicon substrate 110. A schematic side view (configuration example 3) is represented as shown in FIG. In Configuration Example 3 of FIG. 89, the snubber capacitor (CB) is omitted. Similarly, Configuration Example 3 in FIG. 89 also applies a relatively thin silicon substrate 110 and has a configuration advantageous for reducing the height. In the configuration example 3 of FIG. 89, since the inductance element L1 is built in the silicon substrate 110, the area can be reduced in addition to the reduction in height of the module.

(DC / DC converter and output load circuit)
Also, the connection configuration of the output load circuit and the DC / DC converter (DCDC) mounted on the silicon substrate 110 by applying the inductance element according to the fifth embodiment to the output load circuit is shown in FIG. Is represented.

An example of the output circuit of the DC / DC converter (DCDC), as shown in FIG. 90, includes a complementary circuit arrangement consisting of a p-channel MOSFET Q _p 1 · n-channel MOSFET Q _n 1. The source of p-channel MOSFET Q _p 1 is connected to power supply pin P, and the source of n-channel MOSFET Q _n 1 is connected to GND pin N. The output of the DC / DC converter is taken out from the drain of the p-channel MOSFET Q _p 1 and the drain of the n-channel MOSFET Q _n 1.

The output of the DC / DC converter is connected to the external lead pin P1, and the external lead pin P1 is further connected to one electrode of the inductance L1 via the power wiring LX1. Further, the load capacitor C1 is connected between the other electrode of the inductance L1 and the ground potential, and the output voltage V _out 1 is taken _out from both ends of the load capacitor C1.

Further, as shown in FIG. 90, a snubber capacitor CB1 is connected between the power supply pin P and the GND pin N of the DC / DC converter. Further, as shown in FIG. 90, parasitic interconnection inductance L _p1 and interconnection resistance R _p 1 exist in the power interconnection LX1 connected to the external lead pin P1. Therefore, as shown in FIG. 90, the output load circuit connected to the external lead pin P1 of the DC / DC converter is configured by the wiring inductance L _p1 , the wiring resistance R _p1 , the inductance L1 and the load capacitor C1.

  The inductance element according to the fifth embodiment is applicable to the inductance L1 constituting the output load circuit, and is formed on the silicon substrate 110.

  Also, as shown in FIG. 90, the DC / DC converter (DCDC) can be mounted on the silicon substrate 110.

  The load capacitor C1 · snubber capacitor CB1 can also be mounted on the silicon substrate 110 as shown in FIG.

  According to the fifth embodiment, an inductance element having reduced magnetic resistance, eddy current loss, and alternating current resistance, high inductance, and excellent high frequency characteristics, a method of manufacturing the same, and a module to which the above inductance element is applied Can be provided.

Sixth Embodiment
(Configuration of electrode built-in substrate)
FIG. 91A is a schematic plan view showing the electrode-embedded substrate according to the sixth embodiment, and an example in which beam portions have stripe patterns parallel to each other in plan view is represented as shown in FIG. 91A. An example provided with a stripe pattern in which the beam portions intersect with each other at a predetermined angle θ in plan view is represented as shown in FIG. 91 (b).

  A schematic cross-sectional structure taken along line 40A-40A in FIG. 91 (a) is represented as shown in FIG. 92 (a), and a schematic cross-sectional structure taken along line 41A-41A in FIG. 91 (a) is It is expressed as shown in FIG. 92 (b).

As shown in FIGS. 91 to 92, the electrode-embedded substrate 1 according to the sixth embodiment includes a substrate 212, grooves 225 ₁ 225 ₂ 225 ₃ formed inside the substrate 212, and a substrate 212. includes a beam portion 228 _1, 228 _2, 228 ₃ that is disposed on the rear surface opposite to the surface, and a groove portion 225 _1, 225 _2, 225 ₃ embedded in the wiring layers 226 _1, 226 _2, 226 _3. Here, inside which is formed on the groove portions 225 _1, 225 _2, 225 ₃ of the substrate 212, by embedding a metal such as copper (Cu), wiring layers 226 _1, 226 _2, 226 ₃ are formed.

Further, the beam portions 228 _1, 228 _2, 228 _3, as shown in FIG. 91 (a), perpendicular to the wiring layer 226 _1, 226 _2, 226 ₃ in a plan view, and a parallel stripe pattern with each other .

Further, the beam portion 228 ₁ - 228 _2, as shown in FIG. 91 (b), may be provided with a stripe pattern crossing each other at a predetermined angle θ in plan view.

Further, as shown in FIG. 92 (a), the thickness TB of the beam portions 228 _1, 228 _2, 228 ₃ is thinner than the depth TD of the groove. Further, the beam portions 228 _1, 228 _2, 228 _3, as shown in FIG. 91 to FIG. 92, each include a width W1, W2, W3.

In addition, the groove portions 225 ₁ 225 ₂ 225 ₃ , the beam portions 228 ₁ 228 _{2 2 3 3} or the wiring layers 226 _{1 2 6 2 2 2 3 3} are rectangular, circular, oval, octagonal or triangular in plan view. It may have a pattern of either or polygons.

  Further, for example, in the case where the groove portion and the wiring layer have stripe patterns which are parallel and intersect each other at 90 ° in plan view, an electrode-embedded substrate for an inductance element as shown in FIG. Can.

  Further, in the electrode-embedded substrate 1 according to the sixth embodiment, the substrate 212 may include a silicon substrate or a glass substrate.

  In addition, a schematic plane pattern of the electrode-embedded substrate 1 according to the sixth embodiment, which is a relatively long line and space (L & S: Line and Space) formed on the silicon wafer 222. The configuration is represented as shown in FIG. 93, and the schematic cross-sectional structure along line 42A-42A in FIG. 93 is represented as shown in FIG. 94 (a), and the schematic cross section along line 43A-43A in FIG. The cross-sectional structure is represented as shown in FIG.

In the electrode-embedded substrate 1 according to the sixth embodiment, as shown in FIGS. 93 to 94, the silicon wafer 222 and the groove portions 225 ₁ , 225 ₂ , 225 ₃ ... Formed in the silicon wafer 222. 225 _n and the silicon wafer 222 facing the beam portion 228 ₁ - 228 ₂ arranged on the back surface to the surface of the groove portions 225 _1, 225 _2, 225 _3, ..., 225 embedded _n the wiring layers 226 _1, 226 ₂ · 226 ₃ · · · · · · 226 _n . Here, the metal layer such as copper (Cu) is embedded in the grooves 225 ₁ 225 ₂ 225 ₃ ... 225 _n formed in the inside of the silicon wafer 222 to form the wiring layers 226 ₁ 226 _{2. 3} ... 226 _n are formed.

Further, the beam portion 228 ₁ - 228 _2, as shown in FIG. 93, and a parallel stripe pattern in plan view.

Further, as shown in FIG. 94 (a), the thickness TB of the beam portion 228 ₁ is formed thinner than the depth TD of the groove.

  A schematic planar pattern configuration of the electrode-embedded substrate 1B according to the fourth embodiment, which has a relatively long line and space (L & S) formed on a silicon wafer 222, is , As shown in FIG. 95 (a).

Electrodes embedded substrate 1B according to Comparative Example 5, the silicon wafer 222, but comprises internally formed embedded in the through-hole interconnection layer _{226 1 · 226 2 · 226 3} · ... · 226 n of the silicon wafer 222, since having no beam portion structure, as shown in broken line ST portion of FIG. 95 (a), sticking tends to occur where the line between the wiring layers _{226 1 · 226 2 · 226 3} · ... · 226 n are in contact.

  On the other hand, a schematic planar pattern configuration of the electrode-embedded substrate 1 according to the sixth embodiment, which is formed on the silicon wafer 222 and has a relatively long line and space, is shown in FIG. It is expressed as shown in).

Sixth electrode embedded substrate 1 according to the embodiment of a silicon wafer 222, and the interior formed embedded in the through-hole interconnection layer _{226 1 · 226 2 · 226 3} · ... · 226 n of the silicon wafer 222 in order to provide a beam portion 228 ₁ - 228 ₂ provided with stripe patterns crossing each other at a predetermined angle θ in plan view as shown in FIG. 95 (b), _3-wiring layers 226 _1, 226 _2, 226 ... -It is possible to suppress the occurrence of sticking where the 226 _n lines contact with each other.

  In addition, a schematic plane pattern configuration of the electrode-embedded substrate 1B according to the comparative example 5 having the spiral-shaped inductance element formed on the silicon substrate 212 is represented as shown in FIG. .

  In the electrode-embedded substrate 1B according to Comparative Example 5, as shown in FIG. 96, since the wiring layer 226 embedded in the through hole is formed in a coil shape, the silicon substrate 212 is used in the state where the groove of the through hole is formed. Since it is only the portion A of the circle shown by the broken line in FIG. 96 to support, the manufacturing reliability tends to be reduced.

  The electrode-embedded substrate according to the sixth embodiment can be formed, for example, by forming a groove in a silicon substrate and embedding copper in the groove, so that a spiral coil structure can be easily realized inside the silicon substrate. is there.

  The electrode-embedded substrate according to the sixth embodiment can be applied to a lamination module of LSI, an interposer, an inductance element, a shield substrate, and the like as described later.

  The electrode-embedded substrate according to the sixth embodiment can form an electrode-embedded substrate structure by two-step etching of the substrate. In addition, since a grid-like beam portion structure is provided on the back surface, for example, even if the line and space (L & S) of the electrode wiring layer is increased, sticking between lines hardly occurs.

  Further, in the electrode-embedded substrate according to the sixth embodiment, since the portion other than the beam portion has a penetration structure, it is easy to be filled with metal plating such as copper.

  In the sixth embodiment, it is possible to provide an electrode-embedded substrate that has a simple structure and is less likely to cause sticking between lines, and the reliability can be improved.

(Method of manufacturing electrode-embedded substrate)
FIG. 97 (a) shows a schematic surface pattern configuration of the electrode-embedded substrate 1 according to the sixth embodiment, and a schematic cross-sectional view taken along line 44A-44A of FIG. 97 (a). The structure is represented as shown in FIG. 97 (b), and a schematic cross-sectional view taken along line 45A-45A of FIG. 97 (a) is represented as shown in FIG. 97 (c). The schematic back surface pattern configuration corresponding to) is expressed as shown in FIG. FIG. 97 (b) also corresponds to a schematic cross-sectional structure taken along line 44A-44A in FIG. 97 (d). FIG. 97 (c) also corresponds to a schematic cross-sectional structure taken along line 45A-45A in FIG. 97 (d).

In the electrode-embedded substrate 1 according to the sixth embodiment, as shown in FIGS. 97 (a) to 97 (d), the substrate 212 and the groove portions 225 ₁ , 225 ₂ , 225 formed in the substrate 212 are provided. ₃ · 225 ₄ · 225 ₅ and embedded in the beam portions 228 ₁ · _{2 8 2} · ₂ 28 ₃ and the groove portions 225 ₁ · 225 ₂ · 225 ₃ · 225 ₄ · _{25 5} disposed on the back surface opposite to the surface of the substrate 212 Wiring layer 226 ₁ · 226 ₂ · 226 ₃ · 226 ₄ · _{2 2 5} . Here, the metal layer such as copper (Cu) is embedded in the grooves 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ formed in the inside of the substrate 212 to form the wiring layers 226 ₁ 226 ₂ 226. ₃ - 226 ₄ - 226 ₅ are formed.

Further, the beam portions 228 _1, 228 _2, 228 _3, as shown in FIG. 97 (a), FIG. 97 (d), a wiring layer 226 _1, 226 _2, 226 _3, 226 _4, 226 ₅ in a plan view It has stripe patterns which are orthogonal and parallel to each other. Although not shown, the beam portion may have a stripe pattern which intersects with each other at a predetermined angle θ in plan view, as in FIG. 91 (b).

Further, as shown in FIG. 97 (b), the thickness TB of the beam portions 228 _1, 228 _2, 228 ₃ is thinner than the depth TD of the groove. Also, the thickness T of the substrate 212 is equal to TB + TD.

Further, as shown in FIG. 97 (d), the line width of the wiring layers 226 _1, 226 _2, 226 _3, 226 _4, 226 ₅ is equal to Y, the space width is equal to X.

  A method of manufacturing the electrode-embedded substrate according to the sixth embodiment shown in FIG. 97 will be described with reference to FIGS.

In the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, a step of forming grooves 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ inside the substrate 212, and a back surface facing the surface of the substrate 212. in forming a beam portion 228 _1, 228 _2, 228 _3, a wiring layer 226 _1, 226 _2, 226 _3, 226 _4, 226 ₅ to the groove 225 _{1-225 2-225 3-225 4-225 5} And forming a buried layer.

  A schematic surface pattern configuration at the start of the process, which is a process of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. A schematic cross-sectional structure along line 46A-46A is represented as shown in FIG. 98 (b), and a schematic back surface pattern configuration corresponding to FIG. 98 (a) is represented as shown in FIG. 98 (c). Ru. FIG. 98 (b) also corresponds to a schematic cross-sectional structure taken along line 46A-46A in FIG. 98 (c).

  A schematic surface pattern configuration in the photolithography process of the upper surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. 99 (a), and FIG. A schematic cross-sectional structure taken along line 47A-47A of FIG. 99 is expressed as shown in FIG. 99 (b), and a schematic back surface pattern configuration corresponding to FIG. 99 (a) is shown as FIG. 99 (c). expressed. FIG. 99 (b) also corresponds to a schematic cross-sectional structure taken along line 47A-47A in FIG. 99 (c).

  A schematic surface pattern configuration in the etching process of the upper surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. 100 (a), and FIG. 100 (a) A schematic cross-sectional structure along line 48A-48A is represented as shown in FIG. 100 (b), and a schematic back surface pattern configuration corresponding to FIG. 100 (a) is shown in FIG. 100 (c). Be done. FIG. 100 (b) also corresponds to a schematic cross-sectional structure taken along line 48A-48A in FIG. 100 (c).

  A schematic surface pattern configuration in the resist stripping process of the upper surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. 101 (a), and FIG. The schematic cross-sectional structure along line 49A-49A of FIG. 101 is represented as shown in FIG. 101 (b), and the schematic back surface pattern configuration corresponding to FIG. 101 (a) is as shown in FIG. 101 (c) expressed. FIG. 101 (b) also corresponds to a schematic cross-sectional structure taken along line 49A-49A in FIG. 101 (c).

(Step of forming a groove)
(A1) First, as shown in FIGS. 98 (a) to 98 (c), the substrate 212 is prepared. The substrate 212 may comprise a silicon substrate or a glass substrate.
(A2) Next, as shown in FIGS. 99 (a) to 99 (c), a resist 214 is applied on the surface of the silicon substrate 212 and patterned by a photolithography process.
(A3) Next, as shown in FIGS. 100 (a) to 100 (c), etching is performed on the surface of the silicon substrate 212 to form grooves 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ Do.
(A4) Next, as shown in FIGS. 101 (a) to 101 (c), the resist 214 on the surface of the substrate 212 is peeled off. Here, as shown in FIGS. 100 (b) and 101 (b), the width of the grooves 225 ₁ · 225 ₂ · 225 ₃ · 225 ₄ · 225 ₅ is represented by Y, and the grooves 225 ₁ · 225 ₂ · 225 The width between ₃ · 225 ₄ · 225 ₅ is represented by X. Further, the depth of the groove portions 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ is represented by TD. In addition, the thickness of the substrate 212 to be a thinned beam portion is represented by TB. The thickness TB is formed thinner than the depth TD of the groove.

Here, when applying the insulating substrate such as a glass substrate as the substrate 212, but may remain above process, when applying the silicon substrate as the substrate 212, grooves 225 _1, 225 _2, 225 _3, After forming 225 ₄ · 225 ₅ , it is necessary to form an insulating layer by thermal oxidation or chemical vapor deposition (CVD).

(Formation process of beam part)
A schematic surface pattern configuration in the photolithography process of the lower surface, which is one process of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. 102 (a), and FIG. 102 (b) is expressed as shown in FIG. 102 (b), and the schematic sectional structure along line 51A-51A of FIG. 102 (a) is shown in FIG. 102 (c). A schematic back surface pattern configuration which is represented as shown and corresponds to FIG. 102 (a) is represented as shown in FIG. 102 (d). FIG. 102 (b) also corresponds to a schematic cross-sectional structure taken along line 50A-50A in FIG. 102 (d). FIG. 102 (c) also corresponds to a schematic cross-sectional structure taken along line 51A-51A in FIG. 102 (d).

  A schematic surface pattern configuration in the step of etching the lower surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is represented as shown in FIG. 103 (a), and is shown in FIG. A schematic cross-sectional structure taken along line 52A-52A is shown as shown in FIG. 103 (b), and a schematic cross-sectional structure taken along line 53A-53 in FIG. 103 (a) is shown in FIG. 103 (c). As shown in FIG. 103 (d), a schematic back surface pattern configuration corresponding to FIG. 103 (a) is represented. FIG. 103 (b) also corresponds to a schematic cross-sectional structure taken along line 52A-52A in FIG. 103 (d). FIG. 103 (c) also corresponds to a schematic cross-sectional structure taken along line 53A-53 in FIG. 103 (d).

A schematic surface pattern configuration in the step of removing the resist on the lower surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. 104 (a), FIG. A schematic cross-sectional structure taken along line 54A-54A is shown as shown in FIG. 104 (b), and a schematic cross-sectional structure taken along line 55A-55A in FIG. 104 (a) is shown in FIG. A schematic back surface pattern configuration which is represented as shown and corresponds to FIG. 104 (a) is represented as shown in FIG. 104 (d). FIG. 104 (b) also corresponds to a schematic cross-sectional structure taken along line 54A-54A in FIG. 104 (d). FIG. 104 (c) also corresponds to a schematic cross-sectional structure taken along line 55A-55A in FIG. 104 (d).
(B1) Next, as shown in FIGS. 102 (a) to 102 (d), a resist 216 is applied on the back surface of the substrate 212 and patterned by a photolithography process. Here, as shown in FIG. 102 (c), as compared to the opening width of the upper portion of the resist 214 (corresponding to Y ₁ in FIG. 102 (c)), the opening width Y ₂ of the lower portion of the resist 216 is relatively It is desirable to set narrowly. For example, the opening widths Y ₁ and Y ₂ are 50 μm and 30 μm. It is for suppressing generation | occurrence | production of the level | step difference accompanying alignment shift.
(B2) Next, as shown in FIGS. 103 (a) to 103 (d), etching is performed on the back surface of the substrate 212 to form through groove portions 227 _{1 2 2 2 2 3 2 4 2 4 2 5 5} To form beam portions 228 ₁ · 228 ₂ · 228 ₃ . By setting a relatively narrow opening width Y ₂ of the lower part of the resist 216, the substrate 212, the stepped structure as shown in FIG. 103 (c) it is formed. Similar structures are maintained in the following steps.
(B3) Next, as shown in FIGS. 104 (a) to 104 (d), the resist 216 on the back surface of the substrate 212 is removed. Here, as shown in FIGS. 104 (b) and 104 (c), the width of the grooves 225 ₁ · 225 ₂ · 225 ₃ · 225 ₄ · 225 ₅ is represented by Y, and the grooves 225 ₁ · 225 ₂ · 225 The width between ₃ · 225 ₄ · 225 ₅ is represented by X. Further, the depth of the groove portions 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ is represented by TD. The thickness of the silicon substrate 212 portion that becomes the beam portions 228 _1, 228 _2, 228 ₃ is represented by TB. The thickness TB is formed thinner than the depth TD of the groove. In the case of a silicon substrate, an insulating layer can be formed over the entire substrate by further performing a thermal oxidation step.

(Embedding process of wiring layer)
A schematic surface pattern configuration in the metal (Cu) plating embedding step, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is expressed as shown in FIG. A schematic cross-sectional structure taken along line 56A-56A of (a) is represented as shown in FIG. 105 (b), and a schematic cross-sectional structure taken along line 57A-57A of FIG. 105 (a) is shown in FIG. The schematic back surface pattern configuration shown in FIG. 105 (a) is represented as shown in FIG. 105 (d). FIG. 105 (b) also corresponds to a schematic cross-sectional structure taken along line 56A-56A in FIG. 105 (d). FIG. 105 (c) also corresponds to a schematic cross-sectional structure taken along the line 57A-57A in FIG. 105 (d).

A schematic surface pattern configuration in the metal (Cu) plating polishing process of the upper surface and the lower surface, which is one step of the method of manufacturing the electrode-embedded substrate according to the sixth embodiment, is shown in FIG. 106 (a). 106 (a) is represented as shown in FIG. 106 (b), and the schematic cross-sectional structure along line 59A-59A in FIG. 106 (a) is A schematic back surface pattern configuration which is represented as shown in FIG. 106 (c) and corresponds to FIG. 106 (a) is represented as shown in FIG. 106 (d). FIG. 106 (b) also corresponds to a schematic cross-sectional structure taken along line 58A-58A in FIG. 106 (d). FIG. 106 (c) also corresponds to a schematic cross-sectional structure taken along line 59A-59A in FIG. 106 (d).
(C1) Next, as shown in FIGS. 105 (a) to 105 (d), the metal plating layer 226U from the surface side of the substrate 212 with respect to the grooves 225 ₁ 225 ₂ 225 ₃ 225 ₄ 225 ₅ It is formed and to form a metal plating layer 226U-226D from the front surface side and the back side of the through groove 227 _{1-227 2-227 3-227 4-227 5} to the substrate 212. The metal plating layers 226U and 226D may include, for example, a Cu plating layer. Although not shown, the step of forming a seed layer for forming a plating layer is carried out as a step prior to the step of forming the metal plating layers 226U and 226D. In the step of forming the seed layer, a CVD technique, a sputtering technique, a vapor deposition technique, an electroless plating technique, and the like can be applied.

Here, when applying the insulating substrate such as a glass substrate as the substrate 212, but may remain above process, when applying the silicon substrate as the substrate 212, grooves 225 _1, 225 _2, 225 _3, 225 ₄ - 225 ₅ and the through groove 227 _{1-227 2-227 3-227 4-227 5} after the formation, after forming an insulating layer by thermal oxidation or CVD, the formation process of the metal plating layer 226U-226D Conduct.
(C2) Next, as shown in FIGS. 106 (a) to 106 (d), the polishing process of the metal plating layers 226U and 226D is performed on the front and back surfaces of the substrate 212, and the grooves 225 ₁ · 225 ₂ ···. 225 to form a _{3-225 4-225 5} and the through groove 227 _{1-227 2-227 3-227 4-227} wiring layers 226 _1, 226 _2, 226 _3, 226 _4, 226 ₅ embedded within _5. Here, as a polishing process, a chemical mechanical polishing (CMP) technique may be applied.

(Comparison of silicon substrate type and permalloy substrate type inductance elements)
A schematic cross-sectional structure of a silicon substrate type inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment is represented as shown in FIG. Further, a schematic cross-sectional structure (a structural example without backside grinding) of the inductance element of the permalloy substrate type according to Comparative Example 6 is represented as shown in FIG. 108 (a), and a structural example with backside grinding is shown in FIG. It can be expressed as shown in (b). In FIG. 107, the beam structure will be described later with reference to FIG.

  A silicon substrate type inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment is embedded in a substrate 212 and a groove formed in the substrate 212, as shown in FIG. Wiring layer 226, insulating layer 230S disposed on the side surface of the wiring layer 226, insulating layer 230U disposed on the surface of the wiring layer 226, insulating layer 230D disposed on the back surface of the wiring layer 226, and insulating layer 230U And a magnetic layer 10D disposed under the insulating layer 230D. The broken line schematically represents a path through which the magnetic flux in the operating state of the inductance element 232 passes.

  In the silicon substrate method, it is possible to form a high density and large cross section coil by deep etching and through silicon via (TSV: Through Silicon Via) technology. Since the silicon substrate is a nonmagnetic substrate, the magnetic resistance is large and the inductance value is relatively small compared to the Permalloy system, but magnetic saturation is less likely to occur, which is advantageous for increasing the current.

  A schematic cross-sectional structure (a structural example without back surface polishing) of the inductance element of the permalloy substrate type according to the comparative example 6 is formed inside the permalloy substrate 120P and the permalloy substrate 120P as shown in FIG. 108 (a). Wiring layer 262 embedded in the groove, insulating layer 320S disposed on the side and bottom of wiring layer 262, insulating layer 320U disposed on the surface of wiring layer 262, and magnetic layer 102U disposed on insulating layer 320U And The broken line schematically represents a path through which the magnetic flux in the operating state of the inductance element 232 passes.

  A schematic cross-sectional structure (a structural example with backside polishing) of the inductance element of the permalloy substrate type according to the comparative example 6 is formed inside the permalloy substrate 120P and the permalloy substrate 120P as shown in FIG. 108 (b). Wiring layer 262 embedded in the groove, insulating layer 320S arranged on the side surface of wiring layer 262, insulating layer 320D arranged on the bottom of wiring layer 262, insulating layer 320U arranged on the surface of wiring layer 262, and insulation A magnetic layer 102U disposed on the layer 320U and a magnetic layer 102D disposed below the insulating layer 320D. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element.

  In the permalloy substrate method, wet etching is applied to process permalloy, which is disadvantageous for increasing the density of the coil and increasing the cross-sectional area. On the other hand, since the permalloy substrate is a magnetic substrate, the magnetic resistance is small and the inductance value is large.

(Configuration of inductance element)
A schematic bird's-eye view configuration of an inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment is represented as shown in FIG. 109 (a), and 60A-60A in FIG. 109 (a). A schematic cross-sectional structure along the line is represented as shown in FIG. 109 (b).

  The inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment has a substrate 212 and a wiring layer 226 embedded in a groove formed in the substrate 212, as shown in FIG. , Insulating layer 230S disposed on the surface of the wiring layer 226, insulating layer 230U disposed on the surface of the wiring layer 226, insulating layer 230D disposed on the back of the wiring layer 226, and disposed on the insulating layer 230U A magnetic layer 10U and a magnetic layer 10D disposed under the insulating layer 230D are provided.

  In the inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment, the wiring layer 226 embedded in the groove may have a coil shape as shown in FIG.

  Further, as shown in FIG. 109, upper cores (230U and 10U) disposed on the surface of the substrate 212 may be provided.

  Further, as shown in FIG. 109, lower cores (230D and 10D) disposed on the back surface of the substrate 212 may be provided.

  The upper cores (230U and 10U) and the lower cores (230D and 10D) may have a multilayer structure of the magnetic layers 10U and 10D and the insulating layers 230U and 230D.

  Furthermore, as shown in FIG. 109, slits SL may be provided to divide the upper cores (230U and 10U) and the lower cores (230D and 10D) into a plurality. Eddy current loss can be reduced by this slit structure. The magnetic layers 10U and 10D may be provided with a ferromagnetic material such as permalloy or ferrite.

  In addition, the insulating layers 230U and 230D may be provided with any of a ferromagnetic body, a paramagnetic body, and a diamagnetic body. Further, the eddy current radius in the magnetic layers 10U and 10D can be controlled by the thickness of the magnetic layers 10U and 10D and the division of the magnetic layers 10U and 10D by the slits SL.

(Method of manufacturing inductance element: formation process of upper core and lower core)
The method of manufacturing an inductance element formed by applying the electrode-embedded substrate according to the sixth embodiment is the same as the manufacturing process of the electrode-embedded substrate 1 according to the sixth embodiment described above, with reference to FIG. · As shown in FIG. 109 (b), forming the upper core (230U, 10U) on the surface of the substrate 212, and forming the lower core (230D, 10D) on the back surface opposite to the surface of the substrate 212 May be included.
(D1) As shown in FIG. 107 and FIG. 109 (b), a substrate 212 is formed on the electrode-embedded substrate 1 formed by carrying out the manufacturing process of the electrode-embedded substrate 1 according to the sixth embodiment. Insulating layers 230U and 230D are formed on the front and back surfaces of the
(D2) Next, as shown in FIGS. 107 and 109 (b), the magnetic layer 10U is formed on the insulating layer 230U to form the upper cores (230U and 10U).
(D3) Next, as shown in FIGS. 107 and 109B, the magnetic layer 10D is formed under the insulating layer 230D to form the lower core (230D · 10D).

  In the formation of the upper core (230U · 10U) and the lower core (230D · 10D), a multilayer structure of a magnetic layer and an insulating layer may be formed. Here, the magnetic layer can be formed by plating, sputtering, vacuum evaporation, or the like.

  An inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment, the schematic bird's-eye view of the wiring layer portion is represented as shown in FIG. The surface configuration of (a) is represented as shown in FIG. 110 (b), and the back surface configuration of FIG. 110 (a) is represented as shown in FIG. 110 (c).

  Further, the cross-sectional bird's-eye configuration along line 61A-61A in the central portion of FIG. 110 (a) is expressed as shown in FIG. 111 (a), and the cross-sectional configuration viewed from the arrow B1 direction in FIG. , 21 (b), and the enlarged view of the C1 portion of FIG. 111 (b) is represented as shown in FIG. 111 (c).

  In addition, the cross-sectional bird's-eye configuration along line 62A-62A in FIG. 110 (a) is expressed as shown in FIG. 112 (a), and the cross-sectional configuration viewed in the direction of arrow B2 in FIG. b), and an enlarged view of a portion C2 of FIG. 112 (b) is represented as shown in FIG. 112 (c).

  Further, the surface-side schematic bird's-eye configuration of only the silicon substrate in FIG. 110 (a) is expressed as shown in FIG. 113 (a), and the back-surface-side schematic bird's-eye configuration in FIG. 113 (a) is FIG. It is expressed as shown in).

  The inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment is formed by performing a two-step etching and a Cu plating technique on the silicon substrate 212. As shown in FIGS. 110 (a) and 113 (a), the size of the silicon substrate 212 is represented by LX · LY. As a specific numerical example, LX and LY are both about 4.2 mm.

  Further, as shown in FIGS. 110 (c) and 113 (b), the inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment has a beam having a lattice structure on the back surface of the silicon substrate 212. The unit 228 is provided. Here, the width of the cross portion of the lattice of the beam portion 228 is represented by ΔB, and the width of the frame portion of the lattice is represented by ΔEX · ΔEY. As a specific numerical example, each of ΔB · ΔEX · ΔEY is about 100 μm.

  Further, as shown in FIG. 111C, the line and space of the wiring layer 226 pattern is represented by Y and X, the depth of the wiring layer 226 is represented by TD, and the thickness of the beam portion 228 is represented by TB. Be done. As a specific numerical example, the line width Y of the wiring layer 226 is about 50 μm, the distance X is about 15 μm, the depth TD of the wiring layer 226 is about 300 μm, and the thickness TB of the beam portion 228 is about 50 μm.

  Further, as shown in FIG. 112C, the width of the beam portion 228 at the central portion of the substrate 212 is represented by WB. This WB is equal to ΔB in FIGS. 110 (c) and 113 (b) and is about 100 μm.

  In the inductance element 232 formed by applying the electrode-embedded substrate according to the sixth embodiment, an inductance element embedded in the silicon substrate is formed. Therefore, DC / DC in which an IC or a capacitor is disposed on the electrode-embedded substrate It is applicable to a converter etc. Further, by forming the magnetic layers 10U and 10D on the upper and lower sides of the electrode-embedded substrate, it is possible to reduce the influence of noise given to the IC and the capacitor.

(Beam structure)
It is a schematic plan view of the structure of the beam part 228 applicable to the electrode built-in board concerning a 6th embodiment, and a cross type structural example is expressed as shown in Drawing 114 (a), and is a lattice type structure. An example is represented as shown in FIG. 114 (b), an example of a diagonal cross configuration is represented as shown in FIG. 114 (c), and an example of a circular / cross combined configuration is shown in FIG. 114 (d). It is represented as shown in.

  The structure of the beam portion 228 applicable to the electrode-embedded substrate according to the sixth embodiment is, as shown in FIG. 114, cruciform, lattice type, diagonal cross type, circular / cross composite type in plan view It may have any of the following patterns. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  In addition, in the electrode-embedded substrate according to the sixth embodiment, the groove or the wiring layer also has a cross shape, a lattice shape, a diagonal cross shape, a circle / cross composite type, a rectangle, a circle, etc. It may have any pattern such as oval, octagon, triangle or polygon.

(Inductance frequency characteristics)
The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG.

  The simulation result of the frequency characteristic of the alternating current resistance ACR of the inductance element formed by applying the electrode built-in substrate according to the sixth embodiment is expressed as shown in FIG.

  In FIG. 115 and FIG. 116, the curve of “air core” represented by ● plot corresponds to the structure provided with insulating layers 230 U and 230 D on the upper and lower sides of the electrode-embedded substrate, and the “magnetic layer” represented by ▲ plot. The curve corresponds to the structure in which the magnetic layers 10U and 10D are provided on the upper and lower sides of the insulating layers 230U and 230D, and the curve of "magnetic layer & slit" represented by ■ plot further forms slits SL in the magnetic layers 10U and 10D. Corresponding to the structure.

  The frequency characteristic of the inductance L of the inductance element according to the sixth embodiment exhibits a substantially constant value in the measurement range of 100 kHz to 10 MHz. The inductance L can be increased by forming the magnetic layers 10U and 10D.

  The frequency characteristics of the AC resistance ACR of the inductance element according to the sixth embodiment show relatively low values of the AC resistance ACR in the measurement range of 100 kHz to 10 MHz. In particular, by forming the slits SL, relatively low AC resistance ACR can be obtained as compared with the case of using only the magnetic layers 10U and 10D.

(module)
Comparative Example 7
An example of the mounting configuration of the DC / DC converter module according to comparative example 7 is represented as shown in FIG. In the DC / DC converter module according to Comparative Example 7, an inductance element 234, IC236 on a printed circuit board 238, for mounting the capacitor 340 _{1-340 2,} reduction of mounting area it is difficult.

-Configuration example 1-
The integrated circuit block configuration of the configuration example 1 of the DC / DC converter module 3 according to the sixth embodiment is represented as shown in FIG. In FIG. 118, a terminal A1: VIN represents a power supply terminal to which a DC / DC converter input voltage VIN of a voltage E is input, a terminal A2: EN represents an enable terminal, and a terminal A3: GND represents a ground terminal. The terminal B1: LX represents an inductor connection terminal, the terminal B2: FB represents an output voltage feedback input terminal, and the terminal B3: MODE represents a DE / PFM-PWM mode switching terminal. An input capacitor Ci is connected in parallel to the voltage E. Further, an output capacitor Co is connected to the terminal B1: LX via a reactor L, and a DC / DC converter output voltage VOUT can be obtained from both ends of the output capacitor Co.

  In addition, a layered synthetic view of the schematic plane pattern configuration of the configuration example 1 of the DC / DC converter module 3 corresponding to FIG. 118 is expressed as shown in FIG. 119, and is a schematic view along line 63A-63A in FIG. The cross sectional structure is represented as shown in FIG.

In the DC / DC converter module 3 according to the sixth embodiment, as shown in FIG. 120, a substrate 212, a wiring layer 226 embedded in a groove formed inside the substrate 212, and a surface of the wiring layer 226 Insulating layer 230U ₁ / magnetic layer 10U / insulating layer 230U ₂ disposed on the upper surface, insulating layer 230D ₁ / magnetic layer 10D / insulating layer 230D ₂ disposed on the back surface of wiring layer 226, and upper surface on insulating layer 230U ₂ It comprises a IC236-capacitor 340 disposed over the wiring layer 244, a solder layer 245, and a lower surface wiring layer 246, a solder layer 247 disposed on the lower surface of the insulating layer 230D _2. Here, the insulating layer 230S disposed on the side surface of the wiring layer 226, the slit SL formed on the magnetic layers 10U and 10D, and the beam portion 228 formed on the substrate 212 are not shown.

  In the configuration example 1 of the DC / DC converter module 3 according to the sixth embodiment, as shown in FIGS. 119 and 120, an IC 236 and a capacitor 340 can be mounted. Therefore, the mounting area can be reduced by the lamination technique.

  The birdcage configuration of the configuration example 1 of the DC / DC converter module 3 according to the sixth embodiment corresponding to FIGS. 119 and 120 is expressed as shown in FIG.

  As shown in FIG. 121, the IC 236 and the capacitor 340 can be mounted on the inductance element 232 formed by applying the electrode built-in substrate. Therefore, the mounting area can be reduced as compared with Comparative Example 7 by the lamination technique.

  A schematic plan configuration of the lower surface wiring layer 246 in FIGS. 119 to 121 is expressed as shown in FIG. On the lower surface wiring layer 246, a VIN electrode pattern for terminal A1, an EN electrode pattern for terminal A2, a GND electrode pattern for terminal A3, a VOUT electrode pattern for terminal B1, a MODE electrode pattern for terminal B3 and the like are arranged. ing.

  A schematic plan configuration of the inductor layer of FIGS. 119 to 121 is expressed as shown in FIG. As shown in FIG. 123, the wiring layer 226 embedded in the groove formed inside the substrate 212 is arranged in a coil shape. In the central portion of FIG. 123, a through electrode 226T for extracting the electrode of the wiring layer 226 is formed. Here, the through electrode 226T connects the upper surface wiring layer 244 and the lower surface wiring layer 246.

  A schematic plan configuration of the upper surface wiring layer 244 in FIGS. 119 to 121 is expressed as shown in FIG. As shown in FIG. 124, the electrode pattern of the power supply terminal A1: VIN to which the DC / DC converter input voltage VIN of voltage E is input, the electrode pattern of the enable terminal A2: EN, the electrode pattern of the ground terminal A3: GND, inductor connection The electrode pattern of terminal B1: LX, the electrode pattern of output voltage feedback input terminal B2: FB, the electrode pattern of DE / PFM-PWM mode switching terminal B3: MODE, etc. are arranged.

  A schematic plan configuration of the IC / capacitor layer in FIGS. 119 to 121 is expressed as shown in FIG. As shown in FIG. 125, an IC 236, an input capacitor Ci and an output capacitor Co are disposed.

-Configuration example 2-
A schematic cross-sectional structure of Configuration example 2 of the DC / DC converter module 3 according to the sixth embodiment is expressed as shown in FIG.

In Configuration Example 2 of the DC / DC converter module 3 according to the sixth embodiment, as shown in FIG. 126, a substrate 212, a wiring layer 226 embedded in a groove formed inside the substrate 212, and wiring Insulating layer 230U ₁ / magnetic layer 10U / insulating layer 230U ₂ disposed on the surface of layer 226, insulating layer 230D ₁ / magnetic layer 10D / insulating layer 230D ₂ disposed on the back surface of wiring layer 226, and insulating layer 230U It comprises a IC236-capacitor 340 disposed over the top interconnect layer 244, a solder layer 245 on _2, and a lower surface wiring layer 246, a solder layer 247 disposed on the lower surface of the insulating layer 230D _2. Here, the insulating layer 230S disposed on the side surface of the wiring layer 226, the slit SL formed on the magnetic layers 10U and 10D, and the beam portion 228 formed on the substrate 212 are not shown.

  In Configuration Example 2 of the DC / DC converter module 3 according to the sixth embodiment, as shown in FIG. 126, the substrate 212 is processed into a boat shape. An IC 236 and a capacitor 340 can be mounted on the bottom of the substrate 212 processed into a boat shape, as in the first embodiment. Therefore, the mounting technology can reduce the mounting area and reduce the height.

  The area of the DC / DC converter module 3 according to the sixth embodiment can be reduced by the laminated structure. In addition, since an IC built-in substrate or a ferrite substrate is not used, it can be formed inexpensively.

  The DC / DC converter module 3 according to the sixth embodiment can be formed using deep etching of a silicon substrate and copper plating as described in the method of manufacturing the electrode-embedded substrate.

(Shield board)
A schematic bird's-eye view configuration of the shield substrate 202 formed by applying the electrode-embedded substrate according to the sixth embodiment is expressed as shown in FIG. The top view of FIG. 127 is represented as shown in FIG. 128 (a), and the schematic cross-sectional structure along line 64A-64A of FIG. 128 (a) is represented as shown in FIG. 128 (b). A schematic cross-sectional structure taken along line 65A-65A of FIG. 128 (a) is expressed as shown in FIG. 128 (c).

  The shield substrate 202 formed by applying the electrode-embedded substrate according to the sixth embodiment is, as shown in FIGS. 127 and 128 (a) to 128 (c), the inside of the substrate 212 and the substrate 212. Wiring layer 226C embedded in a groove having a rectangular stripe pattern in plan view, a beam portion 228 disposed on the back surface facing the front surface of the substrate 212, and a back surface facing the front surface of the substrate 212 And a back electrode 226B disposed. Here, a wiring layer 226C is formed by embedding a metal such as copper (Cu) in the groove portion formed inside the substrate 212.

  In addition, the beam portion 228 has a cruciform pattern in a plan view of FIGS. 128 (a) to 128 (c).

  In the above configuration, the structure of the wiring layer 226C embedded in the groove having a rectangular pattern in plan view is shown, but the present invention is not limited to this, and a circle, an ellipse, an octagon, a triangle, Alternatively, it may have any pattern such as a polygon. It may be any shape as long as it can exhibit a shielding effect, and any shape pattern may be provided as long as a closed circuit is formed.

  Similar to FIG. 114, the structure of the beam portion 228 may have a cruciform, lattice, diagonal cross, circular / cross composite pattern in plan view. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  Among the substrates 212, the substrate 212I surrounded by the wiring layer 226C embedded in the groove having a rectangular stripe pattern in a plan view is surrounded by the wiring layer 226C and the back surface electrode 226B. Even in the environment of the electromagnetic field EM as shown in c), the influence of noise can be suppressed. For example, the electromagnetic shielding effect can be obtained by digging the substrate 212I and arranging the components. Furthermore, when metal is formed on the upper surface of the wiring layer 226C and the substrate 212I, the influence of noise from the upper surface can also be suppressed.

(Interposer)
A schematic bird's-eye view configuration in which the silicon interposer 251 formed by applying the electrode-embedded substrate according to the sixth embodiment is disposed on the package substrate 252 is represented as shown in FIG. 129 (a). A schematic cross-sectional structure along line 66A-66A of a) is represented as shown in FIG. 129 (b), and an enlarged view of a portion E of FIG. 129 (b) is a table as shown in FIG. 129 (c). Be done.

When mounting the plurality of semiconductor integrated circuit chips 248 ₁ , ₂ 48 ₂ , _{2 3 4 2 4 4 4} on the package substrate 252, the silicon interposer 251 is used as an intermediate layer.

  The electrode built-in substrate according to the sixth embodiment is applicable to the silicon interposer 251.

  The silicon interposer 251 formed by applying the electrode-embedded substrate according to the sixth embodiment includes a silicon substrate and a wiring layer embedded in a groove formed inside the silicon substrate. Further, the beam portion is provided as in the electrode-embedded substrate according to the sixth embodiment. As described above, an insulating layer may be formed at the boundary between the silicon substrate and the wiring layer.

BGA solder balls 254 disposed on the back surface of the package substrate 252 can be connected to the bumps 261 disposed on the surface of the package substrate 252 through the through vias. Further, the bumps 261 can be connected to the micro bumps 256 disposed on the silicon interposer 251 through the through silicon vias (CUTSV) 258 and the interposer integrated electrode 226I. Micro bumps 256 are connected to the semiconductor integrated circuit chip 248 _{1-248 2-248 3-248 4.}

  By providing the beam portion on the silicon substrate as in the case of the electrode-embedded substrate according to the sixth embodiment, the through groove can also be formed, so the design freedom of the silicon interposer 251 is increased.

  According to the silicon interposer to which the electrode-embedded substrate according to the sixth embodiment is applied, it is possible to provide an interposer with high reliability, which is simple in structure and in which sticking between lines is unlikely to occur.

  As described above, according to the sixth embodiment, an electrode-embedded substrate having a simple structure, in which sticking between lines is less likely to occur, and whose reliability can be improved, a method for manufacturing the same, and the electrode-embedded substrate The present invention can provide an inductance element, an interposer, a shield substrate and a module to which

(Other embodiments)
As mentioned above, although described by the embodiment, it should not be understood that the statement and drawing which make a part of this disclosure limit this invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.

  Thus, the present embodiment includes various embodiments not described herein.

  The magnetic structures of the first to fourth embodiments are applicable to all elements using magnetic flux, and are applicable to cores of inductors and transformers, magnetic flux shields, sensors using eddy currents, and the like. In addition, the inductance elements to which the magnetic structures according to the first to fourth embodiments are applied include all electronic parts utilizing inductance such as inductors, transformers, noise filters, isolators, sensor parts such as magnetic sensors and position sensors, and other wireless elements. The present invention is applicable to coils for feeding and the like, and in particular to electronic devices such as DC-DC converters incorporating an inductor and an inductor for mobile devices.

  The inductance element according to the fifth embodiment can be applied to all electronic parts that use inductance such as inductors, transformers, noise filters and isolators, sensor parts such as magnetic sensors and position sensors, and coils for wireless power supply. In particular, the present invention is applicable to electronic devices such as DC-DC converters incorporating inductors and inductors for mobile devices.

  The substrate with a built-in electrode according to the sixth embodiment can be applied to general electronic components that use inductance such as inductors, transformers, noise filters, isolators, sensor components such as magnetic sensors and position sensors, and coils for wireless power supply Furthermore, the present invention is applicable to interposers, shield substrates, etc., and in particular to electronic devices such as DC / DC converter modules incorporating inductors and inductors for mobile devices.

1 ... electrode-containing substrate 2 and 2b, 2U, 2D, 240, 240 _1, 240 ₂ ... magnetic structure 3 ... module 4, 4b ... inductance element 6 ... core 10, 10 _1, 10 _2, 10 _3, ..., 10 _n , 10 _{n + 1} , 10 ₁ U, 10 ₂ U, 10 ₃ U, 10 ₁ D, 10 ₂ D, 10 ₃ D, 10 U, 10 D, 102 U, 102 D ... magnetic layers 12, 12 ₁ , 12 ₂ , ... 12 _n 24 25 insulating layer 14 embedded layer 15 groove 16 inductance coil 20 magnetic metal substrate 22 metal wiring layer 23 inductance coil terminal electrode 38 ₁ 38 ₂ search coil electrode terminal 40 ... Search coil 42 ... Search coil substrate 50 ... Magnetic layer substrate 100 ... Printed circuit board (PCB)
112: Substrate 113, 129, 130S: Seed 114: Through hole 116: Lower core forming portion 118: Lower coil forming portion 120: Upper and lower coil connection portion 120P: Permalloy substrate 122: Lower coil 124: Lower core 125, 131, 133 resist 126 ... upper coil _{128,128B, 128C, 122 1, 122} 2, 242 ... insulating layer 128A ... opening 130 ... upper core 140A ... control integrated circuit (control IC)
140B ... DC / DC converter IC
150: Load capacitor (C1)
160 ... inductance coil 180 ... snubber capacitor (CB)
200 core 202 shield substrate 220 winding coil 212 212I 120 substrate (silicon substrate silicon wafer)
214, 216 ... resist 225 ₁ , 225 ₂ , 225 ₃ ... ... 225 _n ... grooves 226, 226 ₁ , 226 ₂ , 226 ₃ ... ... 226 _n , 262 ... electrode layer (wiring layer)
226B ... back electrode 226C ... shield electrode 226I ... interposer built electrodes 226T ... through electrodes 226U, 226D ... Cu plating layer _{227 1, 227 2, 227 3} , ..., 227 n ... through grooves 228, 228 _1, 228 _2, 228 ₃ , ..., 228 ... beam portion _{230,230U, 230U 1, 230U 2,} 230S, 230D, 230D 1, 230D 2, 320U, 320S, 320D ... insulating layer 232 and 234 ... inductor 236 ... IC (integrated circuit)
238 ... printed circuit board (PCB)
244 ... upper surface wiring layers 245, 247 ... solder layer 246 ... lower surface wiring layers 248 _1, 248 _2, 248 _3, 248 ₄ ... semiconductor integrated circuit chip 251 ... silicon interposer 252 ... package substrate 254 ... BGA solder balls 256 ... micro bumps 258 ... CUTSV (through silicon via)
261: bump 250: electromagnetic shielding target object 260: hollow portion 290: magnetic metal substrate 300: transformer (transformer)
340, 340 ₁ , 340 ₂ ... capacitor 400 ... electromagnetic field shield structure L1 ... primary inductance L2 ... secondary inductance B ... magnetic flux density H ... magnetic field SL, SL1, SL2, SL3 ... slit ΔSL ... slit width SLP ... slit spacing (Slit pitch)
I _e , I _e1 , I _e2, i _e1 , i _e2 ... eddy current ... ... flux θ ... angle

Claims (27)

A substrate having a front side and a back side;
A groove formed to partially penetrate the substrate;
A beam portion disposed on the back surface side of the substrate and partially intersecting the groove portion;
And a wiring layer embedded in the groove.   The wiring embedded substrate according to claim 1, wherein the beam portion has a stripe pattern which is orthogonal to the wiring layer in plan view and is parallel to each other.   The wiring embedded substrate according to claim 1, wherein the beam portion has a stripe pattern which intersects each other at a predetermined angle in a plan view.   The wiring according to claim 1, wherein the groove, the beam or the wiring layer has a rectangular, circular, oval, octagonal, triangular or polygonal pattern in a plan view. Built-in board.   The thickness of the said beam part is thinner than the depth of the said groove part, The wiring built-in board | substrate of any one of the Claims 1-4 characterized by the above-mentioned.   The wiring built-in substrate according to any one of claims 1 to 5, wherein the substrate comprises a silicon substrate or a glass substrate. A wiring built-in substrate according to any one of claims 1 to 6, comprising:
The said groove part and the said wiring layer have coil shape, The wiring built-in board | substrate characterized by the above-mentioned.   The wiring-embedded substrate according to claim 7, further comprising an upper core disposed on the front surface side of the substrate.   9. The wiring built-in substrate according to claim 8, further comprising a lower core disposed on the back surface side of the substrate.   The wiring built-in substrate according to claim 9, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   11. The wiring built-in substrate according to claim 10, further comprising a slit dividing the upper core and the lower core into a plurality of pieces.   12. The wiring built-in substrate according to claim 10, wherein the magnetic layer comprises a ferromagnetic material.   The wiring built-in substrate according to any one of claims 10 to 12, wherein the insulating layer comprises any one of a ferromagnetic body, a paramagnetic body, and a diamagnetic body.   13. The wiring built-in substrate according to claim 11, wherein the eddy current radius in the magnetic layer can be controlled by the thickness of the magnetic layer and the division of the magnetic layer by the slits.   A module using the wiring built-in substrate according to any one of claims 1 to 6 as an interposer. A substrate having a front side and a back side;
A groove having a coil shape formed to partially penetrate the inside of the substrate;
A beam portion formed or disposed on the back surface side of the substrate and partially intersecting the groove portion;
A wiring layer embedded in the groove;
A top wiring layer disposed on the front side of the substrate;
A module comprising: an integrated circuit and a capacitor disposed on the upper wiring layer via a solder layer. An upper core disposed on the surface of the substrate;
And a lower core disposed on the back surface of the substrate, wherein the upper surface wiring layer is disposed on the upper core, and a lower surface wiring layer is formed on the lower core opposite to the substrate or The module according to claim 16, characterized in that it is arranged. The module according to claim 17 , further comprising: a through electrode disposed on the center side of the coil shape in a plan view, penetrating through the substrate, and connecting the upper surface wiring layer and the lower surface wiring layer.   The module according to claim 17, wherein the upper core and the lower core have a multilayer structure of a magnetic layer and an insulating layer.   The module according to claim 19, further comprising a slit dividing the upper core and the lower core into a plurality.   The module according to claim 19 or 20, wherein the magnetic layer comprises a ferromagnetic material.   The module according to any one of claims 19 to 21, wherein the insulating layer comprises any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material.   22. The module according to claim 20, wherein the eddy current radius in the magnetic layer can be controlled by the thickness of the magnetic layer and the division of the magnetic layer by the slits. Forming a groove so as to partially penetrate the inside of the substrate having the front surface and the back surface;
Forming a beam portion partially intersecting the groove portion on the back surface side of the substrate;
And a step of embedding a wiring layer in the groove portion. Forming a coil shaped groove so as to partially penetrate the inside of the substrate having the front and back surfaces;
Forming a beam portion partially intersecting the groove portion on the back surface side of the substrate;
Embedding a wiring layer in the groove;
A method of manufacturing a wiring-embedded substrate, comprising the steps of: forming or arranging an upper core on the surface of the substrate; and / or forming or arranging a lower core on the back side of the substrate. Forming a coil shaped groove so as to partially penetrate the inside of the substrate having the front and back surfaces;
Forming a through groove which is disposed at a central portion of the coil shape in a plan view and penetrates the substrate;
Forming a beam portion partially intersecting the groove portion on the back surface side of the substrate;
Embedding a wiring layer in the groove and embedding a through electrode in the through groove;
Forming or placing an upper core on the surface of the substrate;
Forming an upper surface wiring layer connected to the through electrode on the upper core;
Forming or arranging a lower core on the back side of the substrate;
Forming a lower surface wiring layer connected to the through electrode on the lower core opposite to the substrate side ;
Mounting an integrated circuit and a capacitor on the upper surface wiring layer via a solder layer.   The method according to claim 26, wherein the forming of the groove and the forming of the through groove can be performed simultaneously.