JP2017174920A - Electrode built-in substrate and manufacturing method therefor, inductance element, interposer, shield substrate and module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrode built-in substrate and manufacturing method therefor, inductance element having the same, interposer, shield substrate and module, capable of preventing a beam from being destroyed due to overetching by using a SOI substrate, thus making an isolation layer in the SOI substrate become an etching stop layer.SOLUTION: The electrode built-in substrate includes: an SOI substrate 12; a wiring layer 26embedded into a groove 25formed inside the SOI substrate 12; an etching stop layer 6 inside the SOI substrate 12 except the wiring layer 26; and beam parts 28*28*28arranged on a rear face opposing to a surface of the SOI substrate 12.SELECTED DRAWING: Figure 2

Description

  The present embodiment relates to an electrode-embedded substrate and a manufacturing method thereof, an inductance element, an interposer, a shield substrate, and a module.

  In recent mobile devices, thinning, lightening, energy saving, and long battery life are required. For this purpose, it is particularly necessary to make the power supply circuit thinner, lighter, more energy efficient, and to extend the battery life. Among the components constituting the power supply circuit, an inductance element can be cited as one of large components.

  Wiring structures used in conventional inductance elements include a wound type, a laminated type, and a thin film type. In the winding type, a copper core is wound around a ferromagnetic core, and there are a toroidal and a solenoid depending on the shape.

JP 2004-14837 A JP 2007-214424 A JP-A-9-139313 JP-A-8-88119

  When a wiring board having grooves and beams is formed by two-step etching from the front surface and the back surface, the etching rate varies depending on the groove width and the position in the wafer surface. For this reason, in the process using the silicon substrate, there has been a problem that the beam is broken due to overetching and the wiring portion falls off. Although falling out can be suppressed by increasing the thickness of the beam, the device thickness increases as a contradiction. When the device thickness is not changed, the direct current resistance increases due to the reduction of the wiring cross-sectional area.

  In this embodiment, an SOI (Silicon On Insulator) substrate is used, an insulating layer inside the SOI substrate becomes an etch stop layer, and a substrate with a built-in electrode that can prevent the destruction of the beam due to overetching, and a method for manufacturing the same, An object of the present invention is to provide an inductance element, an interposer, a shield substrate, and a module to which a substrate is applied.

  According to one aspect of the present embodiment, a substrate, a wiring layer embedded in a groove formed inside the substrate, an etch stop layer formed inside the substrate excluding the wiring layer, There is provided a substrate with a built-in electrode including a beam portion disposed on a back surface facing the front surface of the substrate.

  According to another aspect of the present embodiment, an inductance element including the above-described electrode-embedded substrate and having a coil shape as the wiring layer is provided.

  According to another aspect of the present embodiment, an interposer including the above electrode-embedded substrate is provided.

  According to another aspect of the present embodiment, there is provided a shield substrate including the above-described electrode-embedded substrate and a back electrode disposed on the back surface facing the surface of the substrate.

  According to the other aspect of this Embodiment, a module provided with said inductance element is provided.

  According to another aspect of the present embodiment, a substrate, a wiring layer embedded in a groove having a coil shape formed inside the substrate, and the wiring layer formed inside the substrate excluding the wiring layer are formed. An etch stop layer; a beam portion disposed on the back surface facing the surface of the substrate; an upper surface wiring layer disposed on the surface of the substrate; and a lower surface wiring layer disposed on the back surface facing the surface of the substrate; A module including an integrated circuit and a capacitor disposed on the upper wiring layer via a solder layer is provided.

  According to another aspect of the present embodiment, a step of forming a groove in the SOI substrate using an SOI substrate on which an etch stop layer is formed, and a beam on the back surface facing the surface of the SOI substrate. There is provided a method for manufacturing a substrate with a built-in electrode, which includes a step of forming a portion and a step of embedding and forming the wiring layer in the groove.

  According to another aspect of the present embodiment, a step of forming a coil-shaped groove in the SOI substrate using an SOI substrate on which an etch stop layer is formed is opposed to the surface of the SOI substrate. Forming a beam portion on the back surface, embedding and forming a wiring layer in the groove, forming an upper core on the surface of the SOI substrate, and forming a lower core on the back surface facing the surface of the SOI substrate; There is provided a method of manufacturing an inductance element including the step of:

  According to another aspect of the present embodiment, using the SOI substrate in which an etch stop layer is formed, forming a groove having a closed circuit pattern in a plan view inside the SOI substrate; A shield substrate comprising a step of forming a beam portion on the back surface facing the surface of the SOI substrate, a step of embedding a wiring layer in the groove portion, and a step of forming a back electrode on the back surface facing the surface of the SOI substrate A manufacturing method is provided.

  According to another aspect of the present embodiment, a step of forming a coil-shaped groove in the SOI substrate using an SOI substrate on which an etch stop layer is formed, and the inside of the coil shape in a plan view. Forming a through-groove portion that penetrates the SOI substrate, forming a beam portion on the back surface facing the front surface of the SOI substrate, embedding a wiring layer in the groove portion, and forming the through-hole Embedding a through electrode in the groove, forming an upper core on the surface of the SOI substrate, forming an upper surface wiring layer connected to the through electrode on the upper core, A step of forming a lower core on the back surface facing the surface, a step of forming a lower surface wiring layer connected to the through electrode on the lower core, and integration on the upper surface wiring layer via a solder layer Method of manufacturing a module having a step of mounting a road and a capacitor are provided.

  According to the present embodiment, an SOI substrate is used, an insulating layer inside the SOI substrate becomes an etch stop layer, and an electrode built-in substrate that can prevent the destruction of the beam due to overetching, its manufacturing method, and this electrode built-in substrate are applied. Inductive elements, interposers, shield substrates, and modules can be provided.

It is a typical plane pattern block diagram of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) An example in which a beam part is orthogonal to a wiring layer in planar view, and is provided with a stripe pattern parallel to each other, (b) A beam part is An example including stripe patterns that intersect each other at a predetermined angle θ in plan view. FIG. 1A is a schematic cross-sectional structure diagram taken along line I--I in FIG. 1A, and FIG. 1B is a schematic cross-sectional structure diagram taken along line II-II in FIG. The typical plane pattern block diagram of the electrode built-in board | substrate which is an electrode built-in board | substrate which concerns on embodiment, and has a relatively long line and space formed in the SOI substrate wafer. (A) The typical cross-section figure along the III-III line of FIG. 3, (b) The typical cross-section figure along the IV-IV line of FIG. (A) A schematic plane pattern configuration diagram of an electrode-embedded substrate according to a comparative example, which has a relatively long line and space formed on a silicon substrate wafer, and (b) an electrode according to an embodiment The typical plane pattern block diagram of the electrode built-in board | substrate which is a built-in board | substrate and has the relatively long line and space formed in the SOI substrate wafer. The typical plane pattern block diagram of the electrode built-in board | substrate which has the spiral-shaped inductance element formed in the silicon substrate which is a board | substrate with a built-in electrode which concerns on a comparative example. It is an electrode built-in substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the VV line of Fig.7 (a), (c) Fig.7 (a) ) Is a schematic cross-sectional structure diagram taken along line VI-VI, (d) a schematic back surface pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical cross-section figure along the VII-VII line of Fig.8 (a), ( c) A schematic back surface pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the VIII-VIII line of Fig.9 (a), ( c) The typical back surface pattern block diagram corresponding to Fig.9 (a). It is one process of the manufacturing method of the board | substrate with a built-in electrode which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the IX-IX line of Fig.10 (a), ( c) The typical back surface pattern block diagram corresponding to Fig.10 (a). It is 1 process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XX line of Fig.11 (a), ( c) The typical back surface pattern block diagram corresponding to Fig.11 (a). It is 1 process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XI-XI line of Fig.12 (a), ( c) A schematic cross-sectional structure diagram taken along line XII-XII in FIG. 12A, and FIG. 12D a schematic backside pattern configuration diagram corresponding to FIG. It is 1 process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XIII-XIII line | wire of FIG. c) A schematic cross-sectional structure diagram taken along line XIV-XIV in FIG. 13A, and FIG. 13D a schematic backside pattern configuration diagram corresponding to FIG. It is 1 process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XV-XV line | wire of Fig.14 (a), c) A schematic cross-sectional structure diagram taken along line XVI-XVI in FIG. 14A, and FIG. 14D a schematic backside pattern configuration diagram corresponding to FIG. It is one process of the manufacturing method of the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XVII-XVII line of Fig.15 (a), c) A schematic cross-sectional structure diagram taken along line XVIII-XVIII in FIG. 15A, and FIG. 15D is a schematic backside pattern configuration diagram corresponding to FIG. It is 1 process of the manufacturing method of the board | substrate with a built-in electrode which concerns on embodiment, Comprising: (a) Typical surface pattern block diagram, (b) Typical sectional structure drawing which follows the XIX-XIX line | wire of FIG. c) A schematic cross-sectional structure diagram taken along line XX-XX in FIG. 16A, and FIG. 16D a schematic backside pattern configuration diagram corresponding to FIG. 1 is a schematic cross-sectional structure diagram of an SOI substrate type inductance element formed by applying an electrode built-in substrate according to an embodiment. (A) Schematic sectional structure diagram of permalloy substrate type inductance element according to comparative example (structure example without back surface polishing), (b) Schematic sectional structure diagram of permalloy substrate type inductance element according to comparative example (back surface polishing) Example of structure with). (A) The typical bird's-eye view block diagram of the inductance element formed by applying the electrode built-in substrate which concerns on embodiment, (b) The typical cross-section figure which follows the XXI-XXI line of Fig.19 (a). (A) It is an inductance element formed by applying the electrode built-in substrate according to the embodiment, and is a schematic bird's-eye view configuration diagram of the wiring layer portion, (b) a surface configuration diagram of FIG. The back surface block diagram of Fig.20 (a). (A) Cross-sectional bird's-eye view configuration diagram along line XXII-XXII in the central portion of FIG. 20 (a), (b) Cross-sectional configuration diagram viewed from the direction of arrow B1 in FIG. 21 (a), (c) FIG. 21 (b) The enlarged view of C1 part of. (A) Cross-sectional bird's-eye view configuration diagram along line XXIII-XXIII in FIG. 20 (a), (b) Cross-sectional configuration diagram viewed from arrow B2 direction in FIG. 22 (a), (c) C2 portion in FIG. 22 (b) Enlarged view of. (A) Front side schematic bird's-eye view configuration diagram of only the SOI substrate of FIG. 20 (a), (b) Back side schematic bird's-eye view configuration diagram of FIG. 23 (a). It is a schematic plan view of the beam part structure applicable to the electrode built-in board | substrate which concerns on embodiment, Comprising: (a) Cross type structural example, (b) Lattice type structural example, (c) Diagonal direction cross type structural example (D) Circular / cross composite type configuration example. The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the substrate with a built-in electrode according to the embodiment. The simulation result of the frequency characteristic of AC resistance ACR of the inductance element formed by applying the substrate with a built-in electrode according to the embodiment. The mounting structural example of the DC / DC converter module which concerns on a comparative example. The integrated circuit block block diagram of the structural example 1 of the DC / DC converter module which concerns on embodiment. FIG. 29 is a stacked composite diagram of a schematic planar pattern configuration of a configuration example 1 of a DC / DC converter in which an IC and a capacitor are mounted on an inductance element formed by applying the electrode built-in substrate according to the embodiment corresponding to FIG. 28. FIG. 30 is a schematic cross-sectional structure diagram taken along line XXIV-XXIV in FIG. 29. The typical bird's-eye view block diagram of the structural example 1 of the DC / DC converter module which concerns on embodiment. FIG. 32 is a schematic plan view of the lower surface wiring layer of FIGS. 29 to 31. FIG. 32 is a schematic plan view of the inductor layer of FIGS. 29 to 31. FIG. 32 is a schematic plan view of an upper surface wiring layer in FIGS. 29 to 31. FIG. 32 is a schematic plan view of the IC / capacitor layer of FIGS. 29 to 31. The typical cross-section figure of the structural example 2 of the DC / DC converter module which concerns on embodiment. The typical bird's-eye view block diagram of the shield board | substrate formed by applying the electrode built-in board | substrate which concerns on embodiment. The shield substrate formed by applying the electrode built-in substrate according to the embodiment, (a) a top view of FIG. 37, (b) a schematic cross-sectional structure diagram along line XXV-XXV of FIG. (C) The typical cross-section figure which follows the XXVI-XXVI line of Fig.38 (a). (a) A schematic bird's-eye view of a package substrate including an interposer formed by applying the electrode built-in substrate according to the embodiment, (b) a schematic cross-sectional structure diagram taken along line XXVII-XXVII in FIG. c) Enlarged view of portion E in FIG. The typical block block diagram of the multi-channel DC / DC converter module which concerns on embodiment. It is an exploded view of the multi-channel DC / DC converter module which concerns on embodiment, Comprising: (a) Typical bird's-eye view block diagram of wiring layer part, (b) Typical bird's-eye view block diagram of inductor layer part. FIG. 42 is an enlarged view of the relatively large inductance element portion of FIG. 41 formed as a chip.

  Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of the component parts as follows. . Various modifications can be made to the embodiments within the scope of the claims.

[Embodiment]
(Configuration of substrate with built-in electrode)
It is a typical plane pattern block diagram of the electrode built-in substrate which concerns on embodiment, Comprising: The example in which a beam part is provided with a stripe pattern parallel to each other in planar view is represented as shown in FIG. An example having stripe patterns that intersect with each other at a predetermined angle θ in plan view is represented as shown in FIG.

  Moreover, the schematic cross-sectional structure along the II line in FIG. 1A is represented as shown in FIG. 2A, and the schematic cross-sectional structure along the II-II line in FIG. It is expressed as shown in FIG.

As shown in FIGS. 1 to 2, the electrode-embedded substrate 1 according to the embodiment includes a substrate 12 and a wiring layer 26 ₁ embedded in grooves 25 ₁ , 25 _2, and 25 ₃ formed inside the substrate 12. · 26 _2, 26 _3, except wiring layers 26 _1, 26 _2, 26 _3, an etch stop layer 6 formed inside the substrate 12, beam portion 28 disposed on the rear surface opposite to the surface of the substrate 12 ₁・ 28 ₂・ 28 ₃ Here, wiring layers 26 ₁ , 26 _2, and 26 ₃ are formed in the grooves 25 ₁ , 25 _2, and 25 ₃ formed inside the substrate 12 by embedding a metal such as copper (Cu).

As shown in FIG. 2B, the thickness Δ of the etch stop layer 6 is formed thinner than the depth TD of the groove and the thickness TB of the beams 28 ₁ , 28 _2, and 28 ₃ .

The etch stop layer 6 includes a SiO ₂ film (BOX layer) having a resistivity of 10 Ω · cm or more, for example, about 1 μm thick. The etch stop layer 6 may be provided with any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material as long as it has a resistivity of 10 Ω · cm or more.

As shown in FIG. 1A, the beam portions 28 ₁ , 28 _2, and 28 ₃ are provided with stripe patterns that are orthogonal to the wiring layers 26 ₁ , 26 _2, and 26 ₃ in a plan view and are parallel to each other.

Further, as shown in FIG. 1B, the beam portions 28 ₁ and 28 ₂ may be provided with a stripe pattern that intersects with each other at a predetermined angle θ in plan view.

Further, as shown in FIG. 2 (b), the thickness of the beam portions _{28 1 · 28 2 · 28 3} TB ( e.g., about 50 [mu] m), the groove depth TD (e.g., approximately 350 .mu.m) is thinner than ing. The beam portions 28 ₁ , 28 _2, and 28 ₃ have widths W 1, W 2, and W 3 of about 20 μm, for example, as shown in FIGS.

Further, the grooves 25 _1, 25 _2, 25 _3, the beam portion 28 _1, 28 _2, 28 ₃ or the wiring layer 26 _1, 26 _2, 26 _3, in plan view, rectangular, circular, oval, octagonal, triangular Or may have a polygonal pattern.

  Further, for example, when the trench and the wiring layer have stripe patterns that are parallel to each other and intersect each other at 90 ° in plan view, an electrode-embedded substrate for an inductance element as shown in FIG. 20 described later is formed. Can do.

  In the electrode-embedded substrate 1 according to the embodiment, an SOI (Silicon on Insulator) substrate having an etch stop layer 6 formed therein can be used as the substrate 12.

  In addition, a schematic planar pattern configuration of the electrode-embedded substrate 1 according to the embodiment and having a relatively long line and space (L & S) formed on the SOI substrate wafer 120 is as follows. 3, and a schematic cross-sectional structure taken along line III-III in FIG. 3 is represented as shown in FIG. 4A, and a schematic cross-sectional structure taken along line IV-IV in FIG. 3. Is expressed as shown in FIG.

As shown in FIGS. 3 to 4, the substrate with a built-in electrode 1 according to the embodiment includes an SOI substrate wafer 120 and grooves 25 ₁ , 25 ₂ , 25 ₃ ,... 25 formed inside the SOI substrate wafer 120. wiring layer and _{26 1 · 26 2 · 26 3} · ... · 26 n embedded in _n, excluding the wiring layer _{26 1 · 26 2 · 26 3} · ... · 26 n, which is formed inside the SOI substrate wafer 120 The etch stop layer 6 and beam portions 28 ₁ and 28 ₂ disposed on the back surface facing the front surface of the SOI substrate wafer 120 are provided. Here, the trenches 25 ₁ , 25 ₂ , 25 ₃ ,..., 25 _n formed in the SOI substrate wafer 120 are filled with a metal such as copper (Cu) to thereby form the wiring layers 26 ₁ , 26 ₂ ,. 26 ₃ ... 26 _n are formed.

Further, the beam portion 28 _1, 28 _2, as shown in FIG. 3, the wiring layers 26 _1, 26 _2, 26 _3, ..., 26 orthogonal to _n in a plan view, and a parallel stripe pattern with each other.

Further, as shown in FIG. 4A, the thickness TB of the beam portion 28 ₁ is formed thinner than the depth TD of the groove portion. The same applies to the thickness TB of the beam portion 28 ₂ .

The thickness of the etch stop layer 6 is formed to be smaller than the depth TD of the groove and the thickness TB of the beam portions 28 ₁ and 28 ₂ .

  A schematic planar pattern configuration of an electrode-embedded substrate 1A according to a comparative example and having a relatively long line and space (L & S) formed on the silicon substrate wafer 120A is shown in FIG. It is expressed as shown in (a).

The electrode-embedded substrate 1A according to the comparative example includes an SOI substrate wafer 120 and wiring layers 26 ₁ , 26 ₂ , 26 ₃ ,..., 26 _n embedded in through holes formed inside the SOI substrate wafer 120. Since the beam portion structure is not provided, sticking in which the lines of the wiring layers 26 ₁ , 26 ₂ , 26 ₃ ,..., 26 _n come into contact with each other easily occurs as shown by a broken line ST portion in FIG.

  On the other hand, FIG. 5B shows a schematic planar pattern configuration of the electrode built-in substrate 1 according to the embodiment and having a relatively long line and space formed on the SOI substrate wafer 120. Represented as shown.

The electrode-embedded substrate 1 according to the embodiment includes an SOI substrate wafer 120 and wiring layers 26 ₁ , 26 ₂ , 26 ₃ ,..., 26 _n embedded in through holes formed in the SOI substrate wafer 120, Since the beam portions 28 ₁ and 28 ₂ having stripe patterns intersecting each other at a predetermined angle θ in plan view are provided, as shown in FIG. 5B, the wiring layers 26 ₁ , 26 ₂ , 26 ₃ ,. It is possible to suppress the occurrence of sticking where the 26 _n lines come into contact with each other.

  A schematic planar pattern configuration of the electrode built-in substrate 1A according to the comparative example, which is a substrate with built-in electrode 1A having a spiral-shaped inductance element formed on the silicon substrate 12A, is expressed as shown in FIG.

  As shown in FIG. 6, the electrode built-in substrate 1 </ b> A according to the comparative example supports the silicon substrate 12 </ b> A in a state in which the groove portion of the through hole is formed because the wiring layer 26 embedded in the through hole is formed in a coil shape. Since only the portion A of the circle indicated by the broken line in FIG. 6 is produced, the manufacturing reliability tends to be lowered.

  The electrode-embedded substrate according to the embodiment can be formed, for example, by forming a groove portion in an SOI substrate and embedding copper in the groove portion, so that a spiral coil structure can be easily realized inside the SOI substrate.

  The electrode-embedded substrate according to the embodiment can be applied to LSI stacked modules, interposers, inductance elements, shield substrates, and the like, as will be described later.

  The electrode built-in substrate according to the embodiment can form the electrode built-in substrate structure by two-step etching from the front surface and the back surface of the SOI substrate. In addition, for example, since a lattice-like beam structure is provided on the back surface, even if the line and space (L & S) of the electrode wiring layer is lengthened, sticking in which the lines are in contact hardly occurs.

  In addition, since the electrode built-in substrate according to the embodiment has a penetrating structure other than the beam portion, it is easy to fill with metal plating such as copper.

  In the embodiment, it is possible to provide a substrate with a built-in electrode that has a simple structure and is difficult to cause sticking in which lines come into contact with each other and can improve reliability.

  As a result, the yield is improved because it is not affected by variations in the etching rate within the wafer surface. In addition, the width can be changed for each wiring, and the degree of freedom in design has been expanded.

  In this embodiment, since the SOI substrate is used, it is possible to prevent the beam portion from being broken by overetching by the etch stop layer inside the substrate. As described above, since the SOI substrate is hardly affected by variations in the etching rate, the yield of the substrate with a built-in electrode can be improved.

  In addition, a plurality of wiring layers having different wiring widths and sizes can be simultaneously formed on the same SOI substrate, and the degree of freedom in design can be improved.

(Method for manufacturing electrode-embedded substrate)
In the electrode-embedded substrate 1 according to the embodiment, a schematic surface pattern configuration is expressed as shown in FIG. 7A, and a schematic cross-sectional structure along the line VV in FIG. The schematic cross-sectional structure diagram represented as shown in FIG. 7B and taken along the line VI-VI in FIG. 7A is represented as shown in FIG. 7C and corresponds to FIG. A schematic back surface pattern configuration is expressed as shown in FIG. FIG. 7B also corresponds to a schematic cross-sectional structure along the line VV in FIG. FIG. 7C also corresponds to a schematic cross-sectional structure taken along the line VI-VI in FIG.

The electrode-embedded substrate 1 according to the embodiment includes an SOI substrate 12 and groove portions 25 ₁ , 25 ₂ , 25 ₃ formed inside the SOI substrate 12 as shown in FIGS. 7A to 7D. - 25 except the _{4-25 5} embedded in the wiring layers 26 _1, 26 _2, 26 _3, 26 _4, 26 _5, a wiring layer 26 _1, 26 _2, 26 _3, 26 _4, 26 _5, SOI substrate 12 The etch stop layer 6 is formed inside and the beam portions 28 ₁ , 28 _2, and 28 ₃ are disposed on the back surface facing the surface of the SOI substrate 12. Here, the trenches 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ formed inside the SOI substrate 12 are filled with a metal such as copper (Cu) to thereby form the wiring layers 26 ₁ , 26 _2, and so on. 26 ₃ , 26 ₄ and 26 ₅ are formed.

Further, as shown in FIGS. 7A and 7D, the beam portions 28 ₁ , 28 _2, and 28 ₃ are connected to the wiring layers 26 ₁ , 26 ₂ , 26 ₃ , 26 _4, and 26 ₅ in a plan view. The stripe pattern is orthogonal and parallel to each other. Although not shown, the beam portion may be provided with a stripe pattern that intersects with each other at a predetermined angle θ in plan view, as in FIG.

Further, as shown in FIG. 7B, the thickness TB of the beam portions 28 ₁ , 28 _2, and 28 ₃ is formed thinner than the depth TD of the groove portion. The thickness T of the SOI substrate 12 is equal to TB + TD + Δ (the thickness of the etch stop layer 6).

Further, as shown in FIG. 7B, the line widths of the wiring layers 26 ₁ , 26 ₂ , 26 ₃ , 26 ₄ and 26 ₅ are equal to Y, and the space width is equal to X.

  With reference to FIGS. 8-16, the manufacturing method of the electrode built-in board | substrate which concerns on embodiment shown by FIG. 7 is demonstrated.

In the manufacturing method of the electrode built-in substrate according to the embodiment, the grooves 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ are formed inside the SOI substrate 12 by using the SOI substrate in which the etch stop layer is formed. step and a step of forming a beam portion 28 _1, 28 _2, 28 ₃ on the back surface opposite to the surface of the SOI substrate 12, grooves 25 _1, 25 _2, 25 _3, 25 _4, 25 ₅ to the wiring layer 26 ₁ A step of embedding 26 ₂ , 26 ₃ , 26 ₄ and 26 ₅ .

  FIG. 8A shows a schematic surface pattern configuration at the start of the process, which is one step of the method for manufacturing the electrode built-in substrate according to the embodiment, and is VII-VII in FIG. A schematic cross-sectional structure along the line is expressed as shown in FIG. 8B, and a schematic back surface pattern configuration corresponding to FIG. 8A is expressed as shown in FIG. FIG. 8B also corresponds to a schematic cross-sectional structure along the line VII-VII in FIG.

  FIG. 9A shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode-embedded substrate according to the embodiment, which is shown in FIG. A schematic cross-sectional structure along the line -VIII is expressed as shown in FIG. 9B, and a schematic back surface pattern configuration corresponding to FIG. 9A is expressed as shown in FIG. 9C. . FIG. 9B also corresponds to a schematic cross-sectional structure taken along line VIII-VIII in FIG.

  FIG. 10A shows a schematic surface pattern configuration in the upper surface etching process, which is a process of the method for manufacturing the electrode built-in substrate according to the embodiment. A schematic cross-sectional structure along the line IX is expressed as shown in FIG. 10B, and a schematic back surface pattern configuration corresponding to FIG. 10A is expressed as shown in FIG. FIG. 10B also corresponds to a schematic cross-sectional structure along the line IX-IX in FIG.

  FIG. 11A shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode-embedded substrate according to the embodiment, in the resist stripping process on the upper surface, and the X in FIG. A schematic cross-sectional structure along the X-ray is expressed as shown in FIG. 11B, and a schematic back surface pattern configuration corresponding to FIG. 11A is expressed as shown in FIG. . FIG. 11B also corresponds to a schematic cross-sectional structure along the line XX in FIG.

(Groove formation process)
(A1) First, as shown in FIGS. 8A to 8C, an SOI substrate 12 having an etch stop layer 6 formed therein is prepared.
(A2) Next, as shown in FIGS. 9A to 9C, a resist 14 is applied on the surface of the SOI substrate 12 and patterned by a photolithography process.
(A3) Next, as shown in FIGS. 10A to 10C, etching is performed on the surface of the SOI substrate 12 to form grooves 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ . To do.
(A4) Next, as shown in FIGS. 11A to 11C, the resist 14 on the surface of the SOI substrate 12 is removed. Here, as shown in FIGS. 10B and 11B, the width of the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ is represented by Y, and the groove portions 25 ₁ , 25 ₂ , 25 are shown. The width between ₃ · 25 ₄ · 25 ₅ is represented by X. The depths of the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ are represented by TD. The thickness of the thinned beam portion is represented by TB. The thickness TB is formed thinner than the depth TD of the groove.

Furthermore, after forming the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ , it is necessary to form an insulating layer by thermal oxidation or chemical vapor deposition (CVD).

(Beam formation process)
FIG. 12A shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode-embedded substrate according to the embodiment, which is shown in FIG. The schematic cross-sectional structure along the line -XI is represented as shown in FIG. 12 (b), and the schematic cross-sectional structure along the line XII-XII in FIG. 12 (a) is as shown in FIG. 12 (c). A schematic back surface pattern configuration shown and corresponding to FIG. 12A is expressed as shown in FIG. FIG. 12B also corresponds to a schematic cross-sectional structure along the line XI-XI in FIG. FIG. 12C also corresponds to a schematic cross-sectional structure along the line XII-XII in FIG.

  FIG. 13A shows a schematic surface pattern configuration in the lower surface etching process, which is one step of the method for manufacturing the electrode built-in substrate according to the embodiment. A schematic cross-sectional structure along the XIII line is represented as shown in FIG. 13B, and a schematic cross-sectional structure along the XIV-XIV line in FIG. 13A is represented as shown in FIG. 13C. Then, a schematic back surface pattern configuration corresponding to FIG. 13A is expressed as shown in FIG. FIG. 13B also corresponds to a schematic cross-sectional structure taken along line XIII-XIII in FIG. FIG. 13C also corresponds to a schematic cross-sectional structure taken along line XIV-XIV in FIG.

FIG. 14 (a) shows a schematic surface pattern configuration in one process of the method for manufacturing an electrode-embedded substrate according to the embodiment, in the resist removing process on the lower surface, and the XV in FIG. 14 (a). The schematic cross-sectional structure along the line -XV is represented as shown in FIG. 14 (b), and the schematic cross-sectional structure along the line XVI-XVI in FIG. 14 (a) is as shown in FIG. 14 (c). The schematic back surface pattern configuration shown and corresponding to FIG. 14A is expressed as shown in FIG. FIG. 14B also corresponds to a schematic cross-sectional structure taken along line XV-XV in FIG. FIG. 14C also corresponds to a schematic cross-sectional structure taken along line XVI-XVI in FIG.
(B1) Next, as shown in FIGS. 12A to 12D, a resist 16 is applied on the back surface of the SOI substrate 12 and patterned by a photolithography process. Here, as shown in FIG. 12C, the opening width Y ₂ of the lower resist 16 is relatively larger than the opening width of the upper resist 14 (corresponding to Y ₁ in FIG. 12C). It is desirable to set it narrowly. For example, the opening widths Y ₁ and Y ₂ are 50 μm and 30 μm. This is to suppress the occurrence of a step due to the misalignment.
(B2) Next, as shown in FIGS. 13A to 13D, etching is performed on the back surface of the SOI substrate 12 to form the through-groove portions 27 ₁ , 27 ₂ , 27 ₃ , 27 _4, and 27 ₅ . Then, the beam portions 28 ₁ , 28 _2, and 28 ₃ are formed.
(B3) Next, as shown in FIG. 14 (a) ~ FIG 14 (d), exposed to the groove 25 _1, 25 _2, 25 _3, 25 _4, 25 _5, the through grooves 27 _1, 27 _2, After removing the etch stop layer 6 between 27 ₃ , 27 ₄ and 27 ₅ , the resist 16 on the back surface of the SOI substrate 12 is removed. A step structure as shown in FIG. 14C is formed on the SOI substrate 12 by setting the opening width Y ₂ of the lower resist 16 to be relatively narrow. In the following steps, the same structure is maintained.

Here, as shown in FIG. 14B and FIG. 14C, the width of the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ is represented by Y, and the groove portions 25 ₁ , 25 ₂ , 25 are displayed. The width between ₃ · 25 ₄ · 25 ₅ is represented by X. The depths of the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ are represented by TD. The thickness of the portion to be the beam portion 28 _1, 28 _2, 28 ₃ is represented by TB. The thickness TB is formed thinner than the depth TD of the groove.

  Further, the thickness T of the SOI substrate 12 is equal to TB + TD + Δ (the thickness of the etch stop layer 6) as shown in FIG.

  Furthermore, an insulating layer can be formed on the entire substrate by performing a thermal oxidation process.

(Wiring layer embedding process)
FIG. 15A shows a schematic surface pattern configuration in one step of the method for manufacturing the electrode-embedded substrate according to the embodiment, in the metal (Cu) plating embedding step. A schematic cross-sectional structure taken along line XVII-XVII is represented as shown in FIG. 15B, and a schematic cross-sectional structure taken along line XVIII-XVIII in FIG. 15A is shown in FIG. A schematic back surface pattern configuration corresponding to FIG. 15A is expressed as shown in FIG. FIG. 15B also corresponds to a schematic cross-sectional structure along the line XVII-XVII in FIG. FIG. 15C also corresponds to a schematic cross-sectional structure along the line XVIII-XVIII in FIG.

FIG. 16A shows a schematic surface pattern configuration in one step of the method of manufacturing the electrode-embedded substrate according to the embodiment, in the metal (Cu) plating polishing step on the upper surface and the lower surface. A schematic cross-sectional structure taken along line XIX-XIX in FIG. 16A is represented as shown in FIG. 16B, and a schematic cross-sectional structure taken along line XX-XX in FIG. The schematic back surface pattern configuration shown as shown in c) and corresponding to FIG. 16A is shown as shown in FIG. FIG. 16B also corresponds to a schematic cross-sectional structure taken along line XIX-XIX in FIG. FIG. 16C also corresponds to a schematic cross-sectional structure along the line XX-XX in FIG.
(C1) Next, as shown in FIGS. 15A to 15D, a metal plating layer is formed from the surface side of the SOI substrate 12 with respect to the grooves 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ . 26 U is formed, and metal plating layers 26 U and 26 D are formed on the through groove portions 27 ₁ , 27 ₂ , 27 ₃ , 27 ₄ and 27 ₅ from the front surface side and the back surface side of the SOI substrate 12. The metal plating layers 26U and 26D may include, for example, a Cu plating layer. In addition, although illustration is abbreviate | omitted, all perform the process of forming the seed layer for formation of a plating layer as a pre-process of the process of forming metal plating layer 26U * 26D. In the seed layer forming process, a CVD technique, a sputtering technique, a vapor deposition technique, an electroless plating technique, or the like can be applied.

Further, after the grooves 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ and the through grooves 27 ₁ , 27 ₂ , 27 ₃ , 27 _4, and 27 ₅ are formed, an insulating layer is formed by thermal oxidation or CVD. Then, the process of forming the metal plating layers 26U and 26D is performed.
(C2) Next, as shown in FIGS. 16A to 16D, a polishing process of the metal plating layers 26U and 26D is performed on the front surface and the back surface of the SOI substrate 12 to form the grooves 25 ₁ and 25 _2. The wiring layers 26 ₁ , 26 ₂ , 26 ₃ , 26 _4, and 26 ₅ embedded in the 25 ₃ , 25 ₄ , 25 ₅ and the through-groove portions 27 ₁ , 27 ₂ , 27 ₃ , 27 _4, and 27 ₅ are formed. . Here, as the polishing process, a chemical mechanical polishing (CMP) technique may be applied.

Here, in the electrode built-in substrate according to the embodiment, the thickness Δ of the etch stop layer 6 is, for example, about 0.1 μm to 40 μm, and preferably about 0.5 μm to 20 μm. The thickness TB of the beam portions 28 ₁ , 28 _2, and 28 ₃ is, for example, about ₁ μm to 400 μm, and more preferably about 10 μm to 200 μm. The widths W1, W2, and W3 of the beam portions 28 ₁ , 28 _2, and 28 ₃ are, for example, about 1 μm to 200 μm, and more preferably about 5 μm to 100 μm. The depth TD of the grooves 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ is, for example, about 10 μm to 1000 μm, and more preferably about 50 μm to 500 μm. The width Y of the groove portions 25 ₁ , 25 ₂ , 25 ₃ , 25 _4, and 25 ₅ is, for example, about 1 μm to 400 μm, and more preferably about ₅ μm to 200 μm.

  In the following description of the inductance element, interposer, shield substrate, and module to which the electrode-embedded substrate according to this embodiment can be applied, the SOI substrate may be simply described as a substrate (the illustration of the etch stop layer is omitted). included.

(Comparison between SOI substrate type and permalloy substrate type inductance elements)
FIG. 17 shows a schematic cross-sectional structure of an SOI substrate type inductance element formed by applying the electrode built-in substrate according to the embodiment. Moreover, a schematic cross-sectional structure (structure example without back surface polishing) of the permalloy substrate type inductance element according to the comparative example is represented as shown in FIG. 18A, and a structure example with back surface polishing is shown in FIG. It can be expressed as shown in b). In FIG. 17, the beam structure will be described later with reference to FIG.

  The SOI substrate type inductance element 32 formed by applying the electrode built-in substrate according to the embodiment is embedded in the SOI substrate 12 and a groove formed inside the SOI substrate 12 as shown in FIG. The wiring layer 26, the etch stop layer 6 formed inside the SOI substrate 12 excluding the wiring layer 26, and the insulating layer 30S disposed on the side surface of the wiring layer 26 and the insulating layer disposed on the surface of the wiring layer 26 The insulating layer 30D disposed on the back surface of the wiring layer 26, the magnetic layer 10U disposed on the insulating layer 30U, and the magnetic layer 10D disposed below the insulating layer 30D. The beam portion 28 formed on the SOI substrate 12 is not shown. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element 32.

  In the SOI substrate method, a coil having a high density and a large cross-sectional area can be formed by deep etching and a through silicon via (TSV) technique. Since the SOI substrate is a non-magnetic substrate, the magnetic resistance is large and the inductance value is relatively smaller than that of the permalloy method, but magnetic saturation is less likely to occur, which is advantageous for increasing the current.

  As shown in FIG. 18 (a), a schematic cross-sectional structure of a permalloy substrate type inductance element according to a comparative example (structure example without back surface polishing) includes a permalloy substrate 120P and a groove formed inside the permalloy substrate 120P. A wiring layer 260 embedded in the insulating layer 300S, an insulating layer 300S disposed on the side surface / bottom surface of the wiring layer 260, an insulating layer 300U disposed on the surface of the wiring layer 260, and a magnetic layer 100U disposed on the insulating layer 300U. Is provided. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element 32.

  As shown in FIG. 18B, a schematic cross-sectional structure of a permalloy substrate type inductance element according to a comparative example (structure example with backside polishing) is a permalloy substrate 120P and a groove formed inside the permalloy substrate 120P. A wiring layer 260 embedded in the wiring layer 260; an insulating layer 300S disposed on the side surface of the wiring layer 260; an insulating layer 300D disposed on the bottom surface of the wiring layer 260; an insulating layer 300U disposed on the surface of the wiring layer 260; A magnetic layer 100U disposed above 300U and a magnetic layer 100D disposed below the insulating layer 300D. The broken line schematically represents the path through which the magnetic flux passes in the operating state of the inductance element.

  In the permalloy substrate system, wet etching is applied to process the permalloy, which is disadvantageous for increasing the density and the cross-sectional area of the coil. On the other hand, since the permalloy substrate is a magnetic substrate, the magnetic resistance is small and the inductance value is large.

(Configuration of inductance element)
A schematic bird's-eye view configuration of the inductance element 32 formed by applying the electrode-embedded substrate according to the embodiment is represented as shown in FIG. 19A and is along the XXI-XXI line of FIG. A schematic cross-sectional structure is represented as shown in FIG.

  As shown in FIG. 19, the inductance element 32 formed by applying the electrode built-in substrate according to the embodiment includes an SOI substrate 12 and a wiring layer 26 embedded in a groove formed in the SOI substrate 12. The etch stop layer 6 formed inside the SOI substrate 12 excluding the wiring layer 26, the insulating layer 30S disposed on the side surface of the wiring layer 26, the insulating layer 30U disposed on the surface of the wiring layer 26, and the wiring layer 26, the insulating layer 30D disposed on the back surface, the magnetic layer 10U disposed on the insulating layer 30U, and the magnetic layer 10D disposed below the insulating layer 30D. The beam portion 28 formed on the SOI substrate 12 is not shown.

  In the inductance element 32 formed by applying the electrode built-in substrate according to the embodiment, the wiring layer 26 embedded in the groove has a coil shape as shown in FIGS. 20 (a) to 20 (c). May be.

  Moreover, as shown in FIG. 19, you may provide the upper core (30U * 10U) arrange | positioned at the surface of the SOI substrate 12. FIG.

  Moreover, as shown in FIG. 19, you may provide the lower core (30D * 10D) arrange | positioned at the back surface of the SOI substrate 12. FIG.

  Further, the upper core (30U · 10U) and the lower core (30D · 10D) may have a multilayer structure of the magnetic layers 10U · 10D and the insulating layers 30U · 30D.

  Furthermore, as shown in FIG. 19, you may provide the slit SL which divides | segments an upper core (30U * 10U) and a lower core (30D * 10D) into plurality. With this slit structure, eddy current loss can be reduced. The magnetic layers 10U and 10D may include a ferromagnetic material such as permalloy or ferrite.

  The insulating layers 30U and 30D may include any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material. Further, the eddy current radius in the magnetic layers 10U and 10D can be controlled by dividing the magnetic layers 10U and 10D by the thickness of the magnetic layers 10U and 10D and the slit SL.

(Inductance element manufacturing method: upper core / lower core formation process)
In addition to the manufacturing process of the electrode-embedded substrate 1 according to the above-described embodiment, the manufacturing method of the inductance element formed by applying the electrode-embedded substrate according to the embodiment includes FIGS. 17 and 19B. As shown in FIG. 2, the method includes a step of forming an upper core (30U · 10U) on the surface of the SOI substrate 12 and a step of forming a lower core (30D · 10D) on the back surface facing the surface of the SOI substrate 12. May be.
(D1) As shown in FIGS. 17 and 19B, the surface of the SOI substrate 12 and the electrode-embedded substrate 1 formed by carrying out the manufacturing process of the electrode-embedded substrate according to the above embodiment Insulating layers 30U and 30D are formed on the back surface.
(D2) Next, as shown in FIGS. 17 and 19B, the magnetic layer 10U is formed on the insulating layer 30U to form the upper core (30U · 10U).
(D3) Next, as shown in FIGS. 17 and 19B, the magnetic layer 10D is formed under the insulating layer 30D to form the lower core (30D and 10D).

  In forming the upper core (30U · 10U) and the lower core (30D · 10D), a multilayer structure of a magnetic layer and an insulating layer may be formed. Here, the magnetic layer can be formed by a plating technique, a sputtering technique, a vacuum deposition technique, or the like.

  An inductance element 32 formed by applying the electrode built-in substrate according to the embodiment, and a schematic bird's-eye view configuration of the wiring layer portion is expressed as shown in FIG. 20B is represented as shown in FIG. 20B, and the back surface configuration of FIG. 20A is represented as shown in FIG. 20C.

  Furthermore, the cross-sectional bird's-eye view configuration along the line XXII-XXII in the central portion of FIG. 20A is represented as shown in FIG. 21A, and the cross-sectional configuration viewed from the direction of arrow B1 in FIG. 21 (b), and an enlarged view of the portion C1 in FIG. 21 (b) is represented as shown in FIG. 21 (c).

  Moreover, the cross-sectional bird's-eye view configuration along line XXIII-XXIII in FIG. 20A is represented as shown in FIG. 22A, and the cross-sectional configuration viewed from the direction of arrow B2 in FIG. b), and an enlarged view of a portion C2 in FIG. 22B is represented as shown in FIG. 22C.

  Furthermore, the front side schematic bird's-eye view configuration of only the SOI substrate 12 in FIG. 20A is represented as shown in FIG. 23A, and the rear side schematic bird's-eye view configuration in FIG. It is expressed as shown in b).

  The inductance element 32 formed by applying the electrode built-in substrate according to the embodiment is formed by performing two-step etching and Cu plating technology on the SOI substrate 12. As shown in FIGS. 20A and 23A, the size of the SOI substrate 12 is represented by LX · LY. As a specific numerical example, LX and LY are both about 4.2 mm.

  In addition, the inductance element 32 formed by applying the electrode built-in substrate according to the embodiment has a lattice-structure beam 28 on the back surface of the SOI substrate 12 as shown in FIGS. 20 (c) and 23 (b). Prepare. Here, the width of the cross portion of the lattice of the beam portion 28 is represented by ΔB, and the width of the frame portion of the lattice is represented by ΔEX · ΔEY. As specific numerical examples, ΔB, ΔEX, and ΔEY are all about 100 μm.

  In addition, as shown in FIG. 21C, the line and space of the wiring layer 26 is represented by Y and X, the depth of the wiring layer 26 is represented by TD, and the thickness of the beam portion 28 is represented by TB. The As a specific numerical example, the line width Y of the wiring layer 26 is about 50 μm, the interval X is about 15 μm, the depth TD of the wiring layer 26 is about 300 μm, and the thickness TB of the beam portion 28 is about 50 μm.

  Further, as shown in FIG. 22C, the width of the beam portion 28 at the center of the SOI substrate 12 is represented by WB. This WB is equal to ΔB in FIGS. 20C and 23B and is about 100 μm.

  In the inductance element 32 formed by applying the electrode built-in substrate according to the embodiment, since the inductance element built in the SOI substrate is formed, it is used for a DC / DC converter in which an IC or a capacitor is arranged on the electrode built-in substrate. Applicable. Further, by forming the magnetic layers 10U and 10D above and below the electrode-embedded substrate, it is possible to reduce the influence of noise on the IC and the capacitor.

(Beam structure)
FIG. 24 is a schematic plan view of the structure of the beam portion 28 applicable to the electrode built-in substrate according to the embodiment, in which a cross-shaped configuration example is represented as shown in FIG. 24 (b), a diagonal cross type configuration example is shown as shown in FIG. 24 (c), and a circular / cross composite type configuration example is shown in FIG. 24 (d). It is expressed in

  As shown in FIG. 24, the structure of the beam portion 28 applicable to the electrode-embedded substrate according to the embodiment is one of a cross shape, a lattice type, a diagonal cross type, and a circular / cross composite type in plan view. You may have the following pattern. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  Further, in the electrode-embedded substrate according to the embodiment, the groove portion or the wiring layer has a cross shape, a lattice shape, a diagonal cross shape, a circular / cross composite shape, a rectangular shape, a circular shape, an oval shape, as well as the shape of the beam portion. You may have any pattern, such as an octagon, a triangle, or a polygon.

(Inductance frequency characteristics)
The simulation result of the frequency characteristic of the inductance L of the inductance element formed by applying the electrode built-in substrate according to the embodiment is expressed as shown in FIG.

  Further, the simulation result of the frequency characteristics of the AC resistance ACR of the inductance element formed by applying the electrode built-in substrate according to the embodiment is expressed as shown in FIG.

  25 and 26, the “air core” curve represented by the plot corresponds to the structure having the insulating layers 30U and 30D above and below the electrode-embedded substrate, and the “magnetic layer” represented by the plot. The curve corresponds to the structure having the magnetic layers 10U and 10D above and below the insulating layers 30U and 30D, and the “magnetic layer & slit” curve represented by the plot ■ further forms a slit SL in the magnetic layers 10U and 10D. It corresponds to the structure.

  The frequency characteristic of the inductance L of the inductance element according to the embodiment shows a substantially constant value in the measurement range of 100 kHz to 10 MHz. The inductance L can be increased by forming the magnetic layers 10U and 10D.

  The frequency characteristic of the AC resistance ACR of the inductance element according to the embodiment shows a relatively low value of the AC resistance ACR in the measurement range of 100 kHz to 10 MHz. In particular, by forming the slit SL, a relatively low AC resistance ACR can be obtained as compared with the case of only the magnetic layers 10U and 10D.

(module)
―Comparison example―
A mounting configuration example of the DC / DC converter module according to the comparative example is expressed as shown in FIG. In the DC / DC converter module according to the comparative example, since the inductance element 34, the IC 36, and the capacitors 40 ₁ and 40 ₂ are mounted on the printed circuit board 38, it is difficult to reduce the mounting area.

-Configuration example 1-
The integrated circuit block configuration of configuration example 1 of the DC / DC converter module 3 according to the embodiment is expressed as shown in FIG. In FIG. 28, a terminal A1: VIN represents a power supply terminal to which the DC / DC converter input voltage VIN of the voltage E is input, a terminal A2: EN represents an enable terminal, and a terminal A3: GND represents a ground terminal. Terminal B1: LX represents an inductor connection terminal, terminal B2: FB represents an output voltage feedback input terminal, and terminal B3: MODE represents a DE / PFM-PWM mode switching terminal. An input capacitor Ci is connected to the voltage E in parallel. An output capacitor Co is connected to the terminal B1: LX via a reactor L, and a DC / DC converter output voltage VOUT can be obtained from both ends of the output capacitor Co.

  In addition, a stacked composite diagram of the schematic planar pattern configuration of the configuration example 1 of the DC / DC converter module 3 corresponding to FIG. 28 is expressed as shown in FIG. 29 and schematically along the line XXIV-XXIV in FIG. The cross-sectional structure is expressed as shown in FIG.

As shown in FIG. 30, the DC / DC converter module 3 according to the embodiment excludes the SOI substrate 12, the wiring layer 26 embedded in the groove formed inside the SOI substrate 12, and the wiring layer 26. Etch stop layer 6 formed in SOI substrate 12, insulating layer 30 U ₁ / magnetic layer 10 U / insulating layer 30 U ₂ disposed on the surface of wiring layer 26, and insulating layer disposed on the back surface of wiring layer 26 30D ₁ / magnetic layer 10D / insulating layer 30D ₂ , IC 36 and capacitor 40 disposed on the insulating layer 30U ₂ via the upper surface wiring layer 44 and solder layer 45, and the lower surface disposed on the lower surface of the insulating layer 30D ₂ A wiring layer 46 and a solder layer 47 are provided. Here, the insulating layer 30S disposed on the side surface of the wiring layer 26, the slit SL formed in the magnetic layers 10U and 10D and the beam portion 28 formed in the SOI substrate 12 are not shown.

  In the configuration example 1 of the DC / DC converter module 3 according to the embodiment, an IC 36 and a capacitor 40 can be mounted as shown in FIGS. For this reason, the mounting area can be reduced by the lamination technique.

  The bird's-eye view configuration of the configuration example 1 of the DC / DC converter module 3 according to the embodiment corresponding to FIGS. 29 and 30 is expressed as shown in FIG.

  As shown in FIG. 31, an IC 36 and a capacitor 40 can be mounted on an inductance element 32 formed by applying an electrode built-in substrate. For this reason, the mounting area can be reduced by the lamination technique as compared with the comparative example.

  A schematic plan configuration of the lower surface wiring layer 46 of FIGS. 29 to 31 is expressed as shown in FIG. 32. On the lower wiring layer 46, a VIN electrode pattern for the terminal A1, an EN electrode pattern for the terminal A2, a GND electrode pattern for the terminal A3, a VOUT electrode pattern for the terminal B1, a MODE electrode pattern for the terminal B3, and the like are arranged. ing.

  The schematic planar configuration of the inductor layer of FIGS. 29 to 31 is expressed as shown in FIG. As shown in FIG. 33, the wiring layer 26 embedded in the groove formed inside the SOI substrate 12 is arranged in a coil shape. A through electrode 26T for extracting the electrode of the wiring layer 26 is formed at the center of FIG. Here, the through electrode 26 </ b> T connects the upper surface wiring layer 44 and the lower surface wiring layer 46.

  A schematic plan configuration of the upper surface wiring layer 44 of FIGS. 29 to 31 is expressed as shown in FIG. 34. As shown in FIG. 34, a power supply terminal A1: VIN electrode pattern to which a DC / DC converter input voltage VIN of voltage E is input, enable terminal A2: EN electrode pattern, ground terminal A3: GND electrode pattern, inductor connection Terminal B1: LX electrode pattern, output voltage feedback input terminal B2: FB electrode pattern, DE / PFM-PWM mode switching terminal B3: MODE electrode pattern, and the like are arranged.

  A schematic plan configuration of the IC / capacitor layer of FIGS. 29 to 31 is expressed as shown in FIG. As shown in FIG. 35, an IC 36, an input capacitor Ci, and an output capacitor Co are arranged.

-Configuration example 2-
A schematic cross-sectional structure of Configuration Example 2 of the DC / DC converter module 3 according to the embodiment is expressed as shown in FIG.

As shown in FIG. 36, the configuration example 2 of the DC / DC converter module 3 according to the embodiment includes an SOI substrate 12, a wiring layer 26 embedded in a groove formed inside the SOI substrate 12, and a wiring layer. 26, the etch stop layer 6 formed inside the SOI substrate 12, the insulating layer 30U ₁ / magnetic layer 10U / insulating layer 30U ₂ disposed on the surface of the wiring layer 26, and the back surface of the wiring layer 26. Insulating layer 30D ₁ / magnetic layer 10D / insulating layer 30D ₂ , IC 36 and capacitor 40 disposed on insulating layer 30U ₂ via upper surface wiring layer 44 and solder layer 45, and on the lower surface of insulating layer 30D ₂ The lower surface wiring layer 46 and the solder layer 47 are provided. Here, the insulating layer 30S disposed on the side surface of the wiring layer 26, the slit SL formed in the magnetic layers 10U and 10D and the beam portion 28 formed in the SOI substrate 12 are not shown.

  The configuration example 2 of the DC / DC converter module 3 according to the embodiment includes a structure in which the SOI substrate 12 is processed into a ship shape as shown in FIG. Similar to the first configuration example, the IC 36 and the capacitor 40 can be mounted on the bottom of the SOI substrate 12 processed into a ship shape. For this reason, the mounting area can be reduced and the height can be reduced by the lamination technique.

  The area of the DC / DC converter module 3 according to the embodiment can be reduced by the laminated structure. Further, since no IC built-in substrate or ferrite substrate is used, it can be formed at low cost.

  The DC / DC converter module 3 according to the embodiment can be formed by using the deep etching of the SOI substrate and the copper plating technique as described in the method for manufacturing the electrode built-in substrate.

(Shield board)
A schematic bird's-eye view configuration of the shield substrate 2 formed by applying the electrode built-in substrate according to the embodiment is expressed as shown in FIG. Moreover, the top view of FIG. 37 is represented as shown in FIG. 38A, and the schematic cross-sectional structure along the line XXV-XXV of FIG. 38A is represented as shown in FIG. A schematic cross-sectional structure taken along line XXVI-XXVI in FIG. 38A is represented as shown in FIG.

  The shield substrate 2 formed by applying the electrode-embedded substrate according to the embodiment includes an SOI substrate 12 and an SOI substrate 12 as shown in FIGS. 37 and 38 (a) to 38 (c). A wiring layer 26C formed and embedded in a groove having a rectangular stripe pattern in plan view, an etch stop layer 6 formed inside the SOI substrate 12 excluding the wiring layer 26C, and the surface of the SOI substrate 12 The beam part 28 arrange | positioned at the back surface which opposes, and the back surface electrode 26B arrange | positioned at the back surface which opposes the surface of the SOI substrate 12 are provided. Here, a wiring layer 26 </ b> C is formed by embedding a metal such as copper (Cu) in a groove formed in the SOI substrate 12.

  Moreover, the beam part 28 is provided with the cross-shaped pattern in planar view of Fig.38 (a)-FIG.38 (c).

  In the above configuration, the structure of the wiring layer 26C embedded in the groove portion having a rectangular pattern in a plan view is shown. However, the structure is not limited to this, and a circular shape, an elliptical shape, an octagonal shape, a triangular shape, Or you may have any pattern, such as a polygon. Any shape may be used as long as it can exhibit a shielding effect, and any shape pattern may be provided as long as a closed circuit is formed.

  Similarly to FIG. 24, the structure of the beam portion 28 may have a pattern of a cross shape, a lattice shape, a diagonal cross shape, or a circular / cross composite shape in plan view. Furthermore, it may have any pattern such as a rectangle, a circle, an ellipse, an octagon, a triangle, or a polygon.

  Of the SOI substrate 12, the SOI substrate 12I surrounded by the wiring layer 26C embedded in the groove portion having a rectangular stripe pattern in plan view is surrounded by the wiring layer 26C and the back electrode 26B. Even if it is placed in the environment of the electromagnetic field EM as shown in FIG. 38 (c), the influence of noise can be suppressed. For example, the electromagnetic shielding effect can be obtained by digging the SOI substrate 12I and arranging the components. Furthermore, if metal is formed on the upper surface of the wiring layer 26C and the SOI substrate 12I, the influence of noise from the upper surface can be suppressed.

(Interposer)
A schematic bird's-eye view configuration in which the silicon interposer 50 formed by applying the electrode-embedded substrate according to the embodiment is arranged on the package substrate 52 is expressed as shown in FIG. 39 (a) and shown in FIG. 39 (a). A schematic cross-sectional structure along the line XXVII-XXVII is expressed as shown in FIG. 39 (b), and an enlarged view of a portion E in FIG. 39 (b) is expressed as shown in FIG. 39 (c).

When a plurality of semiconductor integrated circuit chips 48 ₁ , 48 ₂ , 48 _3, and 48 ₄ are mounted on the package substrate 52, the silicon interposer 50 is used as an intermediate layer.

  For the silicon interposer 50, the electrode-embedded substrate according to the embodiment can be applied.

  The silicon interposer 50 formed by applying the electrode-embedded substrate according to the embodiment includes an SOI substrate, a wiring layer embedded in a groove formed inside the SOI substrate, and an inside of the substrate excluding the wiring layer. And an etch stop layer (not shown) formed. Moreover, the beam part is provided similarly to the electrode built-in board | substrate which concerns on embodiment. As described above, an insulating layer may be formed at the boundary between the SOI substrate and the wiring layer.

The BGA solder balls 54 arranged on the back surface of the package substrate 52 can be connected to the bumps 60 arranged on the surface of the package substrate 52 through through vias. Further, the bump 60 can be connected to a micro bump 56 disposed on the silicon interposer 50 via a through silicon via (CUTSV) 58 and an interposer built-in electrode 26I. The micro bumps 56 are connected to the semiconductor integrated circuit chips 48 ₁ , 48 ₂ , 48 _3, and 48 ₄ .

  Since the through-groove can be formed by providing the beam portion with respect to the SOI substrate as in the electrode built-in substrate according to the embodiment, the degree of freedom in designing the silicon interposer 50 is increased.

  According to the silicon interposer to which the electrode-embedded substrate according to the present embodiment is applied, it is possible to provide a highly reliable interposer that has a simple structure and is difficult to cause sticking in which lines are in contact with each other.

(Multi-channel DC / DC converter module)
In order to realize a multi-channel DC / DC converter, it is necessary to design an optimum coil / wiring suitable for the output of each channel. In the conventional technology using a silicon substrate, the width of the coil / wiring is constant for suppressing overetching, and different coil structures cannot be formed on the same wafer.
In the electrode built-in substrate according to the embodiment, coils having different widths and sizes can be formed on the same substrate. For this reason, in the multi-channel DC / DC converter module 180 according to the embodiment, it is possible to form a converter in which the coil / wiring width is optimally designed for each output due to the etch stop effect of the SOI substrate.

  A schematic block configuration of the multi-channel DC / DC converter module 180 according to the embodiment is expressed as shown in FIG.

  As shown in FIG. 40, the multi-channel DC / DC converter module 180 according to the embodiment includes a DC power battery 200 and a plurality of types of converters 202A, 202B1, 202B2, 202C1, 202C2, and the like connected to the DC power battery 200. 202C3, 202C4, 202C5, 202C6.

  The inductance elements according to the embodiment can be mounted on the plurality of types of converters 202A, 202B1, 202B2, 202C1, 202C2, 202C3, 202C4, 202C5, and 202C6. Converters 202A, 202B1, 202B2, 202C1, 202C2, 202C3, 202C4, 202C5, and 202C6 can be configured by, for example, a DC / DC converter, an LDO (Low Drop Ouput), a switching regulator, or the like. Converter 202A is for high current conversion, converters 202B1 and 202B2 are for medium current conversion, and converters 202C1, 202C2, 202C3, 202C4, 202C5, and 202C6 are for small current conversion.

The converter 202A can drive, for example, a CPU (Central Processing Unit) 204, and the converters 202B1, 202B2, for example, can drive a memory 206, a driver 208, and converters 202C1, 202C2, 202C3, 202C4, 202C5, 202C6. Can drive, for example, various sensors 210 ₁ , 210 ₂ , 210 ₃ , 210 ₄ , 210 _5, and 210 ₆ for in-vehicle use.

  In the multi-channel DC / DC converter module 180 according to the embodiment, the schematic bird's-eye view configuration of the upper printed circuit board 38 is expressed as shown in FIG. The bird's-eye view configuration is represented as shown in FIG.

  As shown in FIG. 41 (a), the printed circuit board 38 has a board area 38A, 38B1, 38B2, 38C1, 38C2, 38C3, 38C4, 38C5, and 38C6 according to the respective use and driving capacity. Integrated circuits, capacitors, etc. are arranged.

  Here, the integrated circuit may include a DCDC converter control integrated circuit.

  The multi-channel DC / DC converter module 180 according to the embodiment includes an inductance element having a coil shape formed by a wiring layer, and a multi-channel DC / DC converter in which a plurality of inductance elements are arranged on the same substrate. good.

  For example, in the substrate area 38A, an integrated circuit ICA and capacitors CA1 and CA2 for constituting the converter 202A are arranged. In the substrate areas 38B1 and 38B2, an integrated circuit, a capacitor (reference number omitted) and the like constituting the converters 202B1 and 202B2 are arranged, respectively. In the substrate areas 38C1, 38C2, 38C3, 38C4, 38C5, and 38C6, integrated circuits and capacitors (reference numbers omitted) that constitute the converters 202C1, 202C2, 202C3, 202C4, 202C5, and 202C6 are arranged, respectively.

  As shown in FIG. 41 (b), the SOI substrate 12 corresponds to the substrate areas 38A, 38B1, 38B2, 38C1, 38C2, 38C3, 38C4, 38C5, and 38C6 of the printed circuit board 38 on the upper surface. A plurality of inductance elements 108, 106 and 102 having different sizes and wiring widths are arranged.

  That is, the inductance element 108 is disposed at a predetermined position on the SOI substrate 12 corresponding to the substrate area 38A in order to configure the converter 202A. Inductance element 106 is arranged at a predetermined position on SOI substrate 12 corresponding to substrate areas 38B1 and 38B2 in order to constitute converters 202B1 and 202B2. The inductance element 104 is disposed at a predetermined position on the SOI substrate 12 corresponding to the substrate areas 38C1, 38C2, 38C3, 38C4, 38C5, and 38C6 to constitute the converters 202C1, 202C2, 202C3, 202C4, 202C5, and 202C6. The

  On the SOI substrate 12, for example, a plurality of external lead wires 102 are arranged along a pair of parallel sides.

  An enlarged view of the relatively large inductance element 108 shown in FIG. 41 formed as a chip is expressed as shown in FIG. For example, as shown in FIG. 42, the inductance element 108 arranged in the board area 38A of FIG. 41B has an optimal wiring width and size designed according to the output of the converter 202A for large current conversion. Will be.

  According to the multi-channel DC / DC converter module according to the embodiment, the coil having the optimum wiring width for current capacity and frequency control according to the output of each channel due to the effect of suppressing the overetching of the etch stop layer of the SOI substrate Can be designed.

  That is, a plurality of coil structures having different wiring widths and sizes can be simultaneously formed on the same SOI substrate, and the degree of design freedom is increased.

  As described above, according to the present embodiment, an SOI substrate is used, an insulating layer inside the SOI substrate serves as an etch stop layer, and a substrate with a built-in electrode that can prevent the destruction of a beam due to overetching, and a manufacturing method thereof, and An inductance element, an interposer, a shield substrate, and a module to which the electrode built-in substrate is applied can be provided.

(Other embodiments)
As described above, the embodiments have been described. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, this embodiment includes various embodiments not described here.

  The substrate with a built-in electrode according to the present embodiment can be applied to all electronic parts that use inductance such as inductors, transformers, noise filters, and isolators, sensor parts such as magnetic sensors and position sensors, and other coils for wireless power feeding. In addition, the present invention can be applied to an interposer, a shield substrate, and the like, and is particularly applicable to an electronic device such as an inductor for mobile devices and a DC / DC converter module incorporating the inductor.

DESCRIPTION OF SYMBOLS 1 ... Electrode built-in substrate 2 ... Shield substrate 3 ... Module 6 ... Etch stop layer 10U, 10D, 100U, 100D ... Magnetic layer 12, 12I, 120 ... Substrate (SOI substrate, SOI substrate wafer)
14,16 ... resist _{25 1, 25 2, 25 3} , ..., 25 n ... groove _{26,26 1, 26 2, 26 3} , ..., 26 n, 260 ... electrode layer (wiring layer)
26B ... rear electrode 26C ... shield electrode 26I ... interposer built electrode 26T ... through electrodes 26U, 26D ... Cu plated layer _{27 1, 27 2, 27 3} , ..., 27 n ... through the groove 28 _1, 28 _2, 28 ₃ ,..., 28 _n , 29 ₁ , 29 ₂ , 29 ₃ ,..., 29 _n ... Beam portions 30, 30 U, 30 U ₁ , 30 U ₂ , 30 S, 30 D, 30 D ₁ , 30 D ₂ , 300 U, 300 S, 300 D. 32, 34, 104, 106, 108 ... inductance element 36 ... IC (integrated circuit)
38 ... Printed circuit board (PCB)
38A, 38B1, 38B2, 38C1, 38C2, 38C3, 38C4, 38C5, 38C6 ... board area 40, 40 ₁ , 40 ₂ ... capacitor 44 ... upper wiring layer 45, 47 ... solder layer 46 ... lower wiring layer 48 ₁ , 48 ₂ , 48 ₃ , 48 ₄ ... Semiconductor integrated circuit chip 50 ... Silicon interposer 52 ... Package substrate 54 ... BGA solder ball 56 ... Micro bump 58 ... CUTSV (through silicon via)
60 ... Bump 102 ... External extraction wiring 180 ... Multi-channel DC / DC converter module 200 ... DC power battery 202A, 202B1, 202B2, 202C1, 202C2, 202C3, 202C4, 202C5, 202C6 ... Converter 204 ... CPU
206 ... memory 208 ... driver 210 _1, 210 _2, 210 _3, 210 a thickness of _4, 210 _5, 210 ₆ ... sensor SL ... slit theta ... angle delta ... etch stop layer

Claims (20)

A substrate,
A wiring layer embedded in a groove formed in the substrate;
An etch stop layer formed inside the substrate, excluding the wiring layer,
An electrode-embedded substrate comprising: a beam portion disposed on a back surface facing the surface of the substrate.   The electrode built-in substrate according to claim 1, wherein a thickness of the etch stop layer is smaller than a depth of the groove and a thickness of the beam.   The electrode built-in substrate according to claim 1, wherein the etch stop layer has a resistivity of 10 Ω · cm or more. The electrode built-in substrate according to claim 3, wherein the etch stop layer includes a SiO ₂ film.   The electrode built-in substrate according to claim 3, wherein the etch stop layer includes any one of a ferromagnetic material, a paramagnetic material, and a diamagnetic material.   2. The electrode-embedded substrate according to claim 1, wherein the beam portion includes a stripe pattern that is orthogonal to the wiring layer in a plan view and parallel to each other.   The electrode built-in substrate according to claim 1, wherein a plurality of wiring layers having different wiring widths are formed on the substrate.   2. The electrode according to claim 1, wherein the groove, the beam, or the wiring layer has a rectangular, circular, elliptical, octagonal, triangular, or polygonal pattern in plan view. Built-in board.   The electrode built-in substrate according to claim 1, wherein a thickness of the beam portion is thinner than a depth of the groove portion.   The electrode built-in substrate according to claim 1, wherein the substrate is an SOI substrate in which the etch stop layer is formed. The substrate with a built-in electrode according to any one of claims 1 to 10,
The inductance element, wherein the wiring layer has a coil shape.   An interposer comprising the electrode-embedded substrate according to any one of claims 1 to 10. The electrode built-in substrate according to any one of claims 1 to 10,
A shield substrate comprising: a back electrode disposed on a back surface facing the surface of the substrate.   A module comprising the inductance element according to claim 11. A substrate,
A wiring layer embedded in a groove having a coil shape formed inside the substrate;
An etch stop layer formed inside the substrate, excluding the wiring layer,
A beam portion disposed on the back surface facing the front surface of the substrate;
An upper surface wiring layer disposed on the surface of the substrate;
A lower surface wiring layer disposed on the back surface facing the surface of the substrate;
A module comprising: an integrated circuit disposed on the upper wiring layer via a solder layer; and a capacitor. The integrated circuit includes an integrated circuit for controlling a DCDC converter,
The wiring layer includes an inductance element having a coil shape,
The module according to claim 15, further comprising a multi-channel DCDC converter, wherein a plurality of the inductance elements are arranged in the substrate. Using a SOI substrate on which an etch stop layer is formed, forming a groove in the SOI substrate;
Forming a beam portion on the back surface facing the surface of the SOI substrate;
And a step of embedding and forming the wiring layer in the groove. Using a SOI substrate on which an etch stop layer is formed, forming a coil-shaped groove in the SOI substrate;
Forming a beam portion on the back surface facing the surface of the SOI substrate;
A step of embedding a wiring layer in the groove,
Forming an upper core on the surface of the SOI substrate;
Forming a lower core on the back surface opposite to the surface of the SOI substrate. Using a SOI substrate on which an etch stop layer is formed, forming a groove having a closed circuit pattern in a plan view inside the SOI substrate;
Forming a beam portion on the back surface facing the surface of the SOI substrate;
A step of embedding a wiring layer in the groove,
Forming a back electrode on the back surface opposite to the surface of the SOI substrate. Using a SOI substrate on which an etch stop layer is formed, forming a coil-shaped groove in the SOI substrate;
A step of forming a through-groove portion disposed inside the coil shape in plan view and penetrating the SOI substrate;
Forming a beam portion on the back surface facing the surface of the SOI substrate;
A step of embedding a wiring layer in the groove,
Embedding and forming a through electrode in the through groove,
Forming an upper core on the surface of the SOI substrate;
Forming an upper surface wiring layer connected to the through electrode on the upper core;
Forming a lower core on the back surface facing the surface of the SOI substrate;
Forming a lower surface wiring layer connected to the through electrode on the lower core;
And a step of mounting an integrated circuit and a capacitor on the upper wiring layer via a solder layer.