JPWO2016030954A1 - Drive circuit, power conversion device, and motor system - Google Patents

Abstract

The reliability of the power conversion device is improved by preventing false points. The gate drive circuit GD2 that controls on / off of the switch element includes first to fourth switch elements. The transistor T1 has a source connected to a power supply voltage VEE1 that is a negative voltage of about −15V, and a drain connected to an output node VOUT that controls on / off of the switch element. The transistor T2 has a source connected to the power supply voltage VDD of about 15V and a drain connected to the output node VOUT. Transistor T3 has a drain connected to output node VOUT. The transistor T4 has a drain connected to the source of the transistor T3, and a source connected to the power supply voltage VEE2 that is a negative voltage of about −5V.

Description

  The present invention relates to a drive circuit, a power conversion device, and a motor system, and is particularly effective when applied to a power conversion device including a power semiconductor device using a silicon carbide material and a semiconductor drive circuit for driving the power semiconductor device. Technology.

  For example, in Patent Document 1, in order to shorten the mirror time of an insulated gate semiconductor element and shorten the dead time of a PWM (Pulse Width Modulation) inverter provided with the semiconductor element, the gate-emitter between the semiconductor elements is disclosed. A configuration in which a series circuit composed of a capacitor and a switch is inserted is shown.

  Further, Patent Document 2 and Patent Document 3 disclose a method for solving the so-called false ignition problem. The false firing is a phenomenon in which when the lower arm switch is turned off and the upper arm switch is turned on, the gate voltage of the lower arm switch rises, resulting in the switch being erroneously turned on.

  Specifically, a technique is shown in which a so-called switched capacitor circuit is connected to the gate of the lower arm switch, and a negative voltage is dynamically applied to the gate of the lower arm switch using the switched capacitor circuit. Yes. Non-Patent Document 1, Non-Patent Document 2 and Non-Patent Document 3 describe that a threshold voltage fluctuates when a SiC MOSFET (Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor) is continuously energized. Yes.

JP 2000-333441 A JP 2004-159424 A JP 2009-021823 A

Mrinal K. Das, “Commercially Available Cree Silicon Carbide Power Devices: Historical Success of JBS Diodes and Future Switch Prospects”, CS MANTECH Conference, May 16th-19th, 2011, Palm Springs, California, USA Xiao Shen and 7 others, “Atomic-scale origins of bias-temperature instabilities in SiC-SiO2 structures”, APPLIED PHYSICS LETTERS 98, 063507, 2011 Aivars J. Lelis and 6 others, “Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements”, IEEE Transactions on Electron Devices, Vol.55, No.8, pp1835-1840, August 2008

  The importance of the electronics business to reduce environmental impact is increasing in the great social trend of global environmental conservation. In particular, power devices are used as power sources for consumer equipment such as inverters for railway vehicles, hybrid / electric vehicles, inverters for air conditioners, and personal computers. The performance improvement of power devices greatly improves the power efficiency of infrastructure systems and consumer equipment. Contribute.

  Improving power efficiency means that energy resources necessary for system operation can be reduced. In other words, carbon dioxide emissions can be reduced, that is, the environmental load can be reduced. For this reason, research and development for improving the performance of power devices has been actively conducted.

  In general, power devices are made of silicon (Si) as is the case with large-scale integrated circuits (LSIs). In a power conversion device using this Si power device, for example, an inverter, in order to reduce energy loss generated in the inverter, etc., the device structure and impurity concentration profile of the diode and the switch element are optimized to have a low on-resistance. (Ron), development for realizing characteristics such as high current density and high withstand voltage is being actively conducted.

  In recent years, compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), which have a larger band gap than silicon, have attracted attention as power device materials. Since these compound semiconductors have a large band gap, the breakdown voltage is about 10 times that of silicon.

  For this reason, the compound device can be made thinner than the Si device, and the resistance value (Ron) during conduction can be greatly reduced. As a result, the so-called conduction loss (Ron · i2) represented by the product of the resistance value (Ron) and the conduction current (i) can be reduced, which can greatly contribute to the improvement of power efficiency. Focusing on these features, development of diodes and switch elements using compound materials has been actively promoted.

  As an application of such a power device, a so-called inverter device (DC / AC conversion device) as shown in FIG. The inverter device is a device in which two switching elements and freewheeling diodes made of a power device are connected in series between a high voltage side (upper arm) power source and a low voltage side (lower arm) power source.

  By alternately turning on and off the switch elements of the upper and lower arms, the DC level at the front stage of the inverter device is converted to the AC level and supplied to a load circuit such as an AC insulation transformer or motor at the rear stage.

  The loss generated in the inverter at this time is, as described above, conduction loss or recovery loss due to the on-resistance (Ron) of the switch element or diode, or switching operation, that is, the switch element is switched from on to off or from off to on. In the transition period (period in which a potential difference is generated between the drain and the source), the switch loss is mainly caused by the drain-source current flowing. As an element expected to be applied to such a switch element, there is a SiC MOSFET (hereinafter referred to as SiCMOS).

  SiCMOS has almost the same element structure as that of an existing Si MOSFET, and its driving method is the same as that of the Si MOSFET. In other words, since the existing gate drive circuit for the Si element can be used, it is easy to use.

  Furthermore, since the on-resistance is lower than that of the Si element, there is an advantage that the loss accompanying the inverter operation can be reduced. However, as shown in Non-Patent Documents 1 to 3, SiCMOS has been reported to have a problem that the threshold voltage fluctuates when continuously energized.

  For example, when a positive bias is applied to the gate for a long time, the threshold value shifts by δVtp to the positive side (Positive Bias Temperature Instability), and when a negative bias is applied to the gate for a long time, the threshold value shifts by δVtn to the negative side (Negative Bias Temperature Instability). When the threshold value is shifted in this way, the following new problem may occur.

  In other words, since the threshold value is shifted to the negative side, there is a risk that a short-circuit current loss due to a false spot occurs in the inverter device.

  This false spot occurs when, for example, the upper arm changes from OFF to ON while the lower arm is OFF. In this case, when the drain voltage VDSD of the lower arm suddenly increases, a charge / discharge current flows through the gate-drain capacitance of the switch element of the lower arm.

  As a result, the gate-source voltage VGSD of the lower arm switch element rises from the voltage level in the off state. When the voltage level exceeds the threshold value of the switch element, the switch element of the lower arm that is originally turned off is erroneously turned on.

  As described above, the false point arc is a phenomenon in which the wrinkle switch that is originally turned off is erroneously turned on. A false point can occur even when a Si MOSFET is used as the lower arm switching element. However, when the SiCMOS is used in particular, the threshold becomes negative as the negative voltage is continuously applied to the gate during the off period. Since it shifts to, it becomes easier to occur.

  Further, since the shift amount of the threshold value becomes larger as the negative voltage application time becomes longer, the false spot is more likely to occur as the negative voltage application time becomes longer.

  When this error occurs, the lower arm switch element is turned on, so that the high voltage power supply on the upper arm side and the low voltage power supply on the lower arm side are short-circuited, and a large short-circuit current flows between the power supplies.

  This short-circuit current causes an increase in the loss of the inverter device, and in some cases, the switch element may generate heat and break down. In addition, there is a possibility that the shift amount of the threshold value does not shift uniformly among a plurality of chips. May concentrate and the element may generate heat and be destroyed.

  As described above, SiCMOS not only has the advantage of diverting the peripheral circuit of the Si element with a low on-resistance, but also the threshold value fluctuates, resulting in an increase in loss due to the occurrence of false spots and destruction of elements due to current concentration. There is a risk.

  As a means for solving such a problem, there is a so-called switched capacitor system as disclosed in Patent Documents 2 and 3. However, in the methods of Patent Document 2 and Patent Document 3, a negative voltage is continuously applied to the gate while the switch element is off.

  Therefore, as described above, when SiCMOS is used as the switch element, the threshold shift amount increases in a direction in which it is more easily turned on. As a result, a false spot occurs in the lower arm at the moment when the upper arm is turned on while the lower arm is off, or in some cases, an error occurs in the lower arm due to minute noise even after the upper arm is turned on. There is a risk of ignorance.

  Further, in the switched capacitor system such as Patent Document 2 and Patent Document 3, the negative voltage of the gate of the switch element is held by a floating node between the gate node and one end of the capacitor.

  Therefore, it may be difficult to maintain a stable negative voltage for a desired period due to noise, leakage current, or the like. For example, in Patent Document 2 and Patent Document 3, a diode is connected to the floating node. However, a leakage current may be generated through the diode.

  Furthermore, in the switched capacitor method, it is necessary to generate a desired negative voltage level by optimally designing the capacitance value in consideration of the gate capacitance of the switch element. There is a risk of becoming difficult.

  That is, when SiCMOS is used as the switching element, it is necessary to consider the threshold shift amount and the variation of the shift amount between chips as described above, and thus it cannot be said that the optimization of the capacitance value is easy.

  Further, for example, when the switch element itself is changed to another one, it is necessary to redesign the switched capacitor in accordance with it, which may increase the development period.

  The present invention has been made in view of the above, and in a power conversion device including a power semiconductor device and a semiconductor drive circuit that drives the power semiconductor device, it is possible to prevent false spot and improve reliability. It is to provide a technology that can be used.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a typical drive circuit includes a first switch element, a second switch element, a third switch element, and a fourth switch element. The first switch element has a source connected to the first voltage and a drain connected to a signal output node that outputs a drive signal for controlling on / off of the switching circuit.

  The second switch element has a source connected to the second voltage and a drain connected to the signal output node. The third switch element has a drain connected to the signal output node. The fourth switch element has a drain connected to the source of the third switch element, and a source connected to the third voltage.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) A false spot in the power converter can be prevented.

  (2) It is possible to improve the reliability of the power conversion device and a system configured using the power conversion device.

It is explanatory drawing which shows an example of a structure in the principal part of the power converter device by Embodiment 1. FIG. It is explanatory drawing which shows an example of a structure of the gate drive circuit provided in the power converter device of FIG. It is explanatory drawing which paid its attention to the gate drive circuit and switching element of the power converter device of FIG. It is a wave form diagram which shows an example of the operation | movement of FIG. FIG. 2 is an explanatory diagram illustrating an example of a configuration in the gate driver control circuit of FIG. 1. FIG. 10 is an explanatory diagram illustrating an example of a configuration in a gate drive circuit according to a second embodiment. FIG. 10 is an explanatory diagram illustrating an example of a configuration in a gate drive circuit according to a third embodiment. It is the schematic which shows an example of a structure in the power converter device by Embodiment 4. FIG. It is explanatory drawing which shows the structural example of the Schottky barrier diode used as a free-wheeling diode of FIG. It is explanatory drawing which shows the cross section of the schematic structural example of the switch element used for the power converter device of FIG. FIG. 10 is an explanatory diagram showing an example of a configuration in a three-phase motor system according to a fifth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape of the component is substantially the case unless it is clearly specified and the case where it is clearly not apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

  In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. Absent.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

(Embodiment 1)
<Configuration example of main parts of power converter>
FIG. 1 is an explanatory diagram illustrating an example of a configuration of a main part of the power conversion device PT according to the first embodiment.

  The power conversion device PT has, for example, a half bridge circuit configuration. The half bridge circuit is used as a part of a power supply device such as a DC-DC conversion circuit, for example. Also, it can be extended to full bridge circuits, three-phase inverter circuits, etc. and used as part of power supply devices such as DC-AC conversion circuits, and as part of motor control devices, etc. used.

  As shown in FIG. 1, the power conversion device PT includes gate driver control circuits GDCTL1, GDCTL2, a switching element SW1 on the upper arm side, a switching element SW2 on the lower arm side, and freewheeling diodes DI1, corresponding to the switching elements SW1, SW2, respectively. DI2 and gate drive circuits GD1 and GD2 are included. The switch element SW1 and the switch element SW2 are switching circuits.

  The switch element SW1 that is the second transistor switch and the switch element SW2 that is the first transistor switch are configured by, for example, an n-channel SiC MOSFET (SiCMOS). The power supply voltage VCC is supplied to the drain of the switch element SW1, and the drain of the switch element SW2 is connected to the source of the switch element SW1. The ground power supply voltage VSS is supplied to the source of the switch element SW2. A connection portion between the source of the switch element SW1 and the drain of the switch element SW2 is a voltage output node.

  The power supply voltage VCC is about 1500 V, for example, and the ground power supply voltage VSS is about 0 V, for example. The free-wheeling diodes DI1 and DI2 are connected between the source and drain of the switch elements SW1 and SW2, with the source side serving as an anode and the drain side serving as a cathode, respectively.

  The gate driver control circuit GDCTL1 outputs an upper arm driver control signal HO1 based on the upper arm control signal HIN. The gate driver control circuit GDCTL2 outputs a lower arm driver control signal LO1 based on the lower arm control signal LIN. The upper arm control signal HIN and the lower arm control signal LIN are generated by, for example, a microcomputer.

  The gate driver control circuits GDCTL1 and GDCTL2 have, for example, a voltage level conversion function, a timing adjustment function, a noise removal function, and various protection functions for the upper arm control signal HIN and the lower arm control signal LIN.

  The gate drive circuit GD1, which is the second drive circuit, generates a gate drive signal for driving the gate of the switch element SW1 based on the upper arm driver control signal HO1. The gate drive circuit GD2, which is the first drive circuit, generates a gate drive signal for driving the gate of the switch element SW2 based on the lower arm driver control signal LO1.

  Although not particularly limited, for example, the gate driver control circuits GDCTL1 and GDCTL2 and the gate drive circuits GD1 and GD2 are formed as one semiconductor chip as a semiconductor drive circuit. Further, for example, the switch elements SW1 and SW2 are formed of different semiconductor chips. In FIG. 1, as an example, a load circuit (load inductor) LD is connected to a connection portion between the switch elements SW1 and SW2, and the form and connection location of the load circuit are appropriately changed according to the application.

<Configuration example of gate drive circuit>
FIG. 2 is an explanatory diagram showing an example of the configuration of the gate drive circuit GD2 provided in the power conversion device PT of FIG. Although FIG. 2 shows a configuration example of the gate drive circuit GD2, the gate drive circuit GD1 has the same configuration as the gate drive circuit GD2.

  As shown in the figure, the gate drive circuit GD2 includes transistors T1 to T4. The transistor T1 as the first switch element and the transistor T3 as the third switch element are N-channel power MOSFETs. The transistor T2 that is the second switch element and the transistor T4 that is the fourth switch element are formed of P-channel power MOSFETs. These transistors T1 to T4 have built-in diodes D1 to D4, respectively.

  The built-in diode D1 is connected between the source and drain of the transistor T1 with the drain side as a cathode and the source side as an anode. The built-in diode D2 is connected between the source and drain of the transistor T2, with the source side serving as a cathode and the drain side serving as an anode.

  The built-in diode D3 is connected between the source and drain of the transistor T3 with the drain side as a cathode and the source side as an anode. The built-in diode D4 is connected between the source and drain of the transistor T4 with the source side as a cathode and the drain side as an anode.

  A power supply voltage VDD as a second voltage is supplied to the source of the transistor T2, and the drain of the transistor T1 and the drain of the transistor T3 are connected to the drain of the transistor T2.

  A connection node of the transistors T1 to T3 is a signal output node VOUT of the gate drive circuit GD2. A signal output from the signal output node VOUT becomes a gate drive signal for driving the gate of the switch element SW2.

  A power supply voltage VEE1 serving as a first voltage is supplied to the source of the transistor T1. The drain of the transistor T4 is connected to the source of the transistor T3, and the power supply voltage VEE2 that is the third voltage is supplied to the source of the transistor T4.

  The upper arm driver control signal HO1 is input to the gates of the transistors T1 to T4. The transistors T1 to T4 generate a gate drive signal based on the upper arm driver control signal HO1.

  The power supply voltage VEE2 or the power supply voltage VKK is input to the gate of the transistor T1 as the upper arm driver control signal HO1. The power supply voltage VDD or the power supply voltage VPP is input to the gate of the transistor T2 as the upper arm driver control signal HO1.

  The power supply voltage VSS or the power supply voltage VEE2 is input to the gate of the transistor T3 as the upper arm driver control signal HO1. The power supply voltage VEE2 or the power supply voltage VKK is input to the gate of the transistor T4 as the upper arm driver control signal HO1. The lower arm driver control signal LO1 input to the transistors T1 to T4 is output from the gate driver control circuit GDCTL2.

  Here, the power supply voltage VDD is about + 15V, for example, and the power supply voltage VPP is about + 10V, for example. The power supply voltage VSS is about 0V, and the power supply voltage VEE1 is a negative voltage of about −15V. The power supply voltage VEE2 is a negative voltage of about −5V, and the power supply voltage VKK is a negative voltage of about −10V.

  Further, the power supply voltage VDD, the power supply voltage VPP, the power supply voltage VEE1, the power supply voltage VEE2, and the power supply voltage VKK are generated by a power generation / output unit VSPY shown in FIG.

  Based on the lower arm driver control signal LO1, the gate drive circuit GD2 outputs any one of the power supply voltage VDD of about 15V, the power supply voltage VEE1 of about −15V, or the power supply voltage VEE2 of about −5V as a gate drive signal. .

<Operation example of gate drive circuit>
Next, the operation of the gate drive circuit GD2 will be described.

  First, when outputting the power supply voltage VDD as a gate drive signal, the transistor T2 is turned on, and the other transistors T1, T3, and T4 are turned off. In this case, the voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T1 is the power supply voltage VEE1. The voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T2 is the power supply voltage VPP.

  The voltage level of the lower arm driver control signal LO1 input to the gates of the transistors T3 and T4 is the power supply voltage VEE2. When the transistor T2 is turned on, the power supply voltage VDD is output from the signal output node VOUT of the gate drive circuit GD2 as a gate drive signal. At this time, the voltage level of the cathode of the built-in diode D1 is about the power supply voltage VDD, and the voltage level of the anode is about the power supply voltage VEE1.

  The voltage level of the cathode of the built-in diode D3 is about the power supply voltage VDD, and the voltage level of the anode is about the power supply voltage VEE2. In either case, since the voltage level on the cathode side is higher than that on the anode side, a short circuit between the power supplies (VDD-VEE1, VEE2) is prevented via the built-in diodes D1, D3.

  Subsequently, when the power supply voltage VEE1 is output as the gate drive signal, the transistor T1 is turned on and the other transistors T2, T3, and T4 are turned off. In this case, the voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T1 is the power supply voltage VKK.

  The voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T2 is the power supply voltage VDD. The voltage level of the lower arm driver control signal LO1 input to the gates of the transistors T3 and T4 is the power supply voltage VEE2.

  When the transistor T1 is turned on, the power supply voltage VEE1 is output from the signal output node VOUT of the gate drive circuit GD2 as a gate drive signal. At this time, the voltage level of the cathode of the built-in diode D2 is about the power supply voltage VDD, and the voltage level of the anode is about the power supply voltage VEE1.

  The voltage level of the anode of the built-in diode D4 is the power supply voltage VEE1, and the voltage level of the cathode is the power supply voltage VEE2. For this reason, in any case, the voltage level on the cathode side becomes higher than that on the anode side, so that a power supply short circuit (VEE1-VDD, VEE2) is prevented via the built-in diodes D2, D4.

  When the power supply voltage VEE2 is output as the gate drive signal, the transistors T3 and T4 are turned on, and the transistors T1 and T2 are turned off. In this case, the voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T1 is the power supply voltage VEE1, and the voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T2 is The voltage is VDD.

  The voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T3 is the power supply voltage VSS, and the voltage level of the lower arm driver control signal LO1 input to the gate of the transistor T4 is the power supply voltage. VKK.

  Thus, when the transistors T3 and T4 are turned on, the power supply voltage VEE2 is output from the signal output node VOUT of the gate drive circuit GD1 as a gate drive signal.

  At this time, the voltage level of the cathode of the built-in diode D1 is about the power supply voltage VEE2, and the voltage level of the anode is about the power supply voltage VEE1. The voltage level of the cathode of the built-in diode D2 is about the power supply voltage VDD, and the voltage level of the anode is about the power supply voltage VEE2. Therefore, in either case, the voltage level on the cathode side is higher than that on the anode side, so that a power supply short circuit (VEE2-VDD, VEE1) is prevented via the built-in diodes D1 and D2.

  As described above, the gate drive circuit GD2 can output signals of three different voltage levels of the power supply voltage VDD, the power supply voltage VEE1, or the power supply voltage VEE2 as gate drive signals while preventing the occurrence of a short circuit between the power supplies. .

<Drive operation of switch element>
Next, an example of driving the switch elements SW1 and SW2 using the gate drive circuits GD1 and GD2 in FIG. 2 will be described.

  FIG. 3 is an explanatory diagram focusing on the gate drive circuits GD1 and GD2 and the switch elements SW1 and SW2 of the power conversion device PT of FIG. FIG. 4 is a waveform diagram showing an example of the operation of FIG. In the example of FIG. 4, a waveform is shown when the lower arm side switch element SW <b> 2 is in the off state, and the upper arm side switch element SW <b> 1 is changed from the off state to the on state and then changed to the off state again. Has been.

  In FIG. 4, from the upper side to the lower side, waveforms of the voltage VGSU, the voltage VDSU, the voltage VDSD, and the voltage VGSD are shown, respectively. The voltage VGSU is a gate-source voltage of the switch element SW1. The voltage VDSU is a drain-source voltage of the switch element SW1. The voltage VDSD is a drain-source voltage of the switch element SW2. The voltage VGSD is a gate-source voltage of the switch element SW2.

  In the driving method according to the first embodiment, immediately before the switch element SW1 is turned on, the voltage VGSD of the switch element SW2 is changed from the level of the power supply voltage VDD to the level of the negative potential VEE1. Then, after the switching operation of the switch element SW1 is completed, the voltage VGSD is changed from the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2.

  In the off period of the switch element SW2, the voltage VGSD is set to the level of the power supply voltage VEE2 during the period excluding the switching period of the switch element SW1.

  More specifically, first, the voltage VGSU that is the gate-source voltage of the switch element SW1 on the upper arm side is changed from -5V that is the voltage level of the power supply voltage VEE2 to about + 15V that is the voltage level of the power supply voltage VDD, for example. Transition to.

  As a result, the voltage VDSU, which is the drain-source voltage of the switch element SW1, decreases to about the on voltage (˜1V) of the switch element SW1.

  Therefore, the voltage VDSD that is the drain-source voltage of the switch element SW2 on the lower arm side rises from about 0V to about 1500V. At this time, a charge / discharge current flows through the parasitic capacitance Cgd between the gate and the drain of the switch element SW2, and the current flows into the gate of the switch element SW2. As a result, the voltage VGSD, which is the gate-source voltage of the switch element SW2, rises transiently.

  Here, when the driving methods of Patent Document 2 and Patent Document 3 described above are used, a negative potential is dynamically and continuously applied between the gate and the source during the OFF period of the switch element SW2. In this case, in addition to the negative potential being unstable, the threshold voltage of the switch element SW2 is shifted in a time-sequential direction so as to be more easily turned on. For this reason, the switch element SW2 is liable to cause a false spot even at the moment when the switch element SW1 is turned on or thereafter, and as a result, a through current from the upper arm to the lower arm may be generated.

  On the other hand, in the gate drive circuits GD1 and GD2 shown in FIG. 2, the voltage VGSD of the switch element SW2 is changed to the level of the power supply voltage VEE1 immediately before the switch element SW1 is turned on.

  Thus, for example, even when a large current is coupled to the gate of the switch element SW2 at the moment when the switch element SW1 is turned on, an increase in the gate potential can be sufficiently suppressed.

  Further, after the switching operation of the switch element SW1 is completed, the voltage VGSD, which is the gate-source voltage of the switch element SW2, is changed from the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2. The time during which the level of the power supply voltage VEE1 is applied can be shortened. As a result, the threshold voltage shift amount described above can be minimized.

  As a result, it is difficult for the switch element SW2 to have a false spot and a through current from the upper arm toward the lower arm can be prevented.

  As a result, it is possible to realize a low-loss power conversion device that takes advantage of the low on-resistance of SiCMOS, and to improve its reliability.

  On the other hand, when the switch element SW1 transitions from on to off, the voltage VDSD that is the drain-source voltage of the switch element SW2 drops from about 1500V to about 0V. The voltage VGSD, which is a gate-source voltage of the switch element SW2, is also lowered by being dragged by the fall of the voltage VDSD.

  As the voltage VGSD falls, so-called gate noise occurs. If a high electric field is applied to the gate insulating film of the switch element SW2 due to the generation of gate noise, the reliability of the switch element SW2 may be greatly impaired. For this reason, it is desirable that voltage application due to gate noise be as small as possible.

  As described above, after the switching operation of the switch element SW1 is completed, the voltage VGSD is changed from the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2. Even if the switch element SW1 transitions from on to off and gate noise occurs, the voltage VGSD drops to some extent from the voltage level of the power supply voltage VEE2, but is lower than the voltage level of the power supply voltage VEE1. Can be prevented.

  As a result, even when gate noise occurs, the high electric field applied to the gate insulating film of the switch element SW2 can be made lower than the withstand voltage level of the gate insulating film, and the reliability of the switch element SW2 can be improved. it can.

  On the other hand, when the power supply voltage VEE1 is continuously applied to the voltage VGSD even after the switching operation of the switch element SW1 is completed, when the gate noise occurs, the voltage VGSD of the switch element SW2 becomes higher than the power supply voltage VEE1. There is a possibility that the voltage level becomes low, and there is a possibility that a high electric field higher than the withstand voltage is applied to the gate insulating film of the switch element SW2. As a result, the reliability of the switch element SW2 may be impaired.

<Configuration example of gate driver control circuit>
Next, the gate driver control circuit GDCTL1 will be described.

  FIG. 5 is an explanatory diagram showing an example of the configuration of the gate driver control circuit GDCTL1 of FIG. Although FIG. 5 shows the gate driver control circuit GDCTL1, the gate driver control circuit GDCTL2 has the same configuration.

  As shown in FIG. 5, the gate driver control circuit GDCTL1 includes a logic part LG and a power generation / output part VSPY.

  The logic unit LG generates the output control signal OCT based on the upper arm control signal HIN and the lower arm control signal LIN output from the microcomputer. The power supply generation output unit VSPY outputs a gate drive signal to be output to the gate drive circuit GD1 based on the output control signal OCT generated by the logic unit LG.

  The power generation / output unit VSPY includes DC / DC converters DC1 and DC2 and signal selectors SEL1 to SEL3. The DC / DC converter DC1 generates a power supply voltage VPP of about 10V from a power supply voltage VDD of about 15V with reference to the source potential COM (= VSS) of the switch element SW1. The DC / DC converter DC2 generates a power supply voltage VEE2 of about −5V from a power supply voltage VEE1 of about −15V with reference to the source potential COM of the switch element SW1.

  A power supply voltage VDD of about 15 V and a power supply voltage VPP generated by the DC / DC converter DC1 are input to two input sections of the signal selector SEL1. The output control signal OCT generated by the logic unit LG is input to the control terminal of the signal selector SEL1.

  The signal selector SEL1 selects and outputs either the power supply voltage VDD or the power supply voltage VPP based on the output control signal OCT. The signal output from the signal selector SEL1 is input to the gate of the transistor T2 of the gate drive circuit GD1 as a gate drive signal. When the transistor T2 is turned on, the signal selector SEL1 outputs the power supply voltage VPP, and when the transistor T2 is turned off, the signal selector SEL1 outputs the power supply voltage VDD.

  The source potential COM (VSS) and the power supply voltage VEE2 generated by the DC / DC converter DC2 are input to the two input portions of the signal selector SEL2, respectively. The output control signal OCT output from the logic unit LG is input to the control terminal of the signal selector SEL2.

  The signal selector SEL2 selects and outputs either the source potential COM or the power supply voltage VEE2 based on the output control signal OCT. The signal output from the signal selector SEL2 is input to the gate of the transistor T3 of the gate drive circuit GD1 as a gate drive signal. The signal selector SEL2 outputs the source potential COM when turning on the transistor T3, and outputs the power supply voltage VEE2 when turning off the transistor T3.

  The power supply voltage VEE1 and the power supply voltage VKK generated by the DC / DC converter DC3 are input to the two input portions of the signal selector SEL3. The output control signal OCT output from the logic unit LG is input to the control terminal of the signal selector SEL3.

  The signal selector SEL3 selects and outputs either the power supply voltage VKK or the power supply voltage VEE1 based on the output control signal OCT. The signal output from the signal selector SEL3 is input to the gate of the transistor T1 of the gate drive circuit GD1 as a gate drive signal.

  The signal selector SEL3 outputs a power supply voltage VKK when turning on the transistor T1, and outputs a power supply voltage VEE1 when turning off the transistor T1.

  The power supply voltage VEE2 generated by the DC / DC converter DC2 and the power supply voltage VKK generated by the DC / DC converter DC3 are input to the two input portions of the signal selector SEL4, respectively. The output control signal OCT output from the logic unit LG is input to the control terminal of the signal selector SEL4.

  The signal selector SEL4 selects and outputs either the power supply voltage VKK or the power supply voltage VEE2 based on the output control signal OCT. The signal output from the signal selector SEL4 is input to the gate of the transistor T4 of the gate drive circuit GD1 as a gate drive signal.

  The signal selector SEL4 outputs the power supply voltage VKK when turning on the transistor T4, and outputs the power supply voltage VEE2 when turning off the transistor T4.

  Thus, the operation of the transistor T1 of the gate drive circuit GD1 is controlled by the gate drive signal of either the power supply voltage VEE1 or the power supply voltage VKK output from the power supply generation output unit VSPY.

  The operation of the transistor T2 is controlled by a gate drive signal of either the power supply voltage VDD or the power supply voltage VPP output from the power generation / output unit VSPY. Similarly, the operation of the transistor T3 is controlled by the gate drive signal of either the source potential COM or the power supply voltage VEE2 output from the power generation / output unit VSPY, and the transistor T4 is the power supply voltage output from the power generation / output unit VSPY. The operation is controlled by a gate drive signal of either VEE2 or power supply voltage VKK.

  As described above, typically, in the power conversion device PT provided with the power semiconductor device and the semiconductor drive circuit that drives the power semiconductor device, it is possible to prevent false points and improve reliability.

(Embodiment 2)
<Configuration Example of Gate Drive Circuit (Modification 1)>
In the second embodiment, a modified example of the gate drive circuits GD1 and GD2 provided in the power conversion device PT shown in FIG. 1 of the first embodiment will be described.

  FIG. 6 is an explanatory diagram showing an example of the configuration of the gate drive circuit GD2 according to the second embodiment. Although FIG. 6 shows an example of the configuration of the gate drive circuit GD2, the gate drive circuit GD1 has the same configuration as the gate drive circuit GD2.

  The gate drive circuit GD2 shown in FIG. 6 has a configuration in which a resistor R is newly provided in the same configuration as that of FIG. 2 of the first embodiment including the transistors T1 to T4 having the built-in diodes D1 to D4. . The resistor R is connected between the drain of the transistor T4 and the power supply voltage VEE2.

  For example, when the transistors T3 and T4 are off, the connection portion between the source of the transistor T3 and the drain of the transistor T4 may become a floating node and the potential may not be determined. If it becomes a floating node, a malfunction may occur in the transistors T3 and T4. The resistor R is provided to prevent this floating node. The resistance value of the resistor R is preferably a high resistance that does not flow current, such as about 1 MΩ. As a result, the current consumption of the gate drive circuit GD2 can be suppressed.

  As described above, typically, in the power conversion device PT provided with the power semiconductor device and the semiconductor drive circuit that drives the power semiconductor device, it is possible to prevent false points and improve reliability.

(Embodiment 3)
<Configuration Example of Gate Drive Circuit (Modification 2)>
In the third embodiment, a configuration of the gate drive circuit GD2 that can reduce the influence of noise or the like generated when the switch element is turned on / off will be described.

  FIG. 7 is an explanatory diagram showing an example of the configuration of the gate drive circuit GD2 according to the third embodiment. 7 also shows a configuration example of the gate drive circuit GD2, the gate drive circuit GD1 has the same configuration as the gate drive circuit GD2.

  The gate drive circuit GD2 shown in FIG. 7 has a configuration in which resistance selectors RSL1 and RSL2 are newly provided in the same configuration as that of FIG. 2 of the first embodiment including the transistors T1 to T4 having the built-in diodes D1 to D4. It has become.

  The resistance selector RSL1 serving as the first resistance switching unit includes a transistor T5 and resistors R1 and R2. The transistor T5 is composed of a P-channel type power MOSFET. The power source voltage VDD is connected to one connection portion of the source of the transistor T5 and the resistor R2. One connection portion of the resistor R1 is connected to the drain of the transistor T5. The source of the transistor T2 is connected to the other connection portion of the resistors R1 and R2.

  The resistance selector RSL2 serving as the second resistance switching unit includes a transistor T6 and resistors R3 and R4. The transistor T6 is an N-channel power MOSFET. One connection portion of the resistors R3 and R4 is connected to the source of the transistor T1.

  The drain of the transistor T6 is connected to the other connection portion of the resistor R3. A power supply voltage VEE1 is connected to the source of the transistor T6 and the other connection portion of the resistor R4.

  Further, a control signal output from the logic unit LG shown in FIG. 5 of the first embodiment is input to the gates of the transistors T5 and T6. The transistors T5 and T6 are turned on or off based on a control signal input to the gate.

  Here, the resistance value is set so that the combined resistance value of the resistor R1 and the resistor R2 that are the first resistance values is smaller than the resistance value R2 that is the second resistance value. Similarly, the resistance value is set so that the combined resistance value of the resistor R3 and the resistor R4 that are the third resistance value is smaller than the resistance value R4 that is the fourth resistance value.

  Next, the operation of the resistance selector RSL1 will be described.

  When the switch element SW2 is turned on, the resistance selector RSL1 operates so that the power supply voltage VDD is input to the gate of the switch element SW2 via the combined resistance of the resistance R1 and the resistance R2. That is, a control signal for turning on the transistor T5 is output from the logic unit LG.

  As described above, when the switch SW2 starts to be turned on, a high-speed operation of the switch element can be realized by performing control for rapidly raising the gate voltage. However, when the gate voltage rises rapidly, ringing or surge may occur in the input gate voltage, which may cause malfunction of the switch element.

  Therefore, in the resistor selector SL1, when the gate voltage approaches the voltage level of the power supply voltage VDD to some extent, the transistor T5 is turned off and the power supply voltage VDD is supplied only through the resistor R2 having a resistance value higher than the combined resistance value. To control. That is, a control signal for turning off the transistor T5 is output from the logic unit LG. As a result, the rising waveform of the gate voltage becomes smooth, and the occurrence of ringing or surge can be suppressed.

  As described above, the reliability of the switching operation can be improved while realizing the high-speed operation of the switch element.

  The same applies when the switch element SW2 is turned off. The transistor T6 of the resistor selector RSL2 is first turned on, and then the resistor T6 is turned off. As a result, similarly to the case of the resistor selector RSL1, it is possible to perform control for rapidly lowering the gate voltage of the switch SW2. When the gate voltage approaches the voltage level of the power supply voltage VEE1 to some extent, the transistor T6 is turned off, the falling waveform of the gate voltage becomes gentle, and the occurrence of ringing or surge can be suppressed. As described above, the high-speed operation of the switch element and the reliability of the switching operation can be improved. Note that after the ringing of the switch SW2 is suppressed, the transistors T5 and T6 may be controlled to be turned on again. By doing in this way, switching time can be shortened and switching loss can be reduced.

  Subsequently, an operation when a sense signal described later in Embodiment 4 is output from the switch element will be described.

  The sense signal is a signal that is output when the switch element is short-circuited and an overcurrent flows through the switch element by simultaneously turning on the switch element on the upper arm side and the switch element on the lower arm side. .

  When a sense signal is input to the logic unit LG shown in FIG. 5, the logic unit LG performs control to turn off the switch element. As a result, the short-circuit current is interrupted to prevent the switch element from being destroyed.

  When the sense signal is input, the logic unit LG immediately turns off the transistor T6. As a result, the switch element is turned off by the gate voltage supplied via the resistor R4 having a resistance value larger than the combined resistance value.

  As described above, by smoothing the fall of the gate voltage, it is possible to suppress the occurrence of ringing, surge, and the like, and to prevent malfunction of the switch element. When the fall of the gate voltage is abrupt, the switch element off time can be shortened, but the switch element is turned on by ringing or surge generated in the gate voltage, and the switch element is destroyed. There is a risk of being invited. As described above, the reliability of the switching operation of the switch element can be improved even when the switch element is abnormal.

  In FIG. 7, although either the combined resistance value of the resistor R1 and the resistor R2 or the resistance value of the resistor R2 is switched by the transistor T5, the configuration of the resistor selector RSL1 (, RSL2) is two different resistors. The configuration is not limited to this as long as the value can be selected.

  For example, a configuration may be adopted in which a switching transistor is provided in each of the resistor R1 and the resistor R2 having a resistance value larger than that of the resistor R1, and switching is performed by individually operating the transistors.

(Embodiment 4)
<Application example of power converter>
FIG. 8 is a schematic diagram showing an example of the configuration of the power conversion device PT according to the fourth embodiment of the present invention. For example, the power conversion device PT shown in FIG. 8 is obtained by applying the method of the first embodiment to a so-called three-phase inverter device.

  In FIG. 8, switch elements SW1u, SW1v, SW1w, SW2u, SW2v, and SW2w, which are transistor switches, are switch elements using n-channel type SiCMOS. In addition, a transistor switch unit is configured by the switch elements SW1u, SW1v, SW1w, SW2u, SW2v, and SW2w.

  Between the source and drain of the switch elements SW1u, SW1v, SW1w, SW2u, SW2v, SW2w, free-wheeling diodes D1u, D1v, D1w, D2u, D2v, D2w are connected, respectively. These free-wheeling diodes D1u, D1v, D1w, D2u, D2v, and D2w are, for example, Schottky barrier diodes.

  The switch elements SW1u, SW1v, SW1w are respectively arranged on the upper arm side, and the switch elements SW2u, SW2v, SW2w are respectively arranged on the lower arm side. The switch elements SW1u and SW2u are for the U phase, the switch elements SW1v and SW2v are for the V phase, and the switch elements SW1w and SW2w are for the W phase.

  Each switch element SW1u, SW1v, SW1w, SW2u, SW2v, and SW2w is provided with a sense circuit (not shown) that detects an overcurrent, an overvoltage, or a temperature of the switch element.

  The gate drive circuits GD1u, GD1v, GD1w, GD2u, GD2v, and GD2w are a gate drive circuit and a gate driver control circuit as shown in FIG. To do.

  The sense circuit outputs a sense signal SE when it detects an overcurrent flowing through each switch element, an overvoltage applied to the switch element, or an overheat of the switch element. The sense signal SE output from the sense circuit is input to the logic unit LG of the gate driver control circuit. The logic unit LG performs control to stop the operation of all the switch elements when the sense signal SE is input.

  A power supply voltage VCC and a capacitor C0 are connected between one end (drain node) of the upper arm side switch element and one end (source node) of the lower arm side switch element. Each gate drive circuit appropriately drives on / off of the corresponding switch element, thereby generating three-phase (U-phase, V-phase, W-phase) AC signals having different phases from the DC power supply voltage VCC. To do. The load circuit LD is composed of, for example, a motor, and is appropriately controlled by these three-phase (U-phase, V-phase, W-phase) AC signals.

  Here, the detailed operation during the hard switching operation of each of the U phase, the V phase, and the W phase is the same as in FIG. In the three-phase inverter device, the switch element on the lower arm side (for example, switch element SW2u) is turned off, and the switch element on the upper arm side (for example, switch element SW1u) is turned on.

  At this time, the drain potential (VD) on the lower arm side rises to near the level of the power supply voltage VCC. When the drain potential of the lower arm side switch element (for example, the switch element SW2u) rapidly increases, the gate potential of the lower arm side switch element (for example, the switch element SW2u) transiently increases as described with reference to FIG.

  However, since the gate drive circuit according to the present embodiment temporarily applies the power supply voltage VEE1 of about −15 V to the gate of the lower arm side switch element (for example, the switch element SW2u), it prevents erroneous firing in the switch element. can do. Further, after preventing the false firing operation, the gate potential of each switch element is changed to the level of the power supply voltage VEE2 of about −5V.

  As a result, even if the three-phase inverter device is energized for a long time, the shift amount of the threshold voltage of each switch element can be sufficiently suppressed, and a highly reliable and stable power conversion operation can be realized. Is possible.

  In particular, such a three-phase inverter device often operates with a large amount of electric power, and is liable to cause false firing, and damage caused by erroneous firing can be large. Therefore, by using the system of the present embodiment, it is possible to realize a low loss even when operating at a high power by SiCMOS, and to prevent erroneous firing, so that a beneficial effect is obtained.

<Configuration example of Schottky barrier diode>
FIG. 9 is an explanatory diagram showing a configuration example of a Schottky barrier diode used as the free wheeling diode of FIG. FIG. 9A is a plan view of the main part of the semiconductor chip CH on which the Schottky barrier diode is formed, and FIG. 9B is a cross-sectional view of the main part along the line AA ′ of FIG. 9A. It is. 9A and 9B show a Schottky barrier diode in which the termination region has a JTE (Junction Termination Extension) structure.

  On the main surface (the upper surface in FIG. 9B) of the n + type substrate SUBd, an n− type drift layer DFTd is formed. On the upper surface of the drift layer DFTd, a p + type guard ring region PGR, a p type JTE region PJ, and an n + type channel stop region so as to surround the active region ACTd formed in the center of the semiconductor chip in plan view. CSd is formed. Further, an insulating film IL3 is formed on the drift layer DFTd.

  A surface electrode IL1 connected to the guard ring region PGR and the like and a channel stop electrode IL2 connected to the channel stop region CSd are formed through the opening formed in the insulating film IL3. A back surface electrode CA connected to the substrate SUBd is formed on the back surface (the lower surface in FIG. 9B) opposite to the main surface of the substrate SUBd. Although illustration is omitted, a passivation film, a resin film, and the like are formed above the surface electrode IL1 and the channel stop electrode IL2.

  A so-called JBS (Junction Barrier Schottky) Schottky barrier diode in which, for example, p + type regions and n− type regions are alternately arranged is formed in the active region ACTd located at the center of the semiconductor chip CH.

  In the guard ring region PGR arranged near the peripheral edge of the semiconductor chip, the electric field tends to concentrate on the edge portion. However, the JTE region PJ is formed adjacent to the edge portion to thereby concentrate the electric field in the edge portion. Can be relaxed.

  As a result, the breakdown voltage of the power device can be increased. That is, a more reliable power conversion system can be realized by using in combination with the switch element of FIG.

<Configuration example of switch element>
FIG. 10 is an explanatory diagram showing a cross section of a schematic configuration example of a switch element used in the power conversion device PT of FIG. FIG. 10A is an explanatory diagram showing a cross section showing a configuration example of each element transistor in the active element region, and FIG. 10B shows a cross section of a configuration example different from FIG. 10A. It is explanatory drawing.

  First, FIG. 10B shows one vertical SiCMOS having a trench structure. The source layer N + serving as an n + type region connected to the source electrode SPm is connected to the drift layer DFT via a channel formed in the base layer P serving as a p type region. The DFT is, for example, an n− type region and plays a role of ensuring a breakdown voltage. The substrate SUB is, for example, an n + type region, and the drain electrode DRm is connected to the substrate SUB.

  In the case of such a trench structure, since there is no so-called JFET region which is an n-type semiconductor region sandwiched between base layers P, there is an advantage that the on-resistance of the entire SiCMOS can be lowered.

  In other words, by using in combination with the semiconductor driving circuit (gate driving circuit and gate driver control circuit) according to the present embodiment, a power conversion system with less loss can be realized.

  On the other hand, FIG. 10A shows a so-called DMOS (Double Diffusion Metal Oxide Semiconductor) type SiCMOS that does not have a trench structure. In this case, there is an advantage that the element structure is simple and the manufacturing cost can be reduced as compared with the trench structure type SiCMOS.

  As described above, it is possible to provide the power conversion device PT with low power loss and high reliability.

(Embodiment 5)
<Configuration example of three-phase motor system>
In the fifth embodiment, an example in which the power conversion device PT shown in FIG. 8 of the fourth embodiment is applied to a three-phase motor system that drives a motor or the like mounted on a railway vehicle or the like will be described.

  FIG. 11 is an explanatory diagram showing an example of a configuration in the three-phase motor system MS according to the fifth embodiment.

  Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG. The high-voltage AC voltage of the overhead line RT is, for example, about 25 kV or 15 kV. This high-voltage AC voltage is stepped down to an AC voltage of, for example, about 1.5 kV to 3.0 kV by the insulating main transformer MTR.

  The AC voltage stepped down to about 1.5 kV is forward converted to a DC voltage of about 1.5 kV by the AC / DC converter CON.

  Thereafter, the DC voltage is converted into an AC voltage by the DC / AC inverter INV via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor M3, thereby driving the three-phase motor M3.

  The configuration of the DC / AC inverter INV is the same as that in FIG. Further, the gate drive circuit of FIG. 2 can also be used for a gate drive circuit used in, for example, the AC / DC converter CON. In FIG. 11, reference sign WHL indicates a wheel.

  In this way, the above-described power conversion device PT shown in FIG. 8 can be applied to the DC / AC inverter INV constituting the three-phase motor system of the railway vehicle. As a result, the loss of the converter circuit portion and the inverter circuit portion can be reduced, and the number of heat radiation fins can be reduced. As a result, the volume of the three-phase motor system MS can be reduced.

  When the volume of the three-phase motor system MS is reduced, for example, the floor of the railway vehicle can be reduced by downsizing the underfloor parts including the three-phase motor system MS. Further, for example, by downsizing the underfloor parts, it is possible to secure a space where a battery BAT such as a lithium ion battery as shown in FIG.

  When the vehicle is not traveling, the electric power can be stored in the battery BAT without returning the electric power to the overhead line RT via the wheels WHL. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  That is, it goes without saying that various changes are possible as long as the objectives such as prevention of false spots, reduction of the threshold voltage shift amount during long-term energization operation, and reduction of power loss can be achieved.

  Each switch element is not limited to silicon carbide (SiC) but may be a compound device such as silicon (Si) or gallium nitride (GaN). Needless to say, when the compound material is used as a switching element of an inverter device or the like, the loss of the inverter device can be reduced by using it in combination with the semiconductor drive circuit of the embodiment.

  Needless to say, the power conversion device of the present embodiment can be applied to power systems for various purposes to obtain similar effects. Typical examples include an inverter device for an air conditioner, a DC / DC converter for a server power supply, a power conditioner for a solar power generation system, and an inverter device for a hybrid vehicle / electric vehicle.

  In addition, this invention is not limited to above-described embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.

  Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

PT power converter GDCTL1 gate driver control circuit GDCTL2 gate driver control circuit SW1 switch element SW2 switch element DI1 freewheel diode DI2 freewheel diode GD1 gate drive circuit GD2 gate drive circuits T1 to T4 transistors D1 to D4 built-in diode VSPY power supply generation output section LG logic Part DC1, DC2 DC / DC converter SEL1 Signal selector SEL2 Signal selector SEL3 Signal selector R Resistor RSL1, RSL2 Resistor selector RSL2
T5, T6 Transistors R1 to R4 Resistor SW1u Switch element SW1v Switch element SW1w Switch element SW2u Switch element SW2v Switch element SW2w Switch element D1u Freewheel diode D1v Freewheel diode D1w Freewheel diode GD1u Gate drive circuit GD1v Gate drive circuit GD1w Gate drive circuit GD2u Gate drive Circuit GD2v Gate drive circuit GD2w Gate drive circuit C0 Capacitor LD Load circuit CH Semiconductor chip SUBd Substrate DFTd Drift layer ACTd Active region PGR Guard ring region PJ JTE region CSd Channel stop region IL1 Surface electrode IL2 Channel stop electrode IL3 Insulating film CA Back electrode SPm Source electrode N Source layer P Base layer DFT Drift layer SUB Substrate DRm Drain Electrode MS three phase motor system RT overhead wire PG pantograph MTR main transformer CON AC / DC converter INV DC / AC inverter CL capacitor M3 three-phase motor WHL wheels BAT battery

Claims (15)

A drive circuit for controlling on / off of a switching circuit,
A first switch element having a source connected to a first voltage and a drain connected to a signal output node that outputs a drive signal for controlling on / off of the switching circuit;
A second switch element having a source connected to a second voltage and a drain connected to the signal output node;
A third switch element having a drain connected to the signal output node;
A fourth switch element having a drain connected to a source of the third switch element and a source connected to a third voltage;
A driving circuit. The drive circuit according to claim 1,
The second switch element and the fourth switch element are P-type MOS transistors, and the first switch element and the third switch element are N-type MOS transistors. The drive circuit according to claim 2, wherein
The drive circuit, wherein the first to fourth switch elements are power MOSFETs having a built-in diode. The drive circuit according to claim 1,
The drive circuit outputs the third voltage to the signal output node when the switching circuit is off, and applies the second voltage to the signal output node when the switching circuit transitions from off to on. And outputting the third voltage to the signal output node after outputting the first voltage to the signal output node when transitioning the switching circuit from on to off. The drive circuit according to claim 1,
The first voltage output from the first switch element and the third voltage output from the third switch element are negative potentials,
The drive circuit, wherein the third voltage is higher in potential than the first voltage. The drive circuit according to claim 1,
Further, one connection portion has a resistance connected to the connection node of the source of the third switch element and the drain of the fourth switch element, and the other connection portion connected to the third voltage. Drive circuit. A first transistor switch connected between a voltage output node from which a power supply voltage supplied to a load is output and a reference potential;
A second transistor switch connected between the power supply voltage and the voltage output node;
A first drive circuit for controlling on and off of the first transistor switch;
With
The first driving circuit includes:
A first switch element having a source connected to a first voltage and a drain connected to a signal output node that outputs a drive signal for controlling on / off of the first or second transistor switch;
A second switch element having a source connected to a second voltage and a drain connected to the signal output node;
A third switch element having a drain connected to the signal output node;
A fourth switch element having a drain connected to a source of the third switch element and a source connected to a third voltage;
A power converter. The power conversion device according to claim 7, wherein
The first driving circuit outputs the third voltage to the signal output node when the first transistor switch is off, and the first driving circuit switches the first transistor switch from off to on. When the first voltage is output to the signal output node, the third voltage is output to the signal output node when the first transistor switch is switched from on to off. A power converter that outputs to an output node. The power conversion device according to claim 7, wherein
And a second drive circuit for controlling on and off of the second transistor switch,
The second driving circuit outputs the third voltage to the signal output node when the second transistor switch is off, and the second driving circuit changes the second transistor switch from off to on. The second voltage is output to the signal output node, and the third voltage is output to the signal output node after the first voltage is output to the signal output node when the second transistor switch is switched from on to off. A power conversion device that outputs to an output node. The power conversion device according to claim 7, wherein
The first and second transistor switches are power converters configured using silicon carbide or gallium nitride. The power conversion device according to claim 7, wherein
The first and second transistor switches are:
MOSFET,
A free-wheeling diode connected between the source and drain of the MOSFET;
Each having a power conversion device. The power conversion device according to claim 7, wherein
Furthermore, the first drive circuit includes:
A first resistance switching control unit connected between the second voltage and a source of the second switch element;
A second resistance switching control unit connected between the first voltage and a source of the first switch element;
Have
The first resistance switching control unit selects either a first resistance value or a second resistance value higher than the first resistance value based on a control signal;
The second resistance switching control unit is a power conversion device that selects either a third resistance value or a fourth resistance value higher than the third resistance value based on a control signal. The power conversion device according to claim 12, wherein
The second resistance switching control unit selects the fourth resistance value when a sense signal for stopping the first transistor switch is generated. A transformer that steps down the AC voltage;
An AC / DC converter that converts the AC voltage stepped down by the transformer into a DC voltage;
A DC / AC inverter that converts the DC voltage converted by the AC / DC converter into a three-phase AC voltage;
A three-phase motor driven based on a three-phase AC voltage converted by the DC / AC inverter;
With
The DC / AC inverter is
A transistor switch unit that includes a plurality of transistor switches, and converts a DC voltage converted by the AC / DC converter into a three-phase AC voltage by a switching operation;
A plurality of drive circuits for controlling on and off of the transistor switch, and
With
The drive circuit is
A first switch element having a source connected to a first voltage and a drain connected to a signal output node that outputs a drive signal for controlling on / off of the transistor switch;
A second switch element having a source connected to a second voltage and a drain connected to the signal output node;
A third switch element having a drain connected to the signal output node;
A fourth switch element having a drain connected to a source of the third switch element and a source connected to a third voltage;
Having a motor system. The motor system according to claim 14, wherein
The three-phase motor is a motor system that is a motor mounted on a railway vehicle.