DE112014006834B4 - Control circuit, power converter and motor system - Google Patents

Abstract

Drive circuit that controls ON / OFF of a switching circuit comprising: a first switching element (T1) whose source is connected to a first voltage (VEE1) and whose drain is connected to a signal output node (VOUT) that outputs a drive signal that is ON / OFF of the switching circuit (SW1, SW2) controls; a second switching element (T2) whose source is connected to a second voltage (VDD) and whose drain is connected to the signal output node (VOUT); a third switching element (T3) whose drain connected to the signal output node (VOUT); and a fourth switching element (T4) whose drain is connected to the source of the third switching element (T3) and whose source is connected to a third voltage (VEE2), characterized in that a connection to a connection node of the source of the third switching element (T3) and is connected to the drain of the fourth switching element (T4) and the other connection has a resistor (R) which is to be connected to the third voltage (VEE2).

Description

Technical field

The present invention relates to a drive circuit, a power converter, and a motor system, and more particularly, to a technology that is effectively applicable to a power converter that includes a power semiconductor device using a silicon carbide material and a semiconductor drive circuit that drives the power semiconductor device, and the like.

State of the art

For example, Patent Literature 1 discloses a configuration of an insulated gate semiconductor element having a series circuit composed of a capacitor and a switch interposed between its gate and emitter to reduce a mirror voltage time of the semiconductor element and a dead time of a PWM inverter (Pulse Width Modulation Inverter) containing the semiconductor element.

In addition, Patent Literature 2 and Patent Literature 3 disclose methods for addressing a problem of so-called misfire. The misfire is a phenomenon in which when a lower branch switch is turned off and an upper branch switch is turned on, a gate voltage in the lower branch switch is thereby raised and this switch is erroneously turned on.

In particular, technology for connecting a so-called switched capacitor circuit to the gate of the lower branch switch and dynamically applying a negative voltage to the gate of the lower branch switch using the switched capacitor circuit is disclosed. They also describe non-patent literature 1 , Non-patent literature 2 and non-patent literature 3 that continuously energizing an SiC-MOSFET (silicon carbide metal oxide semiconductor field effect transistor) causes variations in its threshold voltage. Furthermore, Patent Literature 4 shows, with a method for controlling a gate drive circuit, how switches are turned on or off to change the level of an output voltage from a first voltage level to a second higher voltage level, and then, the level of the output voltage to one change third level between the first level and the second voltage level when a switching element is turned on. In Patent Literature 5, a gate drive circuit has a variable current carrying path that switches a current carrying path between a drive target device, a DC power source, and a reactor to operate in multiple operating modes including at least one holding mode, a preparation mode, and an execution mode. The variable current path includes a return path to cause a reactor current flowing through the inductor to flow back to the DC source when a gate voltage of the drive target device deviates from a preset allowable voltage range. A drive control part sets the operation mode of the variable current carrying path to the holding mode and holds the ON state or the OFF state of the drive target device, and also switches the operating mode in sequence of the preparation mode and the execution mode and realizes switching on or off of the moving target device. Patent Literature 6 relates to a gate driver circuit of an IGBT of a semiconductor switching device, and more particularly to a gate driver circuit that enables suppression of a surge during shutdown operation and a decrease in switching loss. In Patent Literature 7, a drive circuit for a voltage controlled semiconductor device is provided, which has an ON gate drive circuit for supplying an ON control signal to a control electrode of the semiconductor device, which executes a current switching OFF gate drive circuit, for supplying an OFF control signal to the Control electrode of the semiconductor device and further comprises a high voltage source, which may be connected to one of the ON-gate driver circuit and the OFF-gate driver circuit, for supplying a control current at a predetermined rate of current increase to the control electrode of the semiconductor device, and further a low voltage source for supplying one has sufficient control current to the control electrode to maintain the semiconductor device in a normal state, and further includes a switch for supplying an output of the high voltage current to the control electrode in a previous portion of an egg n or off period and for supplying an output signal of the low voltage source to the control electrode in a normally ON or a normally OFF state. In patent literature 8, a gate driver circuit for a voltage-controlled switching element in a converter is characterized by a detector device for measuring a physical quantity characteristic of a switching process of the switching element and for generating a corresponding control signal, and an actuating device for changing one or more parameters of the gate driver circuit influencing the switching process in accordance with the requirements of the control signal obtained when the switching element is switched on / off. This makes it possible, even without a snubber circuit, to cause interference or interference peaks To reduce switching, which could damage the switching element. In Patent Literature 9, a power conversion device provided with a power semiconductor device and a semiconductor driver circuit for driving the power semiconductor device can be prevented from misfiring, and an improvement in reliability can be achieved. The power conversion device is provided with a first switching element inserted between a power supply voltage and an output node, and is further provided with a second switching element inserted between a ground supply voltage and the output node and with a gate driver circuit for controlling the on / off switching of the second switching element. When the turn-off of the second switching element is controlled, the gate driver circuit drives a gate-source voltage with a level of 0 V, for example. However, when the first switching element is shifted from an OFF state to an ON state at a first time in a state in which the gate-source voltage is driven at the level of 0 V, for example, the gate driver circuit turns on during first period that crosses temporarily a level of a negative voltage as a gate-source voltage on via the first timing. Subject of DE 11 2007 002 270 T5 is the reduction of noise caused by overshoot or the like while reducing the turn-on power loss of the element and the blocking delay loss of the diode in a circuit of a power semiconductor element to which a low-delay current SiC diode is connected in parallel. For this purpose, the gate voltage or collector voltage of the power semiconductor switching element is detected and the gate drive voltage is changed in several stages on the basis of the detected value.

Citation List

• Patent Literature 1: Japanese Unexamined Patent JP 2000 - 333 441 A.
• Patent Literature 2: Japanese Unexamined Patent JP 2004 - 159 424 A
• Patent Literature 3: Japanese Unexamined Patent JP 2009 - 21 823 A.
• Patent Literature 4: JP 2009 - 50 118 A. ; Patent Literature 5: US 2006/0 186 933 A1 ; Patent literature 6: DE 697 28 715 T2 ; Patent literature 7: US 5,089,719 A ; Patent literature 8: DE 197 41 391 A1 ; Patent literature 9: US 2013/0 265 029 A1 ; Patent literature 10: DE 11 2007 002 270 T5

Non-patent literature

• Non-patent literature 1 : Mrinal K. Das, "Commercially Available Cree Silicon Carbide Power Devices: Historical Success of JBS Diodes and Future Switch Prospects", CS MANTECH Conference, 16.-19. May 2011, Palm Springs, California, USA
• Non-patent literature 2 : Xiao Shen and seven others, "Atomic-scale origins of bias-temperature instabilities in SiC-SiO2 structures", AP-PLIED PHYSICS LETTERS 98, 063507, 2011
• Non-patent literature 3 : Aivars J. Lelis and six others, "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements", IEEE Transactions on Electron Devices, Band 55 , No. 8, pages 1835-1840, August 2008

Summary of the invention

Technical problem

In a huge social trend of global environmental protection, an electronics industry that reduces environmental pollution is becoming increasingly important. Among other things, a power device is used as a power supply for a consumer good such. B. uses an inverter of a rail vehicle or a hybrid / electric vehicle, an inverter of an air conditioner and a personal computer, and thus an improvement in the performance of the power device will greatly contribute to improving the electricity efficiency of infrastructure systems and consumer products.

Improving electricity efficiency means saving the energy resources required to operate a system, or in other words reducing CO ₂ emissions or reducing environmental impact. Therefore, research and development for improving the performance of the power device are actively carried out.

In general, power devices are made of silicon (Si), such as. B. a highly integrated circuit (LSI). For a power converter such as B. an inverter using the SI power device to actively reduce the energy loss caused in the inverter, development is carried out to optimize the structure and profile of the impurity concentration of a diode and a switching element, and thereby such properties how to achieve a low ON resistance (Ron), high current density and high dielectric strength.

In addition, compound semiconductors such as As silicon carbide (SiC) and gallium nitride (GaN), which have a larger band gap than silicon, attract attention as a power device material. Because of their large bandgap, these compound semiconductors have a breakdown voltage which is approximately ten times higher than that of silicon.

Thus, when compared to the Si device, the connection device can have a thinner layer thickness and a much lower resistance value (Ron) when energized. This can reduce a so-called line loss (Ron * i2), which is represented by the resistance value (Ron) multiplied by a line current (i), and thereby contribute greatly to the improvement of electricity efficiency. By focusing on such a feature, diodes and switching elements using a connecting material are actively developed.

As an application of such a power device, a so-called inverter device (DC / AC converter device, AC / DC converter device) is as in FIG 6 shown by Patent Literature 1. The inverter device contains two groups of the switching element, which consist of a power device and a freewheeling diode, which are connected in series between a power supply on the high voltage side (upper branch) and a power supply on the low voltage side (lower branch).

By alternately switching on and off the switching elements on the upper and lower branches, the DC level on the stage upstream of the inverter device is converted into the AC level, which is a load circuit in the later stage such. B. an AC protective converter or a motor is supplied.

The loss that can be caused by the inverter mainly includes, as described above, a line loss due to the ON resistance (Ron) of the switching element or the diode, a recovery loss and a switching loss caused by a drain-source current that flows during a switching operation of a transition period of the switching element from the on to the off or the off to the on state (a period in which there is a potential difference between the drain and the source). One element that is expected to be applied to such a switching element would be an SiC-MOSFET (hereinafter SiCMOS).

The SiCMOS is a device structure substantially the same as that of the existing Si-MOSFET, and its driving method is also similar to that of the Si-MOSFET. In other words, it is possible to derive an existing gate drive circuit for an Si element that is easy to use.

There is another advantage to reducing the loss caused by the inverter operation due to the lower ON resistance compared to the Si element. However, as described in Non-Patent Literature 1 to 3, a problem is reported that the threshold voltage varies when it is continuously energized.

For example, when a positive bias is applied to the gate for a long time, a threshold shifts to the positive side by δVtp (positive bias-temperature instability), and when a negative bias is applied to the gate for a long time the threshold to a negative side around δVth (negative bias temperature instability). Moving the threshold in this way will create a new problem as described below.

That is, since the threshold shifts to the negative side, there is a risk that a short-circuit current loss is caused in the inverter device due to the misfire.

The misfire occurs, for example, when the upper branch changes from an OFF state to an ON state while the lower branch is in the OFF state. In this case, because a drain voltage VDSD in the upper branch suddenly increases, a charge / discharge current flows through the gate-drain capacitance in the switching element of the lower branch.

As a result, the gate-source voltage VGSD in the lower branch switching element rises from the voltage level of the OFF state. If the voltage level exceeds the switching element threshold, the switching element of the lower branch, which should normally be switched off, is incorrectly switched on.

As described above, misfire is a phenomenon in which a switch that should normally be turned off is incorrectly turned on. The misfire can occur in a case when the Si-MOSFET is used as the lower branch switching element and is even more likely to occur when the SiCMOS is used because the threshold shifts to the negative side when the negative voltage is during the OFF period is continuously applied to the gate.

In addition, the amount of the shift in the threshold value increases as the negative voltage application time increases, and therefore the misfire occurs more easily as the negative voltage application time increases.

When the misfire occurs, the lower branch switching element is turned on, the high voltage side power supply on the upper branch side and the low voltage side power supply on the lower branch side are short-circuited, and a large short-circuit current flows between the power supplies.

The short-circuit current increases the loss in the inverter device and can possibly damage the switching element through heat generation. The amount of threshold shift cannot shift evenly among multiple chips, in which case reflux currents converge on an element that has a large shift in the threshold (element with a reduced threshold), causing the element to self-heat and damage ,

As described above, the SiCMOS not only has the advantages of its low ON resistance and derivative of a peripheral circuit of the Si element, but also risks of increased loss due to the occurrence of misfire and damage to the element due to current reversal by varying the threshold.

One method of addressing such a problem is a so-called switched capacitor as disclosed in Patent Literature 2 and 3. However, with the method in Patent Literature 2 and 3, the negative voltage is continuously applied to the gate during the OFF period of the switching element.

Therefore, as described above, when the SiCMOS is used as the switching element, the amount of the shift in the threshold increases to make the element easier to turn on. As a result, the misfire in the lower branch can occur as soon as the upper branch is turned on while the lower branch is turned off, and the misfire can occur in the lower branch by a slight noise even after the upper branch is turned on.

In addition, with the switched capacitor disclosed in Patent Literature 2 and 3, the negative voltage in the gate of the switching element is held by a floating node between the gate node and one end of the capacitor.

Thus, it can sometimes be difficult to maintain a stable negative voltage for a desired period of time due to the noise and leakage current. For example, in Patent Literature 2 and 3, a diode is connected in the floating node, and the leakage current can be generated through the diode.

In addition, with the switched capacitor, the desired level of negative voltage must be generated by optimally designing the capacitance value and the like considering the gate capacitance of the switching element, but it may be difficult to optimize the capacitance value.

When the SiCMOS is used as the switching element, it is not easy to optimize the capacitance value because the amount of displacement of the switching element and the variation of the amount of displacement among chips must be considered as described above.

In addition, for example, when the switching element itself is changed to another, a constant of the switched capacitor and the like must be constructed accordingly, which can extend the development time.

The present invention has been made in view of the above-described circumstances, and aims to provide a technology capable of preventing misfire and its reliability in the power converter equipped with the power semiconductor device and the semiconductor drive circuit that drives the device is to improve.

These and other objects and novel features of the present invention will become apparent from the description and accompanying drawings of the invention.

the solution of the problem

Representative embodiments of the present invention disclosed herein are briefly described below.

A representative control circuit contains a first switching element, a second switching element, a third switching element and a fourth switching element. In the first switching element, its source is connected to a first voltage, and its drain is connected to a signal output node that outputs a drive signal that controls ON and OFF of the switching circuit.

In the second switching circuit, its source is connected to a second voltage and its drain is connected to the signal output node. In the third switching circuit, its drain is connected to the signal output node. In the fourth switching circuit, its drain is connected to the source of the third switching circuit, and its source is connected to a third voltage.

Advantageous effects of the invention

• (1) Verhindern der Falschzündung in dem Leistungswandler.
• (2) Verbessern der Zuverlässigkeit des Leistungswandlers und eines Systems, das durch den Leistungswandler gebildet ist.

Effects of the representative embodiments of the disclosed invention are briefly described below.

• (1) Prevent misfire in the power converter.
• (2) Improve the reliability of the power converter and a system formed by the power converter.

list of figures

• 1 12 is an explanatory diagram showing an exemplary configuration of a main part of a power converter according to a first embodiment.
• 2 FIG. 11 is an explanatory diagram showing an exemplary configuration of a gate drive circuit used for the in FIG 1 power converter shown is provided.
• 3 FIG. 12 is an explanatory diagram related to the gate drive circuit and a switching element of FIG 1 shown power converter focused.
• 4 FIG. 14 is a waveform diagram illustrating exemplary operation in FIG 3 shows.
• 5 FIG. 12 is an explanatory diagram showing an exemplary configuration of a device shown in FIG 1 gate driver control circuit shown.
• 6 10 is an explanatory diagram showing an exemplary configuration of a gate driver control circuit according to a second embodiment.
• 7 12 is an explanatory diagram showing an exemplary configuration of a gate driver control circuit according to a third embodiment.
• 8th 14 is a schematic diagram showing an exemplary configuration of a power converter according to a fourth embodiment.
• 9 FIG. 11 is an explanatory diagram showing an exemplary configuration of a Schottky diode used as one in FIG 8th shown freewheeling diode is used.
• 10 FIG. 12 is an explanatory cross-sectional diagram showing a schematic exemplary configuration of a switching element included in the in FIG 8th shown power converter is used.
• 11 10 is an explanatory diagram showing an exemplary configuration of a three-phase motor system according to a fifth embodiment.

Description of embodiments

In the following embodiments, explanations are made separately in several sections or embodiments as necessary for simplification, and unless otherwise specified, the explanations are not irrelevant to each other, but may be a variation, a detailed description, a supplementary explanation of a part of the or entire others.

It is to be noted that when reference is made to a set of elements (including a number, a numerical value, a size, a range, and the like) in the following embodiments, it is not limited to the specified set, but any one smaller or larger quantities may be permitted, unless otherwise specified or unless they are not obviously limited in principle to the specific quantity.

In addition, a component (including an element level and the like) is of course not necessarily essential in the following embodiments unless otherwise specified unless it is obviously essential in principle, or the like.

Similarly, in the following embodiments, when reference is made to a shape, positional relationship, and the like of the components, it should include those that are substantially close to or similar to the shape and the like, unless otherwise specified or unless obviously obvious in principle the case is. This also applies to the numerical values and the range.

Throughout the drawings for describing the embodiments, like components have the same reference numerals as a general rule, and description thereof is not repeated. A top view may even be hatched for clarity.

Although the embodiments use a MOSFET (metal oxide semiconductor field effect transistor) (referred to as a MOS transistor) as an example of one MISFET (metal insulator semiconductor field effect transistor) is used, a non-oxidized layer is not excluded as a gate insulating layer.

Hereinafter, the embodiments will be described in detail based on the drawings.

First embodiment

<Configuration example of a main part of the power converter>

1 FIG. 12 is an explanatory diagram showing an exemplary configuration of a main part of a power converter PT according to a first embodiment.

The power converter PT is configured, for example, as a half-bridge circuit. The half-bridge circuit is used as part of a power supply device such as a DC / DC conversion circuit (DC / DC conversion circuit). It is also expanded to a full-bridge circuit and a three-phase inverter circuit to be used as part of the power supply device such as. B. a DC / AC conversion circuit or part of a motor control device for various applications to be used if necessary.

The power converter PT contains gate driver control circuits GDCTL1 . GDCTL2 , a switching element SW1 on the side of the upper branch, a switching element SW2 on the side of the lower branch, free-wheeling diodes DI1 . DI2 , each of the switching elements SW1 . SW2 correspond, and gate drive circuits GD1 . GD2 , The switching element SW1 and the switching element SW2 are switching circuits.

Each from the switching element SW1 , which is a second transistor switch, and the switching element SW2 , which is a first transistor switch, is formed, for example, by an n-channel SiC-MOSFET (n-channel SiCMOS). A power supply voltage VCC becomes a drain of the switching element SW1 fed, and a drain of the switching element SW2 is with the source of the switching element SW1 connected. A ground power supply voltage VSS becomes the source of the switching element SW2 fed. The connection between the source of the switching element SW1 and the drain of the switching element SW2 is a voltage output node.

The power supply voltage VCC may be approximately 1500 V, and the ground power supply voltage VSS may be approximately 0 V, for example. The freewheeling diodes DI1 . DI2 are between the sources and drains of the switching elements SW1 . SW2 connected using its source side as an anode and its drain side as a cathode.

The gate driver control circuit GDCTL1 outputs a drive control signal HO1 of the upper branch based on a control signal HIN of the upper branch. The gate driver control circuit GDCTL2 outputs a lower branch driver control signal LO1 based on a lower branch control signal LIN. The control signal HIN of the upper branch and the control signal LIN of the lower branch are generated, for example, by a microcomputer.

The gate driver control circuits GDCTL1 . GDCTL2 are responsible, for example, for a voltage conversion function, a time adjustment function, a noise removal function and various protective functions for the upper control signal HIN and the control signal LIN of the lower branch.

The gate drive circuit GD1 , which is a second drive circuit, generates a gate drive signal that is a gate of the switching element SW1 drives, based on the drive control signal HO1 of the upper branch. The gate drive circuit GD2 , which is a first drive circuit, generates a gate drive signal that is a gate of the switching element SW2 drives, based on the driver control signal LO1 of the lower branch.

Although not specifically limited, the gate driver control circuits can GDCTL1 . GDCTL2 and the gate drive circuits GD1 . GD2 be made from a single semiconductor chip as a semiconductor drive circuit. In addition, the switching elements SW1 . SW2 be made from another semiconductor chip. In 1 is as an example a load circuit (load inductor) LD with the connection between the switching elements SW1 . SW2 connected. The arrangement and connection point of this load circuit can vary depending on the application.

<Configuration example of the gate drive circuit>

2 FIG. 12 is an explanatory diagram showing an exemplary configuration of the gate drive circuit GD2 that for the in 1 shown power converter PT is provided. It should be noted that, though 2 the configuration example of the gate drive circuit GD2 shows the gate drive circuit GD1 the same configuration as the gate drive circuit GD2 having.

The gate drive circuit GD2 is through the transistors T1 to T4 formed as in 2 is shown. Everyone from the transistor T1 , which is the first switching element, and the third transistor T3 , which is the third switching element, consists of an N-channel power MOSFET. Everyone from the transistor T2 , which is the second switching element, and the transistor T4 , which is the fourth switching element, consists of a P-channel power MOSFET. These transistors T1 to T4 each contain integrated diodes D1 to D4 ,

The integrated diode D1 is between the source and drain of transistor T1 connected using its drain side as the cathode and its source side as the anode. The integrated diode D2 is between the source and drain of transistor T2 connected using its drain side as the cathode and its source side as the anode.

The integrated diode D3 is between the source and drain of transistor T3 connected using its drain side as the cathode and its source side as the anode. The integrated diode D4 is between the source and drain of transistor T4 connected using its drain side as the cathode and its source side as the anode.

The power supply voltage VDD, which is the second voltage, becomes the source of the transistor T2 fed, and the drain of the transistor T1 and the drain of the transistor T3 are each connected to the drain of the transistor T2 connected.

The connection node of the transistors T1 to T3 is the signal output node VOUT the gate drive circuit GD2 , A signal coming from the signal output node VOUT is output is the gate drive signal which is the gate of the switching element SW2 controls.

The power supply voltage VEE1 , which is a first voltage, becomes the source of the transistor T1 fed. With the source of transistor T3 is the drain of the transistor T4 connected, and the source of the transistor T4 a power supply voltage VE-E2, which is a third voltage, is supplied.

The driver control signal HO1 the top branch goes into each gate of the transistors T1 to T4 entered. The transistors T1 to T4 generate the gate drive signal based on the driver control signal HO1 of the top branch.

The power supply voltage VEE2 or a power supply voltage VKK gets into the gate of the transistor T1 as the driver control signal HO1 of the top branch entered. The power supply voltage VDD or a power supply voltage VPP is applied to the gate of the transistor T2 is input as the upper branch driver control signal HO1.

The power supply voltage VSS or the power supply voltage VEE2 gets into the gate of the transistor T3 as the driver control signal HO1 of the top branch entered. The power supply voltage VEE2 or the power supply voltage VKK gets into the gate of the transistor T4 as the driver control signal HO1 of the top branch entered. The driver control signal LO1 of the lower branch that is in each of these transistors T1 to T4 is entered, the gate driver control circuit GDCTL2 output.

The power supply voltage VDD can be approximately + 15 V, and the power supply voltage VPP can be approximately + 10 V, for example. The power supply voltage VSS can be approximately 0 V and the power supply voltage VEE1 can be a negative voltage of approximately -15 V. The power supply voltage VEE2 can be a negative voltage of about -5 V, and the power supply voltage VKK can be a negative voltage of approximately -10 V.

The power supply voltage VDD , the power supply voltage VPP, the power supply voltage VEE1 , the power supply voltage VEE2 and the power supply voltage VKK are generated by a power generation output unit VSPY generated that in 5 is shown and described later.

The gate drive circuit GD2 outputs one from the power supply voltage VDD of about 15 V, the power supply voltage VEE1 of approximately -15 V and the power supply voltage VEE2 of about -5 V as the gate drive signal based on the lower arm drive control signal LO1.

<Operation example of the gate drive circuit>

An operation of the gate drive circuit GD2 will be described below.

To the power supply voltage VDD to output as the gate drive signal is the transistor T2 turned on and the other transistors T1 . T3 . T4 are switched off. In this case, the voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T1 is entered, the power supply voltage VEE1 his. The voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T2 is entered, the power supply voltage is VPP.

The voltage levels of the driver control signals LO1 of the lower branch that in the gates of the transistors T3 . T4 are entered, both are the power supply voltage VEE2 , By turning on the transistor T2 becomes the power supply voltage VDD from the signal output node VOUT the gate drive circuit GD2 output as the gate drive signal. At this time, the voltage level of the cathode is the integrated diode D1 essentially equal to the power supply voltage VDD , and the anode voltage level is substantially equal to the power supply voltage VEE1 ,

The voltage level of the cathode of the integrated diode D3 is essentially the same as the power supply voltage VDD , and the anode voltage level is substantially equal to the power supply voltage VEE2 , In any case, the voltage level on the cathode side is higher than that on the anode side, which means a short circuit between the power supplies (VDD- VEE1 . VEE2 ) through the integrated diodes D1 . D3 can prevent.

To the power supply voltage VEE1 to output as the gate drive signal is the transistor T1 turned on and the other transistors T2 . T3 . T4 are switched off. In this case, the voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T1 is entered, the power supply voltage VKK.

The voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T2 is entered is the power supply voltage VDD , The voltage levels of the driver control signals LO1 of the lower branch that in the gates of the transistors T3 . T4 are entered, both are the power supply voltage VEE2 ,

By turning on the transistor T1 becomes the power supply voltage VEE1 from the signal output node VOUT the gate drive circuit GD2 output as the gate drive signal. At this time, the voltage level of the cathode is the integrated diode D2 essentially equal to the power supply voltage VEE1 ,

The voltage level of the anode of the integrated diode D4 is the power supply voltage VEE1 , and the cathode voltage level is the power supply voltage VEE2 , Thus, in any case, the voltage level on the cathode side is higher than that on the anode side, causing a power short circuit ( VEE1 -V DD, VEE2 ) through the integrated diodes D2 . D4 can prevent.

To the power supply voltage VEE2 to output as the gate drive signal are the transistors T3 and T4 turned on, and the transistors T1 and T2 are switched off. In this case, the voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T1 is entered, the power supply voltage VEE1 , and the voltage level of the driver control signal LO1 of the lower branch that is in the transistor T2 is entered is the power supply voltage VDD ,

The voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T3 is entered is the power supply voltage VSS , and the voltage level of the driver control signal LO1 of the lower branch, which is in the gate of the transistor T4 is entered is the power supply voltage VKK ,

Thus, by turning on the transistors T3 and T4 the power supply voltage VEE2 from the signal output node VOUT of the gate drive circuit GD1 output as the gate drive signal.

At this time, the voltage level of the cathode is the integrated diode D1 essentially equal to the power supply voltage VEE2 , and the anode voltage level is substantially equal to the power supply voltage VEE1 , The voltage level of the cathode of the integrated diode D2 is essentially the same as the power supply voltage VDD , and the anode voltage level is substantially equal to the power supply voltage VEE2 , Thus, in any case, the voltage level on the cathode side is higher than that on the anode side, causing a power short circuit ( VEE2 - VDD . VEE1 ) through the integrated diodes D1 and D2 can prevent.

As described above, the gate driver circuit GD2 the signal as the gate drive signal at the three different voltage levels of the power supply voltage VDD , the power supply voltage VEE1 or the power supply voltage VEE2 output while preventing the occurrence of a short circuit between these power supplies.

<Driving operation of the switching element>

An example for controlling the switching elements SW1 . SW2 using the gate driver circuits GD1 . GD2 in 2 is now described.

3 Fig. 11 is an explanatory diagram referring to the gate drive circuits GD1 . GD2 and the switching elements SW1 . SW2 of in 1 shown power converter PT focused. 4 FIG. 14 is a waveform diagram illustrating an exemplary operation in FIG 3 shows. This in 4 The example shown shows waveforms in a case where when the switching element SW2 is switched off on the side of the lower branch, the switching element SW1 on the upper branch side is shifted from the OFF state to the ON state and then shifted back to the OFF state.

4 shows the waveforms of a voltage from top to bottom VGSU , a tension VDSU , a tension VDSD and a tension VGSD , The voltage VGSU is the gate-source voltage of the switching element SW1 , The voltage VDSU is the drain-source voltage of the switching element SW1 , The voltage VDSD is the drain-source voltage of the switching element SW2 , The voltage VGSD is the gate-source voltage of the switching element SW2 ,

According to the driving method in the first embodiment, immediately before the switching element SW1 the voltage is switched on VGSD of the switching element SW2 from the level of the power supply voltage VDD to the level of the negative potential VEE1 postponed. The process is characterized by the tension VGSD from the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2 is shifted after the switching operation of the switching element SW1 is finished.

During the OFF period of the switching element SW2 that the switching period of the switching element SW1 excludes, the voltage VGSD is at the level of the power supply voltage VEE2 set.

To describe this in more detail, the voltage VGSU is the gate-source voltage of the switching element SW1 on the side of the upper branch, from -5 V, which is the voltage level of the power supply voltage VEE2 are, for example, about + 15 V, which is the voltage level of the power supply voltage VDD are moved.

That can be the tension VDSU that the drain-source voltage of the switching element SW1 is about the ON voltage of the switching element SW1 Reduce (<1 V).

So the tension increases VDSD that the drain-source voltage of the switching element SW2 on the lower branch side, from about 0 V to about 1500 V. At this time, a charge / discharge current flows through a parasitic capacitance Cgd between the gate and the drain of the switching element SW2 , and this current flows into the gate of the switching element SW2 , As a result, the voltage VGSD, which is the gate-source voltage of the switching element, rises SW2 is temporarily on.

If the driving methods disclosed in Patent Literature 2 and 3 described above are now used, the negative potential is dynamic and continuous between the gate and the source continuously through the OUT -Time span of the switching element SW2 created. In this case, in addition to the fact that the negative potential is unstable, the threshold voltage of the switching element shifts SW2 in one direction to be switched on more easily in chronological order. Thus, a moment when the switching element SW1 is turned on or even afterwards, the misfire in the switching element SW2 are more likely to occur, resulting in a risk of causing a through current from the upper branch to the lower branch.

In contrast, in the in 2 gate drive circuits shown GD1 . GD2 the voltage VGSD of the switching element SW2 immediately before the switching element SW1 turns on to the level of the power supply voltage VEE1 postponed.

In this way, for example, at the moment when the switching element SW1 turns on even when there is a substantial high current at the gate of the switching element SW2 is coupled, the rise in the gate potential can be sufficiently suppressed.

After the switching operation of the switching element SW1 is finished, the tension VGSD that the gate-source voltage of the switching element SW2 is from the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2 shifted, which can reduce the time in which the voltage with the level of the power supply voltage VEE1 to the gate of the switching element SW2 is created. This can minimize the above-mentioned amount of shift in the threshold voltage.

As a result, it becomes likely that the misfire in the switching element SW2 occurs, and thereby the through current from the upper branch to the lower branch is prevented.

This makes it possible to achieve a low-loss power converter by taking advantage of the low ON-resistance property of SiCMOS and to improve reliability.

In contrast, when the switching element falls SW1 is shifted from ON to OFF, the voltage VDSD that the drain-source voltage of the switching element SW2 from approximately 1500 V to approximately 0 V. Drawn by the drop in voltage VDSD the tension drops VGSD that the gate-source voltage of the switching element SW2 is, too.

The drop in tension VGSD causes so-called gate noise. If a high electric field is applied to a gate insulating layer in the switching element SW2 applied by the occurrence of gate noise, the reliability of the switching element SW2 to be severely impaired. Therefore, it is desirable to minimize the voltage applied by the gate noise.

As described above and after the switching operation of the switching element SW1 is completed, the voltage VGSD becomes the level of the power supply voltage VEE1 to the level of the power supply voltage VEE2 changed. Even if the switching element SW1 of ON to OUT shifts to cause the gate noise, the voltage drops VGSD from the voltage level of the power supply voltage VEE2 to a certain extent, but is prevented from becoming lower than the voltage level of the power supply voltage VEE1 ,

Thus, even when gate noise occurs, the high electric field applied to the gate insulating layer of the switching element SW2 is applied to the withstand voltage level of the gate insulating layer or below, and thereby the reliability of the switching element SW2 improved.

In contrast, in a case when the power supply voltage VEE1 continuously on the tension VGSD is applied even after the switching operation of the switching element SW1 finished, the tension VGSD of the switching element SW2 be at a voltage level that is lower than the power supply voltage VEE1 when the gate noise occurs, causing the high electric field, which is higher than the withstand voltage, to the gate insulating layer of the switching element SW2 is created. That can reduce the reliability of the switching element SW2 affect.

<Configuration example of the gate driver control circuit>

Now the gate driver control circuit GDCTL1 described below.

5 FIG. 12 is an explanatory diagram showing an exemplary configuration of the in FIG 1 gate driver control circuit shown GDCTL1 shows. Even though 5 the gate driver control circuit GDCTL1 shows, it is noted that the gate driver control circuit GDCTL2 has the same configuration.

The gate driver control circuit GDCTL1 is from a logic unit LG and a power generation output unit VSPY constructed as in 5 is shown.

The logic unit LG generates an output control signal OCT based on the control signal HIN of the upper branch and the control signal LIN of the lower branch, which are output from the above-mentioned microcomputer. The power generation output unit VSPY outputs the gate drive signal to the gate drive circuit GD1 based on that by the logic unit LG generated output control signal OCT out.

The power generation output unit VSPY contains DC / DC converters DC1 . DC2 and signal selectors SEL1 to SEL3 , The DC / DC converter DC1 generates the power supply voltage VPP of approximately 10 V from the power supply voltage VDD of approximately 15 V based on a source potential COM (= VSS) of the switching element SW1 , The DC / DC converter DC2 generates the power supply voltage VEE2 of approximately -5 V from the power supply voltage VEE1 of approximately -15V based on the source potential COM of the switching element SW1 ,

The input in two input units in a signal selector SEL1 included are the power supply voltage VDD of approximately 15 V and the power supply voltage, respectively VDD by the DC / DC converter DC1 is produced. The input to a control connection of the signal selector SEL1 is the output control signal OCT by the logic unit LG is produced.

The signal selector SEL1 selects one from the power supply voltage VDD and the power supply voltage VPP based on the output control signal OCT and outputs them. The signal coming from the signal selector SEL1 is output is in the gate of the transistor T2 the gate drive circuit GD 1 entered as the gate drive signal. The signal selector SEL1 gives the power supply voltage VPP out to the transistor T2 turn on, and gives the power supply voltage VDD out to the transistor T2 off.

The input to two input units in a signal selector SEL2 are the source potential COM VSS or the power supply voltage VEE2 by the DC / DC converter DC2 is produced. The input to a control connection of the signal selector SEL2 is the output control signal OCT that from logic unit LG is issued.

The signal selector SEL2 selects one from the source potential COM and the power supply voltage VEE2 based on the output control signal OCT and gives it out. The signal coming from the signal selector SEL2 is output is in the gate of the transistor T3 the gate drive circuit GD1 entered. The signal selector SEL2 outputs the source potential COM to the transistor T3 turn on, and gives the power supply voltage VEE2 out to the transistor T3 off.

The input to two input units in a signal selector SEL3 are the power supply voltage VEE1 or the power supply voltage VKK generated by the DC / DC converter DC3. The input to a control connection of the signal selector SEL3 is the output control signal OCT that from logic unit LG is issued.

The signal selector SEL3 selects one of the power supply voltage VKK and the power supply voltage VEE1 outputs and outputs based on the output control signal OCT. The signal coming from the signal selector SEL3 is output is in the gate of the transistor T1 the gate drive circuit GD1 entered as the gate drive signal.

The signal selector SEL3 outputs the power supply voltage VKK to the transistor T1 turn on, and gives the power supply voltage VEE1 out to the transistor T1 off.

The input to two input units in a signal selector SEL4 are the power supply voltage VEE by the DC / DC converter DC2 is generated, or the power supply voltage VKK by the DC / DC converter DC3 is produced. The input to a control connection of the signal selector SEL4 is the output control signal OCT that from logic unit LG is issued.

The signal selector SEL4 selects one from the power supply voltage VKK and the power supply voltage VEE2 based on the output control signal OCT and outputs them. The signal coming from the signal selector SEL4 is output is in the gate of the transistor T4 the gate drive circuit GD1 entered as the gate drive signal.

The signal selector SEL4 outputs the power supply voltage VKK to the transistor T4 turn on, and gives the power supply voltage VEE2 out to the transistor T4 off.

As described above, the transistor T1 the gate drive circuit GD1 by the gate drive signal with either the power supply voltage VEE1 or the power supply voltage VKK coming from the power generation output unit VSPY is output, controlled by operation.

The transistor T2 is by the gate drive signal with either the power supply voltage VDD or the power supply voltage VPP coming from the power generation output unit VSPY is output, controlled by operation. The transistor becomes similar T3 by the gate drive signal with either the source potential COM or the power supply voltage VEE2 coming from the power generation output unit VSPY is output, operationally controlled, and the transistor T4 is by the gate drive signal with either the power supply voltage VEE2 or the power supply voltage VKK coming from the power generation output unit VSPY is output, controlled by operation.

As described above, the representative power converter can PT that includes the power semiconductor device and the semiconductor drive circuit that drives the power semiconductor device prevent misfire and improve reliability.

Second embodiment

<Configuration example of the gate drive circuit (first variation>

In a second embodiment is a variation of the gate drive circuits GD1 . GD2 that for the in 1 shown power converter PT of the first embodiment are described.

6 FIG. 12 is an explanatory diagram showing an exemplary configuration of the gate drive circuit GD2 according to the second embodiment. It should be noted that, though 6 the configuration example of the gate drive circuit GD2 shows the gate drive circuit GD1 the same configuration as the gate drive circuit GD2 having.

In the 6 shown gate drive circuit GD2 has the same configuration as in 2 is shown, the first embodiment, which consists of the transistors T1 to T4 consists of the integrated diodes D1 to D4 have, except that they also resistance R contains. The resistance R is between the drain of the transistor T4 and the power supply voltage VEE2 connected.

For example, if the transistors T3 and T4 are turned off, the connection between the source of the transistor T3 and the drain of the transistor T4 become a floating knot where the potential is not stable. Becoming a floating node involves a risk of malfunction in the transistors T3 . T4 and the like. The resistance R is provided to prevent such a floating knot. A resistance value of the resistance R is preferably a high resistance value such as e.g. B. about 1 MΩ, at which no current is allowed. That can be a consumption current of the gate drive circuit GD2 suppress.

As described above, the representative power converter can PT that includes the power semiconductor device and the semiconductor drive circuit that drives the power semiconductor device prevent misfire and further improve reliability.

Third embodiment

<Configuration example of the gate drive circuit (second variation>

In a third embodiment is a configuration of the gate drive circuit GD2 that can reduce an effect of noise and the like caused when a switching element is turned on / off.

7 FIG. 10 is an explanatory diagram showing an exemplary configuration of a gate drive circuit GD2 according to the third embodiment. It should be noted that, though 7 also the configuration example of the gate drive circuit GD2 shows the gate drive circuit GD1 the same configuration as the gate drive circuit GD2 having.

In the 7 shown gate drive circuit GD2 has the same configuration of the first embodiment as that in FIG 2 is shown that from the transistors T1 to T4 consists of the integrated diodes D1 to D4 except that they also have resistance value selectors RSL1 . RSL2 contains.

The resistance value selector RSL1 serving as a first resistance switching unit includes a transistor T5 and the resistors R1 . R2 , The transistor T5 consists of a P-channel power MOSFET. The power supply voltage VDD is with the source of the transistor T5 and a connection of the resistor R2 connected. The drain of the transistor T5 is with a connection of the resistor R1 connected. The source of the transistor T2 is with the other connection of the resistors R1 . R2 connected.

The resistance value selector RSL2 , which serves as a second resistance switching unit, includes a transistor T6 and the resistors R3 . R4 , The transistor T6 consists of an N-channel power MOSFET. A connection of the resistors R3 . R4 is with the source of transistor T1 connected.

The drain of the transistor T6 is with the other terminal of the resistor R3 connected. The power supply voltage VE-E1 is at the source of the transistor T6 and the other terminal of the resistor R4 connected.

The input to the gates of the transistors T5 . T6 is the control signal resulting from the in 5 logic unit shown LG of the first embodiment. The transistors T5 . T6 turn on or off based on the control signal input to their gates.

Now the respective resistance values are set so that the combined resistance value of the resistor R1 and resistance R2 that is used as a first resistance value is smaller than that of the resistor R2 which is used as a second resistance value. Similarly, respective resistance values are set so that the combined resistance value of the resistor R3 and resistance R4 which is used as a third resistance value is smaller than that of the resistor R4 which is used as a fourth resistance value.

An operation of the resistance selector RSL1 is described below.

If the switching element SW2 turns on, the resistance value selector works RSL1 so that the power supply voltage VDD in the gate of the switching element SW2 about the combined resistance value of the resistor R1 and resistance R2 is entered. That is, the logic unit LG outputs the control signal that the transistor T5 turns.

Thus, if the switch SW2 begins to turn on, by controlling the gate voltage to rise rapidly, a high-speed operation of the switching element can be achieved. However, a rapid rise in gate voltage can cause ringing or a surge, which can cause the switching element to malfunction.

Therefore, since the gate voltage pulls close to the voltage level of the power supply voltage VDD to a certain extent, the resistance value selector SL1 is controlled so that the transistor T5 is turned off and the power supply voltage VDD only through the resistor R2 which has the resistance value higher than the combined resistance value is supplied. That is, the logic unit LG outputs the control signal that the transistor T5 off. This smoothes the rising waveform of the gate voltage, thereby suppressing the occurrence of ringing or a surge.

As described above, it is possible to improve the reliability of the switching operation while achieving the high speed operation of the switching element.

The same applies if the switching element SW2 is turned off, the transistor T6 of the resistance value selector RSL2 is turned on and then the resistor T6 is switched off. In this way, as in the case of the resistance value selector RSL1 , the gate voltage of the switch SW2 controlled so that it rises quickly. In addition, since the gate voltage is close to the voltage level of the power supply voltage to a certain extent VEE1 pulls the transistor T6 is turned off and the falling waveform of the gate voltage becomes smoother, thereby suppressing the occurrence of ringing or surge. As described above, it is possible to improve the reliability of the high-speed operation and the switching operation of the switching element. It should be noted that the transistors T5 and T6 after the switch reverberates SW2 is suppressed, can be switched on again. This can reduce the switching time in order to reduce the switching loss.

An operation when the sensing signal to be described in a fourth embodiment is output from the switching element will now be described below.

The sense signal is output when an overcurrent flows through a switching element due to a short circuit of the switching element caused by both switching elements on the higher arm side and the lower arm side that are turned on at the same time.

When the sensing signal enters the logic unit LG , in the 5 is entered, controls the logic unit LG switch off the switching element. This can prevent the switching element from being damaged by blocking the short-circuit current.

When the sensing signal is entered, the logic unit switches LG the transistor T6 immediately. In this way, the switching element through the gate voltage, through the resistor R4 is supplied, which has a resistance value higher than the combined resistance value, switched off.

Smoothing the fall of the gate voltage in this way can suppress the occurrence of the ringing or the surge and prevent malfunction of the switching element. If the gate voltage drop is made abrupt, the switching element's turn-off period may be reduced, but the switching element is turned on by the ringing or current surge that occurs on the gate voltage, which may ultimately damage the switching element. As described above, it is possible to improve the reliability of the switching operation of the switching element even if the switching element is abnormal.

It should be noted that though 7 the configuration shows either the combined resistance value of the resistors R1 and R2 or the resistance value of the resistor R2 through the transistor T5 is switched, the configuration of the resistance value selector RSL1 ( RSL2 ) is not limited to this if two different resistance values can be selected.

For example, the resistance R1 and the resistance R2 which has a resistance value higher than that of the resistor R1 has respective switching transistors, so that the transistors can be switched by their separate control.

Fourth embodiment

<Application example of the power converter>

8th 12 is a schematic diagram showing an exemplary configuration of the power converter PT according to a fourth embodiment of the present invention. The in 8th shown power converter PT consists of a three-phase inverter device to which, for example, the method of the first embodiment is applied.

In 8th are the switching elements SW1u . SW1V . SW1W . SW2u . SW2v . SW2w serving as transistor switches, switching elements, each of which uses an n-channel SiCMOS. The switching elements SW1u . SW1V . SW1W . SW2u . SW2v . SW2w form a transistor switch unit.

Between the source and the drain of the switching elements SW1u . SW1V . SW1W . SW2u . SW2v . SW2w are free-wheeling diodes D1U . D1V . D1W . d2u . d2v . D2w connected. Each of the free wheeling diodes D1U . D1V . D1W . d2u . d2v . D2w is made, for example, from a Schottky diode.

The switching elements SW1u . SW1V . SW1W are arranged on the side of the upper branch, the switching elements SW2u . SW2v . SW2w are arranged accordingly on the side of the lower arm. The switching elements SW1u . SW2u are used for a U phase, the switching elements SW1V . SW2v are used for a V phase, and the switching elements SW1W . SW2w are used for a W phase.

Each of the switching elements SW1u . SW1V . SW1W . SW2u . SW2v . SW2w is provided with a sensing circuit, not shown, which detects an overcurrent, an overvoltage, a temperature or the like of the switching element.

The gate drive circuits GD1u . GD1v . GD1w . GD2u . GD2v . GD2w are such gate drive circuits and gate drive control circuits as in FIG 5 are shown, each of the switching elements SW1u . SW1V . SW1W . SW2u . SW2v . SW2w drive.

The sensing circuit outputs a sensing signal SE after detecting the overcurrent flowing through each switching element, the overvoltage applied to the switching element, or overheating of the switching element. The sensing signal SE, which is output from the sensing circuit, is in the logic unit LG input to the gate driver control circuit. The logic unit LG executes control to stop the operations of all switching elements when the sensing signal SE is input.

Connected between one end (drain node) of the upper branch side switching element and one end (source node) of the lower branch side switching element are a power supply voltage VCC and a capacitor C0 , Each gate drive circuit drives the corresponding switching element to turn on and off as needed, thereby generating a three-phase AC signal that presents different phases (U-phase, V-phase, W-phase) from the power supply voltage VCC which is the DC voltage. The power shift LD consists, for example, of a motor and is controlled as required by the three-phase AC signal (U-phase, V-phase, W-phase).

Exact operations at the time of hard switching operations in the U-phase, V-phase, W-phase are the same as those in FIG 4 and the same. In the three-phase inverter device, the switching element shifts on the upper branch side (for example, the switching element SW1u ) to the ON state while the switching element on the lower branch side (e.g. the switching element SW2u ) is in the OFF state.

At this time, a drain potential (VD) on the upper arm side rises close to the level of the power supply voltage VCC. If the drain potential of the switching element of the lower branch side (for example, the switching element SW2u ) increases abruptly, the gate potential of the switching element on the lower branch side (for example, the switching element SW2u ) temporarily as with reference to 4 is described.

However, because the gate drive circuit according to this embodiment temporarily the power supply voltage VEE1 of about -15 V to the gate of the switching element of the lower branch side (e.g. the switching element SW2u ) applied, it can prevent the misfire in the switching element. In addition, after preventing the misfire operation, the gate potential of each switching element becomes the level of the power supply voltage VEE2 shifted from about -5 volts.

This makes it possible to sufficiently suppress the amount of shift in the threshold voltage of each switching element. even if a power supply operation is performed on the three-phase inverter device, and thereby a more reliable and stable power conversion operation is achieved.

In particular, such a three-phase inverter device often operates at a high power, which facilitates the occurrence of misfire and can increase the damage in the case of misfire. Thus, by using the method of this embodiment, the SiCMOS can achieve the low loss even when operating at the high power and also avoid the misfire and thereby achieve a useful effect.

<Configuration example of the Schottky diode>

9 FIG. 12 is an explanatory diagram showing an exemplary configuration of a Schottky diode used as the free-wheeling diode as in FIG 8th is shown. 9 (a) 13 is a plan view of the main part of the semiconductor chip with the Schottky diode formed thereon, and 9 (b) FIG. 12 is a cross sectional view taken along a line AA 'in FIG 9 (a) , The 9 (a) and 9 (b) show the Schottky diode having a JTE (junction termination extension) configuration in its junction region.

A drift layer DFTD of the n-minus type is on a main surface of a substrate Subd formed by the n-plus type (top in 9 (b) ). A guard ring area PGR of the p-plus type, a JTE area PJ p-type and a channel stop area CSd of the n-plus type are on top of the drift layer DFTD formed so that they have an active area ACTd , which is formed in the center of the semiconductor chip as seen from above. In addition, there is an insulating layer IL3 on the drift layer DFTD educated.

There is also a surface electrode IL-1 that with the guard ring area PGR is connected, and a channel double electrode IL2 that with the channel stop area CSd through an opening in the insulating layer IL3 is formed, is connected, formed. On the back (bottom in 9 (b) ) opposite the main surface of the substrate Subd is a backside electrode CA formed with the substrate Subd connected is. Although not shown, a passivation layer, a resin layer, and the like are also above the surface electrode IL-1 and the channel double electrode IL2 educated.

On the active area ACTd that is in the middle of the semiconductor chip CH is located, a Schottky diode is formed, which has the so-called JBS structure (barrier layer Schottky structure), in which, for example, a p-plus region and an n-minus region are arranged alternately.

In the case where the guard ring area PGR located near the peripheral surface of the semiconductor chip, electric fields tend to concentrate at an edge portion thereof; by forming the JTE area PJ however, near this range, it is possible to weaken the concentration of the electric field in the edge portion.

This can make the power device resistant to high voltage. That is, by combining it with the in 8th shown switching element or the like, it is possible to achieve a more reliable power conversion system.

<Configuration example of the switching element>

10 FIG. 12 is an explanatory cross-sectional diagram showing a schematic exemplary configuration of a switching element included in the in FIG 8th shown power converter PT is used. 10 (a) FIG. 12 is an explanatory cross-sectional diagram showing a configuration example of each element transistor in an active element region while 10 (b) an explanatory cross-sectional diagram of a configuration example other than 10 (a) is.

First shows 10 (b) a single vertical SiCMOS that has a trench structure. A source layer N +, which is said to be an n-plus type region, with a source electrode SPm is connected to the drift layer DFTD connected via a channel in the base layer P which is to be a p-type region. The DFT can be, for example, an n-minus type area that is responsible for ensuring its dielectric strength. The substrate SUB can be, for example, an n-plus type region with which a drain electrode DRm connected is.

Such a trench structure has the advantage of reducing the ON resistance value in the entire SiCMOS, because no so-called JFET region, which is an n-type semiconductor region, lies between the base layers P is inserted, is present.

In other words, by combining the semiconductor drive circuit according to this embodiment (the gate drive circuit and the gate driver control circuit), it is possible to achieve a power conversion system with less loss.

In contrast, it shows 10 (a) a so-called DMC type (double diffusion metal oxide semiconductor type) which has no trench structure. In this case, the device structure is simple, which has an advantage of reducing the manufacturing cost compared to the trench structure type SiCMOS.

As described above, it is possible to have a more reliable power converter PT with less power loss.

Fifth embodiment

<Configuration example of the three-phase motor system>

In a fifth embodiment, an example is described in which the in 8th power converter shown in the fourth embodiment PT is applied to a three-phase motor system that drives a motor that is mounted on a rail vehicle or the like.

11 FIG. 12 is an explanatory diagram showing an exemplary configuration of the three-phase motor system MS according to the fifth embodiment.

The rail vehicle becomes an overhead line RT via a pantograph PG supplied with electrical power. A high AC voltage in the overhead line RT can for example about 25 kV or 15 kV. The high AC voltage is caused, for example, by an insulated main transformer MTR reduced to approximately 1.5 kV to 3.0 kV.

The AC voltage, which is reduced to approximately 1.5 kV, is converted to a DC voltage of approximately 1.5 kV by an AC / DC converter CON rectified.

The DC voltage is then through a DC / AC inverter INV through a capacitor CL converted to an AC voltage to a desired three-phase AC voltage to a three-phase motor M3 output and thereby the three-phase motor M3 drive.

The configuration of the DC / AC converter INV is the same as in 8th shown. In addition, the in 2 shown gate drive circuit can also be used as the gate drive circuit, for example for the AC / DC converter CON is used. A reference number WHL in 11 indicates a wheel.

As described above, the in 8th shown power converter PT to the DC / AC converter INV applied, which forms the three-phase motor system of the rail vehicle. In this way, a loss in the converter circuit and the inverter circuit can be reduced, and thereby the elimination of a radiation fin and the like is made possible. As a result, the volume of the three-phase motor system MS be reduced.

Reduce the volume of the three-phase motor system MS can lead to a low-floor rail vehicle by reducing the under-floor proportions that make up the three-phase motor system MS contain. In addition, it is possible, for example, by reducing the amount of underfloor parts, to provide a new type of battery BAT release as in 11 consisting of a lithium ion battery or the like.

If the vehicle is not running, it is possible to put electrical energy in the battery BAT to store without the electrical energy through the wheel WHL to the overhead line RT due. This can lead to an improvement in the recovery efficiency of the rail vehicle. In other words, it is possible to reduce the life cycle costs of the rail system.

Of course, although this invention made by the inventors is described above with reference to the embodiments, the invention is not limited to the above embodiments, but can be changed in various ways without departing from the spirit of the invention.

That is, of course, various changes can be made as long as such goals as preventing misfire, reducing the amount of shift in the threshold voltage for long-term power supply operations, and reducing electrical power loss can be achieved.

Each switching element is not limited to silicon carbide (SiC), but can be silicon (Si) or a connecting device such as. B. Use gallium nitride (GaN). Of course, if a connection material as the switching element such as. B. the inverter device is used, the loss in the inverter device can be reduced by combining the switching element with the semiconductor drive circuit in the embodiments.

Also, of course, the power converter according to the embodiments can be applied to electrical power systems for various applications to provide a similar effect. Typical examples may be an inverter device of an air conditioner, a DC / DC converter of a server power supply, an inverter of a solar power system, an inverter device of a hybrid vehicle or an electric vehicle.

It should be noted that the present invention is not limited to the embodiments described above, but contains various variations. For example, the foregoing embodiments have been described in detail for better understanding and are not limited to necessarily including all of the configurations described above.

Part of a configuration in one embodiment may be replaced by a configuration in another embodiment, or a configuration of an embodiment may be added to a configuration of another embodiment. It is also possible to add, eliminate, or replace part of a configuration in any embodiment with another configuration.

LIST OF REFERENCE NUMBERS

PT

power converter

GDCTL1

Gate drive control circuit

GDCTL2

Gate drive control circuit

SW1

switching element

SW2

switching element

DI1

Freewheeling diode

DI2

Freewheeling diode

GD1

Gate drive circuit

GD2

Gate drive circuit

T1 to T4

transistor

D1 to D4

integrated diode

VSPY

Power generation output unit

LG

logic unit

DC1, DC2

DC / DC converter

SEL1

signal selector

SEL2

signal selector

SEL3

signal selector

R

resistance

RSL1, RSL2

Widerstandswertselektor

RSL2

T5, T6

transistor

R1 to R4

resistance

SW1u

switching element

SW1V

switching element

SW1W

switching element

SW2u

switching element

SW2v

switching element

SW2w

switching element

D1U

Freewheeling diode

D1V

Freewheeling diode

D1W

Freewheeling diode

GD1u

Gate drive circuit

GD1v

Gate drive circuit

GD1w

Gate drive circuit

GD2u

Gate drive circuit

GD2v

Gate drive circuit

GD2w

Gate drive circuit

C0

capacitor

LD

Powershift

CH

Semiconductor chip

Subd

substratum

DFTD

drift layer

ACTd

active area

PGR

Guard ring region

PJ

JTE region

CSd

Channel stop region

IL-1

surface electrode

IL2

Channel stop electrode

IL3

insulating

CA

Back electrode

SPm

Source electrode

N

Source layer

P

Base layer

DFT

drift layer

SUB

substratum

DRm

Drain

MS

Three-phase motor system

RT

catenary

PG

pantograph

MTR

main transformer

CON

AC / DC converter

INV

DC / AC inverter

CL

capacitor

M3

Three-phase motor

WHL

wheel

BAT

battery

Claims (14)

Drive circuit that controls ON / OFF of a switching circuit comprising: a first switching element (T1) whose source is connected to a first voltage (VEE1) and whose drain is connected to a signal output node (VOUT) that outputs a drive signal that is ON / OFF of the switching circuit (SW1, SW2) controls; a second switching element (T2) whose source is connected to a second voltage (VDD) and whose drain is connected to the signal output node (VOUT); a third switching element (T3) whose drain is connected to the signal output node (VOUT); and a fourth switching element (T4), the drain of which is connected to the source of the third switching element (T3) and the source of which is connected to a third voltage (VEE2), characterized in that a connection to a connection node of the source of the third switching element (T3 ) and the drain of the fourth switching element (T4) and the other connection has a resistor (R) which is to be connected to the third voltage (VEE2). Control circuit after Claim 1 , wherein the second switching element (T2) and the fourth switching element (T4) each consist of a P-type MOS transistor and the first switching element (T1) and the third switching element (T3) each consist of an N-type MOS transistor consist. Control circuit after Claim 2 , wherein the first to fourth switching elements (T1-T4) are power MOSFETs, each of which contains an integrated diode. Control circuit after Claim 1 , wherein the drive circuit (GD1, GD2) outputs a third voltage (VEE2) to the signal output node (VOUT) when the switching circuit (SW1, SW2) is switched off, outputs a second voltage (VDD) to the signal output node (VOUT) when the Switching circuit (SW1, SW2) is shifted from OFF to ON, and after the first voltage (VEE1) is output to the signal output node (VOUT), the third voltage (VEE2) is output to the signal output node (VOUT) when the switching circuit (SW1, SW2 ) is shifted from ON to OFF. Control circuit after Claim 1 , wherein the first voltage (VEE1) output from the first switching element (T1) and the third voltage (VEE2) output from the third switching element (T3) have a negative potential, and the third voltage (VEE2 ) has a higher potential than the first voltage (VEE1). A power converter (PT) comprising: a first transistor switch (SW1) connected between a voltage output node that outputs a power supply voltage to be supplied to a load and a reference potential; a second transistor switch (SW2) connected between the power supply voltage and the voltage output node; and a first drive circuit (GD1) that controls ON / OFF of the first transistor switch (SW1), the first drive circuit (GD1) including: a first switching element (T1) whose source is connected to a first voltage (VEE1) and whose drain is connected to a signal output node (VOUT) which outputs a drive signal which controls ON / OFF of the first or second transistor switch (SW2); a second switching element (T2) whose source is connected to a second voltage (VDD) and whose drain is connected to the signal output node (VOUT); a third switching element (T3) whose drain is connected to the signal output node (VOUT); and a fourth switching element (T4), the drain of which is connected to the source of the third switching element (T3) and the source of which is connected to a third voltage (VEE2), characterized in that a connection to a connection node of the source of the third switching element (T3 ) and the drain of the fourth switching element (T4) and the other connection has a resistor (R) which is to be connected to the third voltage (VEE2). Power converter (PT) after Claim 6 , wherein the first drive circuit (GD1) outputs the third voltage (VEE2) to the signal output node (VOUT) when the first transistor switch (SW1) is switched off, the second voltage (VDD) to the signal output node (VOUT) when the first transistor switch (SW1) is shifted from OFF to ON, and after the first voltage (VEE1) is output to the signal output node (VOUT), the third voltage (VEE2) is output to the signal output node (VOUT) when the first transistor switch (SW1) is ON OFF is moved. Power converter (PT) after Claim 6 , further comprising: a second drive circuit (GD2) that controls ON / OFF of the second transistor switch (SW2), the second drive circuit (GD2) outputting the third voltage (VEE2) to the signal output node (VOUT) when the second transistor switch ( SW2) is switched off, the second voltage (VDD) to the signal output node (VOUT) when the second transistor switch (SW2) is shifted from OFF to ON, and after the output of the first voltage (VEE1) to the signal output node (VOUT) outputs third voltage (VEE2) to the signal output node (VOUT) when the second transistor switch (SW2) is shifted from ON to OFF. Power converter (PT) after Claim 6 , wherein the first and the second transistor switch (SW1, SW2) consist of silicon carbide or gallium nitride. Power converter (PT) after Claim 6 , the first and second transistor switches (SW1, SW2) each including: a MOSFET; and a free wheeling diode connected between the source and the drain of the MOSFET. Power converter (PT) after Claim 6 , wherein the first drive circuit (GD1) further includes: a first resistance switch control unit (RSL1) connected between the source of the second voltage (VDD) and the second switching element (T2); and a second resistance switch control unit (RSL2) which is connected between the first voltage (VEE1) and the source of the first switching element (T1) is connected, the first resistance switch control unit (RSL1) selecting one of the first resistance value and a second resistance value that is higher than the first resistance value based on a control signal, and the second resistance switch control unit (RSL2) selects one of a third resistance value and a fourth resistance value that is higher than the third resistance value based on a control signal. Power converter (PT) after Claim 11 wherein the second resistance switch control unit (RSL2) selects the fourth resistance value when a sensing signal that stops the first transistor switch (SW1) is generated. A motor system comprising: a transformer (MTR) that reduces an AC voltage; an AC / DC converter (CON) that converts the AC voltage reduced by the transformer (MTR) into a DC voltage; a DC / AC inverter (INV) which converts the DC voltage, which is converted by the AC / DC converter (CON), into a three-phase AC voltage; and a three-phase motor drive based on the three-phase AC voltage implemented by the DC / AC inverter (INV), the DC / AC inverter (INV) including: a transistor switch unit that includes a plurality of transistor switches (SW1u, SWlv, SWlw, SW2u, SW2v , SW2w) and the DC voltage, which is converted by the AD / DC converter (CON), is converted by a switching operation into the three-phase AC voltage; and a plurality of drive circuits (GD1u, GD1v, GD1w, GD2u, GD2v, GD2w), each of which controls ON / OFF of the transistor switches (SW1u, SW1v, SW1w, SW2u, SW2v, SW2w), and the drive circuit (GD1u, GD1v, GDuw , GD2v, GD2w) includes: a first switching element (T1) whose source is connected to a first voltage (VEE1) and whose drain is connected to a signal output node (VOUT) which outputs a drive signal which controls ON / OFF of the transistor switch; a second switching element (T2) whose source is connected to a second voltage (VDD) and whose drain is connected to the signal output node (VOUT); a third switching element (T3) whose drain is connected to the signal output node (VOUT); and a fourth switching element (T4), the drain of which is connected to the source of the third switching element (T3) and the source of which is connected to a third voltage (VEE2), characterized in that a connection to a connection node of the source of the third switching element (T3 ) and the drain of the fourth switching element (T4) and the other connection has a resistor (R) which is to be connected to the third voltage (VEE2). Engine system after Claim 13 , wherein the three-phase motor (M3) is mounted on a rail vehicle.

Images