JPWO2012029549A1 - Semiconductor package and semiconductor device - Google Patents

Abstract

A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board; a semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern; and at least one surface of the one surface and the other surface of the substrate And a reinforcing member joined to the semiconductor package. According to the semiconductor package of the present invention, warping of the wiring board can be suppressed or prevented, and the rigidity of the entire semiconductor package is further increased. Moreover, the heat dissipation of the semiconductor package can be made excellent.

Description

The present invention relates to a semiconductor package and a semiconductor device.
This application is filed in Japanese Patent Application No. 2010-192903 filed in Japan on August 30, 2010, Japanese Patent Application No. 2010-210161 filed in Japan on September 17, 2010, and in Japan on September 17, 2010. Japanese Patent Application No. 2010-210162 filed, Japanese Patent Application No. 2010-210163 filed in Japan on September 17, 2010, Japanese Patent Application No. 2010-210164 filed in Japan on September 17, 2010, 2010 Claim priority based on Japanese Patent Application No. 2010-210167 filed in Japan on September 17, 2010 and Japanese Patent Application No. 2010-210168 filed on September 17, 2010, the contents of which are incorporated herein by reference. .

  In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.

  With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type package system such as CSP (Chip Scale Package) have been proposed.

  In general, an interposer used for a new package such as BGA or CSP is formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.

Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion that is not in contact with the chip has a very low rigidity, and thus tends to warp due to the difference in thermal expansion between the chip and the interposer as described above, resulting in a problem that reliability of electrical connection is lowered.
Moreover, since the chip generates heat, the interposer is required to have excellent heat dissipation. Furthermore, such a semiconductor package is required to have excellent heat dissipation.

JP 2002-270716 A

  An object of the present invention is to provide a semiconductor package and a semiconductor device capable of improving workability at the time of manufacture and preventing occurrence of defects due to heat.

Such an object is achieved by the present inventions (1) to (10) below.
(1) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A semiconductor package comprising: a reinforcing member joined to at least one of the one surface and the other surface of the substrate and made of an Fe-Ni alloy.

(2) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded, and having a smaller coefficient of thermal expansion than the substrate;
A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
At least one of the first reinforcing member and the second reinforcing member is made of an Fe—Ni-based alloy.

  (3) The semiconductor package according to (1) or (2), wherein the Fe—Ni alloy has a smaller thermal expansion coefficient than the substrate.

  (4) The semiconductor package according to (3), wherein the Fe—Ni alloy has a thermal expansion coefficient of 3 ppm / ° C. or more and 10 ppm / ° C. or less.

  (5) The semiconductor package according to any one of (1) to (4), wherein the Fe—Ni-based alloy has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the semiconductor element.

  (6) The semiconductor package according to any one of (1) to (5), wherein the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less.

  (7) The semiconductor package according to any one of (1) to (6), wherein the Fe—Ni-based alloy has a balance content of 0 wt% or more and 15 wt% or less.

  (8) The semiconductor package according to any one of (2) to (7), wherein the first reinforcing member is provided so as to surround a periphery of the semiconductor element.

  (9) The semiconductor package according to any one of (2) to (8), wherein each of the first reinforcing member and the second reinforcing member has a plate shape.

  (10) A semiconductor device comprising the semiconductor package according to any one of (1) to (9).

Moreover, such an object is achieved by the present inventions (11) to (18) below.
(11) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate via an adhesive layer, and having a smaller thermal expansion coefficient than the substrate;
The adhesive layer is composed of a resin composition containing a resin material and an inorganic filler.

  (12) The semiconductor package according to (1), wherein the adhesive layer has an elastic modulus at 25 ° C. of 0.5 MPa to 10 GPa.

  (13) The semiconductor package according to (11) or (12), wherein the adhesive layer has a thermal conductivity of 0.5 W / (m · K) to 100 W / (m · K).

  (14) The semiconductor package according to any one of (11) to (13), wherein an average thickness of the adhesive layer is not less than 5 μm and not more than 150 μm.

  (15) The semiconductor package according to any one of (11) to (14), wherein the reinforcing member has a thermal expansion coefficient of 0.5 ppm / ° C. or more and 10 ppm / ° C. or less.

  (16) The semiconductor package according to any one of (11) to (15), wherein the reinforcing member has a difference in thermal expansion coefficient of 7 ppm / ° C. or less from the semiconductor element.

  (17) The semiconductor package according to any one of (11) to (16), wherein the reinforcing member is made of an Fe—Ni alloy.

  (18) A semiconductor device comprising the semiconductor package according to any one of (11) to (17).

Moreover, such an object is achieved by the present inventions (19) to (28) below.
(19) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-shaped reinforcing member bonded to at least one of the one surface and the other surface of the substrate, and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer and a second layer bonded to a surface of the first layer opposite to the substrate and having a thermal expansion coefficient different from that of the first layer. Semiconductor package.

(20) The reinforcing member is bonded to the one surface of the substrate,
The semiconductor package according to (19), wherein a thermal expansion coefficient of the second layer is larger than a thermal expansion coefficient of the first layer.

  (21) The semiconductor package according to (20), wherein the reinforcing member is provided so as to surround the periphery of the semiconductor element.

(22) The reinforcing member is bonded to the other surface of the substrate,
The semiconductor package according to (19), wherein a thermal expansion coefficient of the second layer is smaller than a thermal expansion coefficient of the first layer.

(23) On the other surface of the substrate, a plurality of metal bumps are provided,
The said reinforcement member is a semiconductor package as described in said (22) which has a part located between the said metal bumps.

  (24) The absolute value of the difference between the coefficient of thermal expansion of the first layer and the coefficient of thermal expansion of the second layer is 0.5 ppm / ° C. or more and 20 ppm / ° C. or less. A semiconductor package according to the above.

(25) When the thickness of the first layer is t1 [mm] and the thickness of the second layer is t2 [mm],
The semiconductor package according to any one of (19) to (24), wherein t2 / t1 is 0.03 or more and 34 or less.

  (26) The semiconductor package according to any one of (19) to (25), wherein the thermal expansion coefficient of the first layer is not less than 0.5 ppm / ° C. and not more than 10 ppm / ° C.

  (27) The semiconductor package according to any one of (19) to (26), wherein the first layer has a difference in thermal expansion coefficient of 7 ppm / ° C. or less with respect to the semiconductor element.

  (28) A semiconductor device comprising the semiconductor package according to any one of (19) to (27).

Such an object is also achieved by the present inventions (29) to (38) below.
(29) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-shaped reinforcing member bonded to at least one of the one surface and the other surface of the substrate, and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer and a second layer bonded to a surface of the first layer opposite to the substrate and having a characteristic different from that of the first layer. .

(30) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-like first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded, and having a smaller coefficient of thermal expansion than the substrate;
A plate-like second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The first reinforcing member and the second reinforcing member are bonded to the first layer and the surface of the first layer opposite to the substrate, respectively, and have a characteristic different from that of the first layer. A semiconductor package comprising:

  (31) The semiconductor package according to (29) or (30), wherein the first layer and the second layer are made of different materials.

  (32) The semiconductor package according to any one of (29) to (31), wherein one of the first layer and the second layer is made of a material harder than the other.

  (33) The semiconductor package according to any one of (29) to (32), wherein the first layer and the second layer are made of materials having different etching rates in predetermined etching.

  (34) The thermal expansion coefficient of at least one of the first layer and the second layer is 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, according to any one of (29) to (33). Semiconductor package.

  (35) In any one of (29) to (34), at least one of the first layer and the second layer has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the semiconductor element. Semiconductor package.

  (36) The semiconductor package according to any one of (29) to (35), wherein at least one of the first layer and the second layer is made of an Fe—Ni alloy.

  (37) The semiconductor package according to any one of (29) to (36), wherein the first reinforcing member is provided so as to surround a periphery of the semiconductor element.

  (38) A semiconductor device comprising the semiconductor package according to any one of (29) to (37).

Moreover, such an object is achieved by the present inventions (39) to (47) below.
(39) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate via an adhesive layer, having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer that contacts the adhesive layer, and a second layer that is bonded to a surface of the first layer opposite to the substrate and is made of a material different from the first layer. The first package has a function of improving adhesion with the adhesive layer.

  (40) The first layer is made of copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, iron, iron alloy, silver, silver alloy, zinc, zinc alloy, gold, gold alloy. The semiconductor package according to (39), which is made of a metal material selected from the group.

  (41) The semiconductor package according to (40), wherein the adhesive layer includes a resin material and an inorganic filler.

  (42) The semiconductor package according to any one of (39) to (41), wherein a contact surface of the first layer with the adhesive layer is roughened.

(43) When the thickness of the first layer is t1, and the thickness of the second layer is t2,
The semiconductor package according to any one of (39) to (42), wherein t2 / t1 is not less than 2 and not more than 80000.

  (44) The semiconductor package according to any one of (39) to (43), wherein the second layer has a thermal expansion coefficient of 0.5 ppm / ° C. or more and 10 ppm / ° C. or less.

  (45) The semiconductor package according to any one of (39) to (44), wherein the second layer has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the semiconductor element.

  (46) The semiconductor package according to any one of (39) to (45), wherein the second layer is made of an Fe—Ni alloy.

  (47) A semiconductor device comprising the semiconductor package according to any one of (39) to (46).

Moreover, such an object is achieved by the present invention described in (48) to (58) below.
(48) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member has a plurality of concave portions or convex portions formed by roughening at least an exposed portion of the surface thereof.

  (49) The semiconductor package according to (48), wherein the plurality of concave portions or convex portions are uniformly distributed over the entire surface of the reinforcing member in a plan view.

  (50) The semiconductor package according to (48) or (49), wherein the plurality of concave portions or convex portions are regularly arranged.

  (51) The semiconductor package according to (50), wherein the roughening process is an etching process.

  (52) The semiconductor package according to (48) or (49), wherein the plurality of concave portions or convex portions are randomly arranged.

  (53) The semiconductor package according to (52), wherein the roughening process is a blast process.

(54) A planar view shape of the concave portion or the convex portion is circular,
The semiconductor package according to any one of (48) to (53), wherein a surface roughness of the roughened surface of the reinforcing member is 0.1 μm or more and 400 μm or less.

  (55) The semiconductor package according to any one of (48) to (54), wherein the roughening treatment is performed on a portion of the surface of the reinforcing member facing the substrate.

  (56) The semiconductor package according to any one of (48) to (55), wherein the reinforcing member is made of a metal material.

  (57) The semiconductor package according to (56), wherein the reinforcing member is made of an Fe—Ni alloy.

  (58) A semiconductor device comprising the semiconductor package according to any one of (48) to (57).

Moreover, such an object is achieved by the present invention described in the following (59) to (67).
(59) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The semiconductor package according to claim 1, wherein the reinforcing member has a plate shape and a plurality of through holes penetrating in the thickness direction.

  (60) The semiconductor package according to (59), wherein the plurality of through holes are regularly arranged in a plan view.

  (61) The semiconductor package according to (59) or (60), wherein the plurality of through holes are uniformly distributed over the entire surface of the reinforcing member in a plan view.

(62) When the area of the reinforcing member in plan view is S1, and the total area of the plurality of through holes in plan view is S2,
The semiconductor package according to (61), wherein S2 / (S1 + S2) is 0.1 or more and 0.9 or less.

  (63) The semiconductor package according to any one of (59) to (62), wherein each through hole has a circular shape in plan view.

(64) having a plurality of metal bumps bonded on the substrate;
The semiconductor package according to any one of (59) to (63), wherein the plurality of through holes are formed so as to expose the plurality of metal bumps.

  (65) The semiconductor package according to any one of (59) to (64), wherein the reinforcing member is made of a metal material.

  (66) The semiconductor package according to (65), wherein the reinforcing member is made of an Fe—Ni alloy.

  (67) A semiconductor device comprising the semiconductor package according to any one of (59) to (66).

According to the semiconductor package of the present invention, warping of the wiring board can be suppressed or prevented, and the rigidity of the entire semiconductor package is further increased. Moreover, the heat dissipation of the semiconductor package can be made excellent.
According to the semiconductor device of the present invention, since the semiconductor package as described above is provided, the reliability is excellent.

1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment. FIG. 14 is a top view showing the semiconductor package shown in FIGS. 1, 6, 9, and 13. FIG. 25 is a bottom view showing the semiconductor package shown in FIGS. 1, 6, 11, 13, and 24. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. FIG. 16 is a diagram showing an example of a manufacturing method of the semiconductor package shown in FIGS. 1, 13, and 15. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically the semiconductor package which concerns on 3A Embodiment. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor package which concerns on 3B embodiment. It is sectional drawing which shows typically the semiconductor device which concerns on 3A and 3B embodiment. It is sectional drawing which shows typically the semiconductor package which concerns on 4th Embodiment. It is sectional drawing which shows typically the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows typically the semiconductor package which concerns on 6A Embodiment. FIG. 16 is a top view showing the semiconductor package shown in FIG. 15. FIG. 16 is a bottom view showing the semiconductor package shown in FIG. 15. It is sectional drawing which shows typically an example of the semiconductor device of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 6B embodiment. It is a top view which shows the semiconductor package which concerns on 6C Embodiment. FIG. 21 is a bottom view showing the semiconductor package shown in FIG. 20. It is a top view which shows the semiconductor package which concerns on 6D Embodiment. FIG. 23 is a bottom view showing the semiconductor package shown in FIG. 22. It is sectional drawing which shows typically the semiconductor package which concerns on 7A Embodiment. FIG. 25 is a top view showing the semiconductor package shown in FIG. 24. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically an example of the semiconductor device of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 7B Embodiment.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor package and a semiconductor device according to the invention will be described with reference to the accompanying drawings.

(1) First Embodiment (1-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  1 is a cross-sectional view schematically showing the semiconductor package according to the first embodiment, FIG. 2 is a top view showing the semiconductor package shown in FIG. 1, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. 4A to 4G are diagrams showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”. 1 to 4 (FIGS. 4A to 4G), each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 1, a semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Increases overall rigidity. In particular, since the thermal expansion coefficient of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. In the same manner, warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.

  Further, it is not necessary to increase the rigidity of the wiring board 2 itself, and the thickness of the wiring board 2 can be reduced, so that the thermal conductivity in the thickness direction of the wiring board 2 can be increased. Therefore, the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.

  For this reason, since the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed, the warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is also suppressed in this respect. Or it can be prevented.

  In particular, in the semiconductor package 1, as described in detail later, the first reinforcing member 4 and the second reinforcing member 5 are each composed of an Fe—Ni-based alloy, and thus have excellent rigidity and heat dissipation, The thermal expansion coefficient is small (close to the semiconductor element 3). Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
The wiring board 2 is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. In addition, the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.

  The wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, 234, and heat transfer posts 24.

  In the first embodiment, the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21. A second conductor pattern electrically connected to the one conductor pattern is formed.

  The substrate 21 includes a plurality (five layers in the first embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order. In addition, the number of the insulating layers which comprise the board | substrate 21 is not limited to this, 1-4 may be sufficient, and six or more layers may be sufficient.

  Each of the insulating layers 211, 212, 213, 214, and 215 is made of an insulating material.

  Specifically, each insulating layer 211, 212, 213, 214, 215 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.

  A base material is used as a core material of each insulating layer 211,212,213,214,215. By having such a base material, the rigidity of the substrate 21 can be increased.

  Examples of the base material include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthetic fiber base material, kraft paper composed of woven fabric or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. And paper base materials mainly composed of cotton linter paper, mixed paper of linter and kraft pulp, and the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Furthermore, the thermal expansion coefficient of the substrate 21 can be reduced.

  As glass which comprises such a glass fiber base material, E glass, C glass, A glass, S glass, D glass, NE glass, T glass, H glass etc. are mentioned, for example. Among these, T glass is preferable. Thereby, the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board | substrate 21 can be made small.

  When the insulating layers 211, 212, 213, 214, and 215 include a base material, the base material content in the insulating layers 211, 212, 213, 214, and 215 is preferably 30 to 70 wt%, respectively. 40 to 60 wt% is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers. Note that at least one of the insulating layers 211, 212, 213, 214, and 215 may be composed of only the resin composition without including the base material.

  The resin composition impregnated in such a base material contains a resin material. As such a resin material, a thermosetting resin is preferably used.

  Examples of the thermosetting resin include an oil-modified resole modified with a novolak-type phenol resin such as a phenol novolak resin, a cresol novolak resin, a bisphenol A novolak resin, an unmodified resole phenol resin, tung oil, linseed oil, walnut oil, and the like. Phenol resin such as phenolic resin, bisphenol type epoxy resin such as bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin, novolac epoxy resin such as cresol novolac epoxy resin, biphenyl type epoxy resin, etc. Epoxy resin, cyanate resin, urea (urea) resin, resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate DOO resins, silicone resins, resins having a benzoxazine ring, cyanate ester resins.

  Among these, a cyanate resin is particularly preferable. Thereby, the thermal expansion coefficient of the board | substrate 21 can be made small enough. Furthermore, the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.

  Moreover, it is preferable that the said resin composition contains a filler. That is, each of the insulating layers 211, 212, 213, 214, and 215 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be lowered.

Examples of the filler include various inorganic fillers or organic fillers.
Examples of the inorganic filler (inorganic filler) include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide. , Calcium carbonate (light, heavy), carbonates such as magnesium carbonate, dolomite, and dawsonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, silica Silicates such as calcium oxide, montmorillonite, bentonite, borate such as zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate, carbon black, graphite, carbon fiber and other iron Powder, copper powder, aluminum powder, zinc white, sulfide Ribuden, boron fiber, potassium titanate, and a lead zirconate titanate.

  Moreover, synthetic resin powder is mentioned as an organic filler. Examples of the synthetic resin powder include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene. And various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins. Other examples of organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.

  Among the fillers as described above, it is preferable to use an inorganic filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be effectively reduced. In addition, the heat transfer properties of the insulating layers 211, 212, 213, 214, and 215 can be increased.

  In particular, among inorganic fillers, silica is preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low thermal expansion.

  Although the average particle diameter of an inorganic filler is not specifically limited, 0.05-2.0 micrometers is preferable and especially 0.1-1.0 micrometer is preferable. As a result, the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, 213, 214, and 215, and the physical strength and insulating properties of the insulating layers 211, 212, 213, 214, and 215 are particularly improved. It can be excellent.

  In addition, the average particle diameter of the said inorganic filler can be measured with a particle size distribution meter (product made from HORIBA, LA-500), for example. Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.

  The content of the inorganic filler in the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but is preferably 30 to 80 wt% when the resin composition excluding the base material is 100 wt%, particularly 45-75 wt% is preferable. When the content is within the above range, the insulating layers 211, 212, 213, 214, and 215 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.

  In addition to the thermosetting resin described above, the resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin.

  Moreover, the said resin composition may contain additives other than the said components, such as a pigment and antioxidant, as needed.

  The insulating layers 211, 212, 213, 214, and 215 may be made of the same material as each other, or may be made of different materials.

  The average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, and more preferably 30 μm or more and 400 μm or less.

  A conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21. In addition, a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213. A conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214. A conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.

  Each of the conductor patterns 221, 222, 223, and 224 functions as a circuit having a plurality of wirings.

  The constituent material of the conductor patterns 221, 222, 223, and 224 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.

  In addition, the average thickness of the conductor patterns 221, 222, 223, and 224 is not particularly limited, but is preferably 5 μm or more and 30 μm or less.

  The insulating layer 211 has a via hole penetrating in the thickness direction, and a conductor post (via post) 231 is provided in the via hole. The conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.

  Similarly, the insulating layer 212 is provided with a conductor post (via post) 232 that penetrates in the thickness direction. The conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.

  The insulating layer 213 is provided with a conductor post (via post) 233 penetrating in the thickness direction. The conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.

  The insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction. The conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.

  The insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening. A metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.

  The metal bump 71 is for electrically connecting the semiconductor package 1 to, for example, a mother board as will be described later.

  In the first embodiment, the metal bump 71 has a substantially spherical shape. The shape of the metal bump 71 is not limited to this.

  The constituent material of the metal bump 71 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin- Various brazing materials (solder) such as copper and tin-silver-copper can be used.

  The substrate 21 is formed with a plurality of via holes penetrating in the thickness direction, and a heat transfer post 24 is provided in each via hole.

  Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21. The heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5. Thus, each heat transfer post 24 connects the first reinforcing member 4 and the second reinforcing member 5.

  Each of the heat transfer posts (heat conduction portions) 24 has higher heat transfer properties than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Further, since each heat transfer post 24 penetrates the substrate 21 in the thickness direction, it can be formed easily and with high accuracy, similarly to a known conductor post.

  Each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post | mailbox 24, For example, circular, an ellipse, a polygon etc. are mentioned. Further, the number of heat transfer posts 24 is not particularly limited and is arbitrary, but is preferably as large as possible so as not to impair the mechanical strength of the wiring board 2.

  Each heat transfer post 24 does not contribute to transmission of an electrical signal. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24.

  In the first embodiment, the plurality of heat transfer posts 24 are arranged side by side along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan. In particular, the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.

  The plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, and 224 described above when the wiring board 2 is viewed in plan. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit between the heat transfer post 24 and the conductor patterns 221, 222, 223, and 224 can be prevented.

  The constituent material of each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.

  Examples of the metal material include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Among these, as such a metal material, it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity. Since copper and a copper-based alloy are excellent in thermal conductivity, the heat dissipation of the wiring board 2 can also be improved.

  Further, the constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 234 described above, but is the same as the constituent material of the conductor posts 231 to 234 (particularly, the constituent material of the conductor posts 234). Is preferred. As a result, the heat transfer posts 24 can be formed simultaneously with the formation of the conductor posts 234. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.

[Semiconductor element]
The semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.

  The semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.

  Specifically, the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the conductor post 231 of the wiring board 2 described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected.

  The constituent material of the metal bump 31 is not particularly limited. For example, as in the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin -Various brazing materials (solder) such as silver-bismuth, tin-copper, and tin-silver-copper can be used.

  Further, the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.

  The adhesive layer 32 is made of a material having adhesiveness and insulation, and is made of, for example, a cured product of an underfill material.

  The underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.

  This 1st reinforcement member 4 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 1st reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that). It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

In the first embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. . Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.

  The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the first embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.

  The first reinforcing member 4 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

Moreover, the 1st reinforcement member 4 is comprised with the Fe-Ni type alloy.
The Fe—Ni alloy not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.

  More specifically, examples of Fe-Ni alloys include Fe-Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar). Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy.

  In addition, Fe-Ni-Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, and KV-25, and Nivarox. ing. Moreover, the Fe-Ni alloy is marketed with brand names, such as NS-5 and D-1 (made by NEOMAX material company), for example. Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal), EL-3 (manufactured by NEOMAX Material).

  In particular, the thermal expansion coefficient of the Fe—Ni-based alloy (that is, the thermal expansion coefficient of the first reinforcing member 4) is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, and preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less. It is more preferable that it is 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  Further, the absolute value of the difference in thermal expansion coefficient between the Fe—Ni-based alloy and the semiconductor element 3 (the absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3) is 7 ppm / ° C. or less. Is preferably 5 ppm / ° C. or less, more preferably 2 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, the Fe—Ni-based alloy preferably has a Ni content of 30 wt% or more and 50 wt% or less, and the Ni content is 35 wt% or more and 45 wt% or less. Is more preferable. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, the Fe—Ni-based alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, and more preferably a total content of Fe and Ni is 90 wt% or more and 100 wt% or less. . That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.

  Moreover, the surface of the 1st reinforcement member 4 may be roughened from a heat-dissipating viewpoint. If the surface of the first reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the first reinforcing member 4 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.

  The magnitude of the surface roughness of the first reinforcing member 4 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring board 2, the shape and size of the first reinforcing member 4, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper membrane | film | coat may be formed in the 1st reinforcement member 4 surface from a viewpoint of the adhesive improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  The average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.

  In the first embodiment, as shown in FIGS. 1 and 2, a thermally conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a heat conductive material 6 is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material.

  Examples of the inorganic filler (inorganic filler) used in the heat conductive material 6 (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, Oxides such as magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate Carbonates such as dolomite and dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate and calcium sulfite, talc, mica, clay, glass fiber, silicates such as calcium silicate, montmorillonite and bentonite, boron Zinc oxide, barium metaborate, aluminum borate, calcium borate, borate Borates such as sodium, carbon black, graphite, carbon, such as carbon fibers, other iron powder, copper powder, aluminum powder, zinc oxide, molybdenum sulfide, boron fiber, potassium titanate, and a lead zirconate titanate. In addition, when what has electroconductivity as an inorganic filler is used, the insulation process is performed to the site | part which the heat conductive material 6 contacts as needed.

  Among these, as the inorganic filler, from the viewpoint of excellent insulation and thermal conductivity, oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.

  Examples of the resin material used for the heat conductive material 6 (resin composition) include various thermoplastic resins and various thermosetting resins.

  Examples of the thermoplastic resin used for the heat conductive material 6 (resin composition) include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66). , Nylon 610, Nylon 612, Nylon 11, Nylon 12, Nylon 6-12, Nylon 6-66), liquid crystalline polymers such as thermoplastic polyimide, aromatic polyester, polyphenylene oxide, polyphenylene sulfide, polycarbonate, polymethyl methacrylate, polyether , Polyether ether ketone, polyether imide, polyacetal, styrene, polyolefin, polyvinyl chloride, polyurethane, polyester, polyamide, polybutadiene, Various thermoplastic elastomers such as polyisoprene-based, fluororubber-based, chlorinated polyethylene, etc., or copolymers, blends, polymer alloys, etc. mainly composed of these are included, one or more of these Can be mixed and used.

  Moreover, as a thermosetting resin used for the heat conductive material 6 (resin composition), for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resins etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.

  Among these, as the resin material used for the heat conductive material 6 (resin composition), it is preferable to use a thermosetting resin (particularly, a liquid that forms a liquid before curing), more preferably a phenol resin or an epoxy resin. It is particularly preferable to use a phenol resin. Thereby, the thermal conductive material 6 can be filled between the first reinforcing member 4 and the semiconductor element 3 without a gap, and the thermal expansion coefficient of the thermal conductive material 6 can be effectively suppressed.

  Such phenolic resins include phenolic novolac resins, cresol novolac resins, bisphenol A novolac resins and other novolac type phenol resins, unmodified resole phenolic resins, oil-modified resole phenolic resins modified with tung oil, linseed oil, walnut oil, etc. Examples thereof include phenolic resins such as resol type phenolic resins.

  In addition, the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.

  This 2nd reinforcement member 5 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 2nd reinforcement member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The second reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21, similar to the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  The second reinforcing member 5 is provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. Part 53. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  In the first embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the first embodiment, the heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  Similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

In particular, the second reinforcing member 5 is made of an Fe—Ni alloy.
As the Fe—Ni alloy, the same material as the first reinforcing member 4 described above can be used.

  Further, the Fe—Ni based alloy constituting the second reinforcing member 5 may be different from the Fe—Ni based alloy constituting the first reinforcing member 4, but the Fe—Ni based alloy constituting the first reinforcing member 4. Preferably it is the same as the alloy. Thereby, the thermal expansion difference of both surfaces of the wiring board 2 can be prevented or suppressed.

  In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  From this point of view, the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.

  Further, the surface of the second reinforcing member 5 may be roughened from the viewpoint of heat dissipation. If the surface of the second reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the second reinforcing member 5 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.

  The magnitude of the surface roughness of the second reinforcing member 5 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring board 2, the shape and size of the second reinforcing member 5, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper film may be formed in the 2nd reinforcement member 5 surface from a viewpoint of adhesiveness improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape and size of the reinforcing member, the type of the resin material, etc. Can be implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  In addition, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and capable of surface treatment for improving adhesion.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.

Such an insulating material 81 has an insulating property and includes a resin material.
Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a solder bonding resin having thermosetting properties.

  Such a solder bonding resin (hereinafter also referred to as “curing flux”) acts as a flux at the time of solder bonding, and then is cured by heating to act as a reinforcing material for the solder bonding portion. Solder bonding resin removes harmful substances such as solder joint surfaces and oxides of solder materials during solder joining, protects the solder joint surfaces, and refines the solder materials to provide good strength and good strength. In addition, the solder bonding resin does not need to be removed by washing after solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.

  Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.

  Although there is no restriction | limiting in particular as resin (A) which has a phenolic hydroxyl group, For example, a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, a polyvinyl phenol resin etc. can be mentioned.

  In the curable flux, the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened | cured material which has sufficient physical property cannot be obtained, and there exists a possibility that joining strength and reliability may fall.

  Further, the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as oxides on the solder and the metal surface by its reducing action, and therefore effectively acts as a solder joint flux.

  Moreover, as a hardening | curing agent (B) of resin (A) which has a phenolic hydroxyl group, an epoxy compound, an isocyanate compound, etc. can be mentioned, for example. Examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolak, alkylphenol novolak, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.

  The compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group and isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. When the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, thereby reducing the bonding strength and reliability. There is. When the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxides on the solder and the metal surface is lowered, and there is a possibility that the solderability is deteriorated.

  Such a solder bonding resin (curable flux) is formed because a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. It is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and soldering with high joining strength and reliability is possible. .

  In addition to the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin, the solder bonding resin as described above is dispersed in a microcrystalline state as a curable antioxidant (C). Compound (D) having phenolic hydroxyl group, curing agent (E), solvent (F), curing catalyst, silane coupling agent for improving adhesion and moisture resistance, and elimination for preventing voids It may contain a foaming agent or a liquid or powder flame retardant.

  According to the semiconductor package 1 configured as described above, both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased. In particular, since the coefficient of thermal expansion of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring substrate 2, the semiconductor device 3 is provided over the entire surface of the wiring substrate 2 in the same manner as the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the semiconductor element 3 and the semiconductor element 3.

  Moreover, since the thickness of the wiring board 2 can be reduced, the thermal conductivity in the thickness direction of the wiring board 2 can be increased. Therefore, the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.

  For this reason, since the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed, the warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is also suppressed in this respect. Or it can be prevented.

(1-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 4A to 4G.
[1]
First, as shown to FIG. 4A, the laminated body of 221 A of metal layers and prepreg 211A is prepared, and the 1st reinforcement member 4 is affixed on the surface at the side of the prepreg 211A of the laminated body.

  Here, the prepreg 211A is for forming the insulating layer 211 of the wiring board 2 described above, and the base material is impregnated with an uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.

  The metal layer 221 </ b> A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as the constituent material of the conductor pattern 221.

[2]
Next, as shown in FIG. 4B, a through hole 2111 (via hole) is formed in the prepreg 211A.

  A method for forming the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.

  Here, for example, a CO2 laser, a UV-YAG laser, or the like can be used as the laser.

  The through hole 2111 can also be formed by machining such as a drill.

[3]
Next, as shown in FIG. 4C, conductor posts 231 are formed in the through holes 2111.

  The method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.

[4]
Next, as shown in FIG. 4D, the conductive layer 221 is formed by patterning the metal layer 221A.

  The patterning method is not particularly limited, but etching is preferably used.

  As described above, the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.

[5]
Next, in the same manner as in the above steps [1] to [4], prepregs for forming the insulating layers 212, 213, 214, and 215 and the conductor patterns 222, 223, and 224 and laminates made of metal layers are respectively prepared. Then, conductor patterns 222, 223, 224 and conductor posts 232, 233, 234, 235 are formed. In addition, after the prepregs for the insulating layers 211, 212, 213, 214, and 215 are stacked, the heat transfer post 24 is formed using the same method as the conductor posts 231, 232, 233, 234, and 235. Thereafter, the prepreg for the insulating layers 211, 212, 213, 214, and 215 is cured (completely cured) to obtain the wiring board 2 as shown in FIG. 4E.

  Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.

  A method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, and for example, heat treatment is preferably used.

  The heat transfer post 24 is formed at the same time as the conductor posts 231, 232, 233, 234, and 235, and the heat transfer post is formed on the prepreg for the insulating layers 211, 212, 213, 214, and 215. These heat transfer posts may be connected and formed by laminating these prepregs.

[6]
Next, after applying an insulating material 81A to the lower surface of the wiring board 2, a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.

  Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. for 10 to 60 seconds. .

  The insulating material 81A is for forming the insulating material 81 described above, and is cured by heating, for example.

  When forming the insulating material 81, for example, as shown in FIG. 4F, the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. The insulating material 81 is obtained.

  The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.

  At this time, the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.

[7]
Next, as shown in FIG. 4G, the second reinforcing member 5 is joined to the lower surface of the wiring board 2. In addition, after applying an underfill material to the upper surface of the wiring board 2, the semiconductor element 3 is joined by solder reflow through the metal bumps 31. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Further, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
Thereafter, a thermally conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4.
The semiconductor package 1 is obtained as described above.

(1-3) Semiconductor Device Next, a semiconductor device manufacturing method and a semiconductor device will be described based on preferred embodiments.

FIG. 5 is a cross-sectional view schematically showing the semiconductor device according to the first embodiment.
As shown in FIG. 5, the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.

  In such a semiconductor device 100, the metal bumps 71 of the semiconductor package 1 are joined to terminals (not shown) of the mother board 200. As a result, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.

  Further, the heat transfer bumps 91 of the semiconductor package 1 are joined to the heat radiation terminals (not shown) of the mother board 200. The heat of the semiconductor package 1 can be efficiently released to the mother board 200 through this joint. When such a heat transfer bump 91 is made of the same material as that of the metal bump 71 described above, the heat transfer bump 91 can be bonded to the mother board 200 at the same time as the metal bump 71 is bonded.

  According to the semiconductor device 100 as described above, since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the first embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.

  Moreover, although 1st Embodiment demonstrated the case where both the 1st reinforcement member 4 and the 2nd reinforcement member 5 were comprised with the Fe-Ni type-alloy, the 1st reinforcement member 4 or the 2nd reinforcement member 5 is the same. You may be comprised with materials other than a Fe-Ni type alloy.

  Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted. In this case, a reinforcing member made of an Fe—Ni alloy may be bonded to any one surface of the wiring board 2.

  In the first embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5, but, for example, provided outside the substrate 21. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Moreover, the opening part formed in the 2nd reinforcement member 5 does not need to respond | correspond one-to-one with each metal bump 71. FIG. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor package of the first embodiment, the reinforcing member made of the Fe—Ni-based alloy has excellent rigidity and heat dissipation and a low coefficient of thermal expansion.

  By joining such a reinforcing member to the surface of the wiring board (interposer) on the semiconductor element side, the wiring board (interposer) is also reinforced by the reinforcing member in parts other than the part joined to the semiconductor element. The rigidity of the entire semiconductor package is increased.

  Further, by bonding the reinforcing member to the surface of the wiring board opposite to the semiconductor element, the difference in thermal expansion between both surfaces of the wiring board can be prevented or suppressed.

  For this reason, it is possible to suppress or prevent the warpage of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element.

  Further, it is not necessary to increase the rigidity of the wiring board itself, and the thickness of the wiring board can be reduced, so that the thermal conductivity in the thickness direction of the wiring board can be increased. Therefore, the semiconductor package of the present invention can release heat from the semiconductor element through the wiring board, and is excellent in heat dissipation. Thereby, since the temperature rise of the semiconductor element and the wiring board can be suppressed, the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element can also be suppressed or prevented.

  Moreover, according to the semiconductor device of 1st Embodiment, since the semiconductor package as mentioned above is provided, it is excellent in reliability.

(2) Second Embodiment Hereinafter, the semiconductor package of the second embodiment will be described with a focus on differences from the first embodiment, and description of similar matters will be omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(2-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  6 is a cross-sectional view schematically showing a semiconductor package according to the second embodiment, FIG. 2 is a top view showing the semiconductor package shown in FIG. 6, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. 7A to 7G are diagrams showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. 2 to 3 and 6 to 8, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 6, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, the wiring substrate (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. 1 The overall rigidity is increased. As a result, it is possible to prevent or suppress warping associated with thermal expansion or thermal contraction of the wiring board 2.

  In particular, as will be described in detail later, the first reinforcing member 4 and the second reinforcing member 5 are bonded to the wiring board 2 via an adhesive (adhesive layer), respectively. Can be low. Therefore, stress between the first reinforcing member 4 and the wiring board 2 and between the second reinforcing member 5 and the wiring board is alleviated, and the first reinforcing member 4 and the second reinforcing member 5 are connected to the wiring board 2. It can be prevented from peeling off.

  Further, the thermal conductivity of the adhesive layer can be increased, and the heat of the wiring board 2 can be efficiently transmitted to the first reinforcing member 4 and the second reinforcing member 5 through the adhesive layer. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
Since the wiring board of the second embodiment is the same as the wiring board of the first embodiment except for the following points, the description thereof is omitted.

According to the first embodiment, “the heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5. The reinforcing member 4 and the second reinforcing member 5 are connected. "
In contrast, the heat transfer post 24 of the second embodiment has an upper end in contact with the adhesive layer 300 and a lower end in contact with the adhesive layer 400. Thus, each heat transfer post 24 is thermally connected to the first reinforcing member 4 via the adhesive layer 300 and is also thermally connected to the second reinforcing member 5 via the adhesive layer 400.

[Semiconductor element]
Since the semiconductor device of the first embodiment is the same as that of the first embodiment, description thereof is omitted.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.

  The first reinforcing member 4 and the substrate 21 are bonded via an adhesive layer 300. In this way, the semiconductor package 1 can be easily manufactured by bonding the first reinforcing member 4 and the substrate 21 using an adhesive.

  The adhesive layer 300 is made of a cured product of an adhesive (resin composition) containing a resin material and an inorganic filler. That is, the adhesive layer 300 includes a resin material and an inorganic filler.

  Examples of the inorganic filler (inorganic filler) used for the adhesive (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, Oxides such as metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate, dolomite, Carbonate such as dosonite, sulfate or sulfite such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, silicate such as calcium silicate, montmorillonite, bentonite, zinc borate, Barium metaborate, aluminum borate, calcium borate, sodium borate Borate such as beam, carbon black, graphite, carbon, such as carbon fibers, other iron powder, copper powder, aluminum powder, zinc oxide, molybdenum sulfide, boron fiber, potassium titanate, and a lead zirconate titanate.

  Among these, as the inorganic filler, from the viewpoint of excellent insulation and thermal conductivity, oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.

  The inorganic filler preferably has a spherical shape, and the average particle size is preferably 0.05 μm or more and 50 μm or less, and more preferably 0.1 μm or more and 5 μm or less. Thereby, the fluidity | liquidity of an adhesive agent can be made excellent.

  Examples of the resin material used for the adhesive (resin composition) include various thermoplastic resins and various thermosetting resins.

  Examples of the thermoplastic resin used for the adhesive (resin composition) include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66, nylon 610). Nylon 612, Nylon 11, Nylon 12, Nylon 6-12, Nylon 6-66), Thermoplastic polyimide, Aromatic polyester and other liquid crystal polymers, Polyphenylene oxide, Polyphenylene sulfide, Polycarbonate, Polymethyl methacrylate, Polyether, Polyether Ether ketone, polyether imide, polyacetal, styrene, polyolefin, polyvinyl chloride, polyurethane, polyester, polyamide, polybutadiene, transpoly Various types of thermoplastic elastomers such as plains, fluororubbers, chlorinated polyethylenes, etc., or copolymers, blends, polymer alloys, etc. mainly composed of these are mentioned. It can be used by mixing.

  Examples of the thermosetting resin used for the adhesive (resin composition) include epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, and polyurethane resin. 1 type or 2 types or more of these can be mixed and used.

  Among them, as the resin material used for the adhesive (resin composition), it is preferable to use a thermosetting resin (particularly, a liquid that forms a liquid before curing), more preferably a phenol resin or an epoxy resin, more preferably a phenol resin. It is particularly preferable to use Thereby, the adhesive layer 300 can be formed between the first reinforcing member 4 and the substrate 21 without a gap, and the thermal expansion coefficient of the adhesive layer 300 can be effectively suppressed.

  Such phenolic resins include phenolic novolac resins, cresol novolac resins, bisphenol A novolac resins and other novolac type phenol resins, unmodified resole phenolic resins, oil-modified resole phenolic resins modified with tung oil, linseed oil, walnut oil, etc. Examples thereof include phenolic resins such as resol type phenolic resins.

  The adhesive layer 300 has an elastic modulus at 25 ° C. of preferably 0.5 MPa or more and 10 GPa or less, and more preferably 1 MPa or more and 3 GPa or less. Thereby, the stress between the 1st reinforcement member 4 and the wiring board 2 can be relieve | moderated effectively.

  On the other hand, when the elastic modulus exceeds the upper limit value, the stress between the first reinforcing member 4 and the wiring board 2 can be alleviated depending on the difference in thermal expansion coefficient between the first reinforcing member 4 and the wiring board 2. Instead, the first reinforcing member 4 may be peeled off from the wiring board 2. Moreover, the filling amount of an inorganic filler increases too much, and the adhesive strength of the contact bonding layer 300 shows the tendency to fall. On the other hand, when the elastic modulus is less than the lower limit value, the filling amount of the inorganic filler becomes too small, and the thermal conductivity of the adhesive layer 300 tends to decrease.

  The thermal conductivity of the adhesive layer 300 is preferably 0.5 W / (m · K) or more and 100 W / (m · K) or less, preferably 1 W / (m · K) or more and 50 W / (m · K). The following is more preferable. Thereby, the thermal conductivity of the adhesive layer 300 can be made excellent.

  On the other hand, if the thermal conductivity is less than the lower limit, depending on the thickness of the adhesive layer 300, the thermal conductivity between the first reinforcing member 4 and the wiring board 2 is not good, and the semiconductor package 1 It shows a tendency for heat dissipation to decrease. On the other hand, when the thermal conductivity exceeds the upper limit, the filling amount of the inorganic filler in the adhesive layer 300 increases so that the adhesive strength of the adhesive layer 300 tends to decrease.

  The content of the resin material in the adhesive layer 300 varies depending on the type of the resin material and inorganic filler used, the content of the additive, the thickness of the adhesive layer 300, the state of the adhesive surface, etc. From the viewpoint of realizing the elastic modulus and thermal conductivity of the adhesive layer 300, for example, it is preferably 20 wt% or more and 90 wt% or less, and more preferably 40 wt% or more and 70 wt% or less.

  Further, the content of the inorganic filler in the adhesive layer 300 is, for example, preferably 1 vol% or more and 80 vol% or less, and more preferably 10 vol% or more and 60 vol% or less.

  The average thickness of the adhesive layer 300 is preferably 5 μm or more and 150 μm or less, and more preferably 10 μm or more and 80 μm or less from the viewpoint of achieving both thermal conductivity and adhesiveness of the adhesive layer 300.

  The adhesive layer 300 (adhesive) may contain additives such as a curing agent, a curing aid, a catalyst, a cocatalyst, and a coupling agent in addition to the resin material and the inorganic filler as described above. Good.

  The first reinforcing member 4 joined to the wiring board 2 through such an adhesive layer 300 has a smaller thermal expansion coefficient than the board 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  In particular, the first reinforcing member 4 includes a first layer 42 and a second layer 43 bonded on the surface of the first layer 42 opposite to the substrate 21. In other words, in the first reinforcing member 4, the first layer 42 and the second layer 43 are laminated on the upper surface of the substrate 21 in this order.

  The bonding method between the first layer 42 and the second layer 43 is not particularly limited, and examples thereof include diffusion bonding, surface activated bonding, bonding with a brazing material, and the like. The first layer 42 can be formed by performing plating treatment such as electrolytic plating and electroless plating, sputtering treatment, and the like on the second layer 43.

  The first layer 42 has a function of improving adhesion with the adhesive layer 300 described above. Thereby, it can prevent that the 1st reinforcement member 4 peels from the wiring board 2. FIG.

  The constituent material of the first layer 42 is not particularly limited as long as it can improve the adhesion with the adhesive layer 300. However, copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, molybdenum It is preferable to use a metal material selected from the group consisting of molybdenum alloy, iron, iron alloy, silver, silver alloy, zinc, zinc alloy, gold, and gold alloy, and particularly preferably copper or copper alloy. Thereby, the adhesiveness with the contact bonding layer 300 of the 1st reinforcement member 4 can be improved.

  Moreover, it is preferable that the surface of the first layer 42 opposite to the second layer 43 is subjected to a roughening treatment. That is, the contact surface of the first layer 42 with the adhesive layer 300 is preferably roughened. Thereby, the adhesive strength of the 1st reinforcement member 4 and the contact bonding layer 300 can be improved according to an anchor effect. Such a roughening treatment may be performed on a surface other than the bonding surface of the first reinforcing member 4. In this case, heat dissipation can be improved by increasing the surface area of the first reinforcing member 4.

  The surface roughening treatment method is not particularly limited, and examples thereof include chemical chemical treatment and mechanical sandblast treatment.

  Moreover, the magnitude | size of the roughness of the surface by which the roughening process was carried out is although it does not specifically limit, For example, the surface roughness represented by arithmetic mean is about 0.1 micrometer or more and 100 micrometers or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

The first layer 42 has a thin film shape.
The thickness of the first layer 42 is not particularly limited, but is preferably 0.001 μm to 10 μm, and more preferably 0.1 μm to 3 μm. Thereby, it is possible to improve the adhesion of the first reinforcing member 4 to the adhesive layer 300 and to prevent the first layer 42 from adversely affecting the first reinforcing member 4.

  On the other hand, the second layer 43 has a function different from that of the first layer 42. Specifically, the second layer 43 is made of a material having a smaller thermal expansion coefficient than the first layer 42 and has a function of suppressing the thermal expansion of the first reinforcing member 4. Thereby, the curvature accompanying the thermal expansion or thermal contraction of the wiring board 2 can be prevented or suppressed.

  The second layer 43 preferably has a difference in thermal expansion coefficient with the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

  The constituent material of the second layer 43 is not particularly limited, and for example, a metal material, a ceramic material, or the like can be used, but it is preferable to use a metal material. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.

  More specifically, examples of Fe-Ni alloys include Fe-Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar). Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy. In addition, Fe-Ni-Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, and KV-25, and Nivarox. ing. Moreover, the Fe-Ni alloy is marketed with brand names, such as NS-5 and D-1 (made by NEOMAX material company), for example. Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal), EL-3 (manufactured by NEOMAX Material).

  The Fe—Co—Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr. For example, an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is used. Is mentioned. Note that the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.

  Further, the Fe—Co alloy is not particularly limited as long as it contains Fe and Co, and in addition to Fe and Co, one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt. It may contain seeds or two or more metals.

  Further, the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt. In addition to Fe and Pt, one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.

  Further, the Fe—Pd-based alloy is not particularly limited as long as it contains Fe and Pd. In addition to Fe and Pd, one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.

  The thermal expansion coefficient of the second layer 43 (first reinforcing member 4) is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less. More preferably, it is 1 ppm / ° C. or more and 5 ppm or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second layer 43 (first reinforcing member 4) and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm. More preferably, the temperature is not higher than / ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, the Fe—Ni-based alloy preferably has a Ni content of 30 wt% or more and 50 wt% or less, and the Ni content is 35 wt% or more and 45 wt% or less. Is more preferable. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, the Fe—Ni-based alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, and more preferably a total content of Fe and Ni is 90 wt% or more and 100 wt% or less. . That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  Further, when the thickness of the first layer 42 is t1 [mm] and the thickness of the second layer 43 is t2 [mm], the first layer 42 has a function of improving adhesion to the adhesive layer, and the second layer From the viewpoint of exhibiting the reinforcing function by 43 in a well-balanced manner, t2 / t1 is preferably 2 or more and 80000 or less, and more preferably 200 or more and 5000 or less.

  The thickness t2 of the second layer 43 is not particularly limited, but is about 0.02 mm or more and 0.8 mm or less.

  The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the reinforcing member 5 of the wiring board 2. Yes, but not particularly limited, for example, about 0.02 mm to 1 mm.

  In the second embodiment, the first reinforcing member 4 is composed of two layers, but the first reinforcing member 4 may be composed of three or more layers. For example, a layer similar to the first layer 42 may be provided on the upper surface of the second layer 43.

  The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that). It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

In the second embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. . Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.

  The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the second embodiment, the first reinforcing member 4 has an annular shape (more specifically, a square annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.

  Moreover, in 2nd Embodiment, as shown in FIG. 6 and FIG. 2, between the 1st reinforcement member 4 and the semiconductor element 3, the heat conductive material 6 is filled. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The heat conductive material 6 is the same as the heat conductive material 6 of the first embodiment.

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.

  The second reinforcing member 5 and the substrate 21 are bonded via an adhesive layer 400. In this manner, the semiconductor package 1 can be easily manufactured by bonding the second reinforcing member 5 and the substrate 21 using an adhesive.

  The adhesive layer 400 is composed of a cured product of an adhesive, and the same adhesive as that used for the adhesive layer 300 described above can be used as the adhesive.

  Further, the elastic modulus at 25 ° C. of the adhesive layer 400 is preferably 0.5 MPa or more and 10 GPa or less, and more preferably 1 MPa or more and 3 GPa or less, like the adhesive layer 300 described above. Thereby, the stress between the 2nd reinforcement member 5 and the wiring board 2 can be relieve | moderated effectively.

  Further, like the adhesive layer 300, the thermal conductivity of the adhesive layer 400 is preferably 0.5 W / (m · K) or more and 100 W / (m · K) or less, and preferably 1 W / (m · K) or more and 50 W. / (M · K) or less is more preferable. Thereby, the thermal conductivity of the adhesive layer 400 can be made excellent.

  The average thickness of the adhesive layer 400 is preferably 5 μm or more and 150 μm or less, and more preferably 10 μm or more and 80 μm or less from the viewpoint of achieving both thermal conductivity and adhesiveness of the adhesive layer 400.

  The second reinforcing member 5 joined to the wiring substrate 2 through the adhesive layer 400 has a smaller thermal expansion coefficient than the substrate 21 like the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  In particular, the second reinforcing member 5 includes a first layer 54 and a second layer 55 bonded on the surface of the first layer 54 opposite to the substrate 21. In other words, in the second reinforcing member 5, the first layer 54 and the second layer 55 are laminated on the lower surface of the substrate 21 in this order.

  The bonding method between the first layer 54 and the second layer 55 is not particularly limited, and examples thereof include diffusion bonding, surface activated bonding, bonding with a brazing material, and the like. The first layer 54 can be formed by performing plating treatment such as electrolytic plating and electroless plating, sputtering treatment, and the like on the second layer 55.

  The first layer 54 has a function of improving adhesion with the adhesive layer 400. As the constituent material of the first layer 54, the same constituent material as that of the first layer 42 of the first reinforcing member 4 described above can be used.

The first layer 54 has a thin film shape.
The thickness of the first layer 54 is not particularly limited, but is preferably 0.001 μm or more and 10 μm or less, and more preferably 0.1 μm or more and 3 μm or less. Thereby, it is possible to improve the adhesion of the second reinforcing member 5 to the adhesive layer 400 and to prevent the first layer 54 from adversely affecting the second reinforcing member 5.

  On the other hand, the second layer 55 has a function of suppressing the thermal expansion of the second reinforcing member 5. As the constituent material of the second layer 55, the same material as the constituent material of the second layer 43 of the first reinforcing member 4 described above can be used.

  Further, when the thickness of the first layer 54 is t3 [mm] and the thickness of the second layer 55 is t4 [mm], the first layer 54 has a function of improving adhesion to the adhesive layer, and the second layer From the viewpoint of exhibiting the reinforcing function by 55 in a well-balanced manner, t4 / t3 is preferably 2 or more and 80000 or less, and more preferably 200 or more and 5000 or less.

  The thickness t4 of the second layer 55 is not particularly limited, but is about 0.02 mm or more and 0.8 mm or less.

  Similarly to the first reinforcing member 4 described above, the second reinforcing member 5 (particularly the second layer 55) preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

  The thermal expansion coefficient of the second reinforcing member 5 (particularly the second layer 55) is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less. More preferably, it is 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 (particularly the second layer 55) and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less. More preferably, it is 2 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 1 mm or less.

  The second reinforcing member 5 is provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. Part 53. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  In the second embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the second embodiment, heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.

Such an insulating material 81 has an insulating property and includes a resin material.
This insulator 81 is the same as the insulator of the first embodiment.

  According to the semiconductor package 1 configured as described above, the wiring board (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 also in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased. As a result, it is possible to prevent or suppress warping associated with thermal expansion or thermal contraction of the wiring board 2.

  In particular, the elastic modulus of the adhesive layer 300 that joins the first reinforcing member 4 and the wiring board 2 and the adhesive layer 400 that joins the second reinforcing member 5 and the wiring board 2 may be relatively low. it can. Therefore, stress between the first reinforcing member 4 and the wiring board 2 and between the second reinforcing member 5 and the wiring board is alleviated, and the first reinforcing member 4 and the second reinforcing member 5 are connected to the wiring board 2. It can be prevented from peeling off.

  Further, the thermal conductivity of the adhesive layers 300 and 400 can be increased, and the heat of the wiring board 2 can be transferred to the first reinforcing member 4 via the adhesive layer 300 or the second reinforcing member 5 via the adhesive layer 400. Can be transmitted efficiently. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent.

(2-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 7A to 7G.
[1]
First, as shown in FIG. 7A, a laminate of a metal layer 221A and a prepreg 211A is prepared.

  Here, the prepreg 211A is for forming the insulating layer 211 of the wiring board 2 described above, and the base material is impregnated with an uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.

  The metal layer 221 </ b> A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as the constituent material of the conductor pattern 221.

[2]-[5]
This is the same as [2] to [5] of the semiconductor package manufacturing method of the first embodiment. 4B to 4E of the first embodiment correspond to FIGS. 7B to 7E of the second embodiment.

[6]
Next, as illustrated in FIG. 7F, the first reinforcing member 4 is attached to the upper surface of the wiring board 2. At that time, the wiring board 2 and the first reinforcing member 4 are bonded to each other through the adhesive layer 300 using the adhesive as described above. Similarly, the second reinforcing member 5 is bonded to the lower surface of the wiring board 2. At that time, the wiring board 2 and the second reinforcing member 5 are bonded to each other through the adhesive layer 400 using the adhesive as described above.

  Further, after applying an insulating material 81A to the lower surface of the wiring board 2, a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.

  Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. for 10 to 60 seconds. .

  The insulating material 81A is for forming the insulating material 81 described above, and is cured by heating, for example.

  When forming the insulating material 81, for example, as shown in FIG. 7F, the insulating material 81A is applied to the mounting portion of the metal ball 71A on the lower surface of the wiring substrate 2, and after soldering as described above, the insulating material is heated by heating. The insulating material 81 is obtained by curing 81A.

  The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.

  At this time, the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.

[7]
Next, as shown in FIG. 7G, after applying an underfill material to the upper surface of the wiring board 2, the semiconductor element 3 is bonded via the metal bumps 31 by solder reflow. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Further, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.

Thereafter, a thermally conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4.
The semiconductor package 1 is obtained as described above.

(2-3) Semiconductor Device Next, a semiconductor device manufacturing method and a semiconductor device will be described based on preferred embodiments.

  FIG. 8 is a cross-sectional view schematically showing a semiconductor device according to the second embodiment. Since the semiconductor device of the second embodiment is the same as the semiconductor device of the first embodiment, description thereof is omitted.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the second embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.

  Moreover, although 2nd Embodiment demonstrated the case where the 1st reinforcement member 4 and the 2nd reinforcement member 5 each have a layer (1st layer) which improves adhesiveness with an adhesive agent, for example, a 1st reinforcement member At least one of the reinforcing members 4 and the second reinforcing member 5 does not have a layer (first layer) that improves the adhesion to the adhesive, and may be formed of one layer.

Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted.
In the second embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5, but, for example, provided outside the substrate 21. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Moreover, the opening part formed in the 2nd reinforcement member 5 does not need to respond | correspond one-to-one with each metal bump 71. FIG. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor package of the second embodiment, since the wiring board (interposer) is reinforced by the reinforcing member even in a portion other than the portion joined to the semiconductor element, the rigidity of the entire semiconductor package is increased. As a result, warpage associated with thermal expansion or contraction of the wiring board can be prevented or suppressed.

  In particular, the elastic modulus of the adhesive layer can be made relatively low. Therefore, the stress between the reinforcing member and the wiring board can be relaxed, and the reinforcing member can be prevented from peeling off from the wiring board.

  Further, the thermal conductivity of the adhesive layer can be increased, and the heat of the wiring board can be efficiently transmitted to the reinforcing member through the adhesive layer. Therefore, the heat dissipation of the semiconductor package can be made excellent.

  Further, according to the semiconductor device of the second embodiment, since the semiconductor package as described above is provided, the reliability is excellent.

(3) Third Embodiment (3-1-A) Third Embodiment A Hereinafter, the semiconductor packages of the third embodiment to the third embodiment will be described with a focus on differences from the first and second embodiments. The explanation of matters is omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(3-1-A-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  9 is a cross-sectional view schematically showing the semiconductor package according to the 3A embodiment, FIG. 2 is a top view showing the semiconductor package shown in FIG. 9, and FIGS. 10A to 10G are diagrams for manufacturing the semiconductor package shown in FIG. It is a figure which shows an example of a method. In the following description, for convenience of explanation, the upper side in FIG. 9 is referred to as “upper” and the lower side is referred to as “lower”. 2 to 3 and 9 to 12, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 9, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, and a reinforcing member 4.

  In this semiconductor package 1, as will be described later, the reinforcing member 4 includes a first layer 42 and a second layer 43 having different thermal expansion coefficients. Therefore, due to the force acting on the wiring board 2 due to the difference in thermal expansion coefficient between the first layer 42 and the second layer 43, the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is caused. The acting force can be offset or alleviated. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  In addition, since it is not necessary to separately provide a reinforcing member for preventing warpage of the wiring board 2 on the surface of the wiring board 2 opposite to the semiconductor element 3, the configuration of the semiconductor package 1 can be simplified. Therefore, the semiconductor package 1 can be easily manufactured and the semiconductor package 1 can be made inexpensive.

  In this specification, unless otherwise specified, the thermal expansion coefficient refers to a thermal expansion coefficient of 30 ° C. to 300 ° C. in a direction (plane direction) parallel to the plate surface of the wiring board 2.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]

Since the third embodiment A is the same as the first embodiment except for the following, the description thereof is omitted.
In the first embodiment, the substrate 21 is formed with a plurality of via holes penetrating in the thickness direction, and the heat transfer posts 24 are provided in the respective via holes. In the 3A embodiment, the heat transfer posts are provided. It is not done.

  Each insulating layer 211, 212, 213, 214, 215 of the third embodiment may be composed of only a resin composition without including a base material.

  In addition, an insulating material 81 is provided around each metal bump 71 of the 3A embodiment. The insulating material 81 is formed so as to surround the periphery of the metal bump 71 and is bonded to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71. The insulating material 81 of the 3A embodiment is the same as the insulating material 81 of the first embodiment.

[Semiconductor element]
Since the semiconductor device of the 3A embodiment is the same as the semiconductor device of the first embodiment, description thereof is omitted.

[Reinforcing member]
The reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.

  The reinforcing member 4 and the substrate 21 can be bonded via an adhesive. Thereby, installation of the reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  The reinforcing member 4 has a plate shape. Thereby, the structure of the reinforcement member 4 can be made simple and small.

  In particular, the reinforcing member 4 includes a first layer 42 and a second layer 43 bonded on the surface of the first layer 42 opposite to the substrate 21. In other words, in the reinforcing member 4, the first layer 42 and the second layer 43 are laminated on the upper surface of the substrate 21 in this order.

  The bonding method between the first layer 42 and the second layer 43 is not particularly limited, and examples thereof include diffusion bonding, surface activated bonding, bonding with a brazing material, and the like.

  The first layer 42 and the second layer 43 have different thermal expansion coefficients. As a result, the reinforcing member 4 exhibits a bimetal-like effect as the temperature changes, and a force (first force) acting on the wiring board 2 due to the difference in thermal expansion coefficient between the first layer 42 and the second layer 43. ), The force (second force) acting on the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be offset or alleviated. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  The difference between the thermal expansion coefficient of the first layer 42 and the thermal expansion coefficient of the second layer 43 is set so as to prevent or suppress the warpage associated with the thermal expansion or thermal contraction of the substrate 21 (or the wiring substrate 2). Has been.

  More specifically, in the 3A embodiment, it is preferable that the thermal expansion coefficient of the second layer 43 is larger than the thermal expansion coefficient of the first layer 42.

  Usually, the thermal expansion coefficient of the wiring board 2 is larger than the thermal expansion coefficient of the semiconductor element 3. Therefore, the wiring board 2 tends to thermally expand more than the semiconductor element 3, and a force (second force) in a direction in which the outer peripheral portion of the wiring board 2 is displaced toward the semiconductor element 3 is generated. On the other hand, when the thermal expansion coefficient of the second layer 43 is larger than the thermal expansion coefficient of the first layer 42, the second layer 43 tends to expand larger than the first layer 42, and the outer peripheral portion of the wiring board 2 is a semiconductor element. A force in the direction of displacement to the opposite side of 3 (a first force in the direction opposite to the second direction) is generated. Therefore, these two forces (first force and second force) can be canceled out. As a result, warpage due to thermal expansion of the wiring board 2 can be prevented or suppressed.

  The absolute value of the difference between the thermal expansion coefficient of the first layer 42 and the thermal expansion coefficient of the second layer 43 is the difference between the thermal expansion coefficient of the wiring board 2 and the thermal expansion coefficient of the semiconductor element 3, Although it is set according to the rigidity, etc., and is not particularly limited, it is 0.5 ppm / ° C. or more and 20 ppm / ° C. or less from the viewpoint of effectively preventing the warping of the wiring board 2 as described above. More preferred.

  Further, from the viewpoint of effectively preventing the warping of the wiring board 2 as described above (from the viewpoint of efficiently generating the first force), the thickness of the first layer 42 is t1 [mm], and the second layer When the thickness of 43 is t2 [mm], t2 / t1 is preferably 0.03 or more and 34 or less, and more preferably 0.3 or more and 10 or less. On the other hand, if t2 / t1 is out of the above range, the first layer 42 or the second layer 43 is too thin, and the difference in thermal expansion coefficient between the first layer 42 and the second layer 43 is large. In addition, it is difficult for the reinforcing member 4 to exhibit a bimetal effect as described above.

  The thickness t1 of the first layer 42 is not particularly limited, but is about 0.03 mm or more and 1 mm or less. Further, the thickness t2 of the second layer 43 is not particularly limited, but is about 0.03 mm or more and 1 mm or less.

  Further, the reinforcing member 4 (particularly the first layer 42) preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the reinforcing member 4 can integrally reinforce the wiring board 2 and suppress the thermal expansion of the entire semiconductor package 1.

  The constituent material of the reinforcing member 4 (the constituent material of the first layer 42 and the second layer 43) is not particularly limited as long as it has a thermal expansion coefficient as described above. Although a material etc. can be used, it is preferable to use a metal material. When the reinforcing member 4 is made of a metal material, the heat dissipation of the reinforcing member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.

  In particular, when the thermal expansion coefficient of the first layer 42 is smaller than the thermal expansion coefficient of the second layer 43, the first layer 42 is preferably made of an alloy containing Fe.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included. More specific Fe—Ni-based alloys are the same as the specific examples given in the second embodiment.

  In particular, the thermal expansion coefficient of the Fe—Ni-based alloy (particularly, the thermal expansion coefficient of the first layer 42) is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less. It is more preferable that it is 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 4 can be reduced and the wiring board 2 can be reinforced as a unit. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the Fe-Ni alloy and the semiconductor element 3 (particularly, the absolute value of the difference in thermal expansion coefficient between the first layer 42 and the semiconductor element 3) is 7 ppm / ° C. or less. Is preferably 5 ppm / ° C. or less, more preferably 2 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 4 can be reduced and the wiring board 2 can be reinforced as a unit. Therefore, warping of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, the Fe—Ni-based alloy preferably has a Ni content of 30 wt% or more and 50 wt% or less, and the Ni content is 35 wt% or more and 45 wt% or less. Is more preferable. Thereby, the thermal expansion coefficient of the reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, the Fe—Ni-based alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, and more preferably a total content of Fe and Ni is 90 wt% or more and 100 wt% or less. . That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The constituent material of the second layer 43 is preferably different from the constituent material of the first layer 42. Thereby, the difference in thermal expansion coefficient between the first layer 42 and the second layer 43 as described above can be easily set.

  When the thermal expansion coefficient of the second layer 43 is larger than the thermal expansion coefficient of the first layer 42, the constituent material of the second layer 43 may be an alloy containing Fe as described above, or Fe You may use metals other than the alloy containing.

  The average thickness of the reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the reinforcing member 4 and the reinforcing member 5 of the wiring board 2, and is particularly limited. For example, it is about 0.02 mm or more and 2 or less.

  The surface (that is, the upper surface) opposite to the substrate 21 of the reinforcing member 4 is the same surface as the surface (that is, the upper surface) opposite to the substrate 21 of the semiconductor element 3 or the substrate 21 side (that is, the lower side). ). Accordingly, when the semiconductor element 3 is installed after the reinforcement member 4 is installed in the manufacture of the semiconductor package 1, the semiconductor element 3 can be easily installed.

  In the 3A embodiment, the surface of the reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) are located on the same surface. Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the reinforcement member 4, the structure can be installed stably.

The reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.
The reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the 3A embodiment, the reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the reinforcement member 4 can be made excellent.

  In addition, the distance between the reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is constant over the entire circumference of the semiconductor element 3. It is formed to become. Thereby, the integrity of the reinforcing member 4 and the semiconductor element 3 is increased, and the reinforcing effect of the wiring board 2 by these is suitably exhibited. Further, heat transfer from the semiconductor element 3 to the reinforcing member 4 through the heat conductive material 6 described later can be efficiently and uniformly generated.

  Further, from the viewpoint of heat dissipation, the surface (upper surface) of the second layer 43 of the reinforcing member 4 may be roughened. If the surface of the second layer 43 of the reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases. The surface roughening method of the 2nd layer 43 of the reinforcement member 4 is not specifically limited, For example, it can implement by chemical chemical | medical solution process, mechanical sandblasting, etc.

  The magnitude of the surface roughness of the second layer 43 of the reinforcing member 4 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the reinforcing member 4, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper film may be formed in the surface of the 1st layer 42 and the 2nd layer 43 of the reinforcement member 4 from a viewpoint of the adhesive improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape, size, type of resin material, etc. of the reinforcing member 4. Can be implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  In addition, the average thickness of the copper film does not affect the thermal expansion coefficient of the reinforcing member 4 and is preferably as thin as possible in a range where surface treatment for improving adhesion can be performed.

  In the 3A embodiment, as shown in FIGS. 9 and 2, the heat conductive material 6 is filled between the reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The thermally conductive material 6 of the 3A embodiment is the same as the thermally conductive material 6 of the first embodiment.

  According to the semiconductor package 1 configured as described above, due to the force acting on the wiring board 2 due to the difference in thermal expansion coefficient between the first layer 42 and the second layer 43 of the reinforcing member 4, The force acting on the wiring board 2 due to the difference in thermal expansion coefficient with the semiconductor element 3 can be offset or alleviated. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  In addition, since it is not necessary to separately provide a reinforcing member for preventing warpage of the wiring board 2 on the surface of the wiring board 2 opposite to the semiconductor element 3, the configuration of the semiconductor package 1 can be simplified. Therefore, the semiconductor package 1 can be easily manufactured and the semiconductor package 1 can be made inexpensive.

(3-1-A-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 10A to 10G.
[1]-[4]
Since [1] to [4] of the semiconductor package manufacturing method of the 3A embodiment are the same as those of the semiconductor package manufacturing method of the first embodiment, description thereof is omitted. 10A to 10D correspond to FIGS. 4A to 4D.

[5]
Next, in the same manner as in the above steps [1] to [4], prepregs for forming the insulating layers 212, 213, 214, and 215 and the conductor patterns 222, 223, and 224 and laminates made of metal layers are respectively prepared. Then, conductor patterns 222, 223, 224 and conductor posts 232, 233, 234, 235 are formed. Thereafter, the prepreg for the insulating layers 211, 212, 213, 214, and 215 is cured (completely cured) to obtain the wiring board 2 as shown in FIG. 10E.

  Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.

  A method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, and for example, heat treatment is preferably used.

[6]
[6] of the semiconductor package manufacturing method according to the third embodiment is the same as the semiconductor package manufacturing method according to the first embodiment, and a description thereof will be omitted. Note that FIG. 10F corresponds to FIG. 4F.

[7]
Next, as shown in FIG. 10G, after applying an underfill material to the upper surface of the wiring substrate 2, the semiconductor element 3 is bonded via the metal bumps 31 by solder reflow. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Further, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.

Thereafter, a thermally conductive material 6 is filled between the semiconductor element 3 and the reinforcing member 4.
The semiconductor package 1 is obtained as described above.

(3-1-B) Third Embodiment Next, a third embodiment of the present invention will be described.

  FIG. 11 is a cross-sectional view schematically showing the semiconductor package according to the third embodiment, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. In the following description, for convenience of explanation, the upper side in FIG. 11 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 11, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the 3B embodiment will be described with a focus on differences from the 3A embodiment, and description of similar matters will be omitted. In FIG. 11, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the 3B embodiment is the same as that of the 3A embodiment except that the reinforcing member and the heat conductive material provided on the upper surface of the wiring board are omitted, and instead the reinforcing member is provided on the lower surface of the wiring board. Is almost the same.

  As shown in FIG. 11, in the semiconductor package 1 </ b> A, a reinforcing member (stiffener) 5 is bonded to the lower surface of the wiring substrate 2 (lower surface of the substrate 21). In the 3B embodiment, a reinforcing member for preventing warpage of the wiring board 2 is not provided on the upper surface of the wiring board 2.

  The reinforcing member 5 and the substrate 21 can be bonded via an adhesive. Thereby, installation of the reinforcing member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used, but those having excellent thermal conductivity are preferable, and the thermal conductive material 6 in the 3A embodiment is preferred. The same can be used.

  The reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21 as in the reinforcing member 4 of the 3A embodiment.

  The reinforcing member 5 has a plate shape. Thereby, the structure of the reinforcing member 5 can be made simple and small.

  In particular, the reinforcing member 5 includes a first layer 54 and a second layer 55 bonded on the surface of the first layer 54 opposite to the substrate 21. In other words, in the reinforcing member 5, the first layer 54 and the second layer 55 are laminated on the lower surface of the substrate 21 in this order.

  The first layer 54 and the second layer 55 have different thermal expansion coefficients. As a result, the reinforcing member 5 exhibits a bimetal-like effect as the temperature changes, and a force (first force) acting on the wiring board 2 due to the difference in thermal expansion coefficient between the first layer 54 and the second layer 55. ), The force (second force) acting on the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be offset or alleviated. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  The difference between the thermal expansion coefficient of the first layer 54 and the thermal expansion coefficient of the second layer 55 is set so as to prevent or suppress the warpage associated with the thermal expansion or thermal contraction of the substrate 21 (or the wiring substrate 2). Has been.

  More specifically, in the 3B embodiment, the thermal expansion coefficient of the second layer 55 is preferably smaller than the thermal expansion coefficient of the first layer 54.

  Usually, the thermal expansion coefficient of the wiring board 2 is larger than the thermal expansion coefficient of the semiconductor element 3. Therefore, the wiring board 2 tends to thermally expand more than the semiconductor element 3, and a force (second force) in a direction in which the outer peripheral portion of the wiring board 2 is displaced toward the semiconductor element 3 is generated. On the other hand, when the thermal expansion coefficient of the second layer 55 is made smaller than the thermal expansion coefficient of the first layer 54 (that is, when the thermal expansion coefficient of the first layer 54 is made larger than the thermal expansion coefficient of the second layer 55), The force in the direction in which the outer peripheral portion of the wiring substrate 2 is displaced to the side opposite to the semiconductor element 3 (first force in the direction opposite to the second direction) tries to expand more thermally than the second layer 55. Occurs. Therefore, these two forces (first force and second force) can be canceled out. As a result, warpage due to thermal expansion of the wiring board 2 can be prevented or suppressed.

  The absolute value of the difference between the thermal expansion coefficient of the first layer 54 and the thermal expansion coefficient of the second layer 55 is the difference between the thermal expansion coefficient of the wiring board 2 and the thermal expansion coefficient of the semiconductor element 3, or the reinforcing member 5. Although it is set according to the rigidity, etc., and is not particularly limited, it is 0.5 ppm / ° C. or more and 20 ppm / ° C. or less from the viewpoint of effectively preventing the warping of the wiring board 2 as described above. More preferred.

  Further, from the viewpoint of effectively preventing the warping of the wiring substrate 2 as described above (from the viewpoint of efficiently generating the first force), the thickness of the first layer 54 is t3 [mm], and the second layer When the thickness of 55 is t4 [mm], t4 / t3 is preferably 0.03 or more and 34 or less, and more preferably 0.3 or more and 10 or less. On the other hand, if t4 / t3 is out of the above range, the thickness of the first layer 54 or the second layer 55 is too thin, and the difference in thermal expansion coefficient between the first layer 54 and the second layer 55 is large. In addition, it is difficult for the reinforcing member 5 to exhibit the action like the bimetal as described above.

  The thickness t3 of the first layer 54 is not particularly limited, but is about 0.03 mm or more and 1 mm or less. The thickness t4 of the second layer 55 is not particularly limited, but is about 0.03 mm or more and 1 mm or less.

  The reinforcing member 5 (particularly the second layer 55) preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the reinforcing member 5 can integrally reinforce the wiring substrate 2 and suppress the thermal expansion of the entire semiconductor package 1A.

  In such a reinforcing member 5, the constituent material of the first layer 54 can be the same as the constituent material of the second layer 43 of the reinforcing member 4 of the 3A embodiment. Further, as the constituent material of the second layer 55, the same constituent material as that of the first layer 42 of the reinforcing member 4 of the 3A embodiment can be used.

  Specifically, the constituent material of the reinforcing member 5 (the constituent material of the first layer 54 and the second layer 55) is not particularly limited as long as it has a thermal expansion coefficient as described above. Although a material, a ceramic material, etc. can be used, it is preferable to use a metal material. When the reinforcing member 5 is made of a metal material, the heat dissipation of the reinforcing member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1A can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used as in the reinforcing member 4 of the 3A embodiment. From the viewpoint of realizing expansion, it is preferable to use an alloy containing Fe.

  In particular, when the thermal expansion coefficient of the second layer 55 is smaller than the thermal expansion coefficient of the first layer 54, the second layer 55 is preferably made of an alloy containing Fe.

  In particular, the thermal expansion coefficient of the reinforcing member 5 (particularly the thermal expansion coefficient of the second layer 55) is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, and preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less. More preferably, it is 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5 can be reduced, and the reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the reinforcing member 5 (particularly the second layer 55) and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5 can be reduced, and the reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The average thickness of the reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the reinforcing member 4 and the reinforcing member 5 of the wiring board 2, and is particularly limited. For example, it is about 0.02 mm or more and 2 or less.

  Moreover, the surface (lower surface) of the 2nd layer 55 of the reinforcement member 5 may be roughened from a heat-dissipating viewpoint. If the surface of the second layer of the reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases. The surface roughening method of the 2nd layer 55 of the reinforcement member 5 is not specifically limited, For example, it can implement by chemical chemical | medical solution processing, mechanical sandblasting, etc.

  The magnitude of the surface roughness of the second layer 55 of the reinforcing member 5 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the reinforcing member 5, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Further, from the viewpoint of improving the adhesion with the resin material, a copper film may be formed on the surfaces of the first layer 54 and the second layer 55 of the reinforcing member 5. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape, size, type of resin material, etc. of the reinforcing member 5. Can be implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  In addition, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the reinforcing member 5 and capable of surface treatment for improving adhesion.

  Further, the reinforcing member 5 is a portion provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. 53. By joining the portion 52 of the reinforcing member 5 and the wiring board 2 (board 21), the reinforcing member 5 can effectively reinforce the wiring board 2. Further, the rigidity of the reinforcing member 5 is increased by joining the portion 53 of the reinforcing member 5 and the wiring board 2.

  More specifically, as shown in FIG. 3, the reinforcing member 5 has a plurality of openings 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the reinforcing member 5 can be made excellent.

  In the 3B embodiment, each opening 51 has a circular shape in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the reinforcing member 5 can also be improved.

  The distance between the reinforcing member 5 and each metal bump 71 (the distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) is constant over the entire circumference of the metal bump 71. It is formed to become. Thereby, the integrity of the reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the third embodiment, heat transfer bumps 91 are provided on the lower surface of the reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to, for example, a mother board. Thereby, the heat of the reinforcing member 5 can be released to the outside (for example, a mother board).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  An insulating material 81 is provided (filled) between the reinforcing member 5 and each metal bump 71. Thereby, the contact between the reinforcing member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1A.

  The warpage caused by the thermal expansion of the wiring board 2 can also be prevented or suppressed by the semiconductor package 1A of the 3B embodiment as described above.

(3-2) Semiconductor Device Next, a semiconductor device manufacturing method and a semiconductor device will be described based on preferred embodiments.

FIG. 12 is a cross-sectional view schematically showing the semiconductor device according to the 3A embodiment.
As illustrated in FIG. 12, the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.

  In such a semiconductor device 100, the metal bumps 71 of the semiconductor package 1 are joined to terminals (not shown) of the mother board 200. As a result, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.

  According to the semiconductor device 100 as described above, since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the 3A embodiment, the reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. For example, a portion missing in a part of the periphery of the semiconductor element 3. (Notch) may be formed.

  In the third and third embodiments, the case where the reinforcing member is provided only on one surface of the wiring board has been described as an example, but the reinforcing member may be provided on both surfaces of the wiring board. In that case, each of the reinforcing members may include the first layer and the second layer having different thermal expansion coefficients, as in the case of combining the 3A embodiment and the 3B embodiment, or only one of the reinforcing members. May have a first layer and a second layer having different thermal expansion coefficients.

  Further, the opening formed in the reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  An intermediate layer may be provided between the first layer and the second layer of the reinforcing member. That is, the first layer and the second layer of the reinforcing member may be joined via the intermediate layer. In this case, the thermal expansion coefficient of the intermediate layer is preferably a value between the thermal expansion coefficient of the first layer and the thermal expansion coefficient of the second layer.

  According to the semiconductor packages of the third and third embodiments, the thermal expansion between the wiring board and the semiconductor element is caused by the force acting on the wiring board due to the difference in thermal expansion coefficient between the first layer and the second layer of the reinforcing member. The force acting on the wiring board due to the coefficient difference can be offset or alleviated. Therefore, it is possible to suppress or prevent the warpage of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element.

  In addition, according to the semiconductor devices of the 3A and 3B embodiments, since the semiconductor package as described above is provided, the reliability is excellent.

(4) Fourth Embodiment Hereinafter, a semiconductor package according to a fourth embodiment will be described with a focus on differences from the first to third embodiments, and description of similar matters will be omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(4-1) Semiconductor Package First, a semiconductor package according to a fourth embodiment will be described.

  13 is a cross-sectional view schematically showing a semiconductor package according to the fourth embodiment, FIG. 2 is a top view showing the semiconductor package shown in FIG. 13, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. 4A to 4G are diagrams showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of explanation, the upper side in FIG. 13 is referred to as “upper” and the lower side is referred to as “lower”. 2 to 4 (FIGS. 4A to 4G) and FIGS. 13 to 14, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 13, a semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, the wiring substrate (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. 1 The overall rigidity is increased. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. Therefore, such a semiconductor package 1 can have excellent electrical connection reliability.

  Further, as will be described in detail later, the first reinforcing member 4 and the second reinforcing member 5 each have two layers (first layer and second layer) having different characteristics (for example, workability), so that the semiconductor package 1 For example, when the first reinforcing member 4 and the second reinforcing member 5 are formed by punching, the generation of burrs can be prevented, and the process of removing burrs is not necessary.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
Since the wiring board in the fourth embodiment is the same as the wiring board in the first embodiment, the description thereof is omitted.

[Semiconductor element]
Since the semiconductor element in the fourth embodiment is the same as the semiconductor element in the first embodiment, description thereof is omitted.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded. As a result, the wiring substrate (interposer) 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, and thus the rigidity of the entire semiconductor package 1 is increased.

  This 1st reinforcement member 4 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 1st reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  In particular, the first reinforcing member 4 includes a first layer 42 and a second layer 43 bonded on the surface of the first layer 42 opposite to the substrate 21. In other words, in the first reinforcing member 4, the first layer 42 and the second layer 43 are laminated on the upper surface of the substrate 21 in this order.

  The bonding method between the first layer 42 and the second layer 43 is not particularly limited, and examples thereof include diffusion bonding, surface activated bonding, bonding with a brazing material, and the like.

  The first layer 42 and the second layer 43 have different characteristics (particularly processability). Thereby, workability | operativity at the time of manufacture of the semiconductor package 1 can be improved.

  For example, by appropriately setting the characteristics of the first layer 42 and the second layer 43, an effect of preventing the generation of burrs when the first reinforcing member 4 is formed by punching, or etching the first reinforcing member 4 is performed. When forming by this, the effect of improving workability can be brought about. Hereinafter, a case where the first reinforcing member 4 is formed by punching and a case where the first reinforcing member 4 is formed by etching will be described.

(When forming the first reinforcing member by punching)
When the first reinforcing member 4 is formed by punching, it is preferable that one of the first layer 42 and the second layer 43 is made of a material harder than the other. That is, it is preferable that one of the first layer 42 and the second layer 43 is made of a hard first material and the other is made of a second material that is softer than the first material.

  Thereby, when forming the 1st reinforcement member 4 using a punching process, generation | occurrence | production of a burr | flash can be prevented. In this case, a plate material (for example, a laminated metal plate) in which a layer made of the same constituent material as that of the first layer 42 and a layer made of the same constituent material as that of the second layer 43 are laminated is prepared. Punching is performed in a state where the plate material is placed on a punching apparatus so that the soft layer side is the upper die (punch) side and the hard layer side is the lower die (die) side. Thereby, the 1st reinforcement member 4 excellent in the dimensional accuracy can be easily manufactured using a punching process. Further, a step for removing burrs is not required, and the manufacture of the first reinforcing member 4 and, consequently, the manufacture of the semiconductor package 1 is simplified.

  The first layer 42 and the second layer 43 preferably include the first layer 42 made of the first material and the second layer 43 made of the second material. That is, the first layer 42 is preferably harder than the second layer 43. In this case, when the first reinforcing member 4 is formed by punching as described above, the corner of the second layer 43 opposite to the first layer 42 is rounded. Therefore, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed when the semiconductor package 1 is manufactured, the semiconductor element 3 can be installed easily. Further, in this case, since burrs generated at the corners of the first layer 42 opposite to the second layers 43 can be prevented, the burrs prevent the bonding between the first reinforcing member 4 and the wiring board 2. The wiring board 2 is not damaged.

  The first material is preferably more brittle than the second material. That is, the first material preferably has a lower ductility than the second material. Thereby, when forming the 1st reinforcement member 4 by stamping, generation | occurrence | production of a burr | flash can be prevented reliably.

  Further, from the viewpoint of preventing burrs as described above, the value of the elongation at break in the tensile test of the first material is smaller than the value of the elongation at break in the tensile test of the second material, and is 20% or more and 70% or less. Is preferred.

  When the first reinforcing member 4 is formed by punching, the thickness of the first layer 42 is set to t1 [mm] and the thickness of the second layer 43 is set to t2 [mm] from the viewpoint of preventing the burr as described above. mm], t2 / t1 is preferably 0.03 or more and 34 or less, and more preferably 0.1 or more and 10 or less. On the other hand, if t2 / t1 is outside the above range, the thickness of the first layer 42 or the second layer 43 is too thin to prevent the generation of burrs, or the characteristics required for the first reinforcing member 4 (Reinforcement, thermal expansion coefficient) may not be ensured.

  Moreover, when forming the 1st reinforcement member 4 by stamping, although thickness t1 of the 1st layer 42 is not specifically limited, It is about 0.03 mm or more and 1 mm or less. Further, the thickness t2 of the second layer 43 is not particularly limited, but is about 0.03 mm or more and 1 mm or less.

  In the fourth embodiment, the first reinforcing member 4 is composed of two layers, but the first reinforcing member 4 may be composed of three or more layers. For example, when the first reinforcing member 4 is composed of three layers, the outer layers may be harder than the intermediate layer.

(When forming the first reinforcing member by etching)
When the first reinforcing member 4 is formed by etching, the first layer 42 and the second layer 43 are preferably made of materials having different etching rates in the etching.

  Thereby, when forming the 1st reinforcement member 4 by etching (especially wet etching), the workability can be made excellent. In this case, a plate material (for example, a laminated metal plate) in which a layer made of the same constituent material as that of the first layer 42 and a layer made of the same constituent material as that of the second layer 43 are laminated is prepared. The plate material is wet etched.

  At that time, by performing etching from the side of the layer having the lower etching rate, the amount of side etching of the layer can be suppressed. Therefore, a narrow through hole can be formed even if etching is performed from one side. Also, for example, when one layer of a plate material has an extremely low etching rate relative to the other layer, one layer on the side with the slower etching rate is used as an etching stop layer, so that only the other layer penetrates. It is also possible to form the recesses in the first reinforcing member 4 with excellent dimensional accuracy. When such a recess is formed on the first layer 42 side, when the first reinforcing member 4 and the wiring board 2 are bonded with an adhesive, the adhesiveness can be improved by the anchor effect. Moreover, when such a recessed part is formed in the 2nd layer 43 side, the surface area of the 1st reinforcement member 4 can be enlarged and the heat dissipation of the 1st reinforcement member 4 can be improved.

  By using such etching, the first reinforcing member 4 can be formed without using the punching process as described above. The first reinforcing member 4 formed by such etching can reduce residual stress. Therefore, distortion of the first reinforcing member 4 can be prevented.

  Moreover, it does not specifically limit as wet etching, A well-known wet etching can be used, for example, when the 1st layer 42 and the 2nd layer 43 are each comprised with the metal material, nitric acid or ferric oxide The thing using etching liquid, such as these, can be used.

  When the first reinforcing member 4 is formed by etching, the thickness t1 of the first layer 42 and the thickness t2 of the second layer 43 are not particularly limited, but are about 0.03 mm or more and 1 mm or less. In this case, the thickness t1 of the first layer 42 and the thickness t2 of the second layer 43 may be the same or different from each other.

  As described above, by making the characteristics of the first layer 42 and the second layer 43 different from each other, the workability and workability in manufacturing the first reinforcing member 4 can be improved.

  Thus, in order to make the characteristics of the first layer 42 and the second layer 43 different from each other, the first layer 42 and the second layer 43 are preferably made of different materials. Thereby, the characteristics of the first layer 42 and the second layer 43 can be made different from each other relatively easily.

  In addition, at least one of the first layer 42 and the second layer 43 (preferably both the first layer 42 and the second layer 43) has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Is preferred. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

  In addition, the constituent materials of the first layer 42 and the second layer 43 are not particularly limited, and for example, a metal material, a ceramic material, or the like can be used. However, it is preferable to use a metal material. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The metal material is not particularly limited, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, it is preferable to use an alloy containing Fe.

  In particular, it is preferable that at least one of the first layer 42 and the second layer 43 is made of an alloy containing Fe.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included. More specific Fe—Ni-based alloys are the same as the specific examples given in the second embodiment.

  In particular, the thermal expansion coefficient of at least one of the first layer 42 and the second layer 43 (preferably both the first layer 42 and the second layer 43) is 0.5 ppm / ° C. or more and 10 ppm / ° C. or less. It is preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first layer 42 and the semiconductor element 3 and the absolute value of the difference in thermal expansion coefficient between the second layer 43 and the semiconductor element 3 are preferably 7 ppm / ° C. or less, It is more preferably 5 ppm / ° C. or less, and further preferably 2 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, the Fe—Ni-based alloy preferably has a Ni content of 30 wt% or more and 50 wt% or less, and the Ni content is 35 wt% or more and 45 wt% or less. Is more preferable. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, the Fe—Ni-based alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, and more preferably a total content of Fe and Ni is 90 wt% or more and 100 wt% or less. . That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. For example, it is about 0.02 mm or more and 2 mm or less.

  The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that). It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

In 4th Embodiment, the surface (namely, upper surface) on the opposite side to the board | substrate 21 of the 1st reinforcement member 4 and the surface (namely, upper surface) on the opposite side to the board | substrate 21 of the semiconductor element 3 are located on the same surface. . Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.

  The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the fourth embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.

  Further, from the viewpoint of heat dissipation, the surface (upper surface) of the second layer 42 of the first reinforcing member 4 may be roughened. If the surface of the second layer 42 of the first reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases. The surface roughening method of the 2nd layer 42 of the 1st reinforcement member 4 is not specifically limited, For example, it can implement by chemical chemical | medical solution processing, mechanical sandblasting, etc. The surface roughness of the second layer 42 of the first reinforcing member 4 depends on the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the first reinforcing member 4, and the like. For example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper film may be formed in the surface of the 1st layer 41 of the 1st reinforcement member 4, and the 2nd layer 42 from a viewpoint of the adhesive improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  The average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.

  Further, in the fourth embodiment, as shown in FIGS. 13 and 2, a thermally conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The thermally conductive material 6 of the fourth embodiment is the same as the thermally conductive material 6 of the first embodiment.

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2. Thereby, since the wiring board 2 is reinforced by the second reinforcing member 5, the rigidity of the entire semiconductor package 1 is increased.

  This 2nd reinforcement member 5 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 2nd reinforcement member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The second reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21, similar to the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  In particular, the second reinforcing member 5 includes a first layer 54 and a second layer 55 bonded on the surface of the first layer 54 opposite to the substrate 21. In other words, in the second reinforcing member 5, the first layer 54 and the second layer 55 are laminated on the lower surface of the substrate 21 in this order.

  The bonding method between the first layer 54 and the second layer 55 is not particularly limited, and examples thereof include diffusion bonding, surface activated bonding, bonding with a brazing material, and the like.

  And the 1st layer 54 and the 2nd layer 55 have mutually different characteristics (especially workability) like the 1st layer 42 and the 2nd layer 43 of the 1st reinforcement member 4 mentioned above. Thereby, workability | operativity at the time of manufacture of the semiconductor package 1 can be improved.

  The second reinforcing member 5 is provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. Part 53. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  In the fourth embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the fourth embodiment, heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  Similarly to the first reinforcing member 4 described above, at least one of the first layer 54 and the second layer 55 (preferably, both the first layer 54 and the second layer 55) are connected to the semiconductor element 3. It is preferable that the difference in thermal expansion coefficient is 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

  In such a second reinforcing member 5, the constituent materials of the first layer 54 and the second layer 55 are the same as the constituent materials of the first layer 42 and the second layer 43 of the reinforcing member 4 of the fourth embodiment. Can be used.

  Specifically, the constituent material of the second reinforcing member 5 (the constituent material of the first layer 54 and the second layer 55) is not particularly limited as long as it has a thermal expansion coefficient as described above. A metal material, a ceramic material, or the like can be used, but a metal material is preferably used. When the 2nd reinforcement member 5 is comprised with the metal material, the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used as in the first reinforcing member 4 described above, but heat dissipation and low thermal expansion can be used. From the viewpoint of realizing the above, it is preferable to use an alloy containing Fe.

  In particular, the thermal expansion coefficient of at least one of the first layer 54 and the second layer 55 (preferably both the first layer 54 and the second layer 55) is 0.5 ppm / ° C. or more and 10 ppm / ° C. or less. It is preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 5 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first layer 54 and the semiconductor element 3 and the absolute value of the difference in thermal expansion coefficient between the second layer 55 and the semiconductor element 3 are 7 ppm / ° C. or less, respectively. Is preferably 5 ppm / ° C. or less, more preferably 2 ppm / ° C. or less. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first layer 54 and the first reinforcing member 4 and the absolute value of the difference in thermal expansion coefficient between the second layer 55 and the first reinforcing member 4 are 2 ppm / ° C., respectively. It is preferably at most 1, more preferably at most 1 ppm / ° C., even more preferably at 0 ppm / ° C. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  From this point of view, the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. For example, it is about 0.02 mm or more and 2 mm or less.

  Further, from the viewpoint of heat dissipation, the surface (upper surface) of the second layer 55 of the second reinforcing member 5 may be roughened. If the surface of the second layer 55 of the second reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases. The surface roughening method of the second layer 55 of the second reinforcing member 5 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like. The surface roughness of the second layer 55 of the second reinforcing member 5 depends on the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the second reinforcing member 5, and the like. For example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Further, from the viewpoint of improving the adhesion with the resin material, a copper film may be formed on the surfaces of the first layer 54 and the second layer 55 of the second reinforcing member 5. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the second reinforcing member 5. Can be selected and implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  In addition, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and capable of surface treatment for improving adhesion.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.

Such an insulating material 81 has an insulating property and includes a resin material.
The insulating material 81 of the fourth embodiment is the same as the insulating material 81 of the first embodiment.

  According to the semiconductor package 1 configured as described above, the wiring board (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 also in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased. Therefore, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. Therefore, such a semiconductor package 1 can have excellent electrical connection reliability.

  In addition, since the first reinforcing member 4 and the second reinforcing member 5 each include two layers (first layer and second layer) having different characteristics (for example, workability), when the semiconductor package 1 is manufactured, for example, When the first reinforcing member 4 and the second reinforcing member 5 are respectively formed by punching, the generation of burrs can be prevented, and the process of removing burrs is not necessary.

(4-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 4A to 4G.
Since the semiconductor package manufacturing methods [1] to [7] of the fourth embodiment are the same as the semiconductor package manufacturing methods [1] to [7] of the first embodiment, a description thereof will be omitted.

(4-3) Semiconductor Device Next, a semiconductor device manufacturing method and a semiconductor device will be described based on preferred embodiments.

FIG. 14 is a cross-sectional view schematically showing a semiconductor device according to the fourth embodiment.
Since the semiconductor device of the fourth embodiment is the same as the semiconductor device of the first embodiment, the description thereof is omitted.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the fourth embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.

  Moreover, although 4th Embodiment demonstrated the case where both the 1st reinforcement member 4 and the 2nd reinforcement member 5 were comprised by two layers from which a characteristic differs, the 1st reinforcement member 4 or the 2nd reinforcement member 5 is the same. It may be composed of a single layer.

  Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted. In this case, a reinforcing member having two layers having different characteristics may be bonded to any one surface of the wiring board 2.

  In the fourth embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5, but, for example, provided outside the substrate 21. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Moreover, the opening part formed in the 2nd reinforcement member 5 does not need to respond | correspond one-to-one with each metal bump 71. FIG. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor package of the fourth embodiment, since the wiring board (interposer) is reinforced by the reinforcing member also in the portion other than the portion joined to the semiconductor element, the rigidity of the entire semiconductor package is increased. Therefore, it is possible to suppress or prevent the warpage of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element. Therefore, such a semiconductor package can have excellent electrical connection reliability.

  In addition, since the reinforcing member includes the first layer and the second layer having different characteristics (for example, workability), workability at the time of manufacturing the semiconductor package can be improved. For example, when one of the first layer and the second layer is made of a hard material and the other is made of a soft material, the formation of burrs can be prevented when the reinforcing member is formed by punching. This eliminates the need to remove the burrs.

  Further, according to the semiconductor device of the fourth embodiment, since the semiconductor package as described above is provided, it is excellent in reliability and inexpensive.

(5) Fifth Embodiment Hereinafter, the semiconductor package of the fifth embodiment will be described with a focus on differences from the first to fourth embodiments, and description of similar matters will be omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(5-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  6 is a cross-sectional view schematically showing a semiconductor package according to the fifth embodiment, FIG. 2 is a top view showing the semiconductor package shown in FIG. 6, and FIG. 3 is a bottom view showing the semiconductor package shown in FIG. 7A to 7G are diagrams showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Also, in FIGS. 2 to 3 and FIGS. 6 to 8, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 6, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, the wiring substrate (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. 1 The overall rigidity is increased.

  In particular, as will be described in detail later, the first reinforcing member 4 and the second reinforcing member 5 are joined to the wiring board 2 via an adhesive (adhesive layer), respectively, so that the first reinforcing member 4 and the second reinforcing member are joined. Since each of the layers 5 has a layer that improves the adhesion to the adhesive (adhesive layer), the first reinforcing member 4 and the second reinforcing member 5 can be prevented from being peeled off from the wiring board 2.

  Moreover, since the 1st reinforcement member 4 and the 2nd reinforcement member 5 each have a layer provided separately from the layer which improves adhesiveness with an adhesive agent, a thermal expansion coefficient is small as a constituent material of the layer You can choose one. Therefore, the thermal expansion coefficients of the entire first reinforcing member 4 and the entire second reinforcing member 5 can be suppressed, respectively, and as a result, warpage associated with thermal expansion or thermal contraction of the wiring board 2 can be prevented or suppressed.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
Since the wiring board of the fifth embodiment is the same as the wiring board of the second embodiment, description thereof is omitted.

[Semiconductor element]
Since the semiconductor device of the fifth embodiment is the same as the semiconductor device of the second embodiment, description thereof is omitted.

[First reinforcing member]
Since the 1st reinforcement member of 5th Embodiment is the same as that of 2nd Embodiment except for the following points, it abbreviate | omits description.
The adhesive layer 300 of the second embodiment is “made of a cured product of an adhesive (resin composition) containing a resin material and an inorganic filler”, but the adhesive layer 300 of the fifth embodiment is a cured adhesive. A resin composition containing a resin material and an inorganic filler can be suitably used. That is, you may be comprised only with the hardened | cured material of the adhesive agent.
Further, as a constituent material of the second layer 43 of the second embodiment, “it is not particularly limited, for example, a metal material, a ceramic material or the like can be used, but it is preferable to use a metal material”. The constituent material of the second layer 43 of the fifth embodiment is not particularly limited as long as it has a smaller thermal expansion coefficient than that of the first layer 42. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use a metal material.

[Second reinforcing member]
Since the 2nd reinforcement member of 5th Embodiment is the same as the 2nd reinforcement member of 2nd Embodiment, description is abbreviate | omitted.

  According to the semiconductor package 1 configured as described above, the wiring board (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5 also in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased.

  In particular, the first reinforcing member 4 and the second reinforcing member 5 are bonded to the wiring board 2 via an adhesive (adhesive layer), respectively, and the first reinforcing member 4 and the second reinforcing member 5 are respectively bonded to the adhesive (adhesive). Therefore, the first reinforcing member 4 and the second reinforcing member 5 can be prevented from being peeled off from the wiring board 2.

  Moreover, since the 1st reinforcement member 4 and the 2nd reinforcement member 5 each have a layer provided separately from the layer which improves adhesiveness with an adhesive agent, a thermal expansion coefficient is small as a constituent material of the layer You can choose one. Therefore, the thermal expansion coefficients of the entire first reinforcing member 4 and the entire second reinforcing member 5 can be suppressed, respectively, and as a result, warpage associated with thermal expansion or thermal contraction of the wiring board 2 can be prevented or suppressed.

(5-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

7A to 7G are an example of a method for manufacturing the semiconductor package 1.
Since the manufacturing method of the semiconductor package of the fifth embodiment is the same as the manufacturing method of the semiconductor package of the second embodiment, description thereof is omitted.

(5-3) Semiconductor Device Next, a semiconductor device manufacturing method and a semiconductor device will be described based on preferred embodiments.

FIG. 8 is a cross-sectional view schematically showing a semiconductor device according to the fifth embodiment.
Since the semiconductor device of the fifth embodiment is the same as the semiconductor device of the first embodiment, description thereof is omitted.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the above-described embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.

  Moreover, although embodiment mentioned above demonstrated the case where both the 1st reinforcement member 4 and the 2nd reinforcement member 5 had a layer (1st layer) which improves adhesiveness with an adhesive agent, for example, a 1st reinforcement The member 4 or the second reinforcing member 5 does not have a layer (first layer) that improves the adhesiveness with the adhesive, and may be constituted by one layer.

Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted.
In the above-described embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Moreover, the opening part formed in the 2nd reinforcement member 5 does not need to respond | correspond one-to-one with each metal bump 71. FIG. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor package of the fifth embodiment, since the wiring board (interposer) is reinforced by the reinforcing member also in the portion other than the portion joined to the semiconductor element, the rigidity of the entire semiconductor package is increased.

  In particular, since the reinforcing member has the first layer that improves the adhesion with the adhesive layer, the reinforcing member can be prevented from being peeled off from the wiring board. Further, since the reinforcing member has the second layer separately from the first layer, a material having a small thermal expansion coefficient can be selected as the constituent material of the second layer. Therefore, the thermal expansion coefficient of the entire reinforcing member can be suppressed, and as a result, warpage associated with thermal expansion or thermal contraction of the wiring board can be prevented or suppressed.

  Moreover, according to the semiconductor device of 5th Embodiment, since the semiconductor package as mentioned above is provided, it is excellent in reliability.

(6) Sixth Embodiment Hereinafter, a semiconductor package according to a sixth embodiment will be described with a focus on differences from the first to fifth embodiments, and description of similar matters will be omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(6-1-A) Sixth Embodiment (6-1-A-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  15 is a cross-sectional view schematically showing a semiconductor package according to the 6A embodiment of the present invention, FIG. 16 is a top view showing the semiconductor package shown in FIG. 15, and FIG. 17 shows the semiconductor package shown in FIG. 4A to 4G are views showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of explanation, the upper side in FIG. 15 is referred to as “upper” and the lower side is referred to as “lower”. Also, in FIGS. 4A to 4G and FIGS. 15 to 23, each part of the semiconductor package is exaggerated for convenience of explanation.

  As shown in FIG. 15, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, since the wiring board (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5, it is caused by a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. The warping of the wiring board can be suppressed or prevented.

  Further, as will be described in detail later, since the exposed portions of the surfaces of the first reinforcing member 4 and the second reinforcing member 5 are formed with a plurality of concave portions or convex portions, respectively, the first reinforcing member 4 and Heat dissipation can be improved by increasing the surface area of the second reinforcing member 5. Therefore, the heat dissipation of the semiconductor package 1 can be improved. Combined with such excellent heat dissipation, warpage associated with thermal expansion or contraction of the wiring board 2 can be prevented or suppressed.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
The wiring board according to the sixth embodiment is the same as the wiring board according to the first embodiment, and a description thereof will be omitted.
Since the substrate 21 as in the sixth embodiment is reinforced by the first reinforcing member 4 and the second reinforcing member 5, it is not necessary to increase the rigidity of the substrate 21 itself, and the thickness of the substrate 21 can be reduced. Therefore, the thermal conductivity in the thickness direction of the substrate 21 can be increased.

[Semiconductor element]
Since the semiconductor device of the sixth embodiment is the same as the semiconductor device of the first embodiment, description thereof is omitted.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded. Thereby, since the wiring board 2 is reinforced by the first reinforcing member 4 also in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire semiconductor package 1 is increased.

  This 1st reinforcement member 4 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 1st reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  The upper surface of the first reinforcing member 4 (exposed portion of the surface) is subjected to a roughening process.

  Therefore, a plurality (large number) of concave portions 42 </ b> A are formed on the upper surface of the first reinforcing member 4. In other words, the convex portion 43A is formed on a portion of the upper surface of the first reinforcing member 4 other than the plurality of concave portions 42A. Thereby, the heat dissipation can be improved by increasing the surface area of the first reinforcing member 4.

  In the 6A embodiment, the planar view shape of each recess 42A is circular. Thereby, the plurality of recesses 42A can be efficiently arranged (with as high an arrangement density as possible). In addition, the planar view shape of each recessed part 42A is not limited to a circle, and is arbitrary and may be, for example, a polygon such as a triangle, a quadrangle, or a pentagon, an ellipse, or a band.

  Each recess 42A has a width that gradually decreases from the upper surface side to the lower surface side of the first reinforcing member 4. In the 6A embodiment, each recess 42A has a hemispherical shape. Note that the width of each recess 42 </ b> A may be constant from one side in the thickness direction of the first reinforcing member 4 toward the other side.

  As shown in FIG. 16, the plurality of concave portions 42 </ b> A are uniformly distributed with respect to the upper surface (plate surface) of the first reinforcing member 4 in plan view. Thereby, the heat dissipation of the first reinforcing member 4 can be made uniform over the entire area of the plate surface of the first reinforcing member 4. Further, the first reinforcing member 4 can reinforce the substrate 21 uniformly and easily.

  The plurality of recesses 42A are regularly arranged in a plan view. In the 6A embodiment, the plurality of recesses 42A are arranged in a staggered pattern. As a result, the plurality of recesses 42A can be uniformly and uniformly distributed over the entire surface of the first reinforcing member 4 in plan view, easily and reliably. Note that the plurality of recesses 42A may be arranged in a matrix.

The plurality of recesses 42A have substantially the same diameter.
A method for forming the plurality of concave portions 42A is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, etching processing, and the like.

  Especially, it is preferable that the formation method (roughening process) of the some recessed part 42A is an etching process (etching process). Thereby, many recessed part 42A can be efficiently formed by regular arrangement | positioning as mentioned above. In addition, when etching is used, a plurality of concave portions having an arbitrary plan view shape and arrangement can be formed in the first reinforcing member 4.

  Further, the width (diameter) of each recess 42A is not particularly limited, but is preferably 0.1 μm or more and 2000 μm or less, and more preferably 5 μm or more and 500 μm or less. Thereby, it is possible to facilitate the formation of the plurality of recesses 42 </ b> A and to prevent or suppress the plurality of recesses 42 </ b> A from adversely affecting the mechanical strength of the first reinforcing member 4. In the present specification, “width of each recess” means an average width of a plurality of recesses.

  The average depth of each recess 42A is not particularly limited, but is preferably 0.1 μm or more and 800 μm or less, and more preferably 5 μm or more and 300 μm or less.

  Further, the surface roughness of the upper surface of the first reinforcing member 4 is preferably 0.1 μm or more and 400 μm or less, and more preferably 1 μm or more and 100 μm or less. Thereby, the plurality of recesses 42A can be formed relatively easily. In addition, it is possible to prevent or suppress the large number of recesses 42 </ b> A from adversely affecting the mechanical strength of the first reinforcing member 4. In the present specification, “surface roughness” refers to surface roughness expressed by an arithmetic average, and can be measured, for example, according to JIS B 0601.

  The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that). It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

In the sixth embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. . Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.

  On the other hand, as shown in FIG. 15, in the 6A embodiment, the lower surface of the first reinforcing member 4 is also roughened. That is, the surface of the first reinforcing member 4 is subjected to a roughening process on the portion facing the substrate 21.

  Therefore, a plurality of (many) recesses 44 are formed on the lower surface of the first reinforcing member 4. In other words, the convex portion 45 is formed in a portion other than the plurality of concave portions 44 on the lower surface of the first reinforcing member 4. Thereby, when the 1st reinforcement member 4 and the board | substrate 21 are joined via an adhesive agent, the adhesive strength of the adhesive agent and the 1st reinforcement member 4 can be improved by an anchor effect.

  In the 6A embodiment, the planar view shape of each recess 44 is circular. Thereby, the some recessed part 44 can be arrange | positioned efficiently (at the arrangement density as high as possible). In addition, the planar view shape of each recessed part 44 is not limited circularly, and is arbitrary, for example, polygons, such as a triangle, a tetragon | quadrangle, and a pentagon, an ellipse, a strip | belt shape, etc. may be sufficient.

  In addition, the width of each recess 44 gradually decreases from the lower surface side to the upper surface side of the first reinforcing member 4. In the 6A embodiment, each recess 44 has a hemispherical shape. Note that the width of each recess 44 may be constant from one side in the thickness direction of the first reinforcing member 4 toward the other side.

  In addition, although not illustrated, the plurality of recesses 44 are arranged uniformly distributed on the lower surface (plate surface) of the first reinforcing member 4 in plan view. Thereby, the anchor effect as described above can be uniformly generated over the entire area of the plate surface of the first reinforcing member 4. Further, the first reinforcing member 4 can reinforce the substrate 21 uniformly and easily.

  The plurality of recesses 44 may be regularly arranged in a plan view or randomly arranged in a plan view, but is preferably arranged in the same manner as the plurality of recesses 42A described above. . Thereby, formation of the some recessed part 44 can be performed using the method similar to 42 A of several recessed parts, and manufacture of the 1st reinforcement member 4 becomes easy.

The plurality of recesses 44 have substantially the same diameter.
A method for forming the plurality of recesses 44 is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing. In addition, when the several recessed part 44 is arrange | positioned at random, the several recessed part 44 can also be formed by a blast process.

  The width (diameter) of each recess 44 is not particularly limited, but is preferably 0.1 μm or more and 1000 μm or less, and more preferably 1 μm or more and 100 μm or less. Thereby, the formation of the plurality of recesses 44 can be facilitated, and the anchor effect as described above can be effectively produced.

  Moreover, the average depth of each recessed part 44 is although it does not specifically limit, It is preferable that they are 0.1 micrometer or more and 1000 micrometers or less, and it is more preferable that they are 1 micrometer or more and 100 micrometers or less.

  The surface roughness of the lower surface of the first reinforcing member 4 is preferably 0.1 μm or more and 100 μm or less, and more preferably 0.5 μm or more and 50 μm or less. Thereby, the several recessed part 44 can be formed comparatively easily. In addition, it is possible to prevent or suppress the large number of recesses 44 from adversely affecting the mechanical strength of the first reinforcing member 4.

  Further, from the viewpoint of improving the adhesion between the first reinforcing member 4 and the adhesive (resin material), for example, a copper film may be formed on the lower surface of the first reinforcing member 4. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented. Although the formation method of the copper film is not particularly limited, for example, it can be carried out by plating treatment such as electrolytic plating or electroless plating, sputtering treatment or the like. The average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.

  The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the 6A embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.

  The first reinforcing member 4 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

  Moreover, it is preferable that the 1st reinforcement member 4 has heat dissipation. Thereby, the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed. As a result, also in this respect, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  In addition, the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use it. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.

  The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included. More specific Fe—Ni-based alloys are the same as the specific examples given in the second embodiment.

  In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The average thickness T2 of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is not limited, for example, it is about 0.02 mm or more and 0.8 mm or less.

  In the 6A embodiment, as shown in FIGS. 15 and 16, the heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The heat conductive material 6 of 6A Embodiment is the same as the heat conductive material 6 of 1st Embodiment.

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2. Thereby, the wiring board 2 is reinforced by the second reinforcing member 5.

  This 2nd reinforcement member 5 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 2nd reinforcement member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The second reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21, similar to the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  And the roughening process is performed to the lower surface (exposed part of the surface) of the 2nd reinforcement member 5. As shown in FIG.

  Therefore, a plurality of (many) recesses 54 are formed on the lower surface of the second reinforcing member 5. In other words, the convex portion 55 is formed in a portion other than the plurality of concave portions 54 on the lower surface of the second reinforcing member 5. Thereby, the heat dissipation can be improved by increasing the surface area of the second reinforcing member 5.

  In the 6A embodiment, the planar view shape of each recess 54 is circular. Thereby, the several recessed part 54 can be arrange | positioned efficiently (at the arrangement density as high as possible). In addition, the planar view shape of each recessed part 54 is not limited circularly, and is arbitrary, For example, polygons, such as a triangle, a tetragon | quadrangle, and a pentagon, an ellipse, a strip | belt shape, etc. may be sufficient.

  Further, the width of each recess 54 gradually decreases from the lower surface side to the upper surface side of the second reinforcing member 5. In the 6A embodiment, each recess 54 has a hemispherical shape. The width of each recess 54 may be constant from one side in the thickness direction of the second reinforcing member 5 toward the other side.

  As shown in FIG. 17, the plurality of recesses 54 are arranged uniformly distributed on the lower surface (plate surface) of the second reinforcing member 5 in plan view. Thereby, the heat dissipation of the second reinforcing member 5 can be made uniform over the entire area of the plate surface of the second reinforcing member 5. Further, the second reinforcing member 5 can reinforce the substrate 21 uniformly and easily.

  The plurality of recesses 54 are regularly arranged in plan view. In the 6A embodiment, the plurality of recesses 54 are arranged side by side along the outer peripheral portion of the lower surface of the second reinforcing member 5 so as to be spaced from each other and to be filled between metal bumps 71 described later. ing. As a result, the plurality of recesses 54 can be uniformly and uniformly distributed over the entire surface of the second reinforcing member 5 in a plan view, easily and reliably.

The plurality of recesses 54 have substantially the same diameter.
The method for forming the plurality of recesses 54 is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing.

  Especially, it is preferable that the formation method (roughening process) of the some recessed part 54 is an etching process (etching process). Thereby, many recessed parts 54 can be efficiently formed by regular arrangement | positioning as mentioned above.

  The width (diameter) of each recess 54 is not particularly limited, but is preferably 0.1 μm or more and 2000 μm or less, and more preferably 5 μm or more and 500 μm or less. This makes it easy to form the plurality of recesses 54 and prevents or suppresses the plurality of recesses 54 from adversely affecting the mechanical strength of the second reinforcing member 5.

  Further, the surface roughness of the lower surface of the second reinforcing member 5 is preferably 0.1 μm or more and 400 μm or less, and more preferably 0.5 μm or more and 100 μm or less. Thereby, the several recessed part 54 can be formed comparatively easily. Moreover, it can prevent or suppress that the many recessed parts 54 exert a bad influence on the mechanical strength of the 2nd reinforcement member 5. FIG.

  On the other hand, as shown in FIG. 15, in the 6A embodiment, the top surface of the second reinforcing member 5 is also roughened. That is, the surface of the second reinforcing member 5 is subjected to a roughening process on the portion facing the substrate 21.

  Therefore, a plurality of (many) recesses 56 are formed on the upper surface of the second reinforcing member 5. In other words, the convex portion 57 is formed on a portion other than the plurality of concave portions 56 on the upper surface of the second reinforcing member 5. Thereby, when the 2nd reinforcement member 5 and the board | substrate 21 are joined via an adhesive agent, the adhesive strength of the adhesive agent and the 2nd reinforcement member 5 can be improved by an anchor effect.

  In the 6A embodiment, the planar view shape of each recess 56 is circular. Thereby, the some recessed part 56 can be arrange | positioned efficiently (at the arrangement density as high as possible). In addition, the planar view shape of each recessed part 56 is not limited to circular, and is arbitrary, for example, polygons, such as a triangle, a tetragon | quadrangle, and a pentagon, an ellipse, a strip | belt shape, etc. may be sufficient.

  In addition, the width of each recess 56 gradually decreases from the upper surface side to the lower surface side of the second reinforcing member 5. In the sixth embodiment, each recess 56 has a hemispherical shape. In addition, the width | variety of each recessed part 56 may be constant from the one side of the thickness direction of the 2nd reinforcement member 5 toward the other side.

  In addition, although not illustrated, the plurality of recesses 56 are arranged uniformly distributed with respect to the upper surface (plate surface) of the second reinforcing member 5 in plan view. Thereby, the anchor effect as described above can be uniformly generated over the entire area of the plate surface of the second reinforcing member 5. Further, the second reinforcing member 5 can reinforce the substrate 21 uniformly and easily.

  The plurality of recesses 56 may be regularly arranged in a plan view or randomly arranged in a plan view, but is preferably arranged in the same manner as the plurality of recesses 54 described above. . Thereby, the formation of the plurality of recesses 56 can be performed using the same method as that for the plurality of recesses 54, and the manufacture of the second reinforcing member 5 is simplified.

The plurality of recesses 56 have substantially the same diameter.
A method for forming such a plurality of recesses 56 is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing. In addition, when the several recessed part 56 is arrange | positioned at random, the several recessed part 56 can also be formed by a blast process.

  The width (diameter) of each recess 56 is not particularly limited, but is preferably 0.1 μm or more and 1000 μm or less, and more preferably 0.5 μm or more and 100 μm or less. As a result, the formation of the plurality of recesses 56 can be facilitated, and the anchor effect as described above can be effectively produced.

  Further, the surface roughness of the upper surface of the second reinforcing member 5 is preferably 0.1 μm or more and 100 μm or less, and more preferably 0.5 μm or more and 50 μm or less. Thereby, the several recessed part 56 can be formed comparatively easily. Moreover, it can prevent or suppress that the many recessed parts 56 exert a bad influence on the mechanical strength of the 2nd reinforcement member 5. FIG.

  Further, from the viewpoint of improving the adhesion between the second reinforcing member 5 and the adhesive (resin material), for example, a copper film may be formed on the upper surface of the second reinforcing member 5. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the second reinforcing member 5. Can be selected and implemented. Although the formation method of the copper film is not particularly limited, for example, it can be carried out by plating treatment such as electrolytic plating or electroless plating, sputtering treatment or the like. In addition, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and capable of surface treatment for improving adhesion.

  The second reinforcing member 5 is provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. Part 53. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the wiring substrate 2 is also reinforced at portions other than the portion joined to the semiconductor element 3, so that the rigidity of the entire semiconductor package 1 is increased. Increase. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings (through holes) 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the sixth embodiment, the heat transfer bump 91 is provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  Similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

  Further, as the constituent material of the second reinforcing member 5, the same constituent material as that of the first reinforcing member 4 described above can be used, and like the first reinforcing member 4, an Fe—Ni-based alloy is used. preferable.

  The constituent material of the second reinforcing member 5 may be different from the constituent material of the first reinforcing member 4, but is preferably the same as the constituent material of the first reinforcing member 4. Thereby, the thermal expansion difference of both surfaces of the wiring board 2 can be prevented or suppressed.

  In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.

Such an insulating material 81 has an insulating property and includes a resin material.
The insulator 81 of the 6A embodiment is the same as the insulator 81 of the first embodiment.

  According to the semiconductor package 1 configured as described above, since the wiring board 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5, the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is reduced. It is possible to suppress or prevent the warping of the wiring board due to the above.

  In addition, since the first reinforcing member 4 and the second reinforcing member 5 are each formed with a plurality of concave portions or convex portions, heat dissipation is improved by increasing the surface areas of the first reinforcing member 4 and the second reinforcing member 5. be able to. Therefore, the heat dissipation of the semiconductor package 1 can be improved.

(6-1-A-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

  Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 4A to 4G. In FIGS. 4A to 4G, for convenience of explanation, the above-described recesses 42A and 44 and recesses 54 and 56 are not shown.

  Since the semiconductor package manufacturing method ([1] to [7]) of the sixth embodiment is the same as the semiconductor package manufacturing method ([1] to [7]) of the first embodiment, description thereof is omitted. .

(6-1-A-3) Semiconductor Device Next, the semiconductor device according to Embodiment 6A will be described based on a preferred embodiment.

FIG. 18 is a cross-sectional view schematically showing an example of the semiconductor device of the 6A embodiment.
The semiconductor device according to the sixth embodiment is the same as the semiconductor device according to the first embodiment, and a description thereof will be omitted.

(6-1-B) Sixth Embodiment Next, a sixth embodiment of the present invention will be described.

  FIG. 19 is a cross-sectional view schematically showing a semiconductor package according to the sixth embodiment of the present invention. In the following description, for convenience of explanation, the upper side in FIG. 19 is referred to as “upper” and the lower side is referred to as “lower”. In FIG. 19, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the 6B embodiment will be described with a focus on differences from the above-described 6A embodiment, and description of similar matters will be omitted. In FIG. 19, the same components as those in the above-described embodiment are denoted by the same reference numerals.

  The semiconductor package of the 6B embodiment is substantially the same as the 6A embodiment except that the first reinforcing member, the heat transfer post, and the heat conductive material are omitted.

  As shown in FIG. 19, the semiconductor package 1A includes a wiring substrate 2A, a semiconductor element 3A mounted on the wiring substrate 2A, and a reinforcement bonded to the lower surface (the other surface) of the substrate 21A of the wiring substrate 2A. 5A.

  The semiconductor package 1A has a wiring board 2A configured in the same manner as the wiring board 2 of the above-described 6A embodiment except that the heat transfer post 24 is omitted. And the reinforcing member 5A comprised similarly to the 2nd reinforcing member 5 of 6A Embodiment mentioned above is joined on the lower surface of the wiring board 2A. On the other hand, a reinforcing member intended to reinforce the wiring board 2A is not joined on the upper surface of the wiring board 2A.

  Since the reinforcing member 5A is bonded to the mounting surface of the semiconductor element 3A and the other surface, the symmetry of the structure of the semiconductor package 1A increases, and as a result, the difference in thermal expansion coefficient between the wiring board 2A and the semiconductor element 3A. It is possible to suppress or prevent the warping of the wiring board 2A due to the above.

  The size of the reinforcing member 5A is determined according to the size / thickness of the semiconductor element 3A, the configuration / thickness of the wiring board 2A, the material type, thickness, opening state, etc. of the reinforcing member 5A. The size is not particularly limited as long as the size is equal to or smaller than that of the wiring board 2A.

  Further, in the 6B embodiment, the heat transfer post 24 in the 6A embodiment is omitted, but the heat generated by the semiconductor element 3A is caused by the metal bump 31, the conductor pattern and the conductor post of the wiring board 2A, the metal bump 71, Since the insulating material 81 and the reinforcing member 5A are transmitted and diffused in this order, the semiconductor package 1A has high heat dissipation.

  The warp of the wiring board 2A can also be prevented by the semiconductor package 1A of the sixth embodiment as described above.

(6-1-C) Sixth Embodiment Next, a sixth embodiment of the present invention will be described.

  20 is a top view showing a semiconductor package according to the sixth embodiment of the present invention, and FIG. 21 is a bottom view showing the semiconductor package shown in FIG. In the following description, for convenience of explanation, the front side of the sheet in FIG. 20 is referred to as “up” and the back side of the sheet is referred to as “down”. 20 and 21, each part of the semiconductor package is exaggerated for convenience of explanation.

  Hereinafter, the semiconductor package of the 6C embodiment will be described mainly with respect to the differences from the above-described 6A embodiment, and description of similar matters will be omitted. 20 and 21, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the 6C embodiment is substantially the same as the 6A embodiment except that the arrangement of the recesses formed on the upper surface of the first reinforcement member and the arrangement of the recesses formed on the lower surface of the second reinforcement member are different. .

  As shown in FIG. 20, the semiconductor package 1 </ b> B has a first reinforcing member 4 </ b> B bonded to the upper surface of the wiring board 2.

  On the upper surface of the first reinforcing member 4B, a roughening process is performed, and a plurality of concave portions 42B arranged at random are formed. Moreover, the convex part 43B is formed in parts other than the some recessed part 42B among the upper surfaces of the 1st reinforcement member 4B. Thereby, heat dissipation can be improved by the increase in the surface area of the 1st reinforcement member 4B.

  The plurality of recesses 42B are composed of a plurality of types of recesses having different diameters. In FIG. 20, for convenience of explanation, the plurality of recesses 42B are formed so as not to overlap each other, and the shape of each recess 42B is circular, but the plurality of recesses 42B partially overlap each other. The planar view shape of each recessed part 42B may be different.

  A method for forming such a plurality of recesses 42B is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, etching processing, and blast processing.

  Especially, it is preferable that the formation method (roughening process) of the some recessed part 42B is a blast process. Thereby, many recessed parts 42B can be efficiently formed by the random arrangement | positioning as mentioned above.

  Further, the surface roughness of the upper surface of the first reinforcing member 4B is preferably 0.1 μm or more and 400 μm or less, and more preferably 0.5 μm or more and 100 μm or less. Thereby, the plurality of recesses 42B can be formed relatively easily. Moreover, it can prevent or suppress that the many recessed parts 42B exert a bad influence on the mechanical strength of the 1st reinforcement member 4B.

  Further, as shown in FIG. 21, the semiconductor package 1 </ b> B has a second reinforcing member 5 </ b> B bonded to the lower surface of the wiring board 2.

  A roughening process is performed on the lower surface of the second reinforcing member 5B, and a plurality of concave portions 54B arranged at random are formed. Moreover, the convex part 55B is formed in parts other than the several recessed part 54B among the lower surfaces of the 2nd reinforcement member 5B. Thereby, heat dissipation can be improved by the increase in the surface area of the 2nd reinforcement member 5B.

  The plurality of recesses 54B are composed of a plurality of types of recesses having different diameters from each other, like the plurality of recesses 42B described above. In FIG. 21, for convenience of explanation, the plurality of recesses 54B are formed so as not to overlap each other, and the shape of each recess 54B is circular, but the plurality of recesses 54B partially overlap each other. It is formed, and the shape of each recess 54B in plan view may be different.

  A method for forming the plurality of recesses 54B is not particularly limited, and a method similar to that for the plurality of recesses 42B described above can be used, but blasting is preferably used. Thereby, many recessed parts 54B can be efficiently formed by the random arrangement as described above.

  Further, the surface roughness of the lower surface of the second reinforcing member 5B is preferably 0.1 μm or more and 400 μm or less, and more preferably 0.5 μm or more and 100 μm or less. Thereby, the plurality of recesses 54B can be formed relatively easily. Moreover, it can prevent or suppress that many recessed parts 54B exert a bad influence on the mechanical strength of the 2nd reinforcement member 5B.

  The warp of the wiring board 2 can also be prevented by the semiconductor package 1B according to the sixth C embodiment as described above.

(6-1-D) Sixth Embodiment Next, a sixth embodiment of the present invention will be described.

  FIG. 22 is a top view showing the semiconductor package according to the sixth embodiment of the present invention, and FIG. 23 is a bottom view showing the semiconductor package shown in FIG. In the following description, for the sake of convenience of explanation, the front side of the paper in FIG. 22 is referred to as “up” and the back side of the paper is referred to as “down”. 22 and 23, each part of the semiconductor package is exaggerated for convenience of explanation.

  Hereinafter, the semiconductor package of the 6D embodiment will be described focusing on the differences from the above-described 6A embodiment, and description of similar matters will be omitted. 22 and 23, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the 6D embodiment is substantially the same as the 6A embodiment except that the arrangement of the recesses formed on the upper surface of the first reinforcement member and the arrangement of the recesses formed on the lower surface of the second reinforcement member are different. .

  As shown in FIG. 22, the semiconductor package 1 </ b> C has a first reinforcing member 4 </ b> C bonded to the upper surface of the wiring board 2.

  On the upper surface of the first reinforcing member 4C, a roughening process is performed, and a plurality of concave portions 42C having a band shape are formed. In addition, a convex portion 43C is formed on a portion of the upper surface of the first reinforcing member 4C other than the plurality of concave portions 42C. Thereby, heat dissipation can be improved by the increase in the surface area of 4 C of 1st reinforcement members.

  Further, the plurality of concave portions 42C are arranged substantially radially in plan view. More specifically, the plurality of recesses 42C are constituted by four groups corresponding to the respective sides of the first reinforcing member 4C having a quadrangular ring shape, and the plurality of recesses 42C are arranged in parallel to each other in each group. Has been.

  A method for forming the plurality of concave portions 42C is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing.

  The width of each recess 42C is not particularly limited, but is preferably 5 μm or more and 3000 μm or less, and more preferably 20 μm or more and 1000 μm or less. This makes it easy to form the plurality of recesses 42C and prevents or suppresses the plurality of recesses 42C from adversely affecting the mechanical strength of the first reinforcing member 4C.

  The pitch of the plurality of recesses 42C in each group is not particularly limited, but is preferably 10 μm or more and 6000 μm or less.

  Further, as shown in FIG. 23, the semiconductor package 1 </ b> C includes a second reinforcing member 5 </ b> C bonded to the lower surface of the wiring board 2.

  A roughening process is performed on the lower surface of the second reinforcing member 5C to form a plurality of concave portions 54C having a strip shape. Further, a convex portion 55C is formed on a portion of the lower surface of the second reinforcing member 5C other than the plurality of concave portions 54C. Thereby, the heat dissipation can be improved by increasing the surface area of the second reinforcing member 5C.

  The plurality of recesses 54C are composed of four groups corresponding to the respective sides of the second reinforcing member 5C having a quadrangular outer shape, like the plurality of recesses 42C described above. The recesses 54C are arranged in parallel to each other.

  A method for forming the plurality of recesses 54C is not particularly limited, and a method similar to that for the plurality of recesses 42C described above can be used.

  Further, the width of each recess 54C is not particularly limited, but is preferably 5 μm or more and 3000 μm or less, and more preferably 20 μm or more and 1000 μm or less. Accordingly, it is possible to easily form the plurality of recesses 54C and to prevent or suppress the plurality of recesses 54C from adversely affecting the mechanical strength of the second reinforcing member 5C.

  The pitch of the plurality of recesses 54C in each group is not particularly limited, but is preferably 10 μm or more and 6000 μm or less.

  The semiconductor package 1C according to the sixth embodiment as described above can also prevent the wiring substrate 2 from warping.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the sixth to sixth embodiments, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A missing part (notch) may be formed in the part.

  Moreover, although the case where the roughening process was performed to both the 1st reinforcement member 4 and the 2nd reinforcement member 5 was demonstrated in 6A-6D embodiment, in the 1st reinforcement member 4 or the 2nd reinforcement member 5, The roughening treatment may not be performed.

  In the sixth to sixth embodiments, the case where the surface of the reinforcing member facing the substrate is roughened is described. However, the surface of the reinforcing member facing the substrate is roughened. May be omitted.

Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted.
In the 6A to 6D embodiments, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion that connects the first reinforcing member 4 and the second reinforcing member 5. A heat conducting member (metal member) provided outside may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Further, the opening 51 formed in the second reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor packages of the sixth to sixth embodiments, since the wiring board (interposer) is reinforced by the reinforcing member, warping of the wiring board due to a difference in thermal expansion coefficient between the wiring board and the semiconductor element is suppressed or prevented. can do.

  In addition, since the reinforcing member is provided with a plurality of concave portions or convex portions, the heat dissipation can be improved by increasing the surface area of the reinforcing member. Therefore, the heat dissipation of the semiconductor package can be improved.

  Further, according to the semiconductor devices of the sixth to sixth embodiments, since the semiconductor package as described above is provided, the reliability is excellent.

(7) Seventh Embodiment Hereinafter, the semiconductor package of the seventh embodiment will be described with a focus on differences from the first to sixth embodiments, and description of similar matters will be omitted. In addition, in the figure, the same code | symbol is attached | subjected about the structure similar to embodiment mentioned above.
(7-1-A) Seventh A Embodiment (7-1-A-1) Semiconductor Package First, the semiconductor package of the present invention will be described.

  24 is a cross-sectional view schematically showing a semiconductor package according to a seventh embodiment of the present invention, FIG. 25 is a top view showing the semiconductor package shown in FIG. 24, and FIG. 3 shows the semiconductor package shown in FIG. 26A to 26G are diagrams showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of explanation, the upper side in FIG. 24 is referred to as “upper” and the lower side is referred to as “lower”. 3 and FIGS. 24 to 28, the respective parts of the semiconductor package are exaggerated for convenience of explanation.

  As shown in FIG. 24, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member (reinforcing member) 4, and a second reinforcing member (reinforcing member). And 5.

  According to such a semiconductor package 1, since the wiring board (interposer) 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5, it is caused by a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. The warping of the wiring board can be suppressed or prevented.

  Further, as will be described in detail later, since the first reinforcing member 4 and the second reinforcing member 5 are each formed with a plurality of through holes, the surface areas of the first reinforcing member 4 and the second reinforcing member 5 are increased. It is also possible to improve heat dissipation and suppress an increase in the mass of the semiconductor package 1 due to the first reinforcing member 4 and the second reinforcing member 5.

Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
Since the wiring board of the seventh embodiment is the same as the wiring board of the sixth embodiment, the description thereof is omitted.

[Semiconductor element]
Since the semiconductor device of the seventh embodiment is the same as the semiconductor device of the first embodiment, description thereof is omitted.

[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded. Thereby, since the wiring board 2 is reinforced by the first reinforcing member 4 also in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire semiconductor package 1 is increased.

  This 1st reinforcement member 4 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 1st reinforcement member 4 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.

  Moreover, the 1st reinforcement member 4 has comprised plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.

  The first reinforcing member 4 is formed with a plurality of through holes 42D penetrating in the thickness direction. Thereby, heat dissipation can be improved by increasing the surface area of the first reinforcing member 4, and an increase in the mass of the semiconductor package 1 by the first reinforcing member 4 can be suppressed.

  In the 7A embodiment, each through hole 42D has a circular shape in plan view. Thereby, the plurality of through holes 42D can be efficiently arranged (with as high an arrangement density as possible) while ensuring the mechanical strength necessary for the first reinforcing member 4. In addition, the planar view shape of each through-hole 42D is not limited to a circle, and is arbitrary, and may be, for example, a polygon such as a triangle, a quadrangle, or a pentagon, an ellipse, or a band.

  In addition, each through hole 42 </ b> D has a constant width across the entire thickness direction of the first reinforcing member 4. A method for forming the plurality of through holes 42D is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing. The width of each through hole 42 </ b> D may have a portion that increases or decreases from one side in the thickness direction of the first reinforcing member 4 toward the other side.

  Further, the width (diameter) of each through hole 42D is not particularly limited, but is preferably 5 μm or more and 2000 μm or less, and more preferably 20 μm or more and 1000 μm or less. This makes it easy to form the plurality of through holes 42 </ b> D and prevents or suppresses the plurality of through holes 42 </ b> D from adversely affecting the mechanical strength of the first reinforcing member 4. The “width of each through hole” refers to the average width of a plurality of through holes.

  Further, the plurality of through holes 42 </ b> D are uniformly distributed over the entire surface of the first reinforcing member 4 in plan view. Thereby, the 1st reinforcement member 4 can reinforce the board | substrate 21 uniformly easily and reliably.

  The plurality of through holes 42D are regularly arranged in a plan view. In the 7A embodiment, the plurality of through holes 42 </ b> D are arranged in parallel along the outer peripheral portion of the substrate 21 at intervals. Thereby, the plurality of through holes 42 </ b> D can be disposed uniformly and uniformly over the entire surface of the first reinforcing member 4 in a plan view.

  When the area of the first reinforcing member 4 in plan view (the area excluding the through hole 42D) is S11 (S1) and the total area of the plurality of through holes 42D in plan view is S12 (S2), S12 / (S11 + S12) is preferably 0.1 or more and 0.9 or less, and more preferably 0.3 or more and 0.7 or less. Thereby, both high rigidity and weight reduction of the 1st reinforcement member 4 can be aimed at.

  The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that). It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.

In the seventh embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. . Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.

  The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the seventh embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.

  Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.

  The first reinforcing member 4 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.

  Moreover, it is preferable that the 1st reinforcement member 4 has heat dissipation. Thereby, the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed. As a result, also in this respect, it is possible to suppress or prevent warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3.

  In addition, the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use it. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.

  Examples of such Fe-containing alloys include Fe-Ni alloys, Fe-Co-Cr alloys, Fe-Co alloys, Fe-Pt alloys, Fe-Pd alloys, and the like. It is preferable to use a base alloy.

  Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.

The Fe—Ni-based alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
More specific Fe—Ni-based alloys are the same as the specific examples given in the second embodiment.

  In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, the warp of the wiring board 2 can be effectively prevented.

  From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.

  Further, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.

  The average thickness T2 of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is not limited, for example, it is about 0.02 mm or more and 0.8 mm or less.

  Moreover, the surface of the 1st reinforcement member 4 may be roughened from a heat-dissipating viewpoint. If the surface of the first reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the first reinforcing member 4 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.

  The magnitude of the surface roughness of the first reinforcing member 4 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring board 2, the shape and size of the first reinforcing member 4, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper membrane | film | coat may be formed in the 1st reinforcement member 4 surface from a viewpoint of the adhesive improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  The average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.

  In the seventh embodiment, as shown in FIGS. 24 and 25, the heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.

  The thermally conductive material 6 of the seventh embodiment is the same as the thermally conductive material 6 of the first embodiment.

  In addition, the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .

[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2. Thereby, the wiring board 2 is reinforced by the second reinforcing member 5.

  This 2nd reinforcement member 5 and the board | substrate 21 can be joined through an adhesive agent. Thereby, installation of the 2nd reinforcement member 5 becomes easy.

  Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.

  The second reinforcing member 5 has a smaller coefficient of thermal expansion than the substrate 21, similar to the first reinforcing member 4 described above.

  The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.

  The second reinforcing member 5 is provided between a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21) and the metal bumps 71. Part 53. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the wiring substrate 2 is also reinforced at portions other than the portion joined to the semiconductor element 3, so that the rigidity of the entire semiconductor package 1 is increased. Increase. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.

  More specifically, the second reinforcing member 5 has a plurality of openings (through holes) 51 formed so as to surround the metal bumps 71 without contacting the metal bumps 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.

  Moreover, each opening part 51 has penetrated the 2nd reinforcement member 5 in the thickness direction. Thereby, the heat dissipation can be improved by increasing the surface area of the second reinforcing member 5, and the increase in the mass of the semiconductor package 1 by the second reinforcing member 5 can be suppressed.

  In the seventh embodiment, the shape of each opening 51 in plan view is a circle. Thereby, a plurality of openings 51 can be efficiently arranged (with as high an arrangement density as possible) while ensuring the mechanical strength necessary for the second reinforcing member 5. In addition, the planar view shape of each opening part 51 is not limited circularly, and is arbitrary, for example, polygons, such as a triangle, a square, and a pentagon, an ellipse, a strip | belt shape, etc. may be sufficient.

  Each opening 51 has a constant width over the entire region of the second reinforcing member 5 in the thickness direction. A method for forming such a plurality of openings 51 is not particularly limited, and examples thereof include drilling, router processing, punching processing, laser processing, and etching processing. The width of each opening 51 may have a portion that increases or decreases from one side in the thickness direction of the second reinforcing member 5 toward the other side.

  The width (diameter) of each opening 51 is not particularly limited, but is preferably 50 μm or more and 1000 μm or less, and more preferably 100 μm or more and 800 μm or less. Thereby, it is possible to facilitate the formation of the plurality of openings 51 and to prevent or suppress the plurality of openings 51 from adversely affecting the mechanical strength of the second reinforcing member 5.

  Further, the plurality of openings 51 are uniformly distributed over the entire surface of the second reinforcing member 5 in plan view. Thereby, the 2nd reinforcement member 5 can reinforce the board | substrate 21 uniformly easily and reliably.

  The plurality of openings 51 are regularly arranged in plan view. In the seventh embodiment, the plurality of openings 51 are arranged in a matrix in plan view. As a result, the plurality of openings 51 can be uniformly and uniformly distributed over the entire surface of the second reinforcing member 5 in a plan view.

  Further, when the area of the second reinforcing member 5 in plan view (the area excluding the opening 51) is S21 (S1) and the total area of the plurality of openings 51 in plan view is S22 (S2), S22 / (S21 + S22) is preferably 0.1 or more and 0.9 or less, and more preferably 0.3 or more and 0.7 or less. Thereby, both high rigidity and weight reduction of the 2nd reinforcement member 5 can be aimed at.

  Each opening 51 is provided corresponding to each metal bump 71 (one-to-one correspondence). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.

  The plurality of openings 51 are formed so as to expose the plurality of metal bumps 71. Thereby, the opening part 51 can be used effectively.

  In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.

In the seventh embodiment, heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).

  The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.

  Similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.

  Further, as the constituent material of the second reinforcing member 5, the same constituent material as that of the first reinforcing member 4 described above can be used, and like the first reinforcing member 4, an Fe—Ni-based alloy is used. preferable.

  The constituent material of the second reinforcing member 5 may be different from the constituent material of the first reinforcing member 4, but is preferably the same as the constituent material of the first reinforcing member 4. Thereby, the thermal expansion difference of both surfaces of the wiring board 2 can be prevented or suppressed.

  In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.

  The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.

  The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.

  Further, the surface of the second reinforcing member 5 may be roughened from the viewpoint of heat dissipation. If the surface of the second reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the second reinforcing member 5 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.

  The magnitude of the surface roughness of the second reinforcing member 5 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring board 2, the shape and size of the second reinforcing member 5, and the like. Although there is no particular limitation, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.

  Moreover, the copper film may be formed in the 2nd reinforcement member 5 surface from a viewpoint of adhesiveness improvement with a resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape and size of the reinforcing member, the type of the resin material, etc. Can be implemented.

  Although the formation method of a copper membrane is not specifically limited, For example, it can implement by plating processing, such as electrolytic plating and electroless plating, sputtering processing.

  In addition, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and capable of surface treatment for improving adhesion.

  An insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be enhanced while improving the reliability of the semiconductor package 1.

  The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.

Such an insulating material 81 has an insulating property and includes a resin material.
The insulating material 81 of the seventh embodiment is the same as the insulating material 81 of the first embodiment.

  According to the semiconductor package 1 configured as described above, since the wiring board 2 is reinforced by the first reinforcing member 4 and the second reinforcing member 5, the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is reduced. It is possible to suppress or prevent the warping of the wiring board due to the above.

  In addition, since the first reinforcing member 4 and the second reinforcing member 5 are each formed with a plurality of through holes, heat dissipation can be improved by increasing the surface area of the first reinforcing member 4 and the second reinforcing member 5, The increase in the mass of the semiconductor package 1 due to the first reinforcing member 4 and the second reinforcing member 5 can also be suppressed.

(7-1-A-2) Semiconductor Package Manufacturing Method The semiconductor package 1 as described above can be manufactured as follows, for example.

  Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIGS. 26A to 26G. In FIG. 26A to FIG. 26G, illustration of the above-described through hole 42 </ b> D and the opening 51 is omitted for convenience of explanation.

  Note that the semiconductor package manufacturing method ([1] to [7]) of the seventh embodiment A is the same as the semiconductor package manufacturing method ([1] to [7]) of the first embodiment. Omitted. 4A to 4G correspond to FIGS. 26A to 26G, respectively.

(Semiconductor device)
Next, the semiconductor device of the present invention will be described based on a preferred embodiment.

FIG. 27 is a cross-sectional view schematically showing an example of the semiconductor device of the present invention.
Since the semiconductor device according to the seventh embodiment is the same as the semiconductor device according to the first embodiment, the description thereof is omitted.

(7-1-B) Seventh Embodiment Next, a seventh embodiment of the present invention will be described.

  FIG. 28 is a sectional view schematically showing a semiconductor package according to the seventh embodiment of the present invention. In the following description, for convenience of explanation, the upper side in FIG. 28 is referred to as “upper” and the lower side is referred to as “lower”. In FIG. 28, for convenience of explanation, each part of the semiconductor package is exaggerated.

  Hereinafter, the semiconductor package of the 7B embodiment will be described focusing on the differences from the 7A embodiment described above, and the description of the same matters will be omitted. In FIG. 28, the same reference numerals are given to the same configurations as those in the above-described embodiment.

  The semiconductor package of the seventh embodiment is substantially the same as the seventh embodiment, except that the first reinforcing member, the heat transfer post, and the heat conductive material are omitted.

  As shown in FIG. 28, the semiconductor package 1A includes a wiring substrate 2A, a semiconductor element 3A mounted on the wiring substrate 2A, and a reinforcement bonded to the lower surface (the other surface) of the substrate 21A of the wiring substrate 2A. 5A.

  The semiconductor package 1A has a wiring board 2A configured in the same manner as the wiring board 2 of the above-described 7A embodiment except that the heat transfer post 24 is omitted. And the reinforcing member 5A comprised similarly to the 2nd reinforcing member 5 of 7A Embodiment mentioned above is joined on the lower surface of the wiring board 2A. On the other hand, a reinforcing member intended to reinforce the wiring board 2A is not joined on the upper surface of the wiring board 2A.

  Since the reinforcing member 5A is bonded to the mounting surface of the semiconductor element 3A and the other surface, the symmetry of the structure of the semiconductor package 1A increases, and as a result, the difference in thermal expansion coefficient between the wiring board 2A and the semiconductor element 3A. It is possible to suppress or prevent the warping of the wiring board 2A due to the above.

  The size of the reinforcing member 5A is determined according to the size / thickness of the semiconductor element 3A, the configuration / thickness of the wiring board 2A, the material type, thickness, opening state, etc. of the reinforcing member 5A. The size is not particularly limited as long as the size is equal to or smaller than that of the wiring board 2A.

  Further, in the 7B embodiment, the heat transfer post 24 in the 7A embodiment is omitted, but the heat generated by the semiconductor element 3A is generated by the metal bump 31, the conductor pattern and the conductor post of the wiring board 2A, the metal bump 71, Since the insulating material 81 and the reinforcing member 5A are transmitted and diffused in this order, the semiconductor package 1A has high heat dissipation.

  The semiconductor package 1A of the seventh embodiment as described above can also prevent the wiring substrate 2A from warping and improve the heat dissipation. In addition, the weight of the semiconductor package 1A can be reduced.

  As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.

  For example, in the seventh to seventh embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A missing part (notch) may be formed in the part.

  In the seventh to seventh embodiments, the case where a plurality of through holes are formed in both the first reinforcing member 4 and the second reinforcing member 5 has been described. However, in the first reinforcing member 4 or the second reinforcing member 5, A plurality of through holes may not be formed.

Further, the first reinforcing member 4 or the second reinforcing member 5 may be omitted.
Further, in the seventh to seventh embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion that connects the first reinforcing member 4 and the second reinforcing member 5. A heat conducting member (metal member) provided outside may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below. Further, depending on the degree of heat dissipation of the wiring board 2 itself, the heat transfer post 24 may be omitted.

  Further, the through holes (openings 51) formed in the second reinforcing member 5 may not correspond to the metal bumps 71 on a one-to-one basis. That is, a through hole may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.

  According to the semiconductor packages of the seventh to seventh embodiments, since the wiring board (interposer) is reinforced by the reinforcing member, warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element is suppressed or prevented. can do.

In addition, since a plurality of through holes are formed in the reinforcing member, heat dissipation can be improved by increasing the surface area of the reinforcing member, and an increase in the mass of the semiconductor package due to the reinforcing member can be suppressed.
Further, according to the semiconductor devices of the seventh to seventh embodiments, since the semiconductor package as described above is provided, the reliability is excellent.

  According to the present invention, the warping of the wiring board can be suppressed or prevented, and the semiconductor package can be excellent in rigidity and heat dissipation. Moreover, since the semiconductor device of the present invention includes such a semiconductor package, it is excellent in reliability.

1 semiconductor package 1A semiconductor package 1B semiconductor package 1C semiconductor package 2 wiring board 2A wiring board 3 semiconductor element 3A semiconductor element 4 first reinforcing member 4B first reinforcing member 4C first reinforcing member 5 second reinforcing member 5A reinforcing member 5B second Reinforcing member 5C Second reinforcing member 6 Thermally conductive material 21 Substrate 21A Substrate 24 Heat transfer post 31 Metal bump 32 Adhesive layer 33 Outer peripheral surface 41 Inner peripheral surface 42 First layer 42A Concave 42B Concave 42C Concave 42D Through hole 43 Second layer 43A Convex part 43B Convex part 43C Convex part 44 Concave part 45 Convex part 51 Opening part (through hole)
52 part 53 part 54 first layer 55 second layer 71 metal bump 71A metal ball 81 insulating material 81A insulating material 91 heat transfer bump 100 semiconductor device 200 motherboard 211 insulating layer 211A prepreg 212 insulating layer 213 insulating layer 214 insulating layer 215 insulating layer 221 Conductor pattern 221A Metal layer 222 Conductor pattern 223 Conductor pattern 224 Conductor pattern 231 Conductor post 232 Conductor post 233 Conductor post 234 Conductor post 2111 Through hole 300 Adhesive layer 400 Adhesive layer 42 Concavity 42B Concavity 42C Concavity 43 Convex 43B Convex 43C Convex Part 44 Concave 45 Convex part 54 Concave part 54B Concave part 54C Concave part 55 Convex part 55B Convex part 55C Convex part 56 Concave part 57 Convex part

Claims (67)

A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A semiconductor package comprising: a reinforcing member joined to at least one of the one surface and the other surface of the substrate and made of an Fe-Ni alloy. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded, and having a smaller coefficient of thermal expansion than the substrate;
A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
At least one of the first reinforcing member and the second reinforcing member is made of an Fe—Ni-based alloy.   The semiconductor package according to claim 1, wherein the Fe—Ni alloy has a smaller coefficient of thermal expansion than the substrate.   The semiconductor package according to claim 3, wherein the thermal expansion coefficient of the Fe-Ni alloy is 3 ppm / ° C or more and 10 ppm / ° C or less.   3. The semiconductor package according to claim 1, wherein the Fe—Ni-based alloy has a difference in coefficient of thermal expansion from the semiconductor element of 7 ppm / ° C. or less.   The semiconductor package according to claim 1, wherein the Fe—Ni-based alloy has a Ni content of 30 wt% or more and 50 wt% or less.   3. The semiconductor package according to claim 1, wherein the Fe—Ni-based alloy has a balance content of 0 wt% or more and 15 wt% or less.   The semiconductor package according to claim 1, wherein the first reinforcing member is provided so as to surround the periphery of the semiconductor element.   The semiconductor package according to claim 1, wherein each of the first reinforcing member and the second reinforcing member has a plate shape.   A semiconductor device comprising the semiconductor package according to claim 1. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate via an adhesive layer, and having a smaller thermal expansion coefficient than the substrate;
The adhesive layer is composed of a resin composition containing a resin material and an inorganic filler.   The semiconductor package according to claim 11, wherein the adhesive layer has an elastic modulus at 25 ° C. of 0.5 MPa to 10 GPa.   The semiconductor package according to claim 11 or 12, wherein the adhesive layer has a thermal conductivity of 0.5 W / (m · K) to 100 W / (m · K).   The semiconductor package according to claim 11 or 12, wherein an average thickness of the adhesive layer is not less than 5 µm and not more than 150 µm.   The semiconductor package according to claim 11 or 12, wherein the reinforcing member has a coefficient of thermal expansion of 0.5 ppm / ° C to 10 ppm / ° C.   The semiconductor package according to claim 11, wherein the reinforcing member has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the semiconductor element.   The semiconductor package according to claim 11, wherein the reinforcing member is made of an Fe—Ni-based alloy.   A semiconductor device comprising the semiconductor package according to claim 11. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-shaped reinforcing member bonded to at least one of the one surface and the other surface of the substrate, and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer and a second layer bonded to a surface of the first layer opposite to the substrate and having a thermal expansion coefficient different from that of the first layer. Semiconductor package. The reinforcing member is bonded to the one surface of the substrate;
The semiconductor package according to claim 19, wherein a thermal expansion coefficient of the second layer is larger than a thermal expansion coefficient of the first layer.   The semiconductor package according to claim 20, wherein the reinforcing member is provided so as to surround a periphery of the semiconductor element. The reinforcing member is bonded to the other surface of the substrate;
The semiconductor package according to claim 19, wherein a thermal expansion coefficient of the second layer is smaller than a thermal expansion coefficient of the first layer. A plurality of metal bumps are provided on the other surface of the substrate,
The semiconductor package according to claim 22, wherein the reinforcing member has a portion located between the metal bumps.   24. The semiconductor package according to claim 19, wherein an absolute value of a difference between a thermal expansion coefficient of the first layer and a thermal expansion coefficient of the second layer is 0.5 ppm / ° C. or more and 20 ppm / ° C. or less. . When the thickness of the first layer is t1 [mm] and the thickness of the second layer is t2 [mm],
24. The semiconductor package according to claim 19, wherein t2 / t1 is not less than 0.03 and not more than 34.   24. The semiconductor package according to claim 19, wherein the first layer has a thermal expansion coefficient of 0.5 ppm / ° C. or more and 10 ppm / ° C. or less.   24. The semiconductor package according to claim 19, wherein the first layer has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the semiconductor element.   24. A semiconductor device comprising the semiconductor package according to claim 19. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-shaped reinforcing member bonded to at least one of the one surface and the other surface of the substrate, and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer and a second layer bonded to a surface of the first layer opposite to the substrate and having a characteristic different from that of the first layer. . A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A plate-like first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded, and having a smaller coefficient of thermal expansion than the substrate;
A plate-like second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The first reinforcing member and the second reinforcing member are bonded to the first layer and the surface of the first layer opposite to the substrate, respectively, and have a characteristic different from that of the first layer. A semiconductor package comprising:   The semiconductor package according to claim 29 or 30, wherein the first layer and the second layer are made of different materials.   31. The semiconductor package according to claim 29, wherein one of the first layer and the second layer is made of a material harder than the other.   The semiconductor package according to claim 29 or 30, wherein the first layer and the second layer are made of materials having different etching rates in predetermined etching.   The semiconductor package according to claim 29 or 30, wherein a thermal expansion coefficient of at least one of the first layer and the second layer is 0.5 ppm / ° C or more and 10 ppm / ° C or less.   31. The semiconductor package according to claim 29, wherein at least one of the first layer and the second layer has a difference in thermal expansion coefficient of 7 ppm / ° C. or less from the semiconductor element.   The semiconductor package according to claim 29 or 30, wherein at least one of the first layer and the second layer is made of an Fe-Ni-based alloy.   31. The semiconductor package according to claim 30, wherein the first reinforcing member is provided so as to surround the periphery of the semiconductor element.   A semiconductor device comprising the semiconductor package according to claim 29 or 30. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate via an adhesive layer, having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member includes a first layer that contacts the adhesive layer, and a second layer that is bonded to a surface of the first layer opposite to the substrate and is made of a material different from the first layer. The first package has a function of improving adhesion with the adhesive layer.   The first layer is selected from the group consisting of copper, copper alloy, nickel, nickel alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, iron, iron alloy, silver, silver alloy, zinc, zinc alloy, gold, gold alloy 40. The semiconductor package according to claim 39, wherein the semiconductor package is made of a metal material.   41. The semiconductor package according to claim 40, wherein the adhesive layer includes a resin material and an inorganic filler.   42. The semiconductor package according to claim 39, wherein a contact surface of the first layer with the adhesive layer is roughened. When the thickness of the first layer is t1, and the thickness of the second layer is t2,
42. The semiconductor package according to claim 39, wherein t2 / t1 is 2 or more and 80000 or less.   42. The semiconductor package according to claim 39, wherein a thermal expansion coefficient of the second layer is not less than 0.5 ppm / ° C. and not more than 10 ppm / ° C.   The semiconductor package according to any one of claims 39 to 41, wherein the second layer has a thermal expansion coefficient difference of 7 ppm / ° C or less with respect to the semiconductor element.   42. The semiconductor package according to claim 39, wherein the second layer is made of a Fe-Ni alloy.   42. A semiconductor device comprising the semiconductor package according to claim 39. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The reinforcing member has a plurality of concave portions or convex portions formed by roughening at least an exposed portion of the surface thereof.   49. The semiconductor package according to claim 48, wherein the plurality of concave portions or convex portions are uniformly distributed over the entire surface of the reinforcing member in a plan view.   50. The semiconductor package according to claim 48 or 49, wherein the plurality of concave portions or convex portions are regularly arranged.   51. The semiconductor package according to claim 50, wherein the roughening process is an etching process.   50. The semiconductor package according to claim 48 or 49, wherein the plurality of concave portions or convex portions are randomly arranged.   53. The semiconductor package according to claim 52, wherein the roughening process is a blast process. The planar view shape of the concave portion or the convex portion is circular,
50. The semiconductor package according to claim 48 or 49, wherein a surface roughness of the roughened surface of the reinforcing member is 0.1 μm or more and 400 μm or less.   50. The semiconductor package according to claim 48 or 49, wherein the roughening treatment is applied to a portion of the surface of the reinforcing member that faces the substrate.   50. The semiconductor package according to claim 48 or 49, wherein the reinforcing member is made of a metal material.   57. The semiconductor package according to claim 56, wherein the reinforcing member is made of an Fe-Ni alloy.   50. A semiconductor device comprising the semiconductor package according to claim 48 or 49. A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to at least one of the one surface and the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
The semiconductor package according to claim 1, wherein the reinforcing member has a plate shape and a plurality of through holes penetrating in the thickness direction.   60. The semiconductor package according to claim 59, wherein the plurality of through holes are regularly arranged in a plan view.   61. The semiconductor package according to claim 59, wherein the plurality of through holes are uniformly distributed over the entire surface of the reinforcing member in a plan view. When the area of the reinforcing member in plan view is S1, and the total area of the plurality of through holes in plan view is S2,
62. The semiconductor package according to claim 61, wherein S2 / (S1 + S2) is 0.1 or more and 0.9 or less.   61. The semiconductor package according to claim 59, wherein each through hole has a circular shape in plan view. A plurality of metal bumps bonded on the substrate;
61. The semiconductor package according to claim 59, wherein the plurality of through holes are formed so as to expose the plurality of metal bumps.   61. The semiconductor package according to claim 59, wherein the reinforcing member is made of a metal material.   66. The semiconductor package according to claim 65, wherein the reinforcing member is made of an Fe-Ni alloy.   61. A semiconductor device comprising the semiconductor package according to claim 59.

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