JPWO2011093405A1 - Optical semiconductor device with chip size package - Google Patents

Abstract

Provided is an optical semiconductor device having a chip size package that can be packaged with a light emitting element formed on a wafer. The light-emitting element includes one or more light-emitting portions formed of a semiconductor, and is bonded to a package substrate having the same size as the light-emitting element using a bonding material. An optical semiconductor device with less thermal stress is realized by using a thermoplastic resin or metal package substrate and a thermoplastic bonding material. The light emitting element can be formed on a silicon substrate other than sapphire, and the substrate can be removed after being attached to the package substrate. A side reflector can be provided in the light emitting unit.

Description

  The present invention relates to an optical semiconductor device having a chip size package, and more specifically, an optical semiconductor device capable of being separately formed into individual chip size packages after bonding a light emitting element formed on a wafer and a package substrate. About.

  Conventionally, various forms are known about a light emitting element and its mounting structure (for example, refer patent documents 1-3). FIG. 1 is a cross-sectional view for explaining an example of a conventional light emitting diode and its structure. In the light emitting diode shown in FIG. 1A, light emitted from the light emitting element is extracted in the light collecting direction z. The light emitting diode includes a light emitting element 9 including a sapphire substrate 1, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film 6, and flip chip electrodes 7 and 8. Further, a package substrate 10 on which the light emitting element is mounted, an electrode 11 for taking out the electrode to the outside, an inclined side wall 12, a phosphor 13, and a cover glass cap 14 are provided. The direction in which light emitted in the active layer 4 at the interface between the P-type and N-type semiconductor layers travels is indicated by p and q in the figure. Of the light generated in the active layer 4, the light traveling in the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and guided to the light collecting direction z (q). The electrode of the P-type semiconductor 5 is connected to the flip chip electrode 7 via the conductive reflection film 6 made of metal. The electrode of the N-type semiconductor 3 is connected to the flip chip electrode 8 via the N + type semiconductor 2. Since FIG. 1 is a cross-sectional view, two flip chip electrodes are shown. However, in order to prevent the light emitting element from being inclined, four flip chip electrodes are necessary in terms of structure. The package of the light emitting element is mounted on an electrode 65 provided on a mother board 340 as shown in FIG. In the case of a white light emitting diode, it is particularly vulnerable to high voltage surges such as static electricity, so it must be handled in a static-eliminated environment. As a countermeasure against static electricity, a surge absorbing element is often mounted in a light emitting diode package.

  In the case of the structure as described above, the volume is large and it is not suitable for applications that require high-density mounting. In order to reduce the size of a packaging device, a light emitting element configured by bonding a light emitting semiconductor die to a bonding pad provided on a substrate of the device is also known (for example, see Patent Document 4). Such packaging enables downsizing of the light emitting semiconductor device suitable for the conventional printed circuit board assembly process, but since the light emitting semiconductor chip cut out from the wafer is mounted on the device substrate and bonded, the semiconductor There is a problem that a large device area is required compared to the chip size. Further, there is a problem that the packaging process cannot be performed in the wafer state in which the light emitting semiconductor is formed.

JP-A-10-93146 JP 2006-303547 A W02006-126330 JP 2009-49408 A

  In order to reduce the size of the light emitting device, when the bare chip is used as it is without using a package, it is conceivable to configure an optical semiconductor device as shown in FIG. 2A is a cross-sectional view of the light emitting element 16, FIG. 2B is a plan view of the light emitting element 16 viewed from below, and FIG. 2C is a view for explaining mounting on the mother board 340. As shown in FIG. 2A, the light emitting element 16 includes a sapphire substrate 1, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film 6, and flip chip electrodes 7, 8. It has. An oxide film 15 is provided on the side surface to protect the P-type semiconductor, N-type semiconductor and active layer from contamination. The direction in which light emitted in the active layer 4 at the interface between the P-type and N-type semiconductor layers travels is indicated by p and q in the figure. Of the light generated in the active layer 4, the light traveling in the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and guided to the light collecting direction z (q). As shown in FIG. 2B, three P electrodes 7 are formed on the P-type semiconductor 5 and one N electrode 8 is formed on the N + type semiconductor 2 as flip-chip electrodes. . As shown in FIG. 2C, an electrode 65 is provided on the mother board 340, and the semiconductor and the mother board are connected via a flip chip electrode. With such a structure, the size of the light-emitting element becomes the size of the package, which can be mounted with a small area. However, when a bare chip is mounted, since a thermal expansion coefficient differs greatly between the semiconductor element and the mother board, it is common to put an adhesive resin at the interface between the bare chip element and the mother board. In this respect, the mounting method is different from that of a normal surface mounting component.

  As the use of light emitting diodes expands, the needs for higher efficiency of light emission, size reduction, cost reduction, and the like are increasing. In order to increase the efficiency of light emission, it is necessary to have a structure in which light in all directions emitted from the light emitting layer is captured and collected in the condensing direction, and a shield is not placed in the condensing direction as much as possible. That is, for each direction of light emitted from the light emitting layer, a reflecting plate for directing in the condensing direction is provided, and an electrode is taken out from the opposite surface without placing an electrode in the condensing direction. It is necessary to have a structure in which nothing is placed, including the substrate, and to suppress reflection of light at each interface. In order to reduce the size, it is preferable to reduce the element size by improving the light emission efficiency and to have a small and simple package structure such as a chip size package (a package having the same size as the chip). However, countermeasures against surges such as static electricity need to be taken into consideration, and depending on the method of use, a method of simultaneously mounting the surge absorbing element function is also necessary. Increasing efficiency and miniaturization of light emitting diodes not only saves energy, but also reduces the number of elements, simplifies the drive circuit, and the like, and is highly effective in reducing costs.

  The present invention has been made in view of such circumstances, and can be packaged in a wafer state, that is, before the light emitting elements are individually separated, and high efficiency and downsizing can be achieved. An object is to provide an optical semiconductor device having a chip size package.

The present invention is as follows.
1. A semiconductor device comprising a light emitting element in which a compound semiconductor layer constituting a light emitting portion is formed on an element substrate and a package substrate on which the light emitting element is mounted, wherein the light emitting element is divided into one or more A light emitting unit and a device electrode for receiving power on a device electrode surface opposite to a light emitting surface from which light is extracted are provided, and the package substrate is substantially the same size as the light emitting device and is mounted with the light emitting device. An internal electrode corresponding to the element electrode on an element mounting surface, and an external electrode connected to the internal electrode and a via on a surface opposite to the element mounting surface, and the element electrode surface of the light emitting element and the By bonding the element mounting surface of the package substrate with a bonding material, the element electrode and the internal electrode are electrically connected, and the element electrode surface and the element mounting surface Is between the sealed optical semiconductor device of a chip size package, characterized in that said light emitting element formed on the wafer is configured to be separated according to the package substrate.
2. The element substrate is formed by removing the element substrate before or after being separated for each package substrate. An optical semiconductor device having the chip size package described.
3. The package substrate is a thermoplastic resin substrate, and the bonding material is an interposer made of a thermoplastic material and / or an anisotropic conductive adhesive. Or 2. An optical semiconductor device having a chip size package according to 1.
4). The package substrate is a metal substrate, and the bonding material is an interposer made of a thermoplastic material and / or an anisotropic conductive adhesive. Or 2. An optical semiconductor device having a chip size package according to 1.
5. The package substrate is a glass epoxy substrate, and an anisotropic conductive adhesive is used as the bonding material. Or 2. An optical semiconductor device having a chip size package according to 1.
6). The package substrate is a substrate having non-linear resistance characteristics. Or 2. An optical semiconductor device having a chip size package according to 1.
7). A substrate having a non-linear resistance characteristic is further interposed between the light emitting element and the package substrate with the bonding material interposed therebetween, and via electrodes provided on both sides of the substrate and vias connecting the electrodes. The element electrode of the light emitting element and the internal electrode of the package substrate are electrically connected. To 5. An optical semiconductor device having a chip size package according to any one of the above.
8). An insulating film and a conductive film are sequentially formed on the element electrode surface of the light emitting element, and a P-type polysilicon and an N-type polysilicon are sequentially formed on the conductive film, and the conductive film, the P-type polysilicon, 1. The bi-directional Zener diode comprising the N-type polysilicon. To 5. An optical semiconductor device having a chip size package according to any one of the above.
9. The element substrate is a transparent substrate. To 8. An optical semiconductor device having a chip size package according to any one of the above.
10. The element substrate is a substrate that does not transmit light. To 8. An optical semiconductor device having a chip size package according to any one of the above.
11. The element substrate is a silicon substrate. An optical semiconductor device having the chip size package described.
12 On the element substrate, the compound semiconductor layer is separated in a groove shape at a boundary separated for each light emitting element. To 11. An optical semiconductor device having a chip size package according to any one of the above.
13. 1. The above-described 1. which is configured by forming a layer containing a fluorescent material on the light emitting surface of the light emitting element or attaching a plate containing the fluorescent material. To 12. An optical semiconductor device having a chip size package according to any one of the above.
14 A transparent film is further formed in contact with the outermost surface on the light emitting surface side of the light emitting element, or a transparent plate is attached, and the refractive index of the transparent film or the transparent plate is substantially the same as the refractive index of the material of the outermost surface. The surface of the transparent film or transparent plate opposite to the surface in contact with the light emitting surface side is roughened. To 12. An optical semiconductor device having a chip size package according to any one of the above.
15. 14. The above-described 14., wherein a layer containing a fluorescent material is further formed on the transparent film or transparent plate, or a plate containing the fluorescent material is bonded together. An optical semiconductor device having the chip size package described.
16. 14. The above-mentioned 14. wherein the transparent film or transparent plate contains a fluorescent material. An optical semiconductor device having the chip size package described.
17. The light emitting device includes a back surface reflecting film on the opposite side of the light emitting surface of the compound semiconductor layer and a side surface reflecting film surrounding a side surface of each light emitting unit. To 16. An optical semiconductor device having a chip size package according to any one of the above.

  In the present invention, an element including at least an element substrate and a light emitting layer and an electrode formed thereon (including an element in an intermediate process state) is referred to as a “light emitting element”. The light emitting element includes one or two or more partitioned light emitting units. This one light emitting unit is referred to as a “light emitting cell”. A side reflector (also referred to as “micromirror”) that is configured integrally with each light emitting cell and surrounds the side surface can be provided, and a light emitting cell having a structure surrounded by the micromirror is referred to as an “optical microcell”. A light emitting element packaged or processed into a state where it can be mounted on a motherboard is referred to as a “light emitting diode” or “optical semiconductor device”.

  According to the optical semiconductor device of the chip size package of the present invention, the light emitting element in which the compound semiconductor layer is formed on the element substrate and the package substrate on which the light emitting element is mounted are provided, and the light emitting element on the wafer state or on the package substrate is separated. Since the chip size package is completed without being mounted and can be directly mounted on the mother board from the state, a small and low-cost light emitting diode can be realized by a simple manufacturing process. Since the light-emitting element includes one or more optical microcells, the efficiency of light emission can be increased. In addition, since the light emitting element includes the element electrode on the element electrode surface opposite to the light emitting surface from which light is extracted, there is nothing to block the light in the light collecting direction and the light can be extracted efficiently. The package substrate can be substantially the same size as the light emitting element, and the light emitting diode can be made extremely small. In addition, since an internal electrode is provided on the element mounting surface of the package substrate on which the light emitting element is mounted, and the element electrode surface of the light emitting element and the element mounting surface of the package substrate are bonded using a bonding material, the element electrode and the internal electrode The electrical connection between the light emitting element and the package substrate is hermetically sealed, and it can be protected from humidity and foreign matter. This optical semiconductor device having a chip size package can be packaged in a wafer state, and can be subjected to electrical inspection and optical inspection in the wafer state. And since it can handle in the wafer state or the state which extended it after isolate | separating into an individual light emitting diode, it becomes possible to reduce a package cost greatly. This optical semiconductor device can be applied not only to white light but also to all light emitting diodes.

  When the element substrate is removed before or after being separated for each package substrate, the light transmittance from the light emitting layer can be increased. In addition, an opaque element substrate can be used. Further, stress due to the difference in thermal expansion coefficient between the element substrate and the package substrate can be eliminated, and the warpage of the substrate can be avoided.

When the package substrate is a thermoplastic resin substrate and the bonding material is an interposer (intermediate substrate material) and / or an anisotropic conductive adhesive made of a thermoplastic material, a simple process using a known material is used. Thus, an optical semiconductor device having a chip size package can be manufactured. Further, since the thermal expansion coefficient of the thermoplastic substrate can be made close to the thermal expansion coefficient of the mother board, the stress when the optical semiconductor device is mounted on the mother board can be reduced.
When the package substrate is a metal substrate and the bonding material is an interposer made of a thermoplastic material and / or an anisotropic conductive adhesive, the chip size has good heat dissipation in applications that generate large amounts of heat such as white light emitting diodes. A package can be realized.
The package substrate is a glass epoxy substrate, and when an anisotropic conductive adhesive is used as the bonding material, an optical semiconductor device of a chip size package is realized by using an inexpensive existing material and a conventional printed circuit board assembly technique. can do.
When the package substrate is a substrate having nonlinear resistance characteristics, an optical semiconductor device protected from a high voltage caused by static electricity can be realized with a simple configuration. Since it is not necessary to provide a surge absorbing element in the package, the package can be made extremely small.
In the case of further including a substrate having nonlinear resistance characteristics with the bonding material interposed between the light emitting element and the package substrate, an optical semiconductor device protected from a high voltage caused by static electricity can be realized. . Since it is not necessary to provide a surge absorbing element in the package, the package can be made extremely small.

  In the case where a bidirectional Zener diode composed of a conductive film, P-type polysilicon, and N-type polysilicon formed on the element electrode surface of the light-emitting element is provided, the light-emitting element itself can have a surge absorption function. Therefore, an optical semiconductor device protected from static electricity can be made extremely small using existing materials and processes.

When the element substrate is a transparent substrate, a light emitting element can be formed using a sapphire substrate or the like that has been conventionally used to form an optical semiconductor device having a chip size package.
In the case where the element substrate is a substrate that does not transmit light, an optical semiconductor device of a chip size package can be configured by more freely selecting the material of the element substrate.
When the element substrate is a silicon substrate, the element substrate can be easily removed without applying stress to the light emitting element by etching.

  On the element substrate, the compound semiconductor layer has a notch formed in advance in a scribe portion for separating the light emitting element when the boundary separated for each light emitting element is removed in a groove shape. Thus, the semiconductor layer is separated for each light emitting element, and the influence due to the difference in thermal expansion coefficient between the semiconductor layer and the package substrate can be reduced. In particular, when the element substrate of the light emitting element is removed, the thermal stress applied to the semiconductor layer by the package substrate can be minimized.

In the case where a layer containing a fluorescent material is formed on the light emitting surface or a plate containing a fluorescent material is bonded together, a white light emitting diode of a chip size package can be realized. Since this fluorescent layer can be added in a wafer state or in a state where individual light emitting elements are not separated, the manufacturing process is simplified.
A transparent film is further formed in contact with the outermost surface on the light emitting surface side of the light emitting element, or a transparent plate is attached, and the refractive index of the transparent film or the transparent plate is substantially the same as the refractive index of the material of the outermost surface. Yes, when the surface of the transparent film or transparent plate opposite to the surface in contact with the light emitting surface side is roughened, the ratio of total reflection of the light emitted from the light emitting layer is reduced. Further, it is possible to reduce total reflection on the rough processed surface side such as a transparent plate, and to extract more light to the outside. Since the transparent plate or the like can be added in a wafer state or in a state where individual light emitting elements are not separated, the manufacturing process is simplified.
When a layer containing a fluorescent material is further formed on the transparent film or transparent plate, or a plate containing a fluorescent material is bonded together, the fluorescent material can be excited by more light. become.
When a fluorescent material is included in the transparent film or the transparent plate, an efficient white light emitting diode can be realized in a chip size by an extremely simple structure and process.
When the light emitting element includes a back surface reflecting film on the opposite side of the light emitting surface of the compound semiconductor layer and a side surface reflecting film surrounding the side surface of each light emitting unit, the light emitting element emits light in each direction. It is possible to extract the light that travels in the light collecting direction, and it is possible to realize a chip-sized optical semiconductor device that is excellent in light collecting efficiency.

The present invention will now be described in the following detailed description, with reference to the referenced drawings, by way of example of exemplary embodiments according to the present invention. Like reference numerals designate like parts or configurations throughout the several views of the drawings.
Sectional drawing for demonstrating the structure of the conventional light emitting diode Sectional drawing for demonstrating the case where a light emitting element is mounted by a bare chip. Conceptual diagram of the light collection method using the reflective film on the back of the light emitting layer and the side reflector Cross-sectional view for explaining the concept of chip size package and its mounting example Sectional drawing for demonstrating the manufacturing process of an optical microcell Sectional drawing and top view for demonstrating the optical microcell of FIG. Sectional drawing and perspective view for demonstrating the light emitting element comprised including the optical microcell of FIG. Sectional drawing when a surge absorption layer is provided in the light emitting device of FIG. Sectional drawing and top view for demonstrating a light emitting element provided with the bidirectional | two-way Zener diode formed on the element electrode surface Sectional drawing for demonstrating the process of forming a semiconductor layer on a silicon substrate Sectional drawing for demonstrating the process of forming an optical microcell on a silicon substrate Sectional drawing and perspective view for demonstrating the light emitting element using a silicon substrate Sectional drawing for demonstrating each embodiment of a light emitting element Sectional drawing for demonstrating one Embodiment of a light emitting diode Sectional drawing for demonstrating the manufacturing process of the light emitting diode of FIG. Sectional drawing for demonstrating another embodiment of a light emitting diode Sectional drawing for demonstrating the manufacturing process of the light emitting diode of FIG. Sectional drawing for demonstrating the manufacturing process which uses a silicon substrate for the light emitting diode of FIG. Sectional drawing for demonstrating another embodiment of a light emitting diode Sectional drawing for demonstrating the manufacturing process of the light emitting diode of FIG. Sectional drawing for demonstrating the manufacturing process which uses a silicon substrate for the light emitting diode of FIG. Sectional drawing for demonstrating embodiment of the light emitting diode which uses a glass epoxy board | substrate Sectional drawing for demonstrating the manufacturing process of the light emitting diode of FIG. Sectional drawing for demonstrating another embodiment of the light emitting diode which uses a glass epoxy board | substrate. Sectional drawing for demonstrating the manufacturing process of the light emitting diode of FIG. Sectional drawing for demonstrating the manufacturing process which uses a silicon substrate for the light emitting diode of FIG. The figure explaining the relationship between a sapphire wafer, a light emitting element, and a light emitting diode The figure explaining the relationship between a silicon wafer, a light emitting element, and a light emitting diode A top view, a cross-sectional view, and a bottom view for explaining the entire light emitting diode The figure for demonstrating the example of mounting to the motherboard of this light emitting diode

  The novel point of the present invention is to manufacture a chip size package in a wafer state and achieve high efficiency, miniaturization and cost reduction at the same time. Furthermore, it is to enable surge countermeasures. A semiconductor device housed in a chip size package of the present invention includes a light emitting element and a package substrate on which the light emitting element is mounted. A light-emitting element is provided with an electrode surface (element electrode surface) on a sapphire substrate (element substrate) in which a light-emitting layer made of a compound semiconductor is formed using flip chip technology, and the element electrode surface and one surface of a package substrate (Element mounting surface) are bonded together. The package substrate can be approximately the same size as the area of the light emitting element when finally separated into individual optical semiconductor devices. As the package substrate, a printed circuit board using a thermoplastic material or metal, a printed circuit board having nonlinear resistance characteristics (hereinafter referred to as “varistor substrate”), or the like can be used. The element mounting surface of the package substrate is provided with a conductor portion (internal electrode) for connecting to a flip chip electrode provided on the element substrate, and a conductor portion (electrode) of the semiconductor device (on the opposite side surface). External electrode) is provided. The internal electrode and the external electrode are connected by a through via. In order for the printed circuit board to become a package material, the electrical connection between the material of the flip chip electrode (for example, gold) provided on the element substrate and the conductor (for example, copper) of the internal electrode of the printed circuit board is ensured. It is necessary to In addition, it is necessary that the element electrode surface of the element substrate and the element mounting surface of the printed board are in close contact with each other. The size and shape of the printed circuit board before being separated into individual optical semiconductor devices may be a round shape equivalent to the wafer size, or may be a square shape with one side larger than the diameter of the wafer. If the flip chip electrode is gold and the printed circuit board conductor is copper, the eutectic temperature of gold and copper is about 250 ° C. It is preferable to bond them together. On the other hand, as a bonding material used for bonding, a material whose fluidity increases at about 300 ° C., such as a synthetic material of thermoplastic PEEK (polyetheretherketone) and PEI (polyetheretherimide), etc. Is preferred. Adhesion and electrical connection between the element electrode surface of the element substrate and the printed circuit board can be ensured by applying pressure and bonding at a temperature of about 300 ° C. using such a bonding material. For example, when a thermoplastic printed circuit board mainly composed of PEEK material is used as the printed circuit board, the element electrode surface and the printed circuit board are in close contact with each other, and the gold on the flip chip electrode and the copper on the printed circuit board are eutectic bonded. Thus, strength and conductivity are ensured. Moreover, when using a thermoplastic substrate, there exists an advantage that the thermal expansion coefficient can be brought close to a motherboard.

As described above, in the state where the element substrate and the package substrate are bonded to each other, the function of physically supporting the light emitting layer can be imposed on the package substrate. When the element substrate is sapphire, the sapphire substrate is the outermost surface in the light collecting direction. Therefore, by removing the sapphire substrate that has supported the light emitting layer so far, it is possible to increase light transmission and avoid warping of the substrate due to a difference in thermal expansion coefficient from the thermoplastic printed circuit board. By removing the sapphire substrate, an extremely thin semiconductor layer which is a light emitting layer is mounted on the package substrate. The sapphire substrate can be peeled off by a known lift-off method. In that case, the sapphire substrate can be reused. According to the lift-off method, it is possible to peel the sapphire substrate at a temperature at the time of bonding or a temperature close thereto after bonding to the package substrate in the wafer state. Thereby, stress due to the difference in thermal expansion between the sapphire substrate and the package substrate can be reduced. Further, since the thermal expansion coefficient of the package substrate and the thermal expansion coefficient of the semiconductor layer remaining thereon are different, the semiconductor substrate is formed on the sapphire substrate, and a cut is made at the position of the scribe line for separating the light emitting elements. It is preferable to form a part. Since the semiconductor layer on the cut portion is removed in a groove shape, the semiconductor layer is separated on the scribe line, and the influence of the difference in thermal expansion coefficient between the semiconductor layer and the package substrate can be minimized.
In the case of a light emitting diode using a phosphor, the phosphor can be applied or bonded in a state where the light emitting layer is bonded to the package substrate in a wafer state. This makes it possible to package the light emitting element in the wafer state and to apply the phosphor.

  As another structure of the light-emitting element, a compound semiconductor layer serving as a light-emitting layer can be formed over a substrate that does not transmit light (for example, a silicon substrate). Similarly to the case of the sapphire substrate, a flip chip electrode can be provided on the silicon substrate, and a chip size package can be formed by bonding to a printed circuit board as a package substrate. In this case, after bonding to the package substrate, the silicon substrate can be removed by etching. By removing the opaque element substrate, an extremely thin semiconductor layer as a light emitting layer or a transparent electrode or transparent film provided on the semiconductor layer becomes the outermost surface in the light collecting direction. Can be released to the outside. Since silicon as a substrate can be etched at 100 ° C. or lower using a KOH aqueous solution or the like, there is an advantage that it can be easily removed without applying temperature stress. The semiconductor layer on the silicon substrate can also be formed by attaching the silicon substrate and the sapphire substrate on which the semiconductor layer is formed in a wafer state, and then lifting off the sapphire substrate. Only inorganic materials such as compound semiconductors, indium oxide films, and silicon oxide films are formed on the sapphire substrate, and there is no organic material with a low glass transition temperature. The alignment and lift-off process can be performed. The idea of using a silicon substrate that does not transmit light as the compound semiconductor substrate and bonding it to the package substrate and then removing the silicon substrate by simple etching is extremely novel and has many advantages.

  A metal base substrate (metal substrate) can also be used as the material of the package substrate. The metal material is not particularly limited, and examples thereof include aluminum and copper. It is also possible to use a thermoplastic bonding material for bonding the metal substrate and the element substrate. For example, a metal substrate and an element substrate on which a compound semiconductor is formed are bonded together via a thermoplastic PEEK / PEI sheet material. In that case, by performing heat treatment at about 300 ° C., bonding and eutectic bonding of the electrodes can be performed simultaneously. The metal substrate is suitable for a field where the feature of good thermal conductivity can be utilized. For example, a high-intensity white light emitting diode has a large heat generation, and a metal substrate is optimal as a chip size package with good heat dissipation. Also in this case, it is desirable to remove the element substrate near the bonding temperature. Further, by forming cuts (grooves) in the scribe line portion of the element substrate so that the light emitting elements are separated after the element substrate is removed, the stress due to the difference in thermal expansion coefficient can be reduced. .

  Further, a widely used glass epoxy substrate can be used as the package substrate. However, the glass epoxy substrate has a heat resistant temperature as low as about 200 ° C. or less, and the thermoplastic bonding material cannot be used. Thus, bonding at about 100 ° C. is possible by bonding the element substrate and the glass epoxy substrate through an anisotropic conductive adhesive in the wafer state. In this case, the bonding between the electrodes is performed through metal particles of about 20 μm. As the anisotropic conductive adhesive, a heat seal material used for connecting a glass substrate and a circuit board in a liquid crystal can be used. Since electrical bonding is contact through metal particles, the contact resistance is about 0.1Ω. For this reason, the above configuration cannot be used for a large current application, but can be sufficiently used for a surface-emitting liquid crystal backlight application or the like having a driving current of about several tens of mA. The feature of this configuration is that a chip size package can be configured by a combination of existing materials and a novel structure. In addition, if the above-described silicon substrate is used as the element substrate, the substrate can be removed at 100 ° C. or lower, so that the process can be easily formed even if a glass epoxy substrate is used. Also in this case, it is desirable to remove the element substrate near the bonding temperature. Further, by forming cuts (grooves) in the scribe line portion of the element substrate so that the light emitting elements are separated after the element substrate is removed, the stress due to the difference in thermal expansion coefficient can be reduced. .

A substrate having a non-linear resistance characteristic (varistor substrate) can also be used as the package substrate. When a voltage exceeding a certain voltage (for example, 12V) is applied between two electrodes, the varistor substrate suddenly decreases in resistance and causes a current to flow in the substrate. Therefore, the light-emitting element can be protected from a high voltage caused by static electricity. . When a varistor substrate is used as the package substrate, a thermoplastic interposer material or an anisotropic conductive adhesive can be used as a bonding material to the element substrate.
It is also possible to constitute a chip size package by combining the thermoplastic substrate or metal substrate and the varistor substrate. Electrodes are provided on both sides of the varistor substrate, and the electrodes on both sides are connected through vias. Then, a varistor substrate is sandwiched between the light emitting element on which the compound semiconductor is formed and the thermoplastic substrate or metal substrate, and heat is applied between the light emitting element and the varistor substrate and between the varistor substrate and the thermoplastic substrate. It can be set as the structure bonded together using a plastic interposer material or an anisotropic conductive adhesive. The element electrode of the light emitting element and the internal electrode of the package substrate are electrically connected via electrodes and vias provided on the varistor substrate. If a thermoplastic PEEK / PEI sheet material is used as an interposer, bonding and eutectic bonding of the electrodes can be performed simultaneously by heat treatment at about 300 ° C.

  As described above, an optical semiconductor device having a chip size package can be formed in a wafer state or in a state where individual light emitting elements are not separated. In addition, optical characteristics and electrical characteristics of the light emitting diode can all be inspected in the wafer state. Then, if the package substrate is divided, an optical semiconductor device packaged in a chip size can be obtained. The optical semiconductor device in a chip size package can be carried in a wafer state, a state in which the package substrate is not separated, a state in which it is attached to an expansion sheet, or the like. It can also be mounted on a motherboard in the same state.

  When each chip size package is provided with a protective element for countermeasures against static electricity, a method of forming a surge absorbing element with a thin film on the light emitting element itself can be used. As a method of forming the surge absorbing element with a thin film, there is a method of forming a Zener diode made of P-type polysilicon and N-type polysilicon. When the surge absorbing element is formed as a thin film in the light emitting element, the surge absorbing element can be incorporated in the wafer state or in a state where the individual light emitting elements are not separated, and there is no need to increase the package size.

In the chip size package formed as described above, there is no one that blocks light from the light emitting layer in the light collecting direction. In this state, it is possible to reduce the ratio at which the emitted light is totally reflected in the light emitting layer by roughening the surface on the light collecting direction side of the light emitting layer with blast or the like. In addition, in a white light emitting diode, a film (phosphor) containing a fluorescent material can be formed in this state. The phosphor can be formed by applying and curing a thick organic phosphor. It is also possible to form the phosphor in a wafer state by attaching an inorganic phosphor in conformity with the shape of the package substrate. When the inorganic phosphor is a ceramic thin plate, the light traveling toward the light-emitting layer among the light having a long wavelength excited inside the phosphor is reduced by reducing the optical refractive index of the transparent adhesive used for bonding. It is also possible to have a structure in which the light is totally reflected as much as possible and directed in the light collecting direction. Further, it is possible to design the surface of the phosphor on the light collecting direction side so that the light is not totally reflected.
Further, in a state where the element substrate is removed after the element substrate and the package substrate are bonded together, a high refractive index layer (transparent film or transparent plate) having a refractive index substantially the same as that of the semiconductor layer or larger than that of the semiconductor layer is disposed in the light collecting direction It can also be provided on the outermost surface. In that case, by making the contact surface of the high refractive index layer with the semiconductor layer a mirror surface, it is possible to reduce total reflection due to a difference in refractive index with respect to light incident from the semiconductor layer. In addition, the surface of the high refractive index layer on the light collecting direction side is subjected to a satin finish or the like to suppress total reflection, and as a whole, a structure that can extract as much light from the light emitting layer as possible in the light collecting direction. it can. Further, a simple structure can be obtained by adding a fluorescent substance to the material of the high refractive index layer. According to this chip size package, it is possible to add a phosphor or a high refractive index layer as necessary in a wafer state or in a state where individual light emitting elements are not separated.

  In the conventional light emitting diode structure, there is a problem that light in the side surface direction of the light emitting element cannot be captured. In a chip size package, light is blocked by a protective resin material in the side surface direction of the light emitting element. As a countermeasure, a structure for extracting the light in the side surface direction in the light collecting direction inside the light emitting element as much as possible is required. This can be realized by providing a side reflector (micromirror) inclined at about 45 degrees in the light emitting element to take out light in the side direction generated in the active layer in the light collecting direction. By the reflection film provided on the side opposite to the light collecting direction and the micromirror, light in all directions generated in the light emitting layer can be directed in the light collecting direction. In a state where each light emitting element configured as described above is packaged in a chip size, most of the light emitted from the light emitting layer can be extracted in the light collecting direction.

  FIG. 3 shows a concept of a method for providing a micromirror in a light emitting element. The light emitting element shown in FIG. 3A includes a semiconductor layer composed of an N-type semiconductor 3, an active layer 4, and a P-type semiconductor 5 on a sapphire substrate 1. Of the light generated from the active layer 4, the light directed in the light collecting direction z is emitted as it is (p), and the light in the opposite direction is reflected and emitted in the light collecting direction by the back reflecting film 6 (q). The light in the direction is reflected by the micromirror 70 provided in the vicinity of the light emitting layer and is emitted toward the light collecting direction (r). In this case, the inclination angle α of the side micromirror is a value within 0 to 90 degrees. Although it is known to provide the back reflecting film 6 on the side opposite to the light emission direction, it is very novel to provide the micromirror 70 in the element in the side surface direction. FIG. 3B shows a cross section of the light emitting element to be constructed based on this concept. This light emitting element is formed on one sapphire substrate 1 and is composed of a plurality of light emitting cells (light emitting portions) 80. In the cross section of the figure, four light emitting cells are represented. Each light emitting cell 80 includes a semiconductor layer similar to that shown in FIG. Each light emitting cell 80 is surrounded by a micromirror 71 on its side surface, and constitutes an optical microcell. A conductive reflective film (back reflective film) 275 is formed below each optical microcell. The method of light propagation from the light emitting layer in the optical microcell is indicated by p, q, and r as in FIG. Note that power is supplied to the semiconductor layer in each optical microcell from the flip chip electrodes 7 and 8 via the wiring layer 90.

  In the white light emitting diode, a phosphor containing a fluorescent material is provided in the light collection direction z of the optical microcell, and the fluorescent material is excited by light extracted from the optical microcell to emit light having a long wavelength. Since this excited light is emitted in all directions in the phosphor, a condensing means for this light is newly required. The light is emitted as it is in the condensing direction, part of the light in the opposite direction is reflected at the interface between the phosphor and the semiconductor layer and emitted in the condensing direction, and part of the light reaches the inside of the semiconductor and is reflected in the condensing direction by the reflective film. It can be made to reflect. As described above, it is preferable to provide a high refractive index layer between the phosphor layer and the semiconductor layer or to provide a half mirror function.

  By the means as described above, a light emitting diode that can achieve high efficiency, miniaturization, and low cost at the same time can be configured. That is, the package is the same size as the chip size of the light-emitting element, and the light emitted from the light-emitting layer and extracted in each direction can be extracted in the light collecting direction, and the element substrate on the surface of the semiconductor layer is removed. Thus, the light can be collected without being attenuated. In the case of a white light emitting diode, the phosphor can be provided directly on the semiconductor layer, and an ideal state is obtained in which there are no inclusions between the semiconductor layer and the phosphor. The expensive sapphire substrate on which the semiconductor layer has been formed can be reused if the lift-off is optimized, and the cost can be further reduced.

  The concept of the package structure of the optical semiconductor device of the present invention is shown in FIG. The light emitting element 16 in the wafer state shown in FIG. 4B, the thermoplastic interposer (intermediate substrate material) 350 having the same size as the wafer shown in FIG. 4C, and the same size as the wafer shown in FIG. 4D. The package substrate 40 is bonded together with the light emitting elements in the wafer state, and packaging and interelectrode connection are performed simultaneously. Thereafter, for white light-emitting diode applications, the same size phosphor 330 shown in FIG. 4A to 4D depict only a portion corresponding to one light emitting element of the wafer or each material having the same size. Thereafter, the light emitting element and the package substrate are integrally divided to form the light emitting diode 21 as shown in FIG. 4F and can be mounted on the mother board 340. In the case of a white light emitting diode, in order to direct secondary light emission from the phosphor 330 in the light collecting direction z, after mounting on the mother board, comprehensive light capture is performed using a reflector 150 as shown in FIG. It is also possible to do. The light emitting element 16 has the same configuration as the light emitting element shown in FIG. For example, the flip chip electrodes 7 and 8 can be formed to have a height of about 20 μm by forming a stud bump of about 30 μm and performing leveling for uniform height. The interposer 350 has a thickness of about 50 μm and is made of a thermoplastic material based on a PEEK / PEI material. The interposer 350 becomes a liquid at 400 ° C., and therefore a material recommended to be bonded at 300 ° C. can be used. The package substrate 40 can be a printed circuit board made of a similar thermoplastic material. Vias 50 are formed in the printed circuit board, and external electrodes 60 and internal electrodes 61 made of copper or the like are connected thereto. The via 50 can be made of a metal whose main material is silver or the like. In applications that generate a large amount of heat, the thermal resistance can be lowered by providing as many vias as possible. A material at a wafer level can be completed by combining the materials shown in FIGS. 4B to 4D in a wafer state and pressurizing and curing in a vacuum of about 300 ° C. If necessary, a phosphor is bonded and divided into light emitting element chips, whereby the light emitting diode 21 is obtained.

  More specifically, the light emitting element 16 shown in FIG. 4B includes a sapphire substrate 1, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a reflective conductive film 6, and a flip chip electrode. 7 and 8. The flip-chip electrode can be formed by gold plating in addition to the stud bump method. As the package substrate 40 serving as a base of the package, a metal substrate, a varistor substrate, or the like may be used in addition to a substrate using a thermoplastic material. The package substrate 40 and the light emitting element 16 are bonded together via an interposer 350 made of a thermoplastic material, and adhesion is ensured by bonding in a vacuum at a temperature exceeding 300 ° C., which is the softening temperature of the material. Moreover, since the edge part of a semiconductor layer is sealed with a thermoplastic material, the thermoplastic material has played the role as the protective material after element division. When the surface of the conductor constituting the internal electrode 61 of the package substrate is copper and the material of the flip chip electrode is gold, the gold and copper are bonded at a temperature equal to or higher than the eutectic temperature so that they are completely bonded. Is done. The light-emitting diode 21 shown in FIG. 4F shows a state separated from the wafer state. The phosphor 330 is added to the sapphire substrate 1, and the phosphor 330 is the outermost surface of the light-emitting element. In the figure, p, q, and r indicate directions in which light (primary light emission) from the light emitting layer travels. The light traveling from the light emitting layer toward the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the reflecting film 6 and emitted in the light collecting direction z (q). A very small part of the light traveling in the direction perpendicular to the light collecting direction z, that is, along the active layer is extracted to the outside (r). The light from the light emitting layer excites the fluorescent material and secondary light emission occurs. The secondary emitted light is emitted in each direction such as directions indicated by s, t and u in the figure.

There are two problems with the light-emitting diode 21 shown in FIG. It is the capture of light in the lateral direction and the mounting of an electrostatic protection element (surge absorbing element). However, when a varistor substrate is used as the printed circuit board 40, the varistor substrate material itself has a high voltage and a low resistance, so no other surge absorbing element is required.
In the process of dividing the light emitting element in the wafer state and mounting it on the mother board as it is, if a protective element is provided in advance at one or a plurality of places on the mother board, no countermeasure against static electricity is required as the light emitting diode. Although such a process is recommended, a surge absorbing element can be provided in the light emitting diode of this chip size package in order to provide versatility.

(Light emitting element)
With reference to FIGS. 5 to 8, a manufacturing process of the light emitting element and a method of providing a micromirror in the light emitting element will be described. FIG. 5 is a cross-sectional view illustrating an example of a manufacturing process of an optical microcell. In FIG. 5A, a light emitting layer composed of an N + GaAlN layer 210, an N-type GaAlN layer 220, an active layer 230, and a P-type GaAlN layer 240 is formed on a sapphire substrate 200 by a known method, and a photoresist pattern is further formed. The state where 260 is formed is shown. FIG. 5B shows a state in which the P-type GaAlN layer 240, the active layer 230, and the N-type GaAlN layer 220 are wet-etched so as to provide an inclined surface (tapered portion) 250 by a taper etching technique. In FIG. 5C, after the photoresist 260 is removed after FIG. 5B, a new photoresist is formed and the N + GaAlN layer 210 on the scribe line is removed by etching. A state is shown in which a cut (groove) portion 47 is provided at the position of the scribe line serving as a boundary and the photoresist is removed thereafter. FIG. 5D shows a state in which a conductive reflective film 270 is then laminated on the entire surface and a pattern is formed by a photolithography technique. The conductive reflective film 270 is formed so as to cover almost the entire surface of the P-type GaAlN layer 240. FIG. 5E shows a state in which the silicon oxide film 280 is formed on the entire surface from that state. FIG. 5F shows a state in which a photoresist is provided in this state, the electrode portion is taper-etched by photolithography, and then the photoresist is removed. The electrode portions 281 and 282 show a state where taper etching has been performed. FIG. 5G shows a state in which a metal thin film is laminated on the entire surface, and thereafter a P-type electrode 290 and an N-type electrode 291 are formed using the same photolithography technique, and the photoresist is removed. Thus, the optical microcell 80 is formed.

  FIG. 6 is a diagram for explaining the structure of the optical microcell formed as described above. FIG. 6A shows a cross section of the optical microcell 80, and the light collection direction z is downward. FIG. 6B is a plan view in which the optical microcells 80 are formed side by side. In FIG. 6A, the directions in which light generated in the active layer 230 of the optical microcell 80 travels are represented by p, q, and r. Light traveling from the active layer 230 in the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the conductive reflection film 270 and emitted in the light collecting direction z (q). The light in the direction along the active layer 230 is reflected by the micromirror 71 and emitted in the light collecting direction (r). The micromirror 71 has a reflective surface constituted by an N-type electrode 291 formed in a tapered shape. In the plan view of FIG. 6B, the boundary between the P-type electrode 290 and the N-type electrode 291 is shown. The region of the active layer 230 of each light emitting cell is indicated by a boundary 231. These boundaries are formed with rounded corners so that the electric field is not concentrated.

  FIG. 7 is a schematic view of the entire light emitting element. One light emitting element is configured to include one or two or more divided light emitting portions (light emitting cells) on an element substrate. As shown in FIGS. 5 and 6, one light emitting unit is composed of light emitting cells (light emitting layers) that are formed one by one. One optical microcell is configured by surrounding the side surface of one light emitting cell with a micromirror. That is, one light emitting element is composed of one or more optical microcells. In the light emitting element 17 shown in FIG. 7A, an optical microcell layer 300 including a plurality of light emitting cells 80 and micromirrors 71 is formed on a sapphire substrate 200, and a conductive reflective film layer 275 is formed thereon. Is formed. One light microcell is constituted by one light emitting cell 80 and the micromirror 71 provided on the entire periphery thereof. A power source connected to the P-type electrode and the N-type electrode of each light emitting cell 80 is wired in the wiring layer 310, and each power source is supplied from the flip chip electrode layer 320. The semiconductor layer formed on the sapphire substrate 200 is removed in the shape of a groove by providing a cut portion 47 at the position of a scribe line that becomes a boundary separated for each light emitting element. FIG. 7B is a perspective view of the light emitting element 17. Although the flip-chip electrode is not shown in the process shown in FIG. 5, it can be formed by forming a gold thin film in the wafer state and etching it. Alternatively, gold bumps may be provided by a stud bump method in the wafer state and then flattened.

  FIG. 8 shows a cross-sectional structure of a light-emitting element in which a Zener diode polysilicon layer is provided in the middle of the process shown in FIG. The light emitting element 18 of FIG. 8 includes a surge absorbing diode layer 95 provided with a bidirectional Zener diode.

  FIG. 9 shows details of the surge absorbing diode. After the P-type electrode 290 and the N-type electrode 291 that also serves as the reflection surface of the micromirror are formed by the process shown in FIG. 5, a planarization layer is formed with a silicon oxide film 285 as shown in FIG. A conductive film 190 made of indium oxide or the like is provided thereon. Further, P-type polysilicon 97 and N-type polysilicon 96 are formed on the conductive film 190 at a low temperature. Even if the temperature is low, the temperature is about 500 ° C. Therefore, the P-type electrode 290 and the N-type electrode 291 must be formed of a material having a high melting point such as chromium or nickel. Polysilicon is recrystallized by laser annealing to complete the diode. FIG. 9B is a plan view thereof. The diode N-type surfaces are 98 and 99, and the P-type surfaces are connected via the conductive film 190 to form a bidirectional Zener diode as a whole.

The manufacturing process and structure of another light emitting device will be described with reference to FIGS. FIG. 10 shows a manufacturing method for forming a semiconductor layer on an element substrate. FIGS. 10A to 10D show a method of providing a semiconductor layer on a silicon substrate, and FIGS. 10E and 10F show a method of providing a semiconductor layer on a sapphire substrate having a rough surface. Show. The meaning of providing a semiconductor layer on a silicon substrate instead of a known sapphire substrate is that the silicon substrate can be easily removed later by etching. That is, in the case of sapphire, a lift-off method is required in which the interface is partially peeled off at a high temperature using a laser or the like, whereas in the case of silicon, it is extremely low at 100 ° C. or less by etching with KOH liquid or the like. Easy to remove. In FIG. 10A, a P-type GaAlN layer 240, an active layer 230, and an N-type GaAlN layer 220 are formed as semiconductor layers on a sapphire substrate 200, an indium oxide film 190 is formed thereon, and silicon is further formed thereon. A state in which the oxide film 180 is formed is shown. The indium oxide film 190 is provided for the purpose of reducing the resistance of the N-type semiconductor layer and for the purpose of end point management during etching of the semiconductor layer. The silicon oxide film 180 is provided for bonding to the silicon substrate. It is also possible to perform CMP (Chemical Mechanical Polishing) as pre-bonding processing. However, in the configuration of this example, the base of the silicon oxide film is all a flat film, and the silicon oxide film is also a flat film, so CMP processing is not necessarily required. As shown in FIG. 10C, the sapphire substrate on which the semiconductor layer is formed and the silicon substrate 170 are bonded together. Thereafter, as shown in FIG. 10D, the sapphire substrate 200 is removed by lift-off. In this state, the silicon substrate becomes a substrate for the light emitting element.
FIGS. 10E and 10F show a method in which a semiconductor layer is provided on a sapphire substrate whose surface is textured. Rather than providing a semiconductor layer on a known sapphire substrate, the meaning of providing a semiconductor layer on a satin-finished sapphire substrate is that when the sapphire substrate is used without being lifted off, the total reflectance of light emitted from the light emitting layer is reduced. In order to make it low, an irregular reflection layer or a multi-surface reflection layer is provided between the light emitting layer and the sapphire substrate. As shown in FIG. 10E, a semiconductor layer is stacked on the sapphire substrate 200 by a known technique. Another sapphire substrate 201 is processed in advance so that the surface is irregularly reflected or multifaceted, and an indium oxide film 191 is formed thereon. The indium oxide film 191 is a thin film that has been planarized by CMP technology, and the surface of the indium oxide film 191 and the surface of the indium oxide film 190 formed on the outermost surface of the sapphire substrate 200 are surface activated. Paste after processing. FIG. 10F shows a state where the sapphire substrate 200 is lifted off after bonding. This substrate is a substrate in which the antireflection structure as described above is provided between the sapphire substrate 201 and the indium oxide film 191. The method of handling the substrate in the subsequent processing steps is the same as that of the semiconductor layer on the sapphire substrate when the matte processing is not performed. As an additional merit, the indium oxide film becomes an etching stopper for the semiconductor layer, so that etching management is easy.

  FIG. 11 shows a procedure for forming an optical microcell on the silicon substrate 170. This is almost the same as the process shown in FIG. In the taper etching of the semiconductor layer shown in FIG. 11B, since the indium oxide 190 serves as a stopper for etching the compound semiconductor, the management of the processing is much easier. The subsequent steps are the same as those in FIG.

  FIG. 12 is a schematic view of the entire light emitting device prepared by the procedure of FIG. In the cross section of the light emitting element 19 shown in FIG. 12A, an optical microcell layer 300 including a plurality of light emitting cells 80 and micromirrors 71 is formed on a silicon substrate 170, and a conductive reflective film is formed thereon. A layer 275 is formed. One light microcell is constituted by one light emitting cell 80 and the micromirror 71 provided on the entire periphery thereof. A power source connected to the P-type electrode and the N-type electrode of each light emitting cell 80 is wired in the wiring layer 310, and each power source is supplied from the flip chip electrode layer 320. FIG. 12B is a perspective view of the light emitting element 19. It is the same as the light emitting element 17 shown in FIG. 7 except that the substrate is different. In FIG. 12A, p, q, and r indicated by broken lines indicate the direction of light from the light emitting layer, but the silicon 170 does not pass light in the state shown in the drawing, and is shown for reference. Silicon 170 is removed in a later process.

  FIG. 13 is a cross-sectional view of each light-emitting element described above. 13A is a structural view of the light emitting element 16 (FIG. 2A), FIG. 13B is a structural view of the light emitting element 17 (FIG. 7A), and FIG. FIG. 13 is a structural diagram of the light emitting element 19 (FIG. 12A). Each represents one of the light emitting elements formed in a wafer state or a state separated for each light emitting element. 13A to 13C, the basic concept of the structure of the chip size package constituting the optical semiconductor device of the present invention is common.

(Optical semiconductor device)
14 to 18 show specific examples of the present optical semiconductor device. Although an example in which a thermoplastic substrate is used as the package substrate will be described, the same applies to the case where a varistor substrate is used.

  FIG. 14 shows a form (cross section) of light emitting diodes 20 to 22 using the light emitting element 16 shown in FIG. 13A and using a thermoplastic material as a package material. Each represents one of the light emitting diodes formed in the wafer state or a state separated for each light emitting diode. The basic form is FIG. 14A, FIG. 14B is a case where the sapphire substrate 1 is removed from the basic form by lift-off, and FIG. 14C is a case where the phosphor 330 is added. The light emitting diode 20 of FIG. 14A is composed of the light emitting element 16, a thermoplastic interposer 42, and a thermoplastic printed board 41. In this light emitting diode, the sapphire substrate 1 side is the light condensing direction, and the printed circuit board 41 side is the electrode side of the chip size package. The important points in the structure are to extract as much light as possible in the light collecting direction, to ensure the electrical connection between the internal electrode 61 of the printed circuit board and the flip chip electrodes 7 and 8, and the surface of the light emitting element 16. This is to ensure the adhesion with the surface of the printed circuit board 41 and the thermoplastic interposer 42 to protect against humidity and foreign matter.

  Of the light emitted from the light emitting layer, the light traveling in the condensing direction is extracted as it is in the condensing direction, and the light traveling in the opposite direction is reflected by the reflecting film 6 and extracted in the condensing direction. Light in the direction along the active layer is not utilized. In order to extract as much light directed toward the light collecting direction to the outside as much as possible, it is also possible to provide a fine scattering layer between the light emitting layer and the sapphire substrate as described above. In addition, as shown in FIG. 14B, the sapphire substrate can be removed by lift-off technology after the light-emitting element and the printed circuit board are combined, and a scattering layer is provided by processing the semiconductor surface after lift-off. Is also possible.

  Between the electrode 61 on the printed circuit board side and the flip chip electrodes 7 and 8, the temperature at the time of bonding is about 300 ° C., so that the copper of the internal electrode of the printed circuit board and the gold of the flip chip electrode are shared. It becomes a crystal state and an intermetallic compound is generated and firmly connected.

  Regarding the adhesion between the surface of the light emitting element 16 and the surface of the printed circuit board 41, since the temperature at the time of bonding is about 300 ° C., both the thermoplastic interposer and the printed circuit board are above the softening point, and the adhesion is complete. Become.

In this way, the structure shown in FIG. 14A satisfies the requirements for configuring a chip size package. In FIG. 14A, if a structure in which the interface between the sapphire substrate and the semiconductor layer is rough (the structure mentioned with reference to FIG. 10F) is used, the total reflection of light in the light emitting layer can be reduced. it can. FIG. 14B shows a state in which the sapphire substrate 1 is removed from the drawing (a) by the lift-off method. Since the thermal expansion coefficient differs between the sapphire substrate and the thermoplastic printed circuit board, it is preferable to lift off the sapphire substrate at a temperature close to the bonding temperature (about 300 ° C.) after the bonding of both. Thereby, the interface stress due to the difference in thermal expansion coefficient can be prevented from remaining. In addition, after the sapphire substrate is removed, the semiconductor layer on the sapphire substrate is present on the printed circuit board. In order to relieve stress between the semiconductor layer and the printed circuit board when the temperature is returned to room temperature, the cut portion 47 can be formed in a scribe line on the sapphire substrate. Thus, after the sapphire substrate is removed, the semiconductor layer is separated from the wafer state for each light emitting element, and the stress generated between the printed board and the semiconductor layer can be minimized.
After this, the temperature is returned to room temperature, and the surface after removal of the sapphire substrate can be roughened as necessary. In addition, a transparent plate 390 (for example, non-alkali glass) made of a material having a refractive index close to that of the semiconductor layer can be bonded without roughening the surface, as indicated by a broken line in FIG. 14B. is there. By making the surface on the semiconductor layer side of the transparent plate 390 a mirror surface and the opposite surface as a satin finish, it is easy to make a structure that easily emits light to the outside. In order to reduce the total reflection of light emitted from the semiconductor layer, it is effective to provide such a material having a close refractive index as an optical buffer. A similar structure can be provided for the phosphor 330 shown in FIG. For example, instead of the transparent plate 390, a thin plate-like phosphor 330 whose base layer is glass or ceramics having a mirror surface on the semiconductor layer side and a matte finish on the opposite surface can be bonded. Optically, it has a structure that lowers the total reflectivity from the semiconductor layer side by making the refractive index of light the same at the interface with the semiconductor layer, and lowers the total reflectivity by scattering on the satin surface. is there. The phosphor 330 is not limited to a glass or ceramic thin plate. For example, in a state where the sapphire substrate is lifted off, or in a state where the surface is blasted from that state, a liquid resin phosphor having a high viscosity is applied to a predetermined thickness by a spinner and then cured to obtain a phosphor. The forming method is simple and effective. Also in this case, reflection of light from the light emitting layer to the air can be reduced by selecting a material whose refractive index after curing is close to that of the semiconductor.
The transparent plate 390 and the phosphor 330 can be applied in a state where the semiconductor layer is bonded to the printed board in a wafer state.

FIG. 15 shows an example of a manufacturing process of the structure shown in FIG. FIG. 15A shows a state in which a light emitting layer and flip chip electrodes 321 and 322 are formed on a sapphire substrate 200 which is an element substrate. The N + semiconductor layer 210 is a layer for reducing the electrical resistance of the N-type semiconductor surface, and a light emitting layer composed of the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 is formed. A cut portion 47 is provided at a scribe line position that becomes a boundary between adjacent light emitting elements. FIG. 15B is a diagram in which a thermoplastic interposer 42 is bonded to a thermoplastic printed circuit board 41. Both are almost the same material. FIG. 15C shows a state in which the element substrate of FIG. 15A and the printed circuit board of FIG. 15B are bonded together. Pressure is applied from the surfaces of the sapphire substrate 200 side and the external electrode 60 side of the printed circuit board in a vacuum, and bonding is performed at 300 ° C. for about 30 minutes. Thereby, adhesion and solid fusion joining of the electrodes are obtained, and the structure shown in FIG. 14A is completed. When the sapphire 200 is lifted off from this state, the state shown in FIG. 15D is obtained, and the structure shown in FIG. 14B is obtained.
In FIG. 15D, the light emitting element is separated at the cut portion 47 at the scribe line position, and the stress due to the difference in thermal expansion coefficient between the printed circuit board 41 and the semiconductor layer such as the N + semiconductor layer 210 is locally stopped. The interposer 42 enters the cut portion 47 at the scribe line position, and is crushed in the lateral direction so that the width becomes a little wider, contributing to adhesion. Furthermore, as shown in FIG. 15E, the structure shown in FIG. 14C is obtained by bonding the phosphor 330 or applying and curing the phosphor.

  FIG. 16 shows a form (cross section) of light emitting diodes 23 to 25 using the light emitting element 17 (FIG. 13B) or the light emitting element 19 (FIG. 13C) and using a thermoplastic material as a packaging material. Is shown. FIGS. 16A to 16C each show one of the light emitting diodes formed in the wafer state or a state separated for each light emitting diode. First, the case where the light emitting element 19 is used will be described. The basic form is shown in FIG. In this figure, a sapphire substrate 200 is depicted as an element substrate, but as described above, a silicon substrate can be used to provide a similar structure. FIG. 6B shows a form in which the silicon substrate 170 as an element substrate is removed by etching from the basic form, and FIG. 6C shows an example in which the phosphor 330 is added. The light emitting diode 23 in FIG. 16A includes a light emitting element 19, a thermoplastic interposer 42, and a thermoplastic printed board 41. However, since the light emitting element 19 uses the silicon substrate 170 that does not transmit light, the silicon substrate needs to be removed by etching. The silicon substrate can be etched at 100 ° C. or lower using an alkaline aqueous solution such as KOH. The advantage of this process is that the substrate can be removed without applying temperature stress compared to laser lift-off. The state in which the silicon substrate is removed is shown in FIG. 16B, which has a function as a light emitting diode. In the light emitting diode 24, the removed silicon substrate 170 side is a light condensing direction, and the printed board 41 side is an electrode side of a chip size package. The important points in the structure are to extract as much light as possible in the light collecting direction, to ensure electrical connection between the internal electrode 61 of the printed circuit board and the flip chip electrode 320, and to the surface of the light emitting element 19 and the printed circuit board 41. This ensures that the thermoplastic interposer 42 functions to protect against humidity, foreign matter, and the like while ensuring adhesion to the surface of the substrate.

  In FIG. 16, p, q, and r represent the directions in which the light emitted from the active layer travels. The light traveling in the condensing direction is extracted as it is in the condensing direction (p), and the light traveling in the opposite direction is reflected by the reflective film layer 275 and extracted in the condensing direction (q). Light in the direction along the layer can be directed in the light collecting direction by the micromirror 71. In order to extract as much light directed toward the condensing direction as possible from the semiconductor layer to the outside, it is possible to provide a fine scattering layer on the surface of the semiconductor layer as described above. The silicon substrate 170 can be removed by etching after bonding the light emitting element and the printed circuit board as shown in FIG. When the temperature is changed to room temperature after bonding at a high temperature, a large stress is generated at the bonding interface due to a difference in thermal expansion coefficient. Therefore, the etching of the silicon substrate is desirably performed at a temperature close to the bonding temperature. That is, when the bonding is performed at about 300 ° C. and the silicon substrate is removed at a temperature in the vicinity thereof, the interfacial stress caused by the difference in thermal expansion coefficient can be reduced. In addition, in the wafer state in which the semiconductor layer is formed on the silicon substrate, the cut portion 47 is formed in the scribe line so that the semiconductor layer is separated for each light emitting element in the wafer state. The stress generated at the interface of the semiconductor layer can be minimized. In addition, stress between the light emitting elements can be separated, and bending of the substrate can be prevented.

Between the internal electrode 61 of the printed circuit board and the flip chip electrode 320, the temperature at the time of bonding is about 300 ° C., so that the copper of the printed circuit board electrode and the gold of the flip chip electrode are in a eutectic state. An intermetallic compound is generated and firmly connected.
Regarding the adhesion between the surface of the light emitting element 19 and the surface of the printed circuit board, the adhesion (complete at about 300 ° C.) is equal to or higher than the softening point of the thermoplastic interposer and the printed circuit board. .

  In this way, the structure shown in FIG. 16A satisfies the requirements for configuring a chip size package. FIG. 16B shows a state in which the element substrate is removed from FIG. 16A, and the surface can be roughened after removal if necessary. In addition, a transparent plate 390 (for example, non-alkali glass) formed of a material having a refractive index close to that of the semiconductor layer can be attached without roughening the surface, as indicated by a broken line in the drawing. By making the surface on the semiconductor layer side of the transparent plate 390 a mirror surface and the opposite surface as a satin finish, it is easy to make a structure that easily emits light to the outside. In order to minimize the total reflection of light emitted from the semiconductor layer, it is effective to provide a layer having a refractive index close to that of the semiconductor layer as an optical buffer. A similar structure can be provided for the phosphor 330 shown in FIG. That is, instead of the transparent plate, a thin plate-like phosphor 330 made of glass or ceramic as a base material in which the semiconductor layer side is a mirror surface and the opposite surface 331 is textured can be bonded. Optically, the total reflectance of light v from the semiconductor layer side is lowered by making the refractive index of light the same at the interface with the semiconductor layer, and the outgoing surface 331 of the satin finishes the light w going to the outside by scattering. It is a structure that lowers the total reflectance. The phosphor 330 in FIG. 16C is not limited to a glass or ceramic thin plate. For example, in a state where the silicon substrate is removed, or in a state where the surface of the semiconductor is blasted from the state, a liquid resin phosphor having a high viscosity is applied to a predetermined thickness by a spinner, and then cured to phosphor. The method of forming is also simple and effective. Even in this case, reflection of light from the light emitting layer to the air can be reduced by selecting a material having a refractive index after curing close to that of the semiconductor.

  Although the example using the light emitting element 19 has been described above, the same applies to the case where the light emitting element 17 is used. Since the light emitting element 17 uses the sapphire substrate 200 as shown in FIG. 16A, the sapphire substrate can be removed by a lift-off technique. The state where the sapphire substrate is removed becomes the state shown in FIG. After that, it is possible to add a phosphor or perform a process for improving the light transmission property, as in the case of using the light emitting element 19.

  17 is a cross-sectional view showing an example of a manufacturing process of the structure shown in FIG. FIG. 17A shows a state in which a light emitting layer and a flip chip electrode 320 are formed on a sapphire substrate 200 which is an element substrate. This is a state in which the light emitting element 17 is formed on the wafer as shown in FIGS. FIG. 17B shows a state in which a thermoplastic interposer 42 is bonded to a thermoplastic printed circuit board 41. Both are almost the same material. FIG. 17C shows a state in which the light emitting element of FIG. 17A and the printed board of FIG. Pressure is applied from the surfaces of the sapphire substrate 200 side and the external electrode 60 side of the printed circuit board in a vacuum, and bonding is performed at 300 ° C. for about 30 minutes. Thereby, adhesion and solid fusion joining of the electrodes are obtained, and the structure shown in FIG. 16A is completed. When the sapphire substrate 200 is lifted off from this state, the state shown in FIG. 17D is obtained, and the structure shown in FIG. 16B is obtained. Further, by bonding the phosphor 330 to this state, or applying and curing the phosphor, the state shown in FIG. 17E is obtained, and the structure shown in FIG. 16C is obtained. Note that, in order to relieve stress between the light emitting elements generated after being bonded to the printed board, a cut portion can be formed at the scribe line position as in the structure shown in FIG.

  18 is a cross-sectional view showing a manufacturing process for forming the structure of the light emitting diode shown in FIG. 16 using a silicon substrate. FIG. 18A shows a state in which a silicon oxide film 180 is formed on a silicon substrate 170 which is an element substrate, and a light emitting layer and a flip chip electrode 320 are formed thereon. This is a state in which the light emitting element 19 is formed on the wafer as shown in FIGS. In FIG. 18, the notch 47 is formed at the scribe line position in order to prevent stress from being generated between the light emitting elements after being bonded to the printed circuit board. FIG. 18B shows a state in which a thermoplastic interposer 42 is bonded to a thermoplastic printed circuit board 41. Both are almost the same material. FIG. 18C shows a state where the light emitting element of FIG. 18A and the printed board of FIG. 18B are bonded together. Pressure is applied from the surfaces of the silicon substrate 170 side and the external electrode 60 side of the printed circuit board in a vacuum, and bonding is performed at 300 ° C. for about 30 minutes. As a result, adhesion and solid melt bonding of the electrodes are obtained. When the silicon substrate 170 is removed by etching from this state, the state shown in FIG. 18D is obtained, and the same structure as that in FIG. 16B is obtained. Furthermore, the phosphor 330 is bonded in this state, or the phosphor is applied and cured, so that the state shown in FIG. 18E is obtained, and the structure shown in FIG. 16C is obtained in this state.

  19 to 21 are examples in which a metal base substrate (metal substrate) is used as a package substrate. It is the structure which replaces the thermoplastic printed circuit board in each said example with a metal substrate. The configuration and processing steps in the case of using a metal substrate are almost the same as those in the case of using a thermoplastic printed circuit board, and only an example in which the metal substrate is used in the configuration shown in FIG. 16 will be described below. Since the configuration shown in FIG. 14 can be easily estimated, description thereof is omitted.

  In FIG. 19, the light-emitting diode 26 using the light-emitting element 17 (FIG. 13B) or the light-emitting element 19 (FIG. 13C) as a light-emitting element, and using a metal substrate 43 and a thermoplastic imposer 42 as package materials. The form (cross section) of -28 is shown. FIGS. 19A to 19C each show one of the light emitting diodes formed in the wafer state or a state separated for each light emitting diode. The external electrode 60, the internal electrode 61, and the via 50 provided in the metal substrate 43 are electrically insulated from the metal base substrate by an insulating film (not shown). FIG. 19A shows a basic form, and FIG. 19B shows a form in which the sapphire substrate is removed by lift-off or the silicon substrate is removed by etching from the basic form. FIG. 6C shows an example in which a phosphor 330 is further added. The light emitting diode 26 in FIG. 19A includes the light emitting element 17 using the sapphire substrate 200, a thermoplastic interposer 42, and a metal substrate 43. The light-emitting diode 26 has a condensing direction on the sapphire substrate 200 side, and an electrode side of the chip size package on the metal substrate 43 side. The important points in the structure are to extract as much light as possible in the light collecting direction, to ensure the electrical connection between the internal electrode 61 of the metal substrate and the flip chip electrode 320, and the surface of the light emitting element 17 and the metal substrate. This ensures that the adhesiveness with the surface of 43 is ensured and the thermoplastic imposer 42 fulfills a protection function against humidity, foreign matter and the like.

  When the bonding temperature is about 300 ° C. between the internal electrode 61 of the metal substrate and the flip chip electrode 320, a melting phenomenon occurs between the copper of the metal substrate electrode and the gold of the flip chip electrode. As a result, an intermetallic compound is generated, so that connection strength is ensured. As for the adhesion between the surface of the light emitting element 17 and the surface of the metal substrate, the adhesion (complete at about 300 ° C.) is equal to or higher than the softening point of the thermoplastic interposer.

  In this way, the structure shown in FIG. 19A satisfies the requirements for configuring a chip size package. FIG. 19B shows a state where the element substrate is removed. FIG. 19A shows an example in which the light emitting element 17 is used, but the case where the light emitting element 19 is used is almost the same. However, since the light emitting element 19 uses a silicon substrate that does not transmit light, it is necessary to remove the silicon substrate by etching. The silicon substrate can be etched at 100 ° C. or lower using an alkaline aqueous solution such as KOH. The state in which the silicon substrate is removed is the same as in FIG. In the case of a silicon substrate, the substrate can be removed without applying temperature stress as compared with laser lift-off, and has a function as a light emitting diode in the state of FIG. FIG. 19C shows a state in which the phosphor 330 is further added from this state. Other additional devices for increasing the amount of light extracted in the light collecting direction are the same as described above.

  FIG. 20 shows an example of a manufacturing process of the structure shown in FIG. FIG. 20A shows a state in which a light emitting layer and a flip chip electrode 320 are formed on a sapphire substrate 200 which is an element substrate. This is a state in which the light emitting element 17 is formed on the wafer as shown in FIGS. FIG. 20B shows the metal substrate 43. The external electrode 60, the internal electrode 61, and the via 50 are made of copper, and are electrically insulated from the metal substrate 43 by an insulating film. FIG. 20C shows a thermoplastic interposer 42. FIG. 20D shows a state where the element substrate of FIG. 20A, the metal substrate of FIG. 20B, and the interposer of FIG. 20C are bonded together. Pressure is applied from the surfaces of the sapphire substrate 200 side and the external electrode 60 side of the metal substrate in a vacuum, and bonding is performed at 300 ° C. for about 30 minutes. Thereby, adhesion and solid fusion joining of the electrodes are obtained, and the structure shown in FIG. 19A is completed. When the sapphire 200 is lifted off from this state, the state shown in FIG. Furthermore, the state shown in FIG. 20F is obtained by bonding the phosphor 330 to this state, or applying and curing the phosphor. Note that, in order to relieve stress between the light-emitting elements generated after bonding to the metal substrate, a cut portion can be formed at the scribe line position of the element substrate, similarly to the structure shown in FIG.

  FIG. 21 shows a manufacturing process when the light emitting element 19 using a silicon substrate is used in the structure shown in FIG. FIG. 21A shows a state in which a silicon oxide film 180 is formed on a silicon substrate 170, and a light emitting layer and a flip chip electrode 320 are formed thereon. This is a state in which the light emitting element 19 is formed on the wafer as shown in FIGS. FIG. 21B is a diagram showing the metal substrate 43, and an external electrode 60 and an internal electrode 61 are provided on each surface of the metal substrate 43, and a via penetrating the substrate is provided. FIG. 21 (c) shows a thermoplastic interposer 42. FIG. 21D shows a state in which the light emitting element of FIG. 21A, the metal substrate of FIG. 21B, and the interposer of FIG. 21C are bonded together. Pressure is applied from the surfaces of the silicon substrate 170 side and the external electrode 60 side of the metal substrate in a vacuum, and bonding is performed at 300 ° C. for about 30 minutes. As a result, adhesion and solid melt bonding of the electrodes are obtained. When the silicon substrate 170 is removed by etching with an alkaline aqueous solution such as KOH from this state, the state shown in FIG. Furthermore, the state shown in FIG. 21F is obtained by bonding the phosphor 330 to this state, or applying and curing the phosphor.

  FIG. 22 shows a structure (cross section) when a glass epoxy substrate is used as a package substrate and the light emitting element 16 shown in FIG. 13A is used as a light emitting element. That is, it is a form of a light emitting diode using an anisotropic conductive adhesive for bonding using a glass epoxy printed circuit board which is widespread and low cost. The basic form is FIG. 22A, FIG. 22B is a form in which the sapphire substrate is removed from the basic form by lift-off, and FIG. 22C is an example in which the phosphor 330 is further added. The light emitting diode 29 in FIG. 22A includes the light emitting element 16, the glass epoxy substrate 45, and an anisotropic conductive adhesive 370. In this light emitting diode, the condensing direction is on the sapphire substrate 1 side, and the glass epoxy substrate side is the electrode side of the chip size package. The important points in the structure are to ensure the electrical connection between the internal electrode 61 of the glass epoxy substrate and the flip chip electrodes 7 and 8, and to ensure the adhesion between the surface of the light emitting element 16 and the surface of the glass epoxy substrate. In other words, the anisotropic conductive adhesive 370 serves to protect against humidity, foreign matter, and the like.

  Between the surface of the glass epoxy substrate and the surface of the light emitting element, when the pressure at the time of bonding is kept at about 100 ° C. while holding and curing, the resin of the anisotropic conductive adhesive shrinks when returned to room temperature. Therefore, a tensile stress is generated between the glass epoxy substrate and the light emitting element. As a result, the glass epoxy substrate and the light emitting element are secured to each other while being pulled. As for the electrical connection, there is a metal sphere of about 20 μm mainly composed of gold between copper as the electrode of the glass epoxy substrate and gold of the flip chip electrode of the light emitting element. The connection between the epoxy substrate and the light emitting element is held through the metal sphere by pulling the resin together with the resin. The anisotropic conductive adhesive (heat seal) itself is a known material, but the amount of the heat seal material needs to be optimized in order to use it for the connection between the light emitting element in the wafer state and the printed circuit board. . For mounting, the necessary dimension between the electrodes is the dimension of the metal sphere, and the thickness of the resin component beyond that is an obstacle to contact. Therefore, when the area is large as in the case of bonding the wafer and the printed board, it is necessary to secure a resin escape portion, that is, a resin buffer portion. For this reason, it is one of the features that the hollow part (adhesive buffer part 375) was provided in a part of printed circuit board. Since the copper of the printed circuit board electrode and the gold of the light emitting element electrode are not eutectic bonded, the contact resistance is not zero, but is as small as several milliohms. Since it can be easily connected by heating and pressurizing at a temperature of 100 ° C., it is a low-cost packaging method for applications where the driving current of one LED is small, such as a liquid crystal surface emitting backlight.

  FIG. 23 is a cross-sectional view for explaining the manufacturing process. FIG. 23A shows the light emitting element 16 composed of the light emitting layer formed on the sapphire substrate 200 and the flip chip electrodes 321 and 322. FIG. 23B shows a glass epoxy substrate 45 including an external electrode 60 on the front surface, an internal electrode 61 on the back surface, and an adhesive buffer portion 375. FIG. 23C shows a state in which the anisotropic conductive adhesive 370 is formed in a sheet shape on the glass epoxy substrate. FIG. 23D shows a state in which the light emitting element of FIG. 23A and the glass epoxy substrate 45 provided with the anisotropic conductive adhesive 370 are bonded to each other. In this state, the glass epoxy substrate is held at 100 ° C. for about 60 minutes while applying pressure to the external electrode 60 side and the sapphire substrate. Thereafter, when the temperature is returned to room temperature, a large shrinkage stress acts on the anisotropic conductive adhesive, so that the electrical connection between the electrodes can be maintained. Thereby, the light emitting diode 29 is completed. FIG. 23 (e) shows a state where the sapphire substrate is lifted off, and FIG. 23 (f) shows a state where a phosphor 330 is further added. The method and purpose of removing the sapphire substrate and adding the phosphor are the same as in the case described above.

  FIG. 24 shows the form (cross section) of the light emitting diodes 32 to 34 using the light emitting element 17 (FIG. 13B). The same applies to the case where the light emitting element 19 (FIG. 13C) is used. As in the previous figure, a glass epoxy substrate and an anisotropic conductive adhesive are used as the package material. The basic form is shown in FIG. 24A, FIG. 24B is an example in which the sapphire substrate is removed from the basic form by lift-off, and FIG. 24C is an example in which a phosphor is further added. When the light emitting element 19 is used instead of the light emitting element 17, the structure is the same as that shown in FIGS. 24B and 24C after the silicon substrate is removed. The light emitting diode 32 in FIG. 24A includes the light emitting element 17, the glass epoxy substrate 45, and an anisotropic conductive adhesive 370. In this light emitting diode, the sapphire substrate 200 side is the light collecting direction, and the glass epoxy substrate side is the electrode side of the chip size package. The important points in the structure are that the electrical connection between the internal electrode 61 of the glass epoxy substrate and the flip chip electrode 320 is ensured, and the adhesion between the surface of the light emitting element 17 and the surface of the printed circuit board is ensured. The conductive conductive adhesive 370 has a function of protecting against humidity and foreign matter. With respect to these points, the structure of the light emitting diode 32 satisfies the requirements for forming a chip size package based on the same principle as described in FIG.

  FIG. 25 is a cross-sectional view for explaining a manufacturing process of the light-emitting diode shown in FIG. FIG. 25A shows the light emitting element 17 including the light emitting layer formed on the sapphire substrate 200 and the flip chip electrode 320. FIG. 25B shows the glass epoxy substrate 45 including the external electrode 60 on the front surface, the internal electrode 61 on the back surface, and the adhesive buffer portion 375. FIG. 25C shows a state in which the anisotropic conductive adhesive 370 is formed in a sheet shape on the glass epoxy substrate. FIG. 25D shows a state in which the light-emitting element of FIG. 25A and the glass epoxy substrate of FIG. In this state, the glass epoxy substrate is held at 100 ° C. for about 60 minutes while applying pressure to the external electrode 60 side and the sapphire substrate. Thereafter, when the temperature is returned to room temperature, a large shrinkage stress acts on the anisotropic conductive adhesive, so that electrical connection between the electrodes can be ensured. Thereby, the light emitting diode 32 is completed. FIG. 25 (e) shows a state where the sapphire substrate is lifted off, and FIG. 25 (f) shows a state where a phosphor 330 is further added. The method and purpose of removing the sapphire substrate and adding the phosphor are the same as in the case described above.

  FIG. 26 is a cross-sectional view for explaining a manufacturing procedure of the light-emitting diode shown in FIG. 24 (b) or (c). FIG. 26A shows the light emitting device 19 in which the silicon oxide film 180 is formed on the silicon substrate 170 and the light emitting layer and the flip chip electrode 320 are provided thereon. FIG. 26B shows a glass epoxy substrate 45 including an external electrode 60 on the front surface, an internal electrode 61 on the back surface, and an adhesive buffer portion 375. FIG. 26C shows a state in which the anisotropic conductive adhesive 370 is formed in a sheet shape on the glass epoxy substrate. FIG. 26D shows a state in which the light-emitting element of FIG. 26A and the glass epoxy substrate of FIG. In this state, the glass epoxy substrate is held at 100 ° C. for about 60 minutes while pressing the external electrode 60 side and the silicon substrate. Thereafter, when the temperature is returned to room temperature, a large shrinkage stress acts on the anisotropic conductive adhesive, so that electrical connection between the electrodes can be ensured. However, since silicon does not transmit light from the light emitting layer in this state, it is necessary to remove the silicon substrate 170 by etching. FIG. 26E shows a state where the silicon substrate is removed, and the light emitting diode 33 is completed in this state. FIG. 26 (f) shows a state where a phosphor 330 is further added. The method and purpose of removing the silicon substrate and adding the phosphor are the same as in the case described above.

  FIG. 27 is a diagram illustrating an example of a relationship among a wafer, a light emitting element in a wafer state, and one light emitting diode. As the sapphire substrate that is an element substrate, for example, a 2-inch wafer 400 as shown in FIG. 27A can be used. As shown in the cross-sectional view of FIG. 27B, one light emitting element can be about 0.4 mm × 0.2 mm. The light-emitting element has an optical microcell structure provided on a sapphire substrate, and can be composed of, for example, two optical microcells in the horizontal direction and one in the vertical direction (not shown). FIG. 27C shows a cross section of the light emitting diode 36 in which the light emitting elements are packaged and individually separated. The light emitting element includes an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode layer 320. The optical microcell layer 300 is formed with two optical microcells in cross section, and each optical microcell includes a light emitting cell 80 and a micromirror 71 surrounding the side surface. In FIG. 27B, a cut portion 47 on a semiconductor scribe line is a boundary with another light emitting element. After the wafer-state light emitting element and the printed circuit board 41 are bonded together, the sapphire substrate 200 is removed by laser lift-off at a temperature close to the bonding temperature (about 300 ° C.). In a state where the sapphire substrate is removed, the semiconductor layer is separated for each light emitting element on the printed circuit board 41, so that even when the temperature is returned to room temperature, the semiconductor layer is held without great stress. Thereafter, as shown in FIG. 27C, the phosphor 330 can be bonded. In order to simplify the laser lift-off in the state of about 300 ° C., laser irradiation is performed in advance at room temperature before bonding, bonding is performed at 300 ° C., and then sapphire is removed only at a temperature condition of 300 ° C. Is also possible. Although a tool is required, it can be performed more easily than irradiating a laser at a high temperature.

  FIG. 28 is a diagram illustrating another example of the relationship among a wafer, a light emitting element in a wafer state, and one light emitting diode. As a silicon substrate which is an element substrate, for example, a 2-inch wafer 400 as shown in FIG. 28A can be used. 27 is the same as the example shown in FIG. 27 except that a silicon substrate is used as the element substrate and the silicon is removed by etching. FIG. 28C shows a cross section of the light emitting diode 37 in which the light emitting element is packaged. The configuration is the same as that of the light-emitting diode 25 shown in FIG. After the wafer-state light emitting element and the printed circuit board 41 are bonded together as shown in FIG. 28 (b), the silicon substrate is heated with a KOH aqueous solution or KOH vapor at a temperature close to the bonding temperature (about 300 ° C.). Removed. Removing the silicon substrate by etching at about 300 ° C. is much easier than laser lift-off of the sapphire substrate, and is an advantage of using the silicon substrate. In the state where the silicon substrate is removed, the semiconductor layer is separated for each light emitting element on the printed circuit board 41, so that even when the temperature is returned to room temperature, the semiconductor layer is maintained without great stress. Thereafter, the phosphor 330 can be bonded together as shown in FIG.

  FIGS. 29A and 29B are diagrams for explaining the entire light emitting diode. FIG. 29A shows an upper surface, FIG. 29B shows a cross section, and FIG. 29C shows an electrode portion on the lower surface. In FIG. 29B, the light emitting element includes an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode layer 320. Two optical microcells are formed in the optical microcell layer 300, and each optical microcell includes a light emitting cell 80 and a micromirror 71 surrounding the side surface thereof. Each internal electrode of the flip chip electrode layer is formed in a cylindrical shape, and can be composed of a flip chip P electrode 321 and a flip chip N electrode 322. The thermoplastic printed circuit board 41 includes an internal electrode 61 and an external electrode 60 on both surfaces, and the internal electrode 61 and the external electrode 60 are connected by a via 50. Through the thermoplastic interposer 42, the surface of the thermoplastic printed circuit board 41 and the electrode side surface of the light emitting element are firmly adhered. Further, the flip chip electrodes 321 and 322 and the respective internal electrodes 61 provided corresponding thereto are firmly connected by metal diffusion. As shown in the figure, the light generated from the active layer of the light emitting cell 80 is emitted as it is in the p direction, the q direction is reflected and emitted by the reflective film layer 275, and the light in the r direction along the active layer is microscopic. It is reflected by the mirror 71 and emitted. A plate-like phosphor 330 is bonded, and the fluorescent material is excited by primary light having a short wavelength coming from the light emitting layer, and light having a long wavelength is secondarily emitted. In the figure, the direction of secondary light emission is indicated by s, t and u. In the case of a white light emitting diode, white light is generated by a combination of the wavelength and intensity of these primary light emission and secondary light emission.

  As shown in FIG. 29A, the light-emitting diode 39 is composed of two optical microcells of 2 × 1. The area of each light emitting cell is indicated by a boundary 81. Since this light emitting device is small in size, it has only two flip chip electrodes (321 and 322). Usually, in an element having a flip chip electrode on a bare chip, the two flip chip electrodes lack stability. However, since the flip chip electrode is an internal electrode in this light emitting diode structure, even two of them are stable. FIG. 29C shows the lower surface (electrode surface) of the light emitting diode. The P electrode 62 and the N electrode 63 are formed by performing solder plating on the surface layer of the copper conductor of the external electrode 60 provided on the printed circuit board 41, and are used for connection to the mother board. The light emitting diode shown in FIG. 29 is completed up to the package in the wafer state as shown in FIG. 27A and FIG. 28A, and then necessary electrical inspection and optical inspection are also performed in the wafer state. This can be done before individually separating the light emitting diodes. In this way, assembly and inspection can be performed using jigs and tools handled in the wafer state.

  FIG. 30 shows an example of mounting the light emitting diode 39 on the mother board 340. In a liquid crystal backlight application, such light emitting diodes are spread vertically and horizontally at a pitch of about 10 mm. Since the light emitting diode 39 is as small as about 0.4 mm × 0.2 mm, it can be picked up and mounted on the motherboard after being scribed from the wafer state and expanded as it is or mounted on the same sheet surface. it can. In this way, surges such as static electricity can be minimized. Since the secondary light emitted from the phosphor provided in the light emitting diode 39 is directed in all directions, it is also effective to provide a reflecting plate 150 on the mother board and direct it in the light collecting direction.

In the above, an example in which a thermoplastic printed board, a metal board, a glass epoxy board, or a varistor board is used as the package board has been described. Moreover, the example which uses a board | substrate combining was given. Although an example in which either a thermoplastic interposer or an anisotropic conductive adhesive is used for bonding between the light emitting element and the package substrate is given, it is also possible to use them in combination. Although it has been described on the assumption that the thermal expansion coefficient of the element substrate of the light emitting element is different from that of the thermoplastic printed circuit board, the material should be selected so that the thermal expansion coefficient of the thermoplastic printed circuit board matches the thermal expansion coefficient of the element substrate. You can also. If it does so, after bonding an element board | substrate and a package board | substrate especially 300 degreeC vicinity, it can be made to fall to room temperature, without the bonded board | substrate bonding. Thereby, since the element substrate can be removed near room temperature, the processing conditions and equipment are simplified. However, in this case, since the thermal expansion coefficient of the package substrate is close to the thermal expansion coefficient value of the element substrate, care must be taken when mounting the package on a mother board or the like. In addition to the above, a configuration combining a metal substrate and an anisotropic conductive adhesive, a configuration combining a ceramic substrate and a thermoplastic interposer, a configuration combining a ceramic substrate and an anisotropic conductive adhesive, and the like are conceivable. Such a combination can be selected in consideration of a value of thermal conductivity, a required value of connection resistance between electrodes, ease of making, and the like.
In addition, the present invention is not limited to the embodiments described in detail above, and various modifications or changes can be made within the scope of the claims of the present invention.

  As the brightness of light-emitting diodes is improved, the applications are expanding along with the needs of the age of energy saving. High efficiency, downsizing, and low cost are the key to widespread use in all applications, such as lamp replacement, liquid crystal backlight replacement, and food factory lighting. The chip size package optical semiconductor device of the present invention can be packaged in the wafer state, and can be subjected to electrical inspection and optical inspection in the wafer state. It can be handled in a banded state, and the package cost can be greatly reduced. The present invention can be applied not only to white light but also to all light-emitting diodes, and a combination of a compound semiconductor and another base material is possible, so that it can be used for a wide range of applications.

  DESCRIPTION OF SYMBOLS 1; Sapphire substrate, 2; N + type semiconductor (GaAlN) layer, 3; N type semiconductor (GaAlN) layer, 4; Active layer, 5: P type semiconductor (GaAlN) layer, 6; Conductive reflective film (back reflective film) , 7; Flip chip (P) electrode, 8; Flip chip (N) electrode, 10; Package substrate, 11; Package substrate electrode part, 12: Package inner wall, 13; Phosphor, 14; Cap, 15; Light emitting element, 20 to 39; Light emitting diode (optical semiconductor device), 40; Printed circuit board, 41; Thermoplastic printed circuit board, 42; Thermoplastic interposer, 43; Metal substrate, 45; Glass epoxy substrate, 47; notch (groove) portion at scribe line position, 50; via, 60; external electrode, 61; internal electrode, 62; solder-plated external P electrode, 63; solder External N electrode, 65; mother board electrode, 70; side reflector, 71; micromirror, 80; light emitting cell, 81; boundary of light emitting cell, 82; light microcell layer, 85; Wiring layer, 95; protective diode layer, 96; N-type polysilicon, 97; P-type polysilicon, 98; N electrode of first Zener diode, 99; N electrode of second Zener diode, 100; Outer frame, 150; external reflector, 180; silicon oxide film, 190, 191; indium oxide film, 200; sapphire substrate, 201; sapphire substrate with a textured surface, 210; N + type GaAlN layer, 220; N type GaAlN Layer, 230; active layer, 231; boundary of active layer, 240; P-type GaAlN layer, 250; taper, 260; photoresist film, 2 0: Conductive reflective film, 275; Conductive reflective film layer, 280, 285; Silicon oxide film, 281 and 282; Electrode part, 290; P-type electrode, 291; N-type electrode, 300; Optical microcell layer, 310; Power supply wiring layer to the micro cell, 320; flip chip electrode layer, 321; flip chip P electrode, 322; flip chip N electrode, 330; phosphor, 331; matte portion of phosphor surface, 340; motherboard, 350; interposer 360; inner layer printed circuit board, 361; electrode, 370; anisotropic conductive adhesive, 375; adhesive buffer portion, 390; transparent plate (non-alkali glass), 400; wafer.

Claims (17)

A semiconductor device comprising: a light emitting element in which a compound semiconductor layer constituting a light emitting portion is formed on an element substrate; and a package substrate on which the light emitting element is mounted.
The light-emitting element includes one or two or more partitioned light-emitting portions, and an element electrode for receiving power from the element electrode surface opposite to the light-emitting surface from which light is extracted.
The package substrate is substantially the same size as the light emitting element, and includes an internal electrode corresponding to the element electrode on an element mounting surface on which the light emitting element is mounted, and an internal electrode and a via on the surface opposite to the element mounting surface. And connected external electrodes,
By bonding the element electrode surface of the light emitting element and the element mounting surface of the package substrate using a bonding material, the element electrode and the internal electrode are electrically connected, and the element electrode surface And the element mounting surface are sealed,
An optical semiconductor device having a chip size package, wherein the light emitting elements formed on a wafer are separated for each package substrate.   2. The chip-sized package optical semiconductor device according to claim 1, wherein the device substrate is formed before or after being separated for each package substrate. The package substrate is a thermoplastic resin substrate;
The optical semiconductor device of the chip size package according to claim 1, wherein the bonding material is an interposer and / or an anisotropic conductive adhesive made of a thermoplastic material. The package substrate is a metal substrate;
The optical semiconductor device of the chip size package according to claim 1, wherein the bonding material is an interposer and / or an anisotropic conductive adhesive made of a thermoplastic material.   3. The chip-sized package optical semiconductor device according to claim 1, wherein the package substrate is a glass epoxy substrate, and an anisotropic conductive adhesive is used as the bonding material.   3. The chip-sized package optical semiconductor device according to claim 1, wherein the package substrate is a substrate having non-linear resistance characteristics.   A substrate having a non-linear resistance characteristic is further interposed between the light emitting element and the package substrate with the bonding material interposed therebetween, and via electrodes provided on both sides of the substrate and vias connecting the electrodes. 6. The chip-sized package optical semiconductor device according to claim 1, wherein the element electrode of the light emitting element and the internal electrode of the package substrate are electrically connected.   An insulating film and a conductive film are sequentially formed on the element electrode surface of the light emitting element, and a P-type polysilicon and an N-type polysilicon are sequentially formed on the conductive film, and the conductive film, the P-type polysilicon, 6. The chip-sized package optical semiconductor device according to claim 1, further comprising a bidirectional Zener diode configured with the N-type polysilicon.   The optical semiconductor device according to claim 1, wherein the element substrate is a transparent substrate.   9. The optical semiconductor device of a chip size package according to claim 2, wherein the element substrate is a substrate that does not transmit light.   11. The optical semiconductor device of a chip size package according to claim 10, wherein the element substrate is a silicon substrate.   12. The chip-sized package optical semiconductor device according to claim 1, wherein a boundary of the compound semiconductor layer separated for each light emitting element is removed in a groove shape on the element substrate.   The optical semiconductor of the chip size package according to any one of claims 1 to 12, wherein a layer containing a fluorescent material is formed on the light emitting surface of the light emitting element, or a plate containing the fluorescent material is bonded together. apparatus. A transparent film is further formed in contact with the outermost surface on the light emitting surface side of the light emitting element or a transparent plate is attached,
The refractive index of the transparent film or transparent plate is substantially the same as the refractive index of the outermost material,
The optical semiconductor device of a chip size package according to any one of claims 1 to 12, wherein a surface of the transparent film or the transparent plate opposite to a surface in contact with the light emitting surface side is processed to be rough.   15. The optical semiconductor device of a chip size package according to claim 14, wherein a layer containing a fluorescent material is further formed on the transparent film or transparent plate, or a plate containing the fluorescent material is bonded together.   The optical semiconductor device of a chip size package according to claim 14, wherein a fluorescent material is included in the transparent film or the transparent plate.   The chip according to any one of claims 1 to 16, wherein the light emitting element includes a back surface reflecting film on a side opposite to the light emitting surface of the compound semiconductor layer and a side surface reflecting film surrounding a side surface of each light emitting unit. Size package optical semiconductor device.

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