WO2011108664A1 - Optical semiconductor device - Google Patents

Optical semiconductor device Download PDF

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Publication number
WO2011108664A1
WO2011108664A1 PCT/JP2011/054966 JP2011054966W WO2011108664A1 WO 2011108664 A1 WO2011108664 A1 WO 2011108664A1 JP 2011054966 W JP2011054966 W JP 2011054966W WO 2011108664 A1 WO2011108664 A1 WO 2011108664A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
light
substrate
emitting element
electrode
Prior art date
Application number
PCT/JP2011/054966
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French (fr)
Japanese (ja)
Inventor
宇佐見 保
Original Assignee
有限会社Mtec
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Publication date
Application filed by 有限会社Mtec filed Critical 有限会社Mtec
Priority to JP2012503262A priority Critical patent/JPWO2011108664A1/en
Publication of WO2011108664A1 publication Critical patent/WO2011108664A1/en

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Definitions

  • the present invention relates to a chip-sized optical semiconductor device having a reflection and condensing structure for extracting light emitted from a compound semiconductor and capable of being formed in a wafer state.
  • FIG. 1 is a cross-sectional view for explaining an example of the structure of a conventional light emitting diode.
  • the light emitting diode includes a light emitting element 9 including a sapphire substrate 1, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film 6, and flip chip electrodes 7 and 8. Further, a package substrate 10 on which the light emitting element is mounted, an electrode 11 for connecting to the outside, an inclined side wall 12, a phosphor 13 and a cap 14 are provided.
  • the direction in which the light emitted in the active layer between the P-type and N-type semiconductor layers travels is indicated by p and q in the figure.
  • the light traveling in the light collecting direction z is emitted as it is (p).
  • the light traveling in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and travels in the light collecting direction z (q).
  • the electrode of the P-type semiconductor is connected to the flip chip electrode 7 via a conductive reflective film.
  • the electrode of the N type semiconductor is connected to the flip chip electrode 8 via the N + type semiconductor. Since FIG. 1 is a cross-sectional view, only two flip chip electrodes are shown.
  • the package of the light emitting element is mounted on an electrode 65 provided on a mother board 340 as shown in FIG.
  • White light emitting diodes are particularly vulnerable to high voltage surges such as static electricity and must be handled in a static-eliminated environment.
  • a surge absorbing element is often mounted in a light emitting diode package.
  • the volume is large and it is not suitable for applications that require high-density mounting.
  • a light-emitting element configured by bonding a semiconductor die to a bonding pad provided on a device substrate is also known (see, for example, Patent Document 4).
  • Patent Document 4 since the semiconductor chip cut out from the wafer is mounted on the device substrate and bonded, there is a problem that a device area larger than the size of the semiconductor chip is required.
  • the packaging process cannot be performed in the wafer state where the semiconductor is formed.
  • the optical semiconductor device is configured as shown in FIG. 2 when used as a bare chip without using a package.
  • FIG. 2A is a cross-sectional view of the light emitting element 16
  • FIG. 2B is a plan view of the light emitting element 16 viewed from below
  • FIG. 2C is a view for explaining mounting on the mother board 340.
  • the light emitting element 16 includes a sapphire substrate 200, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film layer 6, and a flip chip electrode 7. 8 is provided.
  • An oxide film 15 is provided on the side surface to protect the interface and active layer of the P-type semiconductor and N-type semiconductor from contamination.
  • the direction in which the light emitted from the active layer 4 (primary light emission) travels is indicated by p and q in the figure.
  • the light traveling in the light collecting direction z is emitted as it is (p).
  • the light traveling in the direction opposite to the light collecting direction z is reflected by the conductive reflection film 6 and travels in the light collecting direction z (q).
  • a phosphor 330 is provided, and light having a long wavelength is excited in the phosphor by secondary light having a short wavelength (secondary light emission).
  • the secondary emitted light is emitted to the direction s along the light collecting direction z, the oblique direction t, the side surface direction u, and the sapphire substrate side.
  • the side light (r in FIG. 2C) is mostly scattered inside and partly leaks outside.
  • the flip-chip electrode three P electrodes 7 are formed on the P type layer of the light emitting element, and one N electrode 8 is formed on the N type layer. Yes.
  • An electrode 65 is provided on the mother board, and the semiconductor and the mother board are connected via a flip chip electrode. With such a structure, the light emitting element can be mounted in a small area with the size of the chip.
  • FIG. 3 is a diagram for explaining a configuration that gives flexibility to the layout of the flip chip electrode and the light emitting portion.
  • a power supply wiring layer 90 is provided between the compound semiconductor film layer (light emitting portion) 84 composed of the N-type semiconductor 3, the active layer 4 and the P-type semiconductor 5 and the flip chip electrodes 7 and 8. According to this structure, the arrangement of the flip chip electrode and the light emitting cell is free, and one light emitting element can be constituted by a plurality of light emitting portions.
  • the P-type semiconductor 5 and N + type semiconductor 2 of the light emitting section shown in FIG. 3 and the P-electrode 8 and N-electrode 7 of the flip chip are interconnected in the power supply wiring layer 90, respectively.
  • the directions in which the primary emission light in the active layer and the secondary emission light in the phosphor 330 travel are the same as those shown in FIG.
  • the bare chip mounting it is possible to mount the chip in a very small size.
  • the side reflector 150 or the like is required to collect the light u that travels toward the light and the light r that leaks in the lateral direction out of the primary light emission.
  • the spread of light is adjusted by the inclination and position of the side reflector, but there is a need to incorporate a light collecting mechanism instead of this in the light emitting element.
  • the present invention has been made in view of such circumstances, and can collect as much emitted light as possible to the outside, adjust the distribution of irradiated light, and reduce luminance variation.
  • Another object of the present invention is to provide an optical semiconductor device capable of chip size packaging in a wafer state, that is, before a light emitting element is individually separated.
  • the present invention is as follows. 1. Power is supplied to the light emitting portion on one or more light emitting portions that are partitioned by the compound semiconductor layer and formed on the surface of the element substrate, and the device electrode surface opposite to the light emitting surface that extracts light from the light emitting portion.
  • An optical semiconductor comprising: a plurality of light emitting elements formed on a wafer serving as the element substrate; wherein the transparent member is disposed and then separated for each light emitting element. apparatus. 2.
  • the outer periphery and the outer periphery of the light emitting element are substrates of the same size, the inner surface corresponding to the element electrode of the light emitting element is mounted on the element mounting surface on which the light emitting element is mounted, and the surface opposite to the element mounting surface is A package substrate having an external electrode connected to the internal electrode, the device electrode surface of the light emitting device and the device mounting surface of the package substrate facing each other, and bonding the device electrode and The 1. is connected to the internal electrode.
  • the optical semiconductor device described. 3 By bonding the element electrode surface of the light emitting element and the element mounting surface of the package substrate using a bonding material, the element electrode and the internal electrode are electrically connected, and the element electrode surface And the element mounting surface are sealed with the bonding material.
  • the transparent member is a convex lens that narrows a light beam extracted from the light emitting element toward the light collecting direction.
  • a cavity member formed to be inclined so as to spread in a direction; and a phosphor filled in a cavity portion surrounded by the inner wall surface of the cavity member; and the inner wall surface of the cavity member Is formed by sequentially reflecting the light emitted from the light emitting part and the phosphor in the light collecting direction and laminating the cavity member and the transparent member in order on the light emitting surface of the light emitting element.
  • Each of the light emitting units further includes a side surface reflecting film surrounding the side surface, and the side surface reflecting film reflects the light emitted from the light emitting unit and traveling substantially parallel to the element substrate in the light collecting direction.
  • An optical semiconductor device according to any one of the above. 7). 4. The inner wall surface of the cavity member is formed by etching a silicon substrate. Or 6.
  • An optical semiconductor device according to 1. 8). 4. The cavity member is made of metal. Or 6.
  • the light emitting element includes a plurality of the light emitting units, and selectively connects or disconnects power supplied to the light emitting units on the element electrode surface of the element substrate or the surface of the package substrate on which the external electrode is provided.
  • the power supply selection unit for adjusting the luminance of each light emitting element can be adjusted by the power supply selection unit.
  • an element including an element in an intermediate process state including at least an element substrate and a light emitting layer and an electrode formed thereon is referred to as a “light emitting element”.
  • the light emitting element includes one or two or more partitioned light emitting units. This one light emitting unit is referred to as a “light emitting cell”.
  • Each light emitting cell is provided with a side reflection film (also referred to as a “micromirror”) that surrounds the side surface of the light emitting cell, and the light emitting cell surrounded by the micromirror is called an “optical microcell”.
  • a chip-sized frame whose reflecting surface has an inclined inner side surface is called a “microcavity”, and a chip-sized lens that adjusts the spread of light is called a “microlens”.
  • a microlens includes a convex lens and a concave lens, and a convex lens is referred to as a “microconvex lens”.
  • a light emitting element packaged or processed into a state where it can be mounted on a motherboard is referred to as a “light emitting diode” or “optical semiconductor device”.
  • one or two or more light emitting portions formed of the compound semiconductor layer on the element substrate surface and the element electrode surface on the side opposite to the light emitting surface for extracting light from the light emitting portion.
  • a light-emitting element that includes an electrode and extracts light in a light collecting direction perpendicular to the light-emitting surface; and a light-emitting surface side of the light-emitting element having a transparent member that is the same size as the element substrate.
  • a diode can be constructed. Thereby, it is possible to realize a light emitting diode mounted in a bare chip or a light emitting diode in a chip size package.
  • the efficiency of the light-emitting diode can be increased. Further, since the electrode of the light emitting element is provided on the side opposite to the light emitting surface, there is nothing to block light in the light collecting direction, and light can be extracted efficiently. By using a microlens as the transparent member provided on the light emitting surface side, the spread of the light beam emitted from the light emitting element can be adjusted, and the diffusion of the emitted light and the uniform orientation distribution can be easily performed outside. It becomes possible. Further, the light emitting element can be protected by using a transparent plastic plate or the like as the transparent member.
  • a transparent member is disposed in a state in which a plurality of light emitting elements are formed on a wafer which is an element substrate, and then formed separately for each light emitting element.
  • the diode can be realized at a low cost by a simple process.
  • the configuration of the present optical semiconductor device can be applied not only for white but also for all other light emitting diodes such as red.
  • a substrate having the same size as the light emitting element further comprising a package substrate having an internal electrode corresponding to the element electrode on an element mounting surface on which the light emitting element is mounted, and an external electrode on the opposite surface;
  • the element electrode and the internal electrode are electrically connected by bonding the element electrode surface and the element mounting surface of the package substrate to face each other, a light emitting diode of a chip size package can be obtained.
  • electrical connection between the element electrode and the internal electrode can be ensured.
  • the light emitting element and the package substrate are bonded together and then separated for each light emitting element, so that the entire package can be formed in the wafer state, which is extremely simple.
  • the material of the package substrate and the material of the bonding material can be appropriately selected and used in accordance with the application and use environment.
  • the transparent member is a convex lens that narrows the light beam extracted from the light emitting element toward the condensing direction
  • the light beam emitted from the light emitting element can be focused toward the light condensing direction.
  • a frame body mounted on the light emitting surface of the light emitting element the outer periphery of the frame body is the same size as the outer periphery of the element substrate, and the inner wall surface of the frame body is directed from the light emitting surface toward the light collecting direction.
  • the phosphor is excited by light from the light emitting element.
  • a white light emitting diode can be formed, and the light collection ratio in the light collecting direction can be increased by reflecting the light emitted from the light emitting portion and the phosphor by the inner wall surface of the cavity member.
  • the transparent member is disposed in the light collecting direction from the cavity member, the spread of all the light emitted through the cavity member can be adjusted by the transparent member.
  • a cavity member and a transparent member are sequentially stacked and then separated for each light emitting element. Can be realized.
  • each light emitting unit further includes a side reflecting film (micromirror) surrounding the side surface thereof, and the light emitted from the light emitting unit and traveling in a direction substantially parallel to the element substrate is reflected in the light collecting direction, it is difficult to use in the past.
  • the light traveling in the lateral direction can be taken out from the light emitting portion, and the luminance of the light emitting diode can be increased.
  • the inner wall surface of the cavity member is formed by etching a silicon substrate, an inclined reflecting surface can be easily formed using the difference in etching rate depending on the surface orientation of silicon.
  • the cavity member is made of metal, a thin plate such as copper can be used, the cavity member can be formed by forging, etching, or the like, and the inner wall surface can be made highly reflective.
  • the light emitting element includes a plurality of light emitting units, and a power supply selection for selectively connecting or disconnecting power supplied to each light emitting unit on the element electrode surface of the element substrate or the surface on which the external electrode of the package substrate is provided.
  • the brightness of the light emitting element can be measured in the wafer state, and power supply to each light emitting part can be set according to the brightness.
  • variation in luminance for each light-emitting element can be reduced, so that it is not necessary to perform selection that has been required in the past, and the manufacturing cost can be reduced.
  • a light emitting element can be formed by using a conventionally used sapphire substrate or the like, and a light emitting diode mounted in a bare chip or a light emitting diode in a chip size package can be configured.
  • the element substrate is a silicon substrate, etching can be performed at a low temperature much more easily than a sapphire substrate, so that stress applied to the light-emitting element can be reduced.
  • a cavity member can be formed using an element substrate as it is.
  • Sectional drawing for demonstrating the structure of the conventional light emitting diode Sectional drawing for demonstrating the case where a light emitting element is mounted by a bare chip.
  • Sectional drawing for demonstrating the concept of a chip size package provided with a transparent member and a cavity Cross-sectional view for explaining the structure of the microcavity and the manufacturing process Sectional drawing for demonstrating the structure of a micromirror and an optical microcell
  • emitted with a transparent member Sectional drawing for demonstrating the process of forming a semiconductor layer on a silicon substrate
  • FIG. 1 The figure which shows the structure of the whole light emitting diode which can be bare chip mounted Sectional drawing and perspective view for demonstrating the light emitting element created by the process of FIG. Sectional drawing for demonstrating the process of forming an optical microcell on a sapphire substrate Sectional drawing and perspective view for demonstrating the light emitting element created by the process of FIG. Sectional drawing for demonstrating the assembly of the light emitting diode of the chip size package using a sapphire substrate Sectional drawing for demonstrating the manufacturing procedure of the light emitting diode of FIG.
  • the figure for explaining the assembly of the light emitting diode which uses the silicon substrate and has the power supply selection part on the package substrate Sectional drawing for demonstrating the light emitting element comprised from several light emitting cells
  • a diagram for explaining the assembly of a light-emitting diode using a sapphire substrate and having a power supply selector on the package substrate Sectional drawing for demonstrating the various forms of a light emitting element Sectional drawing for demonstrating the structure of the chip size package using the light emitting element of FIG.22 (d), and various package substrates.
  • Sectional drawing for demonstrating the specific manufacturing process of the chip size package using the light emitting element of FIG.22 (d), and a thermoplastic substrate Sectional drawing for demonstrating the manufacturing procedure of the chip size package using the light emitting element of Fig.22 (a), and a thermoplastic substrate. Sectional drawing for demonstrating the manufacturing procedure of the chip size package using the light emitting element of FIG.22 (c), and a glass epoxy board
  • substrate Sectional drawing for demonstrating the specific manufacturing process of the chip size package of FIG. Sectional drawing for demonstrating the specific manufacturing process of another chip size package using the light emitting element of FIG.22 (d), and a glass epoxy substrate. Sectional drawing for demonstrating the manufacture procedure of the chip size package using the light emitting element and glass epoxy substrate of Fig.22 (a).
  • FIG. 32 is a plan view and a cross-sectional view for explaining the structure of the light emitting element portion of FIG. Sectional drawing and top view for demonstrating the electric power feeding selection part provided in the package board
  • the problem of the present invention is that the emitted light can be collected as much as possible outside, the orientation distribution of the irradiated light can be adjusted, and the wafer state, that is, the light emitting element is separated.
  • An object of the present invention is to provide an optical semiconductor device capable of chip size packaging in the previous state. Moreover, it is preferable that the optical semiconductor device can reduce variation in luminance. Furthermore, it is possible to handle without generating a surge, and it is preferable to provide a surge absorbing function when necessary.
  • a micromirror is incorporated in the vicinity of the light emitting layer of the light emitting cell, and the direction along the light emitting layer of the light (primary light emission) generated in the light emitting layer
  • the light can be condensed.
  • a white light-emitting diode is provided with a phosphor
  • side reflection is performed to collect the primary light emitted and the light excited by the light and emitted from the phosphor (secondary light emission).
  • a microcavity having a function can be provided.
  • a microlens can be incorporated to adjust the azimuth distribution of irradiated light.
  • the light emitting element can be formed by separating it into a plurality of light emitting cells, and it can be configured to have means for energizing only the necessary light emitting cells according to the desired luminance.
  • the light emitting element can be formed by separating it into a plurality of light emitting cells, and it can be configured to have means for energizing only the necessary light emitting cells according to the desired luminance.
  • chip size packaging ultra-small packaging is performed when the light emitting element is in a wafer state. Therefore, in the wafer state, it is preferable that the above-described micromirrors, microcavities, phosphors, microlenses, and the like can be formed as necessary, and a means for selectively energizing a plurality of light emitting cells can be provided.
  • the light emitting diodes can be handled in a wafer state, and if necessary, a method such as using a varistor base material that absorbs electrical surges on the package substrate can be adopted. It is preferable.
  • FIG. 4 and 5 show the concept of the structure of the optical semiconductor device that solves the above-mentioned problems.
  • the case where the light emitting element provided with one light emitting cell which does not have a micromirror is illustrated.
  • FIG. 4 is a conceptual diagram when the light-emitting element is used in a bare chip
  • FIG. 5 is a conceptual diagram when the light-emitting element is used in a chip size package.
  • the surface of the light emitting element on the light collecting direction side from which light is extracted is referred to as a “light emitting surface”.
  • FIG. 4A shows a structure in which a microcavity 175, which is a mirror surface with an inclined inner side wall, is bonded to the light emitting surface of the light emitting element 16 shown in FIG. 2, and the phosphor 330 is filled in the microcavity 175.
  • FIG. FIG. 4B shows a micro convex lens 520 as a transparent member for narrowing the emitted light beam at a narrow angle.
  • FIG. 4C shows a cross section of a light emitting diode 35 formed by bonding the light emitting element of FIG.
  • the outer circumferences of the microcavity 175 and the micro convex lens 520 are formed in the same size as the outer circumference of the light emitting element.
  • the shape and size of the microcavity and the micro convex lens as viewed from above are the same as the shape and size of the light emitting surface.
  • p, q, and r indicate the directions in which the primary light emitted from the active layer travels.
  • Light traveling from the active layer in the light collecting direction z travels as it is (p).
  • the light in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and proceeds in the light collecting direction z (q).
  • Most of the light (r) traveling in a direction substantially perpendicular to the light collection direction z, that is, in a direction substantially parallel to the active layer, is scattered and partly leaks in the side surface direction.
  • the primary emission has a short wavelength, and the light incident on the phosphor 330 out of the primary emitted light excites the fluorescent material to generate secondary emission with a long wavelength.
  • the direction in which the secondary emitted light travels is indicated by s, t, u, etc. in the figure.
  • the secondary emission light is emitted in all directions including a direction s parallel to the light collection direction z, an oblique direction t, a vertical side surface direction u, and a light emitting layer direction opposite to the light collection direction.
  • the light s in the light collecting direction z and the light t in the oblique direction are emitted as they are, and the light u in the side surface direction is reflected by the inner wall surface of the microcavity and directed in the light collecting direction z.
  • the light toward the light emitting layer is reflected by the conductive reflection layer and returns to the light collecting direction.
  • the primary light emission and the secondary light emission are emitted from the opening in the light collecting direction z side of the microcavity.
  • FIG. 4C when the micro convex lens 520 is bonded on the micro cavity, the light t in the oblique direction emitting secondary light and the light u reflected by the micro cavity are refracted by the micro convex lens 520.
  • the micro-convex lens is provided to refract both the primary emission light and the secondary emission light to narrow the light beam as a whole from between w1-w1 to between w2-w2. By narrowing the direction of the emitted light in this way, it becomes easy to widen or narrow the optical path thereafter.
  • the directions in which the primary light emission and the secondary light emission travel are indicated by the same reference numerals as those in this figure.
  • FIG. 5 is a conceptual diagram (cross-sectional view) of an optical semiconductor device having a chip size package.
  • 5C shows the light emitting element 16 formed on the sapphire substrate 200
  • FIG. 5D shows a bonding material (interposer) 350
  • FIG. 5E shows the package substrate 40.
  • the outer periphery of the package substrate 40 and the interposer 350 is formed in the same size as the outer periphery of the light emitting element.
  • the package substrate 40 is connected to an internal electrode 61 for connecting to element electrodes (flip chip electrodes) 7 and 8 of the light emitting element, an external electrode 60 for connection to the outside, and the internal electrode 61 and the external electrode 60.
  • a via 50 is provided.
  • the sapphire substrate 200 is removed by a lift-off technique.
  • the mode of the light emitting diode comprised using the light emitting element from which the sapphire substrate was removed is illustrated to FIG.5 (g) and (h).
  • a light emitting diode 137 shown in FIG. 5 (h) is obtained by bonding a transparent plastic plate 521 as a transparent member on the light emitting surface of the light emitting element. The light emitting part after the sapphire substrate is removed can be protected by the transparent plastic plate.
  • the transparent member is not limited to a transparent plastic plate, and may be a convex lens, a concave lens, or the like. Furthermore, by impregnating the transparent member with a phosphor, the primary light emission of the light-emitting element and the secondary light emission of the transparent member can be combined into white light.
  • the light emitting diode 37 shown in FIG. 5G includes a microcavity, a phosphor 330 filled in the cavity, and a transparent member (microconvex lens 520) on the light emitting surface of the light emitting element. Yes.
  • the light-emitting diode 37 can be manufactured by the following procedure.
  • the light emitting element from which the sapphire substrate has been removed and the silicon substrate 173 on which the microcavity 175 shown in FIG. 5B is formed are bonded together in a wafer state.
  • a silicon oxide film 180 is formed in advance on the bottom surface of the silicon substrate 173.
  • a side wall surface 411 surrounding the microcavity 175 is an inclined mirror surface.
  • the microcavity 175 is filled with a phosphor 330.
  • a micro convex lens 520 shown in FIG. 5A is bonded to complete a light emitting diode structure in a wafer state. Thereafter, by dividing each light emitting element, a light emitting diode 37 as shown in FIG.
  • 5G is completed and can be mounted on the mother board 340.
  • the action and effect of the microcavity 175 and the micro convex lens 520 are the same as in FIG. 4, and the light emitted by the primary light emission and the secondary light emission can be taken out in the condensing direction, and the emission angle of the emitted light beam is narrowed.
  • a diode can be realized.
  • secondary light is emitted by the phosphor 330, but the configuration of the optical semiconductor device can also be applied to a light emitting diode that does not use the phosphor.
  • a concave lens may be used instead of the micro convex lens 520, or a transparent plastic plate may be used.
  • the phosphor may be mounted without using the microcavity.
  • a plate-like phosphor whose outer periphery is the same size as the outer periphery of the element substrate of the light-emitting element may be attached on the light-emitting surface of the light-emitting element instead of the microcavity.
  • a transparent member such as a micro convex lens can be provided on the phosphor placed on the light emitting surface.
  • an electrode for connecting the light emitting diode to the outside is not a flip chip but an external electrode 60 provided on a package substrate (a popular printed circuit board or the like). Therefore, it can be mounted on a motherboard with a general-purpose machine.
  • the concept of the optical semiconductor device will be described more specifically.
  • the light emitting diode 35 shown in FIG. 4 is formed by bonding a microcavity onto the light emitting element 16 using the sapphire substrate 200, filling a phosphor, and further bonding a micro convex lens.
  • the process is performed in a wafer state and can be divided into individual light emitting diodes through electrical inspection and optical inspection.
  • the problem of such a structure is that light leaks (r ′) from the sapphire substrate in the lateral direction because the sapphire substrate exists.
  • One solution is to remove the sapphire substrate 200 as in the light emitting diode shown in FIG.
  • a microcavity can be formed in the silicon substrate itself (details will be described later). This eliminates the need for attaching another microcavity substrate and eliminates light leakage in the lateral direction of the substrate. Further, since many portions of silicon as the element substrate become cavities as cavities, an important effect is obtained that the stress generated between the light emitting element and the mother board is relieved by flip chip connection. This eliminates the need for a process of increasing strength with a resin called underfill during flip chip mounting in many applications.
  • the flip chip electrodes 7 and 8 included in the light emitting device shown in FIG. 5C are formed to have a height of about 30 ⁇ m by, for example, stud bumps, and leveling is performed to make the height uniform.
  • the height can be 20 ⁇ m.
  • the flip chip electrode can be formed by gold plating.
  • the interposer 350 shown in FIG. 5 (d) has a thickness of about 50 ⁇ m and is made of a thermoplastic material based on a PEEK (poly ether ether ketone) material, a PEI (poly ether imide) material, or the like. Since it becomes liquid at 400 ° C., a material recommended to be bonded at about 300 ° C. can be used.
  • a printed circuit board made of a heat resistant material or the like can be used.
  • a via 50 is formed in the package substrate, and an external electrode 60 made of copper or the like and an internal electrode 61 are connected by the via 50.
  • a metal whose main material is silver or copper can be used. In applications that generate a large amount of heat, the thermal resistance can be lowered by providing as many vias as possible.
  • the members shown in FIGS. 5C to 5E are combined in a wafer state, pressurized in a vacuum of about 300 ° C., and then cooled and cured to complete the package in the wafer state. In this state, the sapphire substrate 200 is removed by a lift-off technique. Then, each step of bonding the microcavity, filling the phosphor, and bonding the micro convex lens, and the electrical inspection and optical inspection can be performed in a wafer state, and then divided into individual light emitting diodes.
  • the light emitting element 16 includes a sapphire substrate 200, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a reflective conductive film 6, and flip chip electrodes 7 and 8.
  • As the light emitting element it is possible to use a light emitting element in which a light emitting cell as shown in FIG. 3 is divided into a plurality of parts. In that case, the connection between each flip-chip electrode and each light emitting cell can be freely made by providing the power supply wiring layer 90.
  • a substrate using a thermoplastic material can be used as the package substrate 40 serving as a base of the package.
  • thermoplastic package substrate 40 and the light-emitting element having a sapphire substrate as an element substrate can be bonded together via an interposer 350 made of a thermoplastic material, and in vacuum at about 300 ° C., which is the softening temperature of the material. Adhesiveness is ensured by bonding in step. Moreover, since the edge part of the adhesion part is sealed with a thermoplastic interposer, the interposer plays a role as a protective material after element division.
  • the surface of the conductor constituting the internal electrode 61 of the package substrate is copper and the material of the flip chip electrode is gold, the gold and copper are bonded together at about 300 ° C., which is equal to or higher than the eutectic temperature.
  • the gold of the flip chip and the copper on the package substrate side are eutectic bonded to ensure strength and conductivity.
  • the sapphire substrate which is the substrate of the light emitting layer is removed by a lift-off method or the like. This is because the removal of the sapphire substrate has the high hardness of sapphire in addition to the above-mentioned reason, and it becomes an obstacle to full cut when dividing each light emitting element.
  • the substrate that supports the compound semiconductor becomes the package substrate 40.
  • a silicon wafer 173 having a silicon oxide film 180 formed thereon is bonded onto the N + type semiconductor 2 that is a light emitting surface.
  • the microcavity 175 can be formed by etching the silicon.
  • Microcavity formation method primary light emission method for capturing light toward the side, formation method for transparent members such as micro-convex lenses, method for adjusting the spread of luminous flux emitted from a light emitting diode to a desired spread, This is a method for reducing variation and measures against surges such as static electricity. Further, it is a packaging method in which the light emitting element and the package as shown in FIG. 5 are integrated.
  • FIG. 6 is a cross-sectional view for explaining the structure of the microcavity and the manufacturing procedure thereof.
  • the concave portion whose inner wall surface is inclined on a silicon wafer 173 having a thickness of about 100 ⁇ m. It is a structure to do.
  • the concave portion can be formed by etching with a KOH solution or the like using a silicon substrate 173 having a (110) plane orientation.
  • the inner wall surface 411 inclined by 54 ° can be formed by utilizing the fact that the etching stops at the (111) plane of silicon.
  • an optically transparent silicon oxide film 180 is provided also as a silicon etching stopper.
  • the inner wall surface 411 of silicon becomes a mirror surface having an inclination angle of 54 degrees and serves as a light reflection surface.
  • FIG. 6A2 shows a state in which the silicon oxide film 180 is formed on the lower surface of the silicon substrate 173 and the photoresist 265 is formed on the upper surface. Silicon can be etched with an aqueous KOH solution using the photoresist 265 as a mask, and the position of the broken line 410 is the etching end surface.
  • FIG. 6B2 shows a state in which the photoresist is removed after etching, and a microcavity 175 is formed.
  • the inner wall surface 411 after etching has an angle of 54 ° determined by the silicon crystal plane.
  • a silicon oxide film may be used instead of the photoresist.
  • a silicon oxide film is formed on the upper surface of the silicon substrate, and the silicon oxide film is etched to form a pattern similar to that of the photoresist 265.
  • the silicon substrate can be etched using the formed silicon oxide film as a mask.
  • the microcavity forming method using the silicon substrate shown in FIGS. 6A2 and 6B2 can be applied after removing the sapphire substrate when the substrate of the light emitting element is sapphire.
  • the silicon of the element substrate can be used as it is as the base material of the microcavity, so that a simpler structure can be obtained.
  • FIG. 6A1 shows a state in which the compound semiconductor layer (light emitting portion) 84 is formed using the silicon substrate 170 as an element substrate.
  • a silicon oxide film 180 is provided between the silicon substrate 170 and the compound semiconductor layer 84.
  • a silicon oxide film 185 is formed instead of the photoresist, and the silicon substrate 170 is etched using a KOH aqueous solution or the like.
  • FIG. 6B1 shows a state in which the microcavity 175 is formed by the etching.
  • the microcavity is formed using silicon.
  • the microcavity can be formed using not only silicon but also metal.
  • FIG. 6A3 and 6B3 are cross-sectional views illustrating an example in which a copper stud frame is used.
  • the base material 540 of the microcavity shown in FIG. 6 (a3) has a bottom 541 and an inclined side wall 544 formed by a forging technique using a copper plate having a thickness of about 0.2 mm. From this state, the entire surface can be etched from above by isotropic etching to form the stud frame shown in FIG. 6 (b3).
  • the bottom portion 542 is a portion through which light is passed by etching away the metal. After this, by performing nickel plating, silver plating, or the like, a highly reflective inner wall surface 544 can be realized.
  • Such a copper frame can be manufactured by a technique similar to a lead frame often used in a semiconductor package. By forming the stud frame in a region having the same size as the wafer, it can be bonded to the compound semiconductor wafer. A transparent adhesive or the like can be used for bonding.
  • FIG. 7 is a cross-sectional view for explaining the concept of providing a micromirror in the light emitting element in order to capture the light emitted from the side surface that has undergone primary emission.
  • the light emitting element shown in FIG. 7A includes a semiconductor layer made of an N-type semiconductor 3, an active layer 4, and a P-type semiconductor 5 on a sapphire substrate 200.
  • the light directed in the light collecting direction z is emitted as it is (p), and the light in the opposite direction is reflected and emitted in the light collecting direction by the back reflecting film 6 (q).
  • the light in the direction is reflected by the micromirror 70 provided in the vicinity of the light emitting layer and is emitted toward the light collecting direction (r).
  • the inclination angle ⁇ of the micromirror is a value within 0 to 90 degrees.
  • the micromirror 70 can be formed by surrounding the side surface of the light emitting cell.
  • FIG. 7B shows an example of a light emitting element configured based on this concept.
  • the light emitting element is formed on one sapphire substrate 200 and includes a plurality of light emitting cells 80.
  • the light emitting element of this figure is provided with a total of eight light emitting cells, four in the horizontal direction and two in the back direction (not shown).
  • Each light emitting cell 80 includes a semiconductor layer similar to that shown in FIG.
  • Each light emitting cell 80 is surrounded by a micromirror 71 on its side surface, and constitutes an optical microcell.
  • the light directed toward the side surface of the light emitting cell is reflected by the micromirror 71 and emitted toward the light collecting direction (r).
  • a conductive reflective film (back reflective film) 275 is formed below each optical microcell. Power is supplied to the semiconductor layer in each optical microcell from the flip chip electrodes 7 and 8 via the wiring layer 90. As will be described later, a similar structure can be formed using a silicon substrate.
  • FIG. 8A is a perspective view showing a light emitting element composed of eight optical microcells.
  • Each optical microcell comprises a light emitting cell 80 and a micromirror 71 surrounding it.
  • the light-emitting element may be configured using a light-emitting cell that does not have a micromirror.
  • a thin film wiring layer 315 is provided between the power supply wiring layer 310 and the flip chip electrode. In this thin-film wiring layer, a power supply selection portion made up of a power supply wiring pattern shown in FIG. 8C is formed. The areas of the light emitting portions of the eight optical microcells 1 to 8 are weighted as shown in FIG.
  • optical microcell 1 (421) is A
  • optical microcell 5 (425) is A
  • optical microcell 3 (423) is A / 2
  • optical microcell 6 (426) is A / 4
  • the optical microcell 4 (424) is A / 8. Since the amount of light output from the light emitting element corresponds to the area of the light emitting unit, the total amount of light emitted from the light emitting element can be adjusted by changing the number of energized optical microcells. For example, power is initially supplied to all eight optical microcells, and the overall luminance is measured. The light quantity at this time, that is, the total area of the light emitting part is (5 + 7/8) A.
  • the flip chip N electrode 322 and the N electrodes of all the optical microcells are connected.
  • the flip chip P electrode 321 is connected to the P electrodes of all the optical microcells (1, 2, 7, and 8) indicated as P0 in FIG. 8B.
  • flip chip P electrodes 321 are connected to the P electrodes of the optical microcells (5, 3, 6, 4) labeled P1, P2, P3, and P4 by wirings 441, 442, 443, and 444, respectively. ing.
  • each wiring section that supplies power to each optical microcell may be selectively connected. Further, the power supplied to each optical microcell may be selectively connected or disconnected without weighting the area of the light emitting portion of each optical microcell.
  • FIG. 9A shows the light emitting diode 37 mounted on the mother board 340. Without the micro convex lens 520, the light is emitted in a wide angle range (between w1 and w1), but is narrowed by the micro convex lens 520 into a narrow angle range (between w2 and w2) centering on the light collection direction z. Suitable for applications that irradiate light in a narrow angle range.
  • FIG. 9B shows an example in which a light diffusing plate or a light diffusing lens 600 is provided in the light collecting direction from the light emitting diode.
  • the light beam narrowed to a narrow angle range (between w2 and w2) by the micro convex lens 520 of the light emitting diode is spread to a wide angle (between w3 and w3) by the light diffusion lens 600.
  • the light irradiation angle can be set with high accuracy.
  • Such a configuration is optimal for applications that uniformly irradiate a wide area with a wide angle, such as a backlight of a liquid crystal television.
  • FIG. 9C shows the case where the light emitting diode 37 is accommodated in the package as shown in FIG.
  • a concave lens 601 is used as a diffusing lens instead of a cap.
  • a light beam having a desired spread can be created by the combination of the concave lens 601 and the convex lens 520 provided in the light emitting diode 37.
  • GaN-based light-emitting elements are particularly sensitive to surges and need to be considered.
  • This light emitting device and its chip size package can be processed and mounted in the wafer state, and can also be handled in the state of being attached to the extended tape from the wafer state, so it is exposed to static electricity during handling. Can be reduced.
  • a static electricity absorbing function can be provided by using a base material (varistor substrate) having non-linear resistance characteristics for the package substrate.
  • FIG. 10 shows a manufacturing method using a silicon substrate as an element substrate and forming a semiconductor layer on the silicon substrate.
  • the light emitting layer is often formed on a sapphire substrate, but it is difficult to simply form a compound semiconductor on a silicon substrate.
  • the meaning of providing the semiconductor layer on the silicon substrate instead of the sapphire substrate is that the silicon substrate can be easily removed later by etching.
  • sapphire since it is extremely hard, partial removal is difficult, and a lift-off method is required in which the interface is partially peeled off at a high temperature using a laser or the like.
  • silicon it can be easily removed at 100 ° C.
  • a P-type GaAlN layer 240, an active layer 230, and an N-type GaAlN layer 220 are formed as semiconductor layers on a sapphire substrate 201 using a known method.
  • an indium oxide film 190 is formed thereon, and a silicon oxide film 180 is further formed thereon.
  • the indium oxide film 190 is provided for the purpose of reducing the resistance of the N-type semiconductor layer and for the purpose of end point management during semiconductor etching.
  • the silicon oxide film 180 is provided for bonding to the silicon substrate. It is also possible to perform CMP (Chemical Mechanical Polishing) as pre-bonding processing.
  • CMP Chemical Mechanical Polishing
  • FIG. 10B shows a silicon substrate 170 to be a substrate of the light emitting element later.
  • the sapphire substrate on which the semiconductor layer, the indium oxide film, and the silicon oxide film are formed and the silicon substrate 170 are bonded together.
  • the sapphire substrate 201 is lifted off and removed.
  • the silicon substrate 170 becomes a substrate for a light emitting element.
  • FIG. 11 is a cross-sectional view showing an example of a manufacturing process of an optical microcell.
  • FIG. 11A shows a state in which a pattern of a photoresist 260 is formed on the surface of the substrate shown in FIG.
  • FIG. 11B shows a state in which the P-type semiconductor layer 240, the active layer 230, and the N-type semiconductor layer 220 are wet-etched so as to provide an inclined surface (tapered portion) 250 by a taper etching technique. Thereafter, the photoresist 260 is removed, and a conductive reflective film 270 is laminated on the entire surface.
  • FIG. 11C shows a state in which the conductive reflective film 270 is processed so as to remain on the upper surface of the P-type semiconductor layer 240 by photolithography.
  • FIG. 11D shows a state in which the silicon oxide film 280 is formed on the entire surface from that state.
  • FIG. 11E shows a state in which a photoresist is provided in this state, the electrode portions 281 and 282 are subjected to taper etching, and then the photoresist is removed. The side surface of the electrode part 282 is inclined by taper etching.
  • FIG. 11F shows a state in which a metal thin film is laminated on the entire surface, and then a P-type electrode 290 and an N-type electrode 291 are formed on the electrode portion by using a photolithography technique. Thus, an optical microcell is formed.
  • FIG. 12 is a diagram for explaining the structure of the optical microcell formed as described above.
  • FIG. 12A shows a cross section of the optical microcell.
  • the semiconductor layer formed with the side surfaces inclined by the taper etching becomes the light emitting cell 80.
  • the metal film of the N-type electrode 291 formed on the silicon oxide film 280 covering the inclined portion of the semiconductor layer becomes a mirror surface, and the micromirror 71 is configured.
  • the micromirror 71 surrounds the entire circumference of the light emitting cell 80 to form an optical microcell.
  • the light collecting direction z is downward.
  • FIG. 12B is a plan view in which the optical microcells are formed side by side. In the drawing, regions of the P-type electrode 290 and the N-type electrode 291 are shown. The region of the active layer 230 of each light emitting cell is indicated by a boundary 231. These boundaries are formed with rounded corners so that the electric field is not concentrated.
  • FIG. 13 is a diagram for explaining the entire light emitting element.
  • FIG. 13A is a perspective view of the light emitting element
  • FIG. 13B is a cross-sectional view.
  • One light emitting element is configured to include one or two or more divided light emitting portions (light emitting cells) 80 on an element substrate.
  • one light emitting portion is formed of a semiconductor layer that is divided and formed one by one.
  • One optical microcell is configured by surrounding the side surface of one light emitting cell with a micromirror. That is, one light emitting element is composed of one or more optical microcells.
  • an optical microcell layer 300 including a plurality of light emitting cells 80 and micromirrors 71 is formed on a silicon substrate 170, and a conductive reflective film layer 275 is formed thereon.
  • One light microcell is constituted by one light emitting cell 80 and the micromirror 71 provided on the entire periphery thereof.
  • a power source connected to the P-type electrode and the N-type electrode of each light emitting cell 80 is wired in the wiring layer 310, and each power source is supplied from the flip chip electrode layer 320 including the flip chip electrodes 321 and 322.
  • the flip-chip electrode is not shown in the process shown in FIG.
  • a thin film wiring layer 315 is provided between the wiring layer 310 and the flip chip electrode layer 320.
  • the thin film wiring layer 315 is provided with the power supply selection unit referred to in FIG.
  • a silicon oxide film 185 for forming a microcavity is formed on the condensing direction side surface of the silicon substrate 170 shown in FIGS.
  • the silicon oxide film 180 serves as a stopper when etching silicon with a KOH aqueous solution or the like.
  • FIG. 13C shows a state where the cavity 330 surrounded by the side wall surface 411 of silicon formed by etching is filled with the phosphor 330 and the micro convex lens 520 is further bonded.
  • the traveling direction of light shown in the figure is as described above.
  • FIG. 14 is a diagram showing a light emitting device created by the process of FIG. 11, and this light emitting device 19 is mounted on a chip size package which will be described later.
  • FIG. 14A showing the cross section, p, q, and r indicate the directions of light from the light emitting layer.
  • the silicon substrate 170 does not transmit light, and is shown for reference. is there.
  • a microcavity is formed so that light can pass therethrough.
  • FIG. 14B is a perspective view of the light emitting element 19.
  • a total of six flip chip electrodes 321 and 322 are provided as element electrodes for supplying power to eight light emitting cells, and these flip chip electrodes are connected to a package substrate for a package later.
  • FIG. 15 shows a procedure for forming an optical microcell on the sapphire substrate 200. This is almost the same as the process shown in FIG. In the taper etching of the semiconductor layer shown in FIG. 15B, the N + type semiconductor film 210 can be used as a stopper for the compound semiconductor etching.
  • FIG. 16 is a cross-sectional view and a perspective view of the light-emitting element 18 created by the process of FIG. Except that a sapphire substrate is used as the element substrate, it is almost the same as the light emitting element shown in FIG.
  • FIG. 17 is a cross-sectional view for explaining a basic configuration of a chip size package using the light emitting element 18 (FIG. 16), the light emitting element 19 (FIG. 14), and the like.
  • the light emitting element 18 using the sapphire substrate shown in FIG. 17C and the package substrate 40 shown in FIG. 17E are bonded together via an interposer 350 shown in FIG.
  • the flip chip electrodes 320 (321 and 322) of the light emitting element 18 and the internal electrodes 61 provided on the package substrate 40 are in contact with each other and are electrically connected.
  • the sapphire substrate of the light emitting element 18 is removed by a lift-off method, and a silicon substrate 173 (FIG.
  • silicon substrate 17B1 serving as a base material for the microcavity is bonded with a transparent adhesive 480 instead.
  • the lift-off process and the bonding of the silicon substrate 173 are not necessary.
  • a silicon oxide film 180 is formed on the silicon substrate 173 in FIG. 17B1, since the silicon oxide film 180 is already formed on the silicon substrate 170 of the light emitting element 19, the same configuration as the silicon substrate 173 is formed.
  • silicon substrate 170 or 173 for the microcavity is collectively referred to as “silicon substrate 173”). Regardless of which light emitting element is used, the subsequent steps are common.
  • the package substrate 40, the light emitting element from which the sapphire substrate is removed, and the silicon substrate 173 are bonded together.
  • the package substrate 40 and the light emitting element formed on the silicon substrate 170 are bonded to each other.
  • the silicon oxide film 180 and the silicon substrate 173 exist in the light collecting direction from the compound semiconductor.
  • a silicon oxide film 185 shown in FIG. 17B1 is a portion serving as a mask for etching the silicon substrate 173.
  • a micro convex lens 520 shown in FIG. 17A is bonded with a transparent adhesive 480 in the wafer state.
  • the chip size package is completed in the wafer state, and electrical inspection and optical inspection can be performed. If each light emitting element is separated, individual light emitting diodes can be obtained.
  • a light emitting diode can be configured without using a microcavity and a phosphor. In that case, a micro convex lens may be bonded to the light emitting element from which the element substrate is removed.
  • a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens.
  • the external electrodes 60 of the package substrate can be formed as the package substrate P electrode 331 and the N electrode 332, and the power supply selection unit can be provided with the same wiring pattern as the power supply selection unit described in FIG.
  • the phosphor may be mounted without using the microcavity.
  • a phosphor 330 as shown in FIG. 17 (b3) may be attached on the light emitting surface of the light emitting element instead of the microcavity.
  • the outer periphery of the phosphor can be the same size as the outer periphery of the element substrate of the light emitting element.
  • a transparent member such as a micro convex lens can be provided on the phosphor placed on the light emitting surface.
  • the types and materials of the light emitting element, the package substrate, and the bonding material (interposer) can be appropriately selected and combined.
  • a transparent substrate such as sapphire may be used, or a substrate such as silicon that does not transmit light may be used.
  • the number of light emitting cells provided in one light emitting element may be one or two or more.
  • an optical microcell may be configured with a micromirror around each light emitting cell, or may be configured without a micromirror.
  • thermoplastic printed substrate a substrate having a non-linear resistance characteristic (varistor substrate), a glass epoxy printed substrate, a ceramic substrate, a metal substrate (metal base substrate), or the like
  • bonding material interposer
  • a thermoplastic material an anisotropic conductive adhesive, or the like can be used depending on the package substrate to be used.
  • a thermoplastic printed board or a metal board a thermoplastic material can be used for the bonding material.
  • an anisotropic conductive adhesive can be used for a bonding material.
  • thermoplastic printed circuit board and the light emitting element can be bonded together using a thermoplastic interposer.
  • the bonding is performed at about 300 ° C., the gold bumps constituting the flip chip electrode of the light emitting element and the copper of the internal electrode of the package substrate are eutectic bonded, and an ideal metal connection is obtained.
  • a metal substrate is used instead of the thermoplastic printed circuit board.
  • a substrate containing aluminum or copper as a material is excellent in thermal conductivity, and thus is suitable for a chip size package that requires high heat dissipation, such as a high-intensity white light emitting diode.
  • a widely used glass epoxy substrate can be used as the package substrate.
  • the glass epoxy substrate has a low heat resistant temperature of about 200 ° C. or less, the thermoplastic interposer cannot be used. Therefore, the light emitting element in the wafer state and the glass epoxy substrate are bonded together with an anisotropic conductive adhesive. Thereby, bonding can be performed at about 100 degreeC.
  • the connection between the electrodes is made by gold particles having a diameter of about 10 ⁇ m.
  • This bonding material is the same as the heat seal material used for connecting the glass substrate and the circuit board in the liquid crystal. Since this electrical junction is caused by gold particles, it has a contact resistance of about 0.1 ⁇ and is not suitable for applications requiring a large current, but is used for applications where the drive current is about several tens of mA (for example, surface emitting liquid crystal backlights). Etc.) can be used sufficiently.
  • the feature of this configuration is technically that the chip size package can be formed by a combination of existing materials.
  • silicon substrate is used as the substrate of the light emitting element, silicon can be removed in a KOH aqueous solution at a temperature as low as 100 ° C. or lower. Can be formed.
  • FIG. 18 is a cross-sectional view for explaining a silicon etching process for forming a microcavity with the configuration shown in FIG.
  • FIG. 18A shows a state in which the light emitting element 18 and the package substrate 40 are bonded together by an interposer 350.
  • FIG. 18B shows a state where the sapphire substrate 200 is removed thereafter.
  • FIG. 18C shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on one whole surface is bonded.
  • FIG. 18D1 shows a state in which a photoresist 265 is formed in accordance with a pattern for etching silicon.
  • FIG. 18E shows a state where the photoresist or silicon oxide film that has functioned as a mask is removed after the etching of silicon is completed.
  • the microcavity 175 provided with the inclined inner wall surface 411 can be formed using silicon.
  • the copper stud frame 540 can be used as the microcavity.
  • FIG. 18 (d2) shows a state where the stud frame 540 is bonded to the state of FIG. 18 (b) with a transparent adhesive 480. From this state, the microcavity 175 can be formed by isotropically etching copper with hydrochloric acid or the like. A side wall surface having high reflectivity can be easily formed by silver plating on the inner wall surface inclined by copper.
  • the micro-convex lens 520 shown in FIGS. 4, 5 and 17 uses a transparent resin material and is molded by resin molding so as to have an appropriate convex lens shape at a position corresponding to the light-emitting elements arranged on the wafer. Can be made with the same size. The same applies when the transparent member is a concave lens instead of a convex lens or a transparent plastic plate.
  • microcavity which is a basic element for realizing the basic concept described with reference to FIGS. 4 and 5, bonding of a transparent member on the light emitting surface of the light emitting element or on the microcavity, a micromirror , The structure of the chip size package, and the brightness adjusting means using a plurality of light emitting cells.
  • the finished product can be carried in the wafer state, the package substrate is not separated, or attached to the expansion sheet, and can also be mounted on the motherboard in the same state. it can.
  • a protective element such as a bidirectional Zener diode may be mounted on the motherboard in advance.
  • this method has a great merit in terms of cost in applications where a large number of light emitting diodes are mounted on a mother substrate by surface emission, such as in liquid crystal backlight applications.
  • a varistor substrate can be provided with an electrostatic absorption function by using a varistor substrate as a substrate of a chip size package. Thereby, it can be set as the chip size package strong against static electricity.
  • FIG. 19 shows a basic configuration using a chip size package as an embodiment of the present invention.
  • the light emitting element 19 (FIG. 19 (b)) using the silicon substrate 170 and the package substrate 40 (FIG. 19 (d)) are bonded by the process described in FIG. Thereafter, a microcavity is formed in the silicon substrate 170, and a micro convex lens 520 (FIG. 19A) is further bonded thereto.
  • the light emitting element 19 includes an optical microcell layer 300 in which a plurality of optical microcells are formed. As described above, the light emitting element 19 and the package substrate 40 are bonded together by holding the interposer 350 (FIG.
  • FIG. 19C is a view of the package substrate 40 as viewed from below.
  • a P electrode 331 and an N electrode 332 that receive power from the outside, and electrodes (P0, P1, P2, P3, P4) connected to the P electrode of a predetermined optical microcell.
  • the wiring between the P electrode 331 (P0) and the electrodes (P1, P2, P3, P4) is a power supply selection unit for selectively connecting or disconnecting the power supplied to each optical microcell. It is possible to select which optical microcell is supplied with power so that the light emitting element has a desired luminance. For example, according to the luminance of the light emitting element, the corresponding wiring in the cutting line 445 is cut by a laser or the like for an optical microcell that does not supply power.
  • the light emitting diode 39 is obtained by separating each light emitting element.
  • the microcavity 175 may be formed using a copper stud frame as described above. That is, after removing the element substrate (silicon substrate 170 or sapphire substrate 200) from the light emitting element, the stud frame 540 is bonded to the exposed compound semiconductor surface with a transparent adhesive as shown in FIG. 18 (d2). Then, the shape of the microcavity 175 can be made by etching until the bottom portion of the stud frame disappears, and a structure similar to that shown in FIG.
  • the silicon substrate of the light-emitting element may be removed by etching, and a micro convex lens may be attached to the removed surface.
  • a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens.
  • the light-emitting diode according to the present invention can be configured to use a light-emitting element as a bare chip without using a chip-size package.
  • the luminance adjustment can be performed by the power supply selection unit provided in the thin film wiring layer 315 as described in FIG.
  • the light emitting element incorporated in the chip size package is not limited to the one having the optical microcell as shown in FIG.
  • FIG. 20 illustrates an example of a light-emitting element including a plurality of light-emitting cells that do not include a micromirror.
  • Each light emitting cell is composed of a compound semiconductor layer 84.
  • the microcavity can be formed by the silicon substrate 170 as described above.
  • a silicon oxide film 185 is provided as an etching mask to determine the position of the etching end surface 410 that becomes the inner wall surface of the cavity.
  • the size of the package becomes the size of the light emitting diode, and the light is condensed by the micro mirror 71 near the light emitting layer, the side wall 411 of the micro cavity, and the micro convex lens 520, thereby realizing an efficient light emitting diode. Since many portions of the silicon substrate are perforated as microcavities, even when the thermal expansion coefficient of silicon is different from the thermal expansion coefficient of the package substrate, the effect of relieving stress when mounted on the mother board is great. Further, the luminance is measured in the wafer state, and if necessary, the luminance variation of each light emitting diode can be reduced at the wafer level by the power supply selection unit provided on the thin film wiring layer 315 or the package substrate 40.
  • FIG. 21 shows another embodiment of the present invention.
  • the light emitting element 18 (FIG. 21 (c)) using the sapphire substrate 200 and the package substrate 40 (FIG. 21 (e)) are attached by the process described in FIG. Thereafter, the sapphire substrate 200 is removed, and a silicon substrate 173 (FIG. 21B1) on which a microcavity 175 is formed and a micro convex lens 520 (FIG. 21A) are bonded together.
  • the light emitting element 18 includes an optical microcell layer 300 in which a plurality of optical microcells are formed.
  • the light emitting element 18 and the package substrate 40 are brought into close contact with each other by holding the interposer 350 (FIG. 21D) at a temperature of about 300 ° C. for about 30 minutes in a vacuum.
  • the light emitting element 18 after removal of the sapphire substrate and the silicon substrate 173 provided with the silicon oxide film 180 on one side can be bonded together using a transparent adhesive.
  • the procedure for forming the microcavity 175 in the silicon substrate 173 is as described with reference to FIG.
  • the microcavity 175 may be formed before being bonded to the light emitting element 18.
  • the phosphor 330 is filled in the microcavity 175, and the micro convex lens 520 is further bonded.
  • a microcavity can be formed using a copper stud frame 540 (FIG. 21B2), a microconvex lens can be formed by processing a resin in a wafer size, and a process of forming the light emitting diode 38 is performed in a wafer state. The same can be said for the light emitting diode 39.
  • FIG. 21G shows the electrodes and wirings provided on the lower surface of the package substrate 40 as in the case of the light emitting diode 39.
  • This light emitting diode can also be configured without the microcavity and the phosphor. In that case, after removing the sapphire substrate of the light emitting element, a micro convex lens may be attached to the removed surface.
  • a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens.
  • FIG. 22 shows cross sections of various types of light emitting elements that can constitute the light emitting diode according to the present invention. These can be used in bare chips or can be mounted in a chip size package.
  • FIG. 22A shows the light emitting element 16 in which one light emitting cell is provided on a sapphire substrate
  • FIG. 22B shows the light emitting element 17 in which one light emitting cell is provided on a silicon substrate
  • FIG. 22C shows the light emitting element 18 in which a plurality of optical microcells are provided on a sapphire substrate
  • FIG. 22D shows the light emitting element 19 in which a plurality of optical microcells are provided on a silicon substrate.
  • p, q, and r indicate the direction of light from the light emitting layer.
  • a light-emitting element using a silicon substrate the direction of light is shown for reference because silicon does not transmit light in this state. Light is transmitted after the silicon is removed in a later step.
  • the basic concept for constructing a light emitting diode is the same.
  • the mode of the light emitting element is not limited to the above four types.
  • a light emitting element provided with one optical microcell can be given.
  • FIG. 23 shows a cross-section of a chip size package configured by bonding the light emitting element and the package substrate using an interposer suitable for the package substrate, taking the light emitting element 19 as an example.
  • a thermoplastic printed circuit board, a metal substrate, a glass epoxy printed circuit board, or the like can be used as the package substrate.
  • FIG. 23A shows a configuration in which the light emitting element 19 and the thermoplastic printed circuit board 41 are bonded together by the thermoplastic interposer 42
  • FIG. 23B shows a configuration in which the light emitting element 19 and the metal substrate 43 are bonded together by the thermoplastic interposer 42.
  • (C) is a configuration in which the light emitting element 19 and the glass epoxy printed board 45 are bonded together by an anisotropic conductive adhesive 370.
  • the silicon substrate 170 side is the light collecting direction
  • the package substrate side is the electrode side of the chip size package.
  • the important points in the structure are to extract as much light as possible in the light collecting direction, to ensure the electrical connection between the internal electrode 61 of the package substrate and the flip chip electrode 321, etc., the surface of the light emitting element and the package substrate This ensures that the adhesiveness with the surface of the resin and the thermoplastic impose 42 and the anisotropic conductive adhesive 370 serve to protect against moisture and foreign matter.
  • FIG. 24 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 18 and a thermoplastic printed board.
  • FIG. 24A shows a cross section in a state where the light emitting element 18 and the thermoplastic printed circuit board 41 are bonded together by a thermoplastic interposer 42.
  • FIG. 24B shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on the bonding side surface is transparently bonded to a compound semiconductor surface exposed by removing the sapphire substrate 200 by a laser lift-off method. The state of being bonded with the agent 480 is shown. In the case of a light emitting element using a silicon substrate as the element substrate, the process starts from this state.
  • FIG. 24C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173.
  • this step is unnecessary by forming the silicon oxide film 185 in advance at the position of the photoresist 265 in the step before being bonded to the package substrate.
  • the microcavity 175 is formed by etching the silicon substrate 173 using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed and the microcavity 175 is filled with the phosphor 330 as shown in FIG. In this state, the light emitting diode 28 of the chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, a full cut is performed to separate the individual light emitting diodes, and the expanded tape state can be completed.
  • thermoplastic printed circuit board is used as the package substrate.
  • the procedure is also applicable when a varistor substrate or a metal substrate is used instead of the thermoplastic printed circuit board and the light emitting element is bonded using a thermoplastic interposer. It is exactly the same.
  • a light-emitting element including a plurality of light-emitting cells that do not have a micromirror the same procedure can be used.
  • a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed on the silicon substrate 173 or 170 in advance. This mask pattern can be easily formed only in the state of the silicon substrate before being combined with the package substrate.
  • FIG. 25 shows details of the procedure shown in FIG.
  • FIG. 25D shows a thermoplastic interposer 42 (FIG. 25C) between the light emitting element 18 in the wafer state (FIG. 25A) and the thermoplastic printed circuit board 41 (FIG. 25B).
  • the sandwiched state is shown. In this state, adhesion is completed by pressing and holding from the light emitting element 18 side and the printed circuit board 41 side in vacuum at about 300 ° C. for about 30 minutes. The two are in close contact with each other because of the thermoplastic material, and the copper of the electrode of the printed board and the gold of the flip chip material of the light emitting element are bonded together in a eutectic state.
  • a silicon substrate 173 having a silicon oxide film 180 formed thereon is bonded to the surface of the compound semiconductor exposed by removing the sapphire substrate 200 with a transparent adhesive 480 to form a photoresist pattern 265, as shown in FIG. It is a state. Thereafter, the silicon substrate 173 is etched to remove the photoresist.
  • the state shown in FIG. 25G is that the microcavity 175 formed thereby is filled with the phosphor 330.
  • a micro convex lens 520 can be further bonded with a transparent adhesive 480. And if it cuts fully along the division line 510 shown in the figure, the light emitting diode separated separately will be obtained.
  • FIG. 26 shows the details of the manufacturing procedure when the light emitting element 19 of the silicon substrate is used.
  • FIG. 26D shows a thermoplastic interposer 42 (FIG. 26C) between the light emitting element 19 in the wafer state (FIG. 26A) and the thermoplastic printed circuit board 41 (FIG. 26B). The sandwiched state is shown. As in the previous figure, they can be bonded together by holding under pressure at high temperature and in vacuum.
  • the silicon substrate 170 is etched using the already formed silicon oxide film 185 as a mask.
  • the assumed etching end surface is indicated by a broken line 410.
  • the microcavity 175 is formed.
  • the silicon oxide film 185 used as a mask is removed with hydrofluoric acid.
  • the phosphor 330 is filled (FIG. 26 (f)), and if necessary, a micro convex lens 520 is further bonded and a full cut is made along the dividing line 510, individually. A separated light emitting diode is obtained.
  • FIG. 27 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 16 and a thermoplastic printed board.
  • FIG. 27A shows a cross section in a state where the light emitting element 16 and the thermoplastic printed circuit board 41 are bonded together by a thermoplastic interposer 42.
  • FIG. 27B shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on a surface on the bonding side is formed on a compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method, and a transparent adhesive.
  • 480 shows the state of being bonded together. In the case of a light emitting element using a silicon substrate, the process starts from this state.
  • FIG. 27A shows a cross section in a state where the light emitting element 16 and the thermoplastic printed circuit board 41 are bonded together by a thermoplastic interposer 42.
  • FIG. 27B shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on
  • FIG. 27C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173.
  • this step is unnecessary because a silicon oxide film 185 is formed in advance at the position of the photoresist 265 in a step before being bonded to the package substrate.
  • the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed and the phosphor 330 is filled in the microcavity 175 as shown in FIG.
  • the light emitting diode 22 of the chip size package is obtained.
  • a micro convex lens 520 can be further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, a full cut is performed to separate the individual light emitting diodes, and the expanded tape state can be completed.
  • thermoplastic printed circuit board 41 is used as the package substrate.
  • a procedure may be used in the case where a varistor substrate or a metal substrate is used instead of the thermoplastic printed circuit board and the light emitting element is bonded using a thermoplastic interposer. Is exactly the same. The same procedure can be used when a light emitting element including a plurality of light emitting cells is used.
  • a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed in advance on the silicon substrate 173 or 170.
  • the details of the procedure shown in FIG. 27 are the same as the manufacturing procedure shown in FIGS. 25 and 26 except that the form of the light emitting element is different.
  • FIG. 28 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 18 and the glass epoxy printed board.
  • FIG. 28A shows a cross section in a state where the light emitting element 18 and the glass epoxy printed board 45 provided with the adhesive buffer portion 375 are bonded together by the anisotropic conductive adhesive 370.
  • FIG. 28B shows a state in which the silicon substrate 173 in which the silicon oxide film 180 is formed on the surface on the bonding side is formed on the compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method.
  • 480 shows the state of being bonded together. In the case of a light emitting element using a silicon substrate as the element substrate, the process starts from this state.
  • FIG. 28A shows a cross section in a state where the light emitting element 18 and the glass epoxy printed board 45 provided with the adhesive buffer portion 375 are bonded together by the anisotropic conductive adhesive 370.
  • FIG. 28B shows a state in which the silicon substrate
  • FIG. 28C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173.
  • this step is not necessary because the silicon oxide film 185 is formed in advance at the position of the photoresist 265 in the step before being bonded to the package substrate.
  • the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed, and the phosphor 330 is filled in the microcavity 175 as shown in FIG.
  • a light emitting diode 32 of a chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, and a full cut is performed to separate individual light emitting diodes, which can be completed in an expanded tape state.
  • a light-emitting element having a plurality of light microcells is used.
  • a light-emitting element having a plurality of light-emitting cells not having a micromirror is used, the same procedure can be used.
  • a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed on the silicon substrate 173 or 170 in advance.
  • FIG. 29 is a cross-sectional view for explaining details of the procedure shown in FIG.
  • FIG. 29A shows the light emitting element 18 in the wafer state
  • FIG. 29B shows the glass epoxy printed board 45.
  • the glass epoxy printed circuit board 45 is provided with an adhesive buffer portion 375 as a relief space for the anisotropic conductive adhesive.
  • FIG. 29C shows a state where the anisotropic conductive adhesive 370 is attached to the glass epoxy printed board 45 in a sheet form.
  • FIG. 29D shows a state in which the light emitting element 18 and the glass epoxy printed board 45 are bonded to each other with the anisotropic conductive adhesive 370 interposed therebetween. Adhesion is completed by pressing and holding from the light emitting element side and the printed circuit board side at about 100 ° C.
  • a silicon substrate 173 having an oxide film 180 formed thereon is bonded to the surface of the compound semiconductor exposed by removing the sapphire substrate 200 with a transparent adhesive 480 to form a photoresist pattern 265 as shown in FIG. State.
  • the assumed etching end surface is indicated by a broken line 410.
  • the photoresist is removed. The state shown in FIG.
  • 29F is that the phosphor 330 is filled in the microcavity 175 formed thereby. If necessary, the micro convex lens 520 can be further bonded with a transparent adhesive 480. Then, if it cuts fully along the dividing line 510 shown in a figure, it can isolate
  • FIG. 30 shows a manufacturing procedure in the case of using the light emitting element 19 of the silicon substrate.
  • FIG. 30D shows an anisotropic conductive bonding between the light emitting element 19 in the wafer state (FIG. 30A) and the glass epoxy printed board 45 (FIG. 30B) provided with the adhesive buffer 375. The state where it is bonded via the agent 370 is shown. As in the case of the previous figure, they can be bonded together by holding under pressure at a high temperature.
  • FIG. 30E the silicon substrate 170 is etched using the silicon oxide film 185 on which the pattern has already been formed as a mask. The assumed etching end surface is indicated by a broken line 410.
  • the silicon oxide film 185 used as a mask is removed with hydrofluoric acid.
  • the phosphor 330 is filled (FIG. 30 (f)), and if necessary, a micro convex lens 520 can be further bonded. Then, if it cuts fully along the dividing line 510 shown in a figure, it can isolate
  • FIG. 31 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 16 and the glass epoxy printed board.
  • FIG. 31A shows a cross section in a state where the light emitting element 16 and the glass epoxy printed board 45 are bonded together by the anisotropic conductive adhesive 370.
  • An adhesive buffer 375 is provided on the glass epoxy substrate so that excess anisotropic conductive adhesive is confined inside and does not hinder the bonding.
  • FIG. 31 (b) shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on the bonding side surface is exposed to a transparent adhesive on a compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method. 480 shows the state of being bonded together.
  • FIG. 31C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the silicon surface.
  • this step is not necessary because the silicon oxide film 185 is formed in advance at the position of the photoresist 265 in the step before being bonded to the package substrate.
  • the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask.
  • the photoresist or silicon oxide film is removed, and the microcavity 175 is filled with the phosphor 330 as shown in FIG. In this state, the light emitting diode 26 of the chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, and a full cut is performed to separate individual light emitting diodes, which can be completed in an expanded tape state.
  • a light-emitting element including one light-emitting cell that does not have a micromirror is used.
  • the same procedure may be used. it can.
  • a silicon oxide film 185 serving as a mask when forming a microcavity by etching may be formed in advance on the silicon substrate 173 or 170.
  • the details of the procedure shown in FIG. 31 are the same as the manufacturing procedure shown in FIGS. 29 and 30 except that the form of the light emitting element is different.
  • the heat sealing technique using the anisotropic conductive adhesive 370 given in the above example is a technique that is often used for the connection between a glass substrate and a flexible substrate.
  • the amount of heat seal material needs to be optimized. That is, the required mounting dimension between the two electrodes is the size of the gold particles, and the thickness of the resin component exceeding that is an obstacle to contact.
  • a recess is provided in a part of the printed circuit board as a resin escape portion. Since the copper of the printed circuit board electrode and the gold of the light emitting element electrode are not eutectic bonded, the contact resistance is not zero, but is as small as several m ⁇ . Since it can be easily connected by heating and pressurizing at a temperature of 100 ° C., it can be applied at low cost as a light emitting diode package for applications with a small driving current.
  • thermoplastic printed board a metal board, a varistor board, or a glass epoxy printed board is used as the package board, and a thermoplastic interposer or anisotropic conductive adhesive is used as the bonding material between the light emitting element and the package board.
  • the material of the package substrate and the combination with the bonding material are not limited to this.
  • a chip size package can be configured by a combination of a metal substrate and an anisotropic conductive adhesive, a combination of a ceramic substrate and a thermoplastic interposer, a combination of a ceramic substrate and an anisotropic conductive adhesive, or the like. it can.
  • the material can be appropriately selected in consideration of the thermal conductivity of each material, the required connection resistance value between the electrodes, ease of production, and the like.
  • the microcavity using a silicon substrate uses a wall surface with an inclination angle of 54 ° formed on the inner surface by etching silicon with a KOH aqueous solution or the like.
  • a silver thin film is formed on the wall surface. Etc. are effective.
  • the bottom surface of the microcavity is an insulating silicon oxide film and the side wall surface is conductive silicon, a silver thin film or a multilayer thin film containing silver is formed as it is by electroplating technology to improve the reflectivity. It is possible to increase.
  • a microcavity can be formed using a thin metal plate such as copper.
  • a metal plate having a thickness of about 100 ⁇ m can be etched and forged so that the inclination of the wall surface serving as the inner surface of the microcavity is about 45 °.
  • silver plating can also be formed on the side wall surface. Such processing is possible with the same equipment and materials as those used in the production of IC lead frames.
  • a microcavity corresponding to each light emitting element is formed on a thin plate having the same size as the wafer, and can be bonded to the light emitting element in a wafer state using a transparent adhesive.
  • the package substrate is the substrate of the package, it can be bonded stably. Further, there is no problem in terms of structure since the temperature is not increased after this step.
  • a microcavity using a copper stud frame or silicon is also applicable to a light emitting diode not using a phosphor.
  • the method of selecting the power supply to the optical microcell for adjusting the luminance of the light emitting diode has been described.
  • it is required that the luminance at a constant driving current has a certain tolerance.
  • the luminance adjustment of the light emitting diode in the present invention is a method of adjusting the light emitting area, it is suitable for adjustment according to the luminance under a constant voltage.
  • the luminance when a constant voltage is applied can be adjusted in proportion to the light emitting area.
  • changing the light emitting area according to the luminance changes the current density flowing in the light emitting cell, and a large adjustment cannot be expected. Therefore, in a constant current driving application, it is necessary to create a luminance map under a constant current for the light emitting cells on the wafer and perform layering. In order to reduce the width of each layer, the brightness adjustment by this method is useful.
  • FIG. 32 is a diagram illustrating an example of a relationship among a wafer, a light emitting element in a wafer state, and one light emitting diode.
  • a silicon substrate which is an element substrate, for example, a 3-inch wafer 400 as shown in FIG. 32A can be used.
  • one light emitting element can be about 0.5 mm ⁇ 0.5 mm.
  • the light emitting element 19 is illustrated as a light emitting element.
  • the light-emitting element 19 has an optical microcell structure provided on a silicon substrate, and can be composed of a total of eight optical microcells, for example, 4 in the horizontal direction and 2 in the depth direction (not shown). .
  • the light emitting element includes a flip chip electrode layer including an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode 322.
  • the optical microcell layer 300 is formed with four optical microcells in cross-section, and each optical microcell includes a light emitting cell 80 and a micromirror 71 surrounding the side surface.
  • the light emitting element is bonded to the thermoplastic printed circuit board 41, and a microcavity 175 is formed in 170 parts of the silicon substrate.
  • the microcavity 175 is filled with the phosphor 330, and the micro convex lens 520 is further bonded.
  • FIG. 32C shows a cross section of the light emitting diode 39 individually separated from the wafer state.
  • 32C collectively shows the traveling direction of light (primary light emission) generated in the active layer (pqr).
  • the light p directed from the active layer in the light collecting direction z is emitted as it is
  • the light q opposite to the light collecting direction z is reflected by the reflective film layer 275
  • the light r in the side direction along the active layer is The light is reflected by the micromirror 71 and both are emitted toward the phosphor 330.
  • the fluorescent material is excited by the primary light having a short wavelength coming from the semiconductor layer, and secondary light having a long wavelength is generated.
  • light s1 in the secondary light emission toward the light collecting direction z travels straight and is emitted from the light emitting diode (s2).
  • the light t1 traveling in the oblique direction is refracted and emitted in the light collecting direction by the micro convex lens (t2).
  • Light u0 in a direction perpendicular to the light collecting direction z is reflected by the side wall surface 411 of the microcavity (u1), and further refracted in the light collecting direction by the micro convex lens and emitted (u2).
  • the secondary emitted light is directed in the condensing direction and can be efficiently collected.
  • white light is generated by a combination of the wavelength and intensity of primary light emission and secondary light emission.
  • a micro convex lens When a micro convex lens is used as the transparent member of the present light emitting diode, the light from the light emitting element is condensed in the condensing direction due to the effect of the micro convex lens, and the light flux is greatly reduced as shown in FIG. Can do. And as shown in FIG.9 (b), a light beam can be spread
  • a light emitting diode having excellent overall characteristics such as luminance and color unevenness.
  • luminance in particular, light along the light emitting layer can be reflected by the micromirror, and light in all directions emitted from the light emitting layer can be extracted in the light collecting direction. Further, the light excited by the phosphor can be taken out in the light collecting direction by the microcavity, and can be further taken out by being focused by the micro convex lens.
  • color unevenness uniform white light can be obtained by combining light of primary light emission having a short wavelength and light of secondary light emission having a long wavelength together in the light collecting direction. Further, by diffusing the light, it is possible to obtain a broad and uniform white light.
  • FIG. 33 (a) is a plan view showing the arrangement of the optical microcells in the light emitting element section shown in FIG. 32 (b).
  • the light emitting element is composed of a total of eight optical microcells, 4 in the horizontal direction and 2 in the vertical direction, and the area of each optical microcell is indicated by a broken line 81.
  • FIG. 33B illustrates a cross section of a light emitting diode using the light emitting element.
  • the light emitting element includes a flip chip layer (320) including an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and flip chip electrodes 321 and 322.
  • the optical microcell layer 300 is provided with the eight optical microcells, and a light emitting cell 80 surrounded by the micromirror 71 is formed in each optical microcell.
  • the flip chip N electrode 322 connected to the N electrode common to each optical microcell shown in FIG. 20A and the P electrode of each optical microcell are divided into P0 to P4, respectively.
  • FIG. 34A is a cross-sectional view of the same light emitting diode as in the previous figure, and FIG. 34B represents the lower surface thereof, that is, the surface of the package substrate 41 on the external electrode 60 side.
  • Eight optical microcells are weighted with light emitting areas as indicated by P0 to P4 in FIG. 8B.
  • a substrate N electrode 332 provided on the lower surface of the printed circuit board 41 is connected to the N electrode of each optical microcell.
  • the substrate P electrode 331 is connected to the P electrode of the optical microcell P0.
  • the terminals P1 to P4 connected to the substrate P electrode 331 on the lower surface of the printed circuit board 41 are connected to the P electrodes of the optical microcells P1 to P4, respectively.
  • Each wiring is selectively cut by the cutting unit 445 so that power is not supplied to the corresponding optical microcell, and the luminance of the light emitting diode can be adjusted.
  • the packaging, electrical inspection, optical inspection, brightness selection and adjustment of the chip-sized light emitting diode can be performed before the wafer state, that is, the light emitting diodes are individually separated. Since it can be handled in a wafer state, a surge countermeasure element in the light emitting diode can be eliminated.
  • the silicon substrate is used as the substrate of the light emitting element.
  • the same configuration and operation can be obtained even when the sapphire substrate is used.
  • the sapphire substrate may be left as it is or may be removed.
  • Various members can also be selected for the microcavity and the chip size package.
  • the configuration example of the white light emitting diode including the microcavity and the phosphor is mainly shown.
  • the light emitting diode can be applied not only for white but also for all other red light emitting diodes.
  • the microcavity (170 or 173) and the phosphor 330 are not necessary, and other configurations are exactly the same.
  • FIG. 35 is a diagram illustrating a configuration example of the present light-emitting diode when a microcavity is not used, and illustrates a relationship among a wafer, a light-emitting element in a wafer state, and one light-emitting diode.
  • a sapphire substrate or silicon substrate that is an element substrate of the light emitting element for example, a 3-inch wafer 400 as shown in FIG. 35A can be used.
  • one light emitting element can be about 0.5 mm ⁇ 0.5 mm.
  • the light emitting element 19 using a silicon substrate is shown here, all the light emitting elements exemplified so far can be used.
  • the element substrate may be a sapphire substrate or a silicon substrate, and one light emitting element may include one or more light emitting cells 80, and the light emitting cell may not include a micromirror.
  • An optical microcell may be configured.
  • the optical microcell composed of the light-emitting cell 80 and the micromirror 71 surrounding the side surface thereof is 4 in the horizontal direction and in the depth direction (not shown). A total of eight are provided.
  • the light emitting element 19 includes an optical microcell layer 300 on which optical microcells are formed, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode layer including flip chip electrodes 321 and 322.
  • the transparent member 521 can be bonded to the light emitting surface side of such a light emitting element, and then separated into individual light emitting diodes.
  • a transparent plastic plate for protecting the light emitting portion after the element substrate is removed can be used as appropriate.
  • a plate-like phosphor may be sandwiched between the light emitting surface of the light emitting element and the transparent member 521. For example, when a phosphor and a micro convex lens are sequentially laminated on the light emitting surface, white light is generated by the primary light emission from the light emitting element and the secondary light emission excited by the phosphor, and the micro convex lens is used in the light collecting direction.
  • a light emitting diode can be configured by attaching a package substrate to the element electrode surface side.
  • FIG. 35 shows an example in which a light emitting diode is configured by bonding a light emitting element and a thermoplastic printed circuit board 41 via a bonding material 42.
  • FIG. 35C shows a cross section of the light emitting diode 139 individually separated from the wafer state. Even when a hard sapphire substrate is used as the element substrate in the wafer state, each element can be easily separated by full cut because the element substrate is removed.
  • FIG. 35 (c) shows the traveling direction of light (primary light emission) generated in the active layer.
  • the light p directed from the active layer in the light collecting direction z is emitted as it is, and the light q opposite to the light collecting direction z is reflected by the reflective film layer and emitted, and the light in the lateral direction along the active layer is emitted.
  • r is reflected by the micromirror and emitted.
  • all the light (p, q, and r) generated in the active layer in each direction is emitted from the light emitting surface in the light collecting direction z.
  • a micro convex lens or a concave lens is formed as the transparent member 521, the spread of light emitted from the light emitting surface can be adjusted.
  • the light-emitting element can be mounted on the motherboard with a bare chip, or can be mounted in a chip size package.
  • light emitting diodes are laid vertically and horizontally at a pitch of several tens of mm.
  • the light emitting diode of the present invention is as small as about 0.5 mm ⁇ 0.5 mm, it is scribed from the wafer state and picked up in the expanded state or mounted on the same sheet surface and mounted on the motherboard. It is preferable to do. In this way, surges such as static electricity are minimized, and it is only necessary to provide a surge absorbing element on the motherboard.
  • a light diffusing plate is provided in the light collecting direction from the light emitting diode, the irradiation light can be equalized.
  • the irradiation light is made uniform as possible regardless of the direction from the light emitting diode.
  • light emitting diodes are used in a grid pattern on a mother board, light is emitted from individual light emitting diodes to a limited range at a certain height on the mother board. For this reason, for example, the illuminance may decrease at an intermediate point on the diagonal line of the lattice.
  • the light emitting diode of the present invention it is easy to make uniform or change the light direction distribution by devising the shape and layout of the light emitting part as the light source, the shape and curvature of the micro convex lens, etc. Is possible.
  • the light emitting diode of the present invention can be used in a wide range of fields such as lamps, liquid crystal backlights, and food factory lighting.
  • the present invention can be applied not only to white light but also to all light emitting diodes.

Abstract

Disclosed is a chip-size optical semiconductor device, whereby the light collection rate is improved, and spread of a radiated luminous flux is adjusted. In the optical semiconductor device, each of the light emitting elements is provided with: one or more light emitting sections which are formed of a compound semiconductor layer, said light emitting sections being formed on the element substrate surface; and an element electrode on the surface on the reverse side of the light emitting surface, from which light is extracted. On the light emitting surface side of each of the light emitting elements, a transparent member having the size equivalent to that of the element substrate is provided. The transparent member is disposed in the state wherein the light emitting elements are formed on a wafer, then the wafer is divided into the light emitting elements. A package substrate having the size equivalent to that of each light emitting element is provided, and the optical semiconductor device, i.e., a chip size package, is formed. As the transparent member, a lens can be formed.

Description

光半導体装置Optical semiconductor device
 本発明は、化合物半導体により発光した光を取り出すための反射及び集光構造を備え、ウエーハ状態で形成可能なチップサイズの光半導体装置に関する。 The present invention relates to a chip-sized optical semiconductor device having a reflection and condensing structure for extracting light emitted from a compound semiconductor and capable of being formed in a wafer state.
 従来、発光ダイオードの構造についてさまざまな形態が知られている(例えば、特許文献1~3を参照)。図1は、従来の発光ダイオードの構造の例を説明するための断面図である。図1(a)において、発光素子9の発する光は集光方向zに取り出される。この発光ダイオードは、サファイア基板1、N+型半導体2、N型半導体3、活性層4、P型半導体5、導電反射膜6、及びフリップチップ電極7、8からなる発光素子9を備えている。また、発光素子を実装するパッケージ基板10、外部と接続するための電極11、傾斜した側壁12、蛍光体13、及びキャップ14を備えている。P型及びN型半導体層の間の活性層において発光する光の進む方向を、図中p、qで示す。活性層で発生する光のうち集光方向zへ向かう光は、そのまま放出される(p)。集光方向zとは反対側へ向かう光は、反射膜6により反射されて集光方向zへ向かう(q)。P型半導体の電極は、導電反射膜経由でフリップチップ電極7へ接続されている。N型半導体の電極は、N+型半導体を経由してフリップチップ電極8に接続される。図1は断面図であるのでフリップチップ電極は2つのみ表わされている。上記発光素子のパッケージは、図1(b)に示すように、マザーボード340に設けられた電極65上に搭載される。白色用の発光ダイオードの場合には、特に静電気等の高電圧サージに弱いため、除電された環境で取扱う必要がある。静電気対策のために、発光ダイオードのパッケージ内にサージ吸収素子が実装される場合も多い。 Conventionally, various forms of the structure of the light emitting diode are known (see, for example, Patent Documents 1 to 3). FIG. 1 is a cross-sectional view for explaining an example of the structure of a conventional light emitting diode. In FIG. 1A, the light emitted from the light emitting element 9 is extracted in the light collecting direction z. The light emitting diode includes a light emitting element 9 including a sapphire substrate 1, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film 6, and flip chip electrodes 7 and 8. Further, a package substrate 10 on which the light emitting element is mounted, an electrode 11 for connecting to the outside, an inclined side wall 12, a phosphor 13 and a cap 14 are provided. The direction in which the light emitted in the active layer between the P-type and N-type semiconductor layers travels is indicated by p and q in the figure. Of the light generated in the active layer, the light traveling in the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and travels in the light collecting direction z (q). The electrode of the P-type semiconductor is connected to the flip chip electrode 7 via a conductive reflective film. The electrode of the N type semiconductor is connected to the flip chip electrode 8 via the N + type semiconductor. Since FIG. 1 is a cross-sectional view, only two flip chip electrodes are shown. The package of the light emitting element is mounted on an electrode 65 provided on a mother board 340 as shown in FIG. White light emitting diodes are particularly vulnerable to high voltage surges such as static electricity and must be handled in a static-eliminated environment. As a countermeasure against static electricity, a surge absorbing element is often mounted in a light emitting diode package.
 上記のような構造の場合には体積が大きく、高密度実装が必要な用途には適さない。デバイスを小型化するために、半導体ダイをデバイス基板上に設けられたボンディングパッドに接合して構成される発光素子も知られている(例えば、特許文献4を参照)。しかし、ウエーハから切出した半導体チップをデバイス基板上に搭載してボンディングするため、半導体チップのサイズに比べて大きなデバイス面積が必要となってしまうという問題があった。また、半導体を形成したウエーハ状態のままでパッケージング工程を行うことができないという問題があった。 In the case of the structure as described above, the volume is large and it is not suitable for applications that require high-density mounting. In order to reduce the size of a device, a light-emitting element configured by bonding a semiconductor die to a bonding pad provided on a device substrate is also known (see, for example, Patent Document 4). However, since the semiconductor chip cut out from the wafer is mounted on the device substrate and bonded, there is a problem that a device area larger than the size of the semiconductor chip is required. In addition, there is a problem that the packaging process cannot be performed in the wafer state where the semiconductor is formed.
特開平10-93146号JP-A-10-93146 特開2006-303547号JP 2006-303547 A W02006-126330号W02006-126330 特開2009-49408号JP 2009-49408 A
 光半導体装置を小型化するため、パッケージを用いずにベアチップのままで使用する場合、図2に示すように光半導体装置を構成することが考えられる。図2(a)は発光素子16の断面、(b)は発光素子16を下方から見た平面、(c)はマザーボード340への実装、をそれぞれ説明するための図である。図2(a)に示すように、発光素子16は、サファイア基板200、N+型半導体2、N型半導体3、活性層4、P型半導体5、導電反射膜層6、及びフリップチップ電極7、8を備えている。P型半導体及びN型半導体の界面と活性層を汚れから保護するために、酸化膜15が側面に設けられている。活性層4において発光(1次発光)する光の進む方向を、図中p、qで示している。活性層で発生する光のうち集光方向zへ向かう光は、そのまま放出される(p)。集光方向zとは反対側へ向かう光は、導電反射膜6により反射されて集光方向zへ向かう(q)。白色用の発光ダイオードの場合には蛍光体330を備え、1次発光した波長の短い光により蛍光体中で波長の長い光が励起される(2次発光)。2次発光した光は集光方向zに沿った方向s、斜め方向t、側面方向u及びサファィア基板側に放出される。また1次発光の光のうち側面方向の光(図2(c)のr)は、多くは内部で散乱されてしまい一部が外部に洩れる。また、図2(b)に示すように、フリップチップ電極として、発光素子のP型層の上に3つのP電極7が形成され、N型層の上に1つのN電極8が形成されている。マザーボード上には電極65が設けられており、半導体とマザーボードとはフリップチップ電極を介して接続される。このような構造により、発光素子のチップのサイズで、小さな面積に実装することができる。 In order to reduce the size of the optical semiconductor device, it is conceivable that the optical semiconductor device is configured as shown in FIG. 2 when used as a bare chip without using a package. 2A is a cross-sectional view of the light emitting element 16, FIG. 2B is a plan view of the light emitting element 16 viewed from below, and FIG. 2C is a view for explaining mounting on the mother board 340. As shown in FIG. 2A, the light emitting element 16 includes a sapphire substrate 200, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a conductive reflective film layer 6, and a flip chip electrode 7. 8 is provided. An oxide film 15 is provided on the side surface to protect the interface and active layer of the P-type semiconductor and N-type semiconductor from contamination. The direction in which the light emitted from the active layer 4 (primary light emission) travels is indicated by p and q in the figure. Of the light generated in the active layer, the light traveling in the light collecting direction z is emitted as it is (p). The light traveling in the direction opposite to the light collecting direction z is reflected by the conductive reflection film 6 and travels in the light collecting direction z (q). In the case of a white light emitting diode, a phosphor 330 is provided, and light having a long wavelength is excited in the phosphor by secondary light having a short wavelength (secondary light emission). The secondary emitted light is emitted to the direction s along the light collecting direction z, the oblique direction t, the side surface direction u, and the sapphire substrate side. Of the primary emitted light, the side light (r in FIG. 2C) is mostly scattered inside and partly leaks outside. Further, as shown in FIG. 2B, as the flip-chip electrode, three P electrodes 7 are formed on the P type layer of the light emitting element, and one N electrode 8 is formed on the N type layer. Yes. An electrode 65 is provided on the mother board, and the semiconductor and the mother board are connected via a flip chip electrode. With such a structure, the light emitting element can be mounted in a small area with the size of the chip.
 図3は、フリップチップ電極と発光部のレイアウトに自由度を持たせる構成を説明するための図である。N型半導体3、活性層4及びP型半導体5からなる化合物半導体膜層(発光部)84とフリップチップ電極7及び8との間に電源配線層90が設けられている。この構造によれば、フリップチップ電極と発光セルの配置が自由になり、1つの発光素子を複数個の発光部により構成することも可能になる。図3に示す発光部のP型半導体5及びN+型半導体2と、フリップチップのP電極8及びN電極7との間は、電源配線層90においてそれぞれ相互配線がなされている。活性層にて1次発光する光及び蛍光体330にて2次発光する光がそれぞれ進む方向は、図2に示した場合と同様である。 FIG. 3 is a diagram for explaining a configuration that gives flexibility to the layout of the flip chip electrode and the light emitting portion. A power supply wiring layer 90 is provided between the compound semiconductor film layer (light emitting portion) 84 composed of the N-type semiconductor 3, the active layer 4 and the P-type semiconductor 5 and the flip chip electrodes 7 and 8. According to this structure, the arrangement of the flip chip electrode and the light emitting cell is free, and one light emitting element can be constituted by a plurality of light emitting portions. The P-type semiconductor 5 and N + type semiconductor 2 of the light emitting section shown in FIG. 3 and the P-electrode 8 and N-electrode 7 of the flip chip are interconnected in the power supply wiring layer 90, respectively. The directions in which the primary emission light in the active layer and the secondary emission light in the phosphor 330 travel are the same as those shown in FIG.
 上記いずれのベアチップ実装の場合においても、チップサイズでの超小型の実装が可能である。しかし、図2(c)に示したように、フリップチップ電極を用いたベアチップ実装において、1次発光した光により蛍光体で波長の長い光を2次発光させる場合、2次発光して側面方向に向かう光uと1次発光のうち側面方向へ洩れる光rを集光するためには側面反射板150等が必要になるという問題がある。また、光の広がりは側面反射板の傾きや位置により調整されるが、これに代わる集光機構を発光素子に組み込みたいというニーズがある。 In any case of the bare chip mounting described above, it is possible to mount the chip in a very small size. However, as shown in FIG. 2C, in the case of bare chip mounting using a flip chip electrode, when light having a long wavelength is emitted secondarily by a fluorescent material by the light emitted by the primary light emission, the light is emitted secondarily and the lateral direction is obtained. There is a problem that the side reflector 150 or the like is required to collect the light u that travels toward the light and the light r that leaks in the lateral direction out of the primary light emission. Further, the spread of light is adjusted by the inclination and position of the side reflector, but there is a need to incorporate a light collecting mechanism instead of this in the light emitting element.
 また、いずれの発光素子にも共通する課題として、1次発光の光量のばらつきや蛍光体において励起される光量のばらつきが大きく、一定の輝度を得るためには発光素子を光出力のクラス別に選別する必要があった。この選別を含む組立ての総費用が大きくなり、コスト低減に大きな障害となっているため、輝度のばらつきを小さくする手段が望まれている。 In addition, as a problem common to all light-emitting elements, there are large variations in the amount of primary light emission and the amount of light excited in the phosphor, and in order to obtain a constant luminance, the light-emitting elements are sorted by light output class. There was a need to do. Since the total cost of assembling including this selection becomes large and becomes a great obstacle to cost reduction, a means for reducing the luminance variation is desired.
 発光ダイオードの用途が拡大するにつれて、コスト低減、省エネルギーのための高効率化、輝度ばらつきの低減、パッケージの小型化のニーズが高まってきている。コスト低減の為には小型で簡素なパッケージ構造とすること、光の広がりを調整する機能を持つこと、発光効率の向上により素子サイズを小さくすること、輝度ばらつきを少なくすることによる調整工数の低減などが必要である。高効率化のためには、発光部で発光するあらゆる方向の光を補足して集光方向に集め、集光方向にはできるだけ遮蔽物を置かない構造とする必要がある。高効率化は、省エネルギーだけではなく、素子サイズの小型化や素子数の削減、駆動回路の簡素化を促進して、コスト低減にも効果が大きい。輝度ばらつきの低減は、照明品質の向上のために必要であるだけではなく、製品適用時の組立工数の低減に寄与し、コスト低減にも効果が大きい。小型化のためには、チップサイズと同じ大きさのパッケージ(チップサイズパッケージ)とすることである。また、レンズのような光の広がりの調整機能をもウエーハ状態で作りこむことができれば、小型化だけではなくパッケージのコストを飛躍的に低減することができる。 As the use of light emitting diodes expands, there are increasing needs for cost reduction, high efficiency for energy saving, reduction in luminance variations, and downsizing of packages. To reduce costs, use a small and simple package structure, have a function to adjust the spread of light, reduce the element size by improving the luminous efficiency, and reduce the adjustment man-hours by reducing the luminance variation Etc. are necessary. In order to increase efficiency, it is necessary to have a structure in which light in all directions emitted from the light emitting unit is captured and collected in the light collecting direction, and a shield is not placed as much as possible in the light collecting direction. Higher efficiency not only saves energy, but also promotes the reduction of the element size, the number of elements, and the simplification of the drive circuit, thereby greatly reducing the cost. The reduction in luminance variation is not only necessary for improving the illumination quality, but also contributes to a reduction in the number of assembly steps when the product is applied, and has a great effect on cost reduction. In order to reduce the size, a package having the same size as the chip size (chip size package) is used. Further, if the function of adjusting the spread of light like a lens can be built in the wafer state, not only the size can be reduced, but the cost of the package can be drastically reduced.
 本発明は、この様な事情に鑑みなされたものであり、発光した光をできるだけ多く外部へ集光することができ、照射される光の分布の調整することができ、輝度ばらつきを低減することができる光半導体装置であって、しかも、ウエーハ状態すなわち発光素子が個別に分離される前の状態でチップサイズパッケージングが可能な光半導体装置を提供することを目的とする。 The present invention has been made in view of such circumstances, and can collect as much emitted light as possible to the outside, adjust the distribution of irradiated light, and reduce luminance variation. Another object of the present invention is to provide an optical semiconductor device capable of chip size packaging in a wafer state, that is, before a light emitting element is individually separated.
 本発明は、以下の通りである。
 1.素子基板面上に区画されて化合物半導体層により形成された1又は2以上の発光部と、該発光部からの光を取り出す発光面とは反対側の素子電極面に該発光部に電源を供給する素子電極とを具備し、該発光面に垂直な集光方向に光を取り出す発光素子と、前記発光素子の前記発光面側に、前記素子基板の外周と外周が同一サイズの透明部材と、を備え、複数の前記発光素子が前記素子基板となるウエーハに形成された状態において、前記透明部材が配設され、その後に該発光素子ごとに分離されて形成されることを特徴とする光半導体装置。
 2.前記発光素子の外周と外周が同一サイズの基板であって、前記発光素子を搭載する素子搭載面に該発光素子の前記素子電極に対応した内部電極と、該素子搭載面とは反対面に該内部電極と接続された外部電極と、を具備するパッケージ基板を更に備え、前記発光素子の前記素子電極面と前記パッケージ基板の前記素子搭載面とを対向させて貼り合わせることにより、前記素子電極と前記内部電極とが電気的に接続される前記1.記載の光半導体装置。
 3.前記発光素子の前記素子電極面と前記パッケージ基板の前記素子搭載面とを接合材を用いて貼り合わせることにより、前記素子電極と前記内部電極とが電気的に接続されるとともに、前記素子電極面と前記素子搭載面との間が該接合材により密閉される前記2.記載の光半導体装置。
 4.前記透明部材は、前記発光素子から取り出す光束を前記集光方向に向けて狭める凸レンズである前記1.乃至3.のいずれかに記載の光半導体装置。
 5.前記発光素子の前記発光面上に載置される枠体であって、該枠体の外周は前記素子基板の外周と同一サイズであり、該枠体の内側壁面は前記発光面から前記集光方向に向けて広がるように傾斜して形成されているキャビティ部材と、前記キャビティ部材の前記内側壁面に囲まれた空洞部に充填される蛍光体と、を更に備え、前記キャビティ部材の前記内側壁面は前記発光部及び前記蛍光体で発光した光を前記集光方向に反射し、前記発光素子の前記発光面上に前記キャビティ部材及び前記透明部材が順に積層されて形成される前記1.乃至4.のいずれかに記載の光半導体装置。
 6.前記発光部ごとにその側面を囲む側面反射膜を更に備え、前記側面反射膜は前記発光部で発光して前記素子基板と略平行に進む光を前記集光方向に反射する前記1.乃至5.のいずれかに記載の光半導体装置。
 7.前記キャビティ部材の前記内側壁面は、シリコン基板をエッチングすることにより形成される前記5.又は6.に記載の光半導体装置。
 8.前記キャビティ部材は金属で形成されている前記5.又は6.に記載の光半導体装置。
 9.前記発光素子と前記パッケージ基板とが貼り合わされた後に、該発光素子の前記素子基板が除去されて形成される前記2.乃至8.のいずれかに記載の光半導体装置。
 10.前記発光素子は複数の前記発光部を備え、前記素子基板の前記素子電極面又は前記パッケージ基板の前記外部電極が設けられる面には、各前記発光部に供給する電源を選択的に接続又は切断するための給電選択部を備え、前記給電選択部により前記発光素子ごとの輝度を調整可能とした前記1.乃至9.のいずれかに記載の光半導体装置。
 11.前記素子基板は透明基板である前記1.乃至10.のいずれかに記載の光半導体装置。
 12.前記素子基板はシリコン基板である前記1.乃至10.のいずれかに記載の光半導体装置。
The present invention is as follows.
1. Power is supplied to the light emitting portion on one or more light emitting portions that are partitioned by the compound semiconductor layer and formed on the surface of the element substrate, and the device electrode surface opposite to the light emitting surface that extracts light from the light emitting portion. A light emitting element that extracts light in a light collecting direction perpendicular to the light emitting surface, and a transparent member having the same outer periphery and outer periphery of the element substrate on the light emitting surface side of the light emitting element; An optical semiconductor comprising: a plurality of light emitting elements formed on a wafer serving as the element substrate; wherein the transparent member is disposed and then separated for each light emitting element. apparatus.
2. The outer periphery and the outer periphery of the light emitting element are substrates of the same size, the inner surface corresponding to the element electrode of the light emitting element is mounted on the element mounting surface on which the light emitting element is mounted, and the surface opposite to the element mounting surface is A package substrate having an external electrode connected to the internal electrode, the device electrode surface of the light emitting device and the device mounting surface of the package substrate facing each other, and bonding the device electrode and The 1. is connected to the internal electrode. The optical semiconductor device described.
3. By bonding the element electrode surface of the light emitting element and the element mounting surface of the package substrate using a bonding material, the element electrode and the internal electrode are electrically connected, and the element electrode surface And the element mounting surface are sealed with the bonding material. The optical semiconductor device described.
4). The transparent member is a convex lens that narrows a light beam extracted from the light emitting element toward the light collecting direction. To 3. An optical semiconductor device according to any one of the above.
5. A frame body placed on the light emitting surface of the light emitting element, wherein an outer periphery of the frame body is the same size as an outer periphery of the element substrate, and an inner wall surface of the frame body is the light condensing from the light emitting surface A cavity member formed to be inclined so as to spread in a direction; and a phosphor filled in a cavity portion surrounded by the inner wall surface of the cavity member; and the inner wall surface of the cavity member Is formed by sequentially reflecting the light emitted from the light emitting part and the phosphor in the light collecting direction and laminating the cavity member and the transparent member in order on the light emitting surface of the light emitting element. To 4. An optical semiconductor device according to any one of the above.
6). Each of the light emitting units further includes a side surface reflecting film surrounding the side surface, and the side surface reflecting film reflects the light emitted from the light emitting unit and traveling substantially parallel to the element substrate in the light collecting direction. To 5. An optical semiconductor device according to any one of the above.
7). 4. The inner wall surface of the cavity member is formed by etching a silicon substrate. Or 6. An optical semiconductor device according to 1.
8). 4. The cavity member is made of metal. Or 6. An optical semiconductor device according to 1.
9. After the light emitting element and the package substrate are bonded together, the element substrate of the light emitting element is removed and formed. To 8. An optical semiconductor device according to any one of the above.
10. The light emitting element includes a plurality of the light emitting units, and selectively connects or disconnects power supplied to the light emitting units on the element electrode surface of the element substrate or the surface of the package substrate on which the external electrode is provided. The power supply selection unit for adjusting the luminance of each light emitting element can be adjusted by the power supply selection unit. To 9. An optical semiconductor device according to any one of the above.
11. The element substrate is a transparent substrate. To 10. An optical semiconductor device according to any one of the above.
12 The element substrate is a silicon substrate. To 10. An optical semiconductor device according to any one of the above.
 本発明において、少なくとも素子基板とその上に形成された発光層及び電極を備えて構成される素子(その中間工程の状態にあるものを含む)を「発光素子」という。発光素子は、1又は2以上の区画された発光部を備えて構成される。この1つの発光部を「発光セル」という。各発光セルと不可分にその側面を囲む側面反射膜(「マイクロミラー」ともいう。)を設け、このマイクロミラーによって囲まれた構造の発光セルを「光マイクロセル」という。また、内側側面が傾斜した反射面とされたチップサイズの枠体を「マイクロキャビティ」と呼び、光の広がりを調整するチップサイズのレンズを「マイクロレンズ」と呼ぶ。マイクロレンズには凸レンズ及び凹レンズを含み、凸レンズとしたものを「マイクロ凸レンズ」と呼ぶ。発光素子をパッケージングした状態、又はマザーボードに実装可能な状態に加工したものを、「発光ダイオード」又は「光半導体装置」と呼ぶ。 In the present invention, an element (including an element in an intermediate process state) including at least an element substrate and a light emitting layer and an electrode formed thereon is referred to as a “light emitting element”. The light emitting element includes one or two or more partitioned light emitting units. This one light emitting unit is referred to as a “light emitting cell”. Each light emitting cell is provided with a side reflection film (also referred to as a “micromirror”) that surrounds the side surface of the light emitting cell, and the light emitting cell surrounded by the micromirror is called an “optical microcell”. A chip-sized frame whose reflecting surface has an inclined inner side surface is called a “microcavity”, and a chip-sized lens that adjusts the spread of light is called a “microlens”. A microlens includes a convex lens and a concave lens, and a convex lens is referred to as a “microconvex lens”. A light emitting element packaged or processed into a state where it can be mounted on a motherboard is referred to as a “light emitting diode” or “optical semiconductor device”.
 本発明の光半導体装置によれば、素子基板面上に化合物半導体層により形成された1又は2以上の発光部と、発光部からの光を取り出す発光面とは反対側の素子電極面に素子電極とを具備し、発光面に垂直な集光方向に光を取り出す発光素子と、発光素子の発光面側に、素子基板と同一サイズの透明部材とを備えるため、発光素子のチップサイズで発光ダイオードを構成することができる。これにより、ベアチップで実装される発光ダイオードや、チップサイズパッケージの発光ダイオードを実現することができる。発光素子は、1又は2以上の光マイクロセルを備えるため、発光ダイオードの高効率化を図ることができる。また、発光素子の電極は発光面とは反対側に備えられるため、集光方向に光を遮るものがなく、効率良く光を取り出すことができる。発光面側に備える透明部材をマイクロレンズとすることにより、発光素子から放射される光束の広がりを調整することができ、外部で出射光の拡散や方位分布の均一化等を容易に行うことも可能になる。また、透明部材を透明プラスチック板等とすることにより、発光素子を保護することができる。本光半導体装置は、複数の発光素子が素子基板となるウエーハに形成された状態において透明部材が配設され、その後に発光素子ごとに分離されて形成されるため、超小型で高輝度の発光ダイオードを、簡素な工程により低コストで実現することが可能になる。本光半導体装置の構成は、白色用だけでなく、赤色その他すべての発光ダイオードに適用することできる。 According to the optical semiconductor device of the present invention, one or two or more light emitting portions formed of the compound semiconductor layer on the element substrate surface and the element electrode surface on the side opposite to the light emitting surface for extracting light from the light emitting portion. A light-emitting element that includes an electrode and extracts light in a light collecting direction perpendicular to the light-emitting surface; and a light-emitting surface side of the light-emitting element having a transparent member that is the same size as the element substrate. A diode can be constructed. Thereby, it is possible to realize a light emitting diode mounted in a bare chip or a light emitting diode in a chip size package. Since the light-emitting element includes one or more optical microcells, the efficiency of the light-emitting diode can be increased. Further, since the electrode of the light emitting element is provided on the side opposite to the light emitting surface, there is nothing to block light in the light collecting direction, and light can be extracted efficiently. By using a microlens as the transparent member provided on the light emitting surface side, the spread of the light beam emitted from the light emitting element can be adjusted, and the diffusion of the emitted light and the uniform orientation distribution can be easily performed outside. It becomes possible. Further, the light emitting element can be protected by using a transparent plastic plate or the like as the transparent member. In this optical semiconductor device, a transparent member is disposed in a state in which a plurality of light emitting elements are formed on a wafer which is an element substrate, and then formed separately for each light emitting element. The diode can be realized at a low cost by a simple process. The configuration of the present optical semiconductor device can be applied not only for white but also for all other light emitting diodes such as red.
 前記発光素子と同一サイズの基板であって、発光素子を搭載する素子搭載面に素子電極に対応した内部電極と、その反対面に外部電極と、を具備するパッケージ基板を更に備え、発光素子の素子電極面とパッケージ基板の素子搭載面とを対向させて貼り合わせることにより、素子電極と内部電極とが電気的に接続される場合は、チップサイズパッケージの発光ダイオードとすることができる。この貼り合わせにより、素子電極と内部電極との電気的接続を確実にすることができる。また、複数の発光素子がウエーハに形成された状態において、発光素子とパッケージ基板とが貼り合わされ、その後に発光素子ごとに分離されるため、パッケージをすべてウエーハ状態で形成することができ、極めて簡素な工程により製造することができる。電気的検査や光学的検査もウエーハ状態で可能になる。そして、発光ダイオードを個別に分離した後もエキスバンドした状態等で扱うことができるため、そのままマザーボードに実装することができ、静電気の影響を受けにくい製造と取扱が可能になり、パッケージ内にサージ対策素子を特に備える必要もなくなる。
 前記発光素子と前記パッケージ基板の素子搭載面とを接合材を用いて貼り合わせる場合は、素子電極と内部電極との電気的接続を確実にするとともに、発光素子とパッケージ基板を貼り合わせた端面が接合材により封じられるため、内部の化合物半導体層等を湿気や異物等から保護することができる。また、用途や使用環境に応じて、パッケージ基板の材料や接合材の材料を適宜に選択して用いることができる。
 前記透明部材は、前記発光素子から取り出す光束を集光方向に向けて狭める凸レンズである場合は、発光素子から放射される光束を集光方向に向けて絞ることができるため、発光ダイオードに集光機能を備え、更に、外部で出射光の拡散や方位分布の均一化等を容易に行うことが可能になる。
A substrate having the same size as the light emitting element, further comprising a package substrate having an internal electrode corresponding to the element electrode on an element mounting surface on which the light emitting element is mounted, and an external electrode on the opposite surface; When the element electrode and the internal electrode are electrically connected by bonding the element electrode surface and the element mounting surface of the package substrate to face each other, a light emitting diode of a chip size package can be obtained. By this bonding, electrical connection between the element electrode and the internal electrode can be ensured. In addition, in a state where a plurality of light emitting elements are formed on the wafer, the light emitting element and the package substrate are bonded together and then separated for each light emitting element, so that the entire package can be formed in the wafer state, which is extremely simple. It can be manufactured by a simple process. Electrical inspection and optical inspection are also possible in the wafer state. And since it can be handled in an expanded state even after the light emitting diodes are separated individually, it can be mounted on the motherboard as it is, making it possible to manufacture and handle it less susceptible to static electricity, and surge in the package There is no need to provide a countermeasure element.
When bonding the light emitting element and the element mounting surface of the package substrate using a bonding material, the electrical connection between the element electrode and the internal electrode is ensured, and the end surface where the light emitting element and the package substrate are bonded is Since it is sealed by the bonding material, the internal compound semiconductor layer and the like can be protected from moisture and foreign matter. In addition, the material of the package substrate and the material of the bonding material can be appropriately selected and used in accordance with the application and use environment.
In the case where the transparent member is a convex lens that narrows the light beam extracted from the light emitting element toward the condensing direction, the light beam emitted from the light emitting element can be focused toward the light condensing direction. In addition, it is possible to easily diffuse the emitted light and make the orientation distribution uniform outside.
 前記発光素子の前記発光面上に載置される枠体であって、その枠体の外周は前記素子基板の外周と同一サイズであり、枠体の内側壁面は発光面から集光方向に向けて広がるように傾斜して形成されているキャビティ部材と、キャビティ部材の内側壁面に囲まれた空洞部に充填される蛍光体と、を更に備える場合は、発光素子からの光で蛍光体を励起することにより白色発光ダイオードを構成することができ、キャビティ部材の内側壁面により発光部及び蛍光体で発光した光を反射させることによって集光方向への集光率を高めることができる。キャビティ部材から集光方向に前記透明部材が配設されることとなるため、キャビティ部材を介して放射される全ての光の広がり等を透明部材により調整することが可能になる。また、複数の発光素子が素子基板となるウエーハに形成された状態において、キャビティ部材及び透明部材が順に積層され、その後に発光素子ごとに分離されるため、簡素な工程により白色用の発光ダイオードを実現することができる。 A frame body mounted on the light emitting surface of the light emitting element, the outer periphery of the frame body is the same size as the outer periphery of the element substrate, and the inner wall surface of the frame body is directed from the light emitting surface toward the light collecting direction. In the case of further comprising a cavity member formed so as to be inclined and a phosphor filled in the cavity surrounded by the inner wall surface of the cavity member, the phosphor is excited by light from the light emitting element. Thus, a white light emitting diode can be formed, and the light collection ratio in the light collecting direction can be increased by reflecting the light emitted from the light emitting portion and the phosphor by the inner wall surface of the cavity member. Since the transparent member is disposed in the light collecting direction from the cavity member, the spread of all the light emitted through the cavity member can be adjusted by the transparent member. In addition, in a state in which a plurality of light emitting elements are formed on a wafer serving as an element substrate, a cavity member and a transparent member are sequentially stacked and then separated for each light emitting element. Can be realized.
 前記発光部ごとにその側面を囲む側面反射膜(マイクロミラー)を更に備え、発光部で発光して素子基板と略平行に進む光を集光方向に反射する場合は、従来利用することが困難であった発光部から側面方向に進む光を取り出すことができ、発光ダイオードの輝度を高めることができる。 When each light emitting unit further includes a side reflecting film (micromirror) surrounding the side surface thereof, and the light emitted from the light emitting unit and traveling in a direction substantially parallel to the element substrate is reflected in the light collecting direction, it is difficult to use in the past. Thus, the light traveling in the lateral direction can be taken out from the light emitting portion, and the luminance of the light emitting diode can be increased.
 前記キャビティ部材の内側壁面は、シリコン基板をエッチングすることにより形成される場合は、シリコンの面方位によるエッチング速度の差を利用して、傾斜した反射面を容易に形成することができる。
 キャビティ部材を金属で形成する場合は、銅等の薄板を使用し、鍛造、エッチング加工等によりキャビティ部材を形成することができ、反射率の高い内側壁面とすることができる。
When the inner wall surface of the cavity member is formed by etching a silicon substrate, an inclined reflecting surface can be easily formed using the difference in etching rate depending on the surface orientation of silicon.
When the cavity member is made of metal, a thin plate such as copper can be used, the cavity member can be formed by forging, etching, or the like, and the inner wall surface can be made highly reflective.
 前記発光素子と前記パッケージ基板とが貼り合わされた後に、発光素子の素子基板が除去される場合は、透明な素子基板であっても通過光の損失を無くすことができ、光を通さない基板も使用することが可能になる。また、発光素子とパッケージ基板の熱膨張率の違いに起因するストレスを無くし、基板の反りを避けることができる。 When the element substrate of the light emitting element is removed after the light emitting element and the package substrate are bonded together, loss of passing light can be eliminated even with a transparent element substrate. It becomes possible to use. Further, it is possible to eliminate the stress caused by the difference in thermal expansion coefficient between the light emitting element and the package substrate, and to avoid the warpage of the substrate.
 前記発光素子は複数の発光部を備え、素子基板の素子電極面又は前記パッケージ基板の外部電極が設けられる面には、各発光部に供給する電源を選択的に接続又は切断するための給電選択部を備える場合は、ウエーハ状態において発光素子の輝度を計測し、その輝度に応じて各発光部への給電を設定することができる。これによって発光素子ごとの輝度のばらつきを減らすことができるため、従来必要であった選別を不要とし、製造コストを低減することが可能になる。 The light emitting element includes a plurality of light emitting units, and a power supply selection for selectively connecting or disconnecting power supplied to each light emitting unit on the element electrode surface of the element substrate or the surface on which the external electrode of the package substrate is provided. In the case where the light emitting element is provided, the brightness of the light emitting element can be measured in the wafer state, and power supply to each light emitting part can be set according to the brightness. As a result, variation in luminance for each light-emitting element can be reduced, so that it is not necessary to perform selection that has been required in the past, and the manufacturing cost can be reduced.
 前記素子基板が透明基板である場合は、従来一般に用いられているサファイア基板等を用いて発光素子を形成し、ベアチップで実装される発光ダイオード又はチップサイズパッケージの発光ダイオードを構成することができる。
 素子基板がシリコン基板である場合は、サファイア基板に比べてはるかに容易に低温でエッチング加工することができるため、発光素子に与えるストレスを低減することができる。また、素子基板をそのまま利用して、キャビティ部材を形成することができる。
When the element substrate is a transparent substrate, a light emitting element can be formed by using a conventionally used sapphire substrate or the like, and a light emitting diode mounted in a bare chip or a light emitting diode in a chip size package can be configured.
When the element substrate is a silicon substrate, etching can be performed at a low temperature much more easily than a sapphire substrate, so that stress applied to the light-emitting element can be reduced. Moreover, a cavity member can be formed using an element substrate as it is.
 本発明について、本発明による典型的な実施形態の例を挙げ、言及された複数の図面を参照しつつ以下の詳細な記述にて説明する。同様の参照符号は図面のいくつかの図を通して同様の部品又は構成を示す。
従来の発光ダイオードの構造を説明するための断面図 発光素子をベアチップで実装する場合を説明するための断面図 複数の発光セルを配設した発光素子を説明するための断面図 透明部材及びキャビティを備える発光素子の概念を説明するための断面図 透明部材及びキャビティを備えるチップサイズパッケージの概念を説明するための断面図 マイクロキャビティの構造及びその制作工程を説明するための断面図 マイクロミラー及び光マイクロセルの構成を説明するための断面図 複数の発光部への給電を選択するために素子基板の素子電極面に設けた給電選択部を説明するための図 透明部材により、放射される光の広がりの調整手法等を説明するための断面図 シリコン基板上に半導体層を形成する工程を説明するための断面図 シリコン基板上に光マイクロセルを形成する工程を説明するための断面図 図11の工程により形成された光マイクロセルの構造を説明するための断面図及び平面図 ベアチップ実装可能な発光ダイオード全体の構成を示す図 図11の工程により作成された発光素子を説明するための断面図及び斜視図 サファイア基板上に光マイクロセルを形成する工程を説明するための断面図 図15の工程により作成された発光素子を説明するための断面図及び斜視図 サファイア基板を用いたチップサイズパッケージの発光ダイオードの組立を説明するための断面図 図17の発光ダイオードの製造手順を説明するための断面図 シリコン基板を使用し、パッケージ基板に給電選択部を備えた発光ダイオードの組立を説明するための図 複数の発光セルから構成される発光素子を説明するための断面図 サファイア基板を使用し、パッケージ基板に給電選択部を備えた発光ダイオードの組立を説明するための図 発光素子の各種形態を説明するための断面図 図22(d)の発光素子と各種パッケージ基板を用いたチップサイズパッケージの構造を説明するための断面図 図22(c)の発光素子と熱可塑性基板を用いたチップサイズパッケージの製造手順を説明するための断面図 図24のチップサイズパッケージの具体的な製造工程を説明するための断面図 図22(d)の発光素子と熱可塑性基板を用いたチップサイズパッケージの具体的な製造工程を説明するための断面図 図22(a)の発光素子と熱可塑性基板を用いたチップサイズパッケージの製造手順を説明するための断面図 図22(c)の発光素子とガラスエポキシ基板を用いたチップサイズパッケージの製造手順を説明するための断面図 図28のチップサイズパッケージの具体的な製造工程を説明するための断面図 図22(d)の発光素子とガラスエポキシ基板を用いた別のチップサイズパッケージの具体的な製造工程を説明するための断面図 図22(a)の発光素子とガラスエポキシ基板を用いたチップサイズパッケージの製造手順を説明するための断面図 シリコンのウエーハと発光素子及び発光ダイオードの関係を説明する図 図32の発光素子部の構造を説明するための平面図及び断面図 図32のパッケージ基板に設けられた給電選択部を説明するための断面図及び平面図 ウエーハ状態の発光素子及び発光ダイオードの関係を説明する図
The present invention will now be described in the following detailed description, with reference to the referenced drawings, by way of example of exemplary embodiments according to the present invention. Like reference numerals designate like parts or configurations throughout the several views of the drawings.
Sectional drawing for demonstrating the structure of the conventional light emitting diode Sectional drawing for demonstrating the case where a light emitting element is mounted by a bare chip. Sectional drawing for demonstrating the light emitting element which arrange | positioned several light emitting cells. Sectional drawing for demonstrating the concept of a light emitting element provided with a transparent member and a cavity. Sectional drawing for demonstrating the concept of a chip size package provided with a transparent member and a cavity Cross-sectional view for explaining the structure of the microcavity and the manufacturing process Sectional drawing for demonstrating the structure of a micromirror and an optical microcell The figure for demonstrating the electric power feeding selection part provided in the element electrode surface of an element board | substrate in order to select the electric power feeding to several light emission parts. Sectional drawing for demonstrating the adjustment method of the spread of the light radiated | emitted with a transparent member Sectional drawing for demonstrating the process of forming a semiconductor layer on a silicon substrate Sectional drawing for demonstrating the process of forming an optical microcell on a silicon substrate Sectional drawing and top view for demonstrating the structure of the optical microcell formed by the process of FIG. The figure which shows the structure of the whole light emitting diode which can be bare chip mounted Sectional drawing and perspective view for demonstrating the light emitting element created by the process of FIG. Sectional drawing for demonstrating the process of forming an optical microcell on a sapphire substrate Sectional drawing and perspective view for demonstrating the light emitting element created by the process of FIG. Sectional drawing for demonstrating the assembly of the light emitting diode of the chip size package using a sapphire substrate Sectional drawing for demonstrating the manufacturing procedure of the light emitting diode of FIG. The figure for explaining the assembly of the light emitting diode which uses the silicon substrate and has the power supply selection part on the package substrate Sectional drawing for demonstrating the light emitting element comprised from several light emitting cells A diagram for explaining the assembly of a light-emitting diode using a sapphire substrate and having a power supply selector on the package substrate Sectional drawing for demonstrating the various forms of a light emitting element Sectional drawing for demonstrating the structure of the chip size package using the light emitting element of FIG.22 (d), and various package substrates. Sectional drawing for demonstrating the manufacture procedure of the chip size package using the light emitting element of FIG.22 (c), and a thermoplastic substrate. Sectional drawing for demonstrating the specific manufacturing process of the chip size package of FIG. Sectional drawing for demonstrating the specific manufacturing process of the chip size package using the light emitting element of FIG.22 (d), and a thermoplastic substrate. Sectional drawing for demonstrating the manufacturing procedure of the chip size package using the light emitting element of Fig.22 (a), and a thermoplastic substrate. Sectional drawing for demonstrating the manufacturing procedure of the chip size package using the light emitting element of FIG.22 (c), and a glass epoxy board | substrate. Sectional drawing for demonstrating the specific manufacturing process of the chip size package of FIG. Sectional drawing for demonstrating the specific manufacturing process of another chip size package using the light emitting element of FIG.22 (d), and a glass epoxy substrate. Sectional drawing for demonstrating the manufacture procedure of the chip size package using the light emitting element and glass epoxy substrate of Fig.22 (a). The figure explaining the relationship between a silicon wafer, a light emitting element, and a light emitting diode FIG. 32 is a plan view and a cross-sectional view for explaining the structure of the light emitting element portion of FIG. Sectional drawing and top view for demonstrating the electric power feeding selection part provided in the package board | substrate of FIG. The figure explaining the relationship between the light emitting element of a wafer state, and a light emitting diode
 前記のとおり、本願発明の課題は、発光した光をできるだけ多く外部へ集光することができ、照射される光の方位分布の調整することができ、しかも、ウエーハ状態すなわち発光素子が分離される前の状態でチップサイズパッケージングが可能な光半導体装置を提供することである。また、その光半導体装置は、輝度ばらつきを低減することができることが好ましい。更に、サージが発生しない扱いが可能であり、必要な場合にはサージ吸収機能を備えることが好ましい。
 発光素子で発光した光をできるだけ多く外部へ集光するためには、発光セルの発光層近傍にマイクロミラーを組み込み、発光層にて発生する光(1次発光)のうち発光層に沿った方向の光を集光するようにすることができる。また、蛍光体を備えて白色用の発光ダイオードとする場合には、その1次発光した光、及びそれに励起されて蛍光体で発光する光(2次発光)を集光するために、側面反射機能を有するマイクロキャビティを備えるようにすることができる。また、照射される光の方位分布の調整のためには、マイクロレンズを組み込むことができる。また、輝度のばらつきの低減のためには、発光素子を複数個の発光セルに分離して形成し、所望の輝度に応じて必要な発光セルだけに通電する手段を持つ構成とすることができる。そして、チップサイズパッケージの手段としては、超小型のパッケージングを発光素子がウエーハ状態の時に行うことである。したがって、ウエーハ状態において、必要に応じて上記のマイクロミラー、マイクロキャビティ、蛍光体、マイクロレンズ等を形成可能であり、複数の発光セルの選択的な通電手段を備えることができることが好ましい。更に、電気サージからの保護のために、発光ダイオードの取り扱いが全てウエーハ状態で可能であり、必要な場合にはパッケージ基板に電気サージを吸収するバリスタ基材を用いる等の方法を採用可能であることが好ましい。
As described above, the problem of the present invention is that the emitted light can be collected as much as possible outside, the orientation distribution of the irradiated light can be adjusted, and the wafer state, that is, the light emitting element is separated. An object of the present invention is to provide an optical semiconductor device capable of chip size packaging in the previous state. Moreover, it is preferable that the optical semiconductor device can reduce variation in luminance. Furthermore, it is possible to handle without generating a surge, and it is preferable to provide a surge absorbing function when necessary.
In order to collect as much light emitted from the light emitting element as possible to the outside, a micromirror is incorporated in the vicinity of the light emitting layer of the light emitting cell, and the direction along the light emitting layer of the light (primary light emission) generated in the light emitting layer The light can be condensed. Further, when a white light-emitting diode is provided with a phosphor, side reflection is performed to collect the primary light emitted and the light excited by the light and emitted from the phosphor (secondary light emission). A microcavity having a function can be provided. In addition, a microlens can be incorporated to adjust the azimuth distribution of irradiated light. Further, in order to reduce the variation in luminance, the light emitting element can be formed by separating it into a plurality of light emitting cells, and it can be configured to have means for energizing only the necessary light emitting cells according to the desired luminance. . As a means of chip size packaging, ultra-small packaging is performed when the light emitting element is in a wafer state. Therefore, in the wafer state, it is preferable that the above-described micromirrors, microcavities, phosphors, microlenses, and the like can be formed as necessary, and a means for selectively energizing a plurality of light emitting cells can be provided. Furthermore, in order to protect against electrical surges, the light emitting diodes can be handled in a wafer state, and if necessary, a method such as using a varistor base material that absorbs electrical surges on the package substrate can be adopted. It is preferable.
 図4及び図5に、前記課題を解決する光半導体装置の構造の概念を示す。ここでは、マイクロミラーを有しない1つの発光セルを備えた発光素子を使用する場合を例示する。図4は、その発光素子をベアチップで使用する場合の概念図であり、図5は、その発光素子をチップサイズパッケージに実装して使用する場合の概念図である。光を取り出す集光方向側の発光素子の表面を「発光面」と呼ぶ。 4 and 5 show the concept of the structure of the optical semiconductor device that solves the above-mentioned problems. Here, the case where the light emitting element provided with one light emitting cell which does not have a micromirror is illustrated. FIG. 4 is a conceptual diagram when the light-emitting element is used in a bare chip, and FIG. 5 is a conceptual diagram when the light-emitting element is used in a chip size package. The surface of the light emitting element on the light collecting direction side from which light is extracted is referred to as a “light emitting surface”.
 図4(a)は、図2に示した発光素子16の発光面に、内側の側壁が傾斜した鏡面であるマイクロキャビティ175を貼り合わせ、そのマイクロキャビティ175内に蛍光体330を充填した構造を表わす断面図である。図4(b)は、透明部材として、放射される光束を狭角に絞るためのマイクロ凸レンズ520を示す。図4(c)は、(a)の発光素子に(b)のマイクロ凸レンズを貼り合わせて形成した発光ダイオード35の断面を表わしている。マイクロキャビティ175及びマイクロ凸レンズ520の外周は、発光素子の外周と同一サイズに形成されている。すなわちマイクロキャビティ及びマイクロ凸レンズを上面視した形状及び大きさは、前記発光面の形状及び大きさと同じである。
 図4(a)中p、q及びrは、活性層で1次発光した光が進む方向を示している。活性層から集光方向zに向かう光はそのまま進む(p)。集光方向zとは反対向きの光は、反射膜6で反射されて集光方向zへ進む(q)。集光方向zと略垂直すなわち活性層にほぼ平行な方向に向かう光(r)は、多くは散乱され一部が側面方向へ洩れる。1次発光は波長が短く、1次発光した光のうち蛍光体330に入射した光は蛍光物質を励起して、波長の長い2次発光が生じる。2次発光した光が進む方向を、図中s、t及びu等で示す。2次発光の光は、集光方向zに対して平行な方向s、斜め方向t、垂直な側面方向u、及び集光方向とは反対の発光層方向、の全方向へ放出される。集光方向zへの光s及び斜め方向への光tはそのまま放出され、側面方向への光uはマイクロキャビティの内側壁面により反射して集光方向zへ向けられる。発光層方向への光は導電反射層により反射され集光方向へ戻る。このようにして、1次発光及び2次発光した光はマイクロキャビティの集光方向z側の開口から放出される。図4(c)に示すようにマイクロキャビティ上にマイクロ凸レンズ520を貼り合わせた場合には、2次発光する斜め方向の光tや、マイクロキャビティにより反射された光uは、マイクロ凸レンズ520により屈折されて集光方向z寄りに出射される(t2、u2)。マイクロ凸レンズは、1次発光の光も2次発光の光も屈折させて、全体として光束をw1-w1間からw2-w2間へ狭くするために設けられている。この様に出射光の方向を狭くすることにより、その後に光路を広げたり、より絞ったりすることが容易になる。尚、以下の図面において、1次発光及び2次発光の光が進む方向は本図と同様の参照符号を付して表示する。
4A shows a structure in which a microcavity 175, which is a mirror surface with an inclined inner side wall, is bonded to the light emitting surface of the light emitting element 16 shown in FIG. 2, and the phosphor 330 is filled in the microcavity 175. FIG. FIG. FIG. 4B shows a micro convex lens 520 as a transparent member for narrowing the emitted light beam at a narrow angle. FIG. 4C shows a cross section of a light emitting diode 35 formed by bonding the light emitting element of FIG. The outer circumferences of the microcavity 175 and the micro convex lens 520 are formed in the same size as the outer circumference of the light emitting element. That is, the shape and size of the microcavity and the micro convex lens as viewed from above are the same as the shape and size of the light emitting surface.
In FIG. 4A, p, q, and r indicate the directions in which the primary light emitted from the active layer travels. Light traveling from the active layer in the light collecting direction z travels as it is (p). The light in the direction opposite to the light collecting direction z is reflected by the reflective film 6 and proceeds in the light collecting direction z (q). Most of the light (r) traveling in a direction substantially perpendicular to the light collection direction z, that is, in a direction substantially parallel to the active layer, is scattered and partly leaks in the side surface direction. The primary emission has a short wavelength, and the light incident on the phosphor 330 out of the primary emitted light excites the fluorescent material to generate secondary emission with a long wavelength. The direction in which the secondary emitted light travels is indicated by s, t, u, etc. in the figure. The secondary emission light is emitted in all directions including a direction s parallel to the light collection direction z, an oblique direction t, a vertical side surface direction u, and a light emitting layer direction opposite to the light collection direction. The light s in the light collecting direction z and the light t in the oblique direction are emitted as they are, and the light u in the side surface direction is reflected by the inner wall surface of the microcavity and directed in the light collecting direction z. The light toward the light emitting layer is reflected by the conductive reflection layer and returns to the light collecting direction. In this way, the primary light emission and the secondary light emission are emitted from the opening in the light collecting direction z side of the microcavity. As shown in FIG. 4C, when the micro convex lens 520 is bonded on the micro cavity, the light t in the oblique direction emitting secondary light and the light u reflected by the micro cavity are refracted by the micro convex lens 520. And emitted toward the light collecting direction z (t2, u2). The micro-convex lens is provided to refract both the primary emission light and the secondary emission light to narrow the light beam as a whole from between w1-w1 to between w2-w2. By narrowing the direction of the emitted light in this way, it becomes easy to widen or narrow the optical path thereafter. In the following drawings, the directions in which the primary light emission and the secondary light emission travel are indicated by the same reference numerals as those in this figure.
 図5はチップサイズパッケージとした光半導体装置の概念図(断面図)である。図5(c)はサファイア基板200上に形成した前記発光素子16、(d)は接合材(インターポーザ)350、(e)はパッケージ基板40を示している。パッケージ基板40及びインターポーザ350の外周は、発光素子の外周と同一サイズに形成されている。パッケージ基板40には、発光素子の素子電極(フリップチップ電極)7及び8と接続するための内部電極61、外部との接続用の外部電極60、及び内部電極61と外部電極60とを接続するビア50が設けられている。発光素子16がウエーハ状態のままで、そのウエーハサイズで形成されたインターポーザ350及びパッケージ基板40と貼り合わせることにより、パッケージングと電極間接続を同時に行うことができる。その後、サファイア基板200はリフトオフ技術にて除去される。サファイア基板が除去された発光素子を用いて構成される発光ダイオードの態様を、図5(g)及び(h)に例示する。先ず、図5(h)に示す発光ダイオード137は、上記発光素子の発光面上に、透明部材として透明プラスチック板521を貼り合わせたものである。透明プラスチック板により、サファイア基板が除去された後の発光部を保護することができる。透明部材は透明プラスチック板に限られず、凸レンズ、凹レンズ等とすることもできる。さらに、透明部材に蛍光体を含浸させることにより、発光素子の1次発光と透明部材における2次発光とを合わせて白色光とすることもできる。次に、図5(g)に示す発光ダイオード37は、上記発光素子の発光面上に、マイクロキャビティ及びその空洞部に充填された蛍光体330と、透明部材(マイクロ凸レンズ520)とを備えている。この発光ダイオード37は、以下のような手順で作ることができる。サファイア基板が除去された発光素子と、図5(b)に示すマイクロキャビティ175を形成したシリコン基板173とをウエーハ状態で貼り合わせる。シリコン基板173の底面には、予めシリコン酸化膜180が形成されている。マイクロキャビティ175を囲む側壁面411は、傾斜した鏡面である。白色発光ダイオード用途では、マイクロキャビティ175内に蛍光体330が充填される。更に、図5(a)に示すマイクロ凸レンズ520を貼り合わせて、ウエーハ状態で発光ダイオードの構造を完成させる。その後、発光素子ごとに分割することにより、図5(g)に示すような発光ダイオード37が完成し、マザーボード340に実装することができる。マイクロキャビティ175及びマイクロ凸レンズ520の作用効果は図4の場合と同様であり、1次発光及び2次発光した光を集光方向に取り出すことができ、放射する光束の広がる角度が狭められた発光ダイオードが実現できる。白色発光ダイオードの場合には蛍光体330により2次発光をさせるが、本光半導体装置の構成は、蛍光体を用いない発光ダイオードにも適用できる。また、透明部材として、マイクロ凸レンズ520の代わりに凹レンズとしてもよいし、透明プラスチック板を用いてもよい。また、マイクロキャビティを使用しないで、蛍光体が実装されてもよい。その場合、外周が発光素子の素子基板の外周と同一サイズの板状の蛍光体を、上記のマイクロキャビティの代わりに発光素子の発光面上に貼り付ければよい。そして、発光面上に載置した蛍光体の上に、マイクロ凸レンズ等透明部材を備えることができる。
 上例の発光ダイオード137、37のいずれの場合も、発光ダイオードを外部に接続するための電極はフリップチップではなく、パッケージ基板(普及しているプリント基板等)に設けられた外部電極60であるため、マザーボードへの実装を汎用機で行うことができる。
FIG. 5 is a conceptual diagram (cross-sectional view) of an optical semiconductor device having a chip size package. 5C shows the light emitting element 16 formed on the sapphire substrate 200, FIG. 5D shows a bonding material (interposer) 350, and FIG. 5E shows the package substrate 40. FIG. The outer periphery of the package substrate 40 and the interposer 350 is formed in the same size as the outer periphery of the light emitting element. The package substrate 40 is connected to an internal electrode 61 for connecting to element electrodes (flip chip electrodes) 7 and 8 of the light emitting element, an external electrode 60 for connection to the outside, and the internal electrode 61 and the external electrode 60. A via 50 is provided. When the light emitting element 16 remains in the wafer state and is bonded to the interposer 350 and the package substrate 40 formed in the wafer size, packaging and interelectrode connection can be performed simultaneously. Thereafter, the sapphire substrate 200 is removed by a lift-off technique. The mode of the light emitting diode comprised using the light emitting element from which the sapphire substrate was removed is illustrated to FIG.5 (g) and (h). First, a light emitting diode 137 shown in FIG. 5 (h) is obtained by bonding a transparent plastic plate 521 as a transparent member on the light emitting surface of the light emitting element. The light emitting part after the sapphire substrate is removed can be protected by the transparent plastic plate. The transparent member is not limited to a transparent plastic plate, and may be a convex lens, a concave lens, or the like. Furthermore, by impregnating the transparent member with a phosphor, the primary light emission of the light-emitting element and the secondary light emission of the transparent member can be combined into white light. Next, the light emitting diode 37 shown in FIG. 5G includes a microcavity, a phosphor 330 filled in the cavity, and a transparent member (microconvex lens 520) on the light emitting surface of the light emitting element. Yes. The light-emitting diode 37 can be manufactured by the following procedure. The light emitting element from which the sapphire substrate has been removed and the silicon substrate 173 on which the microcavity 175 shown in FIG. 5B is formed are bonded together in a wafer state. A silicon oxide film 180 is formed in advance on the bottom surface of the silicon substrate 173. A side wall surface 411 surrounding the microcavity 175 is an inclined mirror surface. For white light emitting diode applications, the microcavity 175 is filled with a phosphor 330. Further, a micro convex lens 520 shown in FIG. 5A is bonded to complete a light emitting diode structure in a wafer state. Thereafter, by dividing each light emitting element, a light emitting diode 37 as shown in FIG. 5G is completed and can be mounted on the mother board 340. The action and effect of the microcavity 175 and the micro convex lens 520 are the same as in FIG. 4, and the light emitted by the primary light emission and the secondary light emission can be taken out in the condensing direction, and the emission angle of the emitted light beam is narrowed. A diode can be realized. In the case of a white light emitting diode, secondary light is emitted by the phosphor 330, but the configuration of the optical semiconductor device can also be applied to a light emitting diode that does not use the phosphor. Further, as the transparent member, a concave lens may be used instead of the micro convex lens 520, or a transparent plastic plate may be used. Further, the phosphor may be mounted without using the microcavity. In that case, a plate-like phosphor whose outer periphery is the same size as the outer periphery of the element substrate of the light-emitting element may be attached on the light-emitting surface of the light-emitting element instead of the microcavity. Then, a transparent member such as a micro convex lens can be provided on the phosphor placed on the light emitting surface.
In any of the light emitting diodes 137 and 37 in the above example, an electrode for connecting the light emitting diode to the outside is not a flip chip but an external electrode 60 provided on a package substrate (a popular printed circuit board or the like). Therefore, it can be mounted on a motherboard with a general-purpose machine.
 上記光半導体装置の概念について、更に具体的に説明する。図4に示した発光ダイオード35は、サファイア基板200を用いた発光素子16の上へマイクロキャビティを貼り合わせ、蛍光体を充填し、更にマイクロ凸レンズを貼り合わせて形成されている。その工程はウエーハ状態で行われ、電気的検査及び光学的検査を経て個別の発光ダイオードに分割することができる。このような構造の課題は、サファイア基板が存在するため、サファイア基板から横方向へ光が漏れる(r’)という点である。この解決策の1つは、図5に示した発光ダイオードのようにサファイア基板200を除去することである。別の解決策として、発光素子の基板にシリコン基板を用いる方法がある。シリコン基板を用いることにより、シリコン基板自身にマイクロキャビティを形成することができる(詳しくは後述)。それによって、別のマイクロキャビティ用の基板を貼り合わせる工程が不要となると共に、基板の横方向への光の漏れを解消できる。更に、素子基板であるシリコンの多くの部分がキャビティとして空洞になるため、フリップチップ接続によって発光素子とマザーボードとの間に生じる応力が緩和されるという重要な効果も得られる。これにより、フリップチップ実装時のアンダーフィルと呼ばれる樹脂で強度を増加させる工程が、多くの用途で不要になる。 The concept of the optical semiconductor device will be described more specifically. The light emitting diode 35 shown in FIG. 4 is formed by bonding a microcavity onto the light emitting element 16 using the sapphire substrate 200, filling a phosphor, and further bonding a micro convex lens. The process is performed in a wafer state and can be divided into individual light emitting diodes through electrical inspection and optical inspection. The problem of such a structure is that light leaks (r ′) from the sapphire substrate in the lateral direction because the sapphire substrate exists. One solution is to remove the sapphire substrate 200 as in the light emitting diode shown in FIG. As another solution, there is a method in which a silicon substrate is used as the substrate of the light emitting element. By using a silicon substrate, a microcavity can be formed in the silicon substrate itself (details will be described later). This eliminates the need for attaching another microcavity substrate and eliminates light leakage in the lateral direction of the substrate. Further, since many portions of silicon as the element substrate become cavities as cavities, an important effect is obtained that the stress generated between the light emitting element and the mother board is relieved by flip chip connection. This eliminates the need for a process of increasing strength with a resin called underfill during flip chip mounting in many applications.
 図5(c)に示した発光素子に備えられるフリップチップ電極7及び8は、例えば、スタッドバンプで約30μmの高さに形成し、高さの均一化のためのレべリングを行って約20μmの高さとすることができる。その他、フリップチップ電極は金メッキで形成することも可能である。図5(d)のインターポーザ350は、厚さ約50μm程度で、PEEK(ポリ・エーテル・エーテル・ケトン)材及びPEI(ポリ・エーテル・イミド)材等をベースとする熱可塑性の材料からなり、400℃では液状となるため約300℃で貼り合わせを推奨される材料を用いることができる。図5(e)に示したパッケージ基板40として、耐熱性材料からなるプリント基板等を用いることができる。パッケージ基板にはビア50が作り込まれており、ビア50により銅等からなる外部電極60と内部電極61とが接続されている。ビア50には銀又は銅等を主材料とする金属を用いることができる。発熱が大きい用途では、できるだけ多数のビアを設けることにより熱抵抗を下げることができる。図5(c)~(e)の部材をウエーハの状態で合体させて約300℃の真空中で加圧し、その後冷却して硬化させることによりウエーハ状態でパッケージを完成させることができる。この状態でサファイア基板200をリフトオフ技術で除去する。そしてマイクロキャビティを貼り合わせ、蛍光体を充填し、マイクロ凸レンズを貼り合わせる各工程と、電気検査及び光学検査をウエーハ状態で行い、その後に個別の発光ダイオードに分割することができる。 The flip chip electrodes 7 and 8 included in the light emitting device shown in FIG. 5C are formed to have a height of about 30 μm by, for example, stud bumps, and leveling is performed to make the height uniform. The height can be 20 μm. In addition, the flip chip electrode can be formed by gold plating. The interposer 350 shown in FIG. 5 (d) has a thickness of about 50 μm and is made of a thermoplastic material based on a PEEK (poly ether ether ketone) material, a PEI (poly ether imide) material, or the like. Since it becomes liquid at 400 ° C., a material recommended to be bonded at about 300 ° C. can be used. As the package substrate 40 shown in FIG. 5E, a printed circuit board made of a heat resistant material or the like can be used. A via 50 is formed in the package substrate, and an external electrode 60 made of copper or the like and an internal electrode 61 are connected by the via 50. For the via 50, a metal whose main material is silver or copper can be used. In applications that generate a large amount of heat, the thermal resistance can be lowered by providing as many vias as possible. The members shown in FIGS. 5C to 5E are combined in a wafer state, pressurized in a vacuum of about 300 ° C., and then cooled and cured to complete the package in the wafer state. In this state, the sapphire substrate 200 is removed by a lift-off technique. Then, each step of bonding the microcavity, filling the phosphor, and bonding the micro convex lens, and the electrical inspection and optical inspection can be performed in a wafer state, and then divided into individual light emitting diodes.
 前記発光素子16は、サファイア基板200、N+型半導体2、N型半導体3、活性層4、P型半導体5、反射導電膜6、フリップチップ電極7及び8からなっている。発光素子として、図3に示したような発光セルが複数個に分割されて構成されている発光素子を用いることも可能である。その場合、各フリップチップ電極と各発光セルとの接続は、電源配線層90を設けることにより自由に行うことができる。また、パッケージの土台となるパッケージ基板40として、熱可塑性の材料を用いた基板を使用することができる。熱可塑性のパッケージ基板40と、サファイア基板を素子基板とする発光素子とは、熱可塑性の材料からなるインターポーザ350を介して貼り合わせることができ、該材料の軟化温度である300℃程度で真空中において接着されることにより密着性が確保される。また、その接着部の端部は熱可塑のインターポーザにより封止されるため、インターポーザは素子分割後の保護材としての役割を果たしている。パッケージ基板の内部電極61を構成する導体の表面が銅であり、フリップチップ電極の材料が金である場合、これらの金と銅との間が共晶温度以上である300℃程度で貼り合わされるため、フリップチップの金とパッケージ基板側の銅とは共晶結合して、強度と導電性が確保される。
 化合物半導体により発光層が形成された発光素子とパッケージ基板とが貼り合わされた後に、発光層の基板であるサファイア基板はリフトオフ手法等により除去される。サファイア基板の除去は前記理由の他、サファイアの硬度が高く、発光素子ごとに分割する際のフルカットに障害ともなるからである。サファイア基板が除去された状態では、化合物半導体を支える基板はパッケージ基板40となる。この状態で、発光面であるN+型半導体2の上に、シリコン酸化膜180を形成したシリコンウエーハ173を貼り合わせる。そのシリコンをエッチングすることによりマイクロキャビティ175を形成することができる。
The light emitting element 16 includes a sapphire substrate 200, an N + type semiconductor 2, an N type semiconductor 3, an active layer 4, a P type semiconductor 5, a reflective conductive film 6, and flip chip electrodes 7 and 8. As the light emitting element, it is possible to use a light emitting element in which a light emitting cell as shown in FIG. 3 is divided into a plurality of parts. In that case, the connection between each flip-chip electrode and each light emitting cell can be freely made by providing the power supply wiring layer 90. In addition, a substrate using a thermoplastic material can be used as the package substrate 40 serving as a base of the package. The thermoplastic package substrate 40 and the light-emitting element having a sapphire substrate as an element substrate can be bonded together via an interposer 350 made of a thermoplastic material, and in vacuum at about 300 ° C., which is the softening temperature of the material. Adhesiveness is ensured by bonding in step. Moreover, since the edge part of the adhesion part is sealed with a thermoplastic interposer, the interposer plays a role as a protective material after element division. When the surface of the conductor constituting the internal electrode 61 of the package substrate is copper and the material of the flip chip electrode is gold, the gold and copper are bonded together at about 300 ° C., which is equal to or higher than the eutectic temperature. Therefore, the gold of the flip chip and the copper on the package substrate side are eutectic bonded to ensure strength and conductivity.
After the light emitting element having the light emitting layer formed of the compound semiconductor and the package substrate are bonded together, the sapphire substrate which is the substrate of the light emitting layer is removed by a lift-off method or the like. This is because the removal of the sapphire substrate has the high hardness of sapphire in addition to the above-mentioned reason, and it becomes an obstacle to full cut when dividing each light emitting element. In a state where the sapphire substrate is removed, the substrate that supports the compound semiconductor becomes the package substrate 40. In this state, a silicon wafer 173 having a silicon oxide film 180 formed thereon is bonded onto the N + type semiconductor 2 that is a light emitting surface. The microcavity 175 can be formed by etching the silicon.
 前記発光ダイオード35、37、137等を実現するには次のような課題がある。マイクロキャビティの形成方法、1次発光し側面方向に向かう光の捕捉方法、マイクロ凸レンズ等透明部材の形成方法、発光ダイオードから出射された光束の広がりを所望の広がりに調整する方法、光の輝度のばらつきの低減方法、静電気等のサージ対策である。また、図5に示したような発光素子とパッケージとを一体化するパッケージング方法である。
 図6は、マイクロキャビティの構造及びその製造手順を説明するための断面図である。図6(b2)に示すマイクロキャビティ175は、厚さ約百μmのシリコンウエーハ173に内側壁面が傾斜した凹部を設けて、その凹部の底面は光を通過し、凹部の側壁面は光を反射する構造である。上記凹部は、(110)面方位のシリコン基板173を用いて、KOH液等でエッチングすることにより形成することができる。そのエッチングがシリコンの(111)面で停止することを利用して、54°に傾斜した内側壁面411を形成することができる。シリコン基板173の底面には、光学的には透明なシリコン酸化膜180がシリコンのエッチングストッパーを兼ねて設けられている。シリコンの内側壁面411は54度の傾斜角度を持った鏡面となり、光の反射面となる。図6(a2)は、シリコン基板173の下面にシリコン酸化膜180を形成し、上面にフォトレジスト265を形成した状態を表わす。フォトレジスト265をマスクとしてKOH水溶液でシリコンをエッチングすることができ、破線410の位置がエッチングの終止面である。図6(b2)はエッチング後にフォトレジストを除去した状態を示し、マイクロキャビティ175が形成されている。エッチング後の内側壁面411が、シリコン結晶面で決まる54°の角度となる。フォトレジストの代わりにシリコン酸化膜を用いてもよい。すなわち、シリコン基板上面にシリコン酸化膜を形成し、そのシリコン酸化膜をエッチングすることによりフォトレジスト265と同様のパターンを形成する。形成されたシリコン酸化膜をマスクとして、シリコン基板をエッチングすることができる。図6(a2)及び(b2)に示したシリコン基板を用いるマイクロキャビティの形成法は、発光素子の基板がサファイアである場合には、サファイア基板を除去した後に適用することができる。発光素子の基板がシリコンである場合には、素子基板のシリコンをそのままマイクロキャビティの母材とすることができるため、より簡素な構造とすることができる。図6(a1)は、シリコン基板170を素子基板として化合物半導体層(発光部)84が形成された状態を示している。シリコン基板170と化合物半導体層84の間にはシリコン酸化膜180が設けられている。シリコン基板170をエッチングするためのマスクとして、フォトレジストの代わりにシリコン酸化膜185が形成してあり、シリコン基板170はKOH水溶液等を用いてエッチングされる。図6(b1)は、そのエッチングによってマイクロキャビティ175が形成された状態を示す。以上に説明した例ではいずれもシリコンを用いてマイクロキャビティを形成したが、マイクロキャビティはシリコンに限らず金属を用いて形成することもできる。図6(a3)及び(b3)は、銅のスタッドフレームを用いる例を示す断面図である。図6(a3)に示されるマイクロキャビティの母材540は、板厚0.2mm程度の銅板を用いて、鍛造技術により底部541、傾斜した側壁544が成形されている。この状態から、全面等方エッチングにより全体を上部からエッチングして、図6(b3)に示すスタッドフレームの形状にすることができる。底部542は金属がエッチングで取り去られ、光が通過する部分となる。この後にニッケルメッキ、銀メッキ等をすることにより、高反射率の内側壁面544を実現することができる。この様な銅のフレームは、半導体パッケージで多く用いられているリードフレームと同様な技術で製作することができる。スタッドフレームをウエーハと同じ大きさの領域に形成することにより、化合物半導体のウエーハと貼り合わせることができる。貼り合わせには透明接着剤等を用いることができる。
In order to realize the light emitting diodes 35, 37, 137 and the like, there are the following problems. Microcavity formation method, primary light emission method for capturing light toward the side, formation method for transparent members such as micro-convex lenses, method for adjusting the spread of luminous flux emitted from a light emitting diode to a desired spread, This is a method for reducing variation and measures against surges such as static electricity. Further, it is a packaging method in which the light emitting element and the package as shown in FIG. 5 are integrated.
FIG. 6 is a cross-sectional view for explaining the structure of the microcavity and the manufacturing procedure thereof. The microcavity 175 shown in FIG. 6 (b2) is provided with a concave portion whose inner wall surface is inclined on a silicon wafer 173 having a thickness of about 100 μm. It is a structure to do. The concave portion can be formed by etching with a KOH solution or the like using a silicon substrate 173 having a (110) plane orientation. The inner wall surface 411 inclined by 54 ° can be formed by utilizing the fact that the etching stops at the (111) plane of silicon. On the bottom surface of the silicon substrate 173, an optically transparent silicon oxide film 180 is provided also as a silicon etching stopper. The inner wall surface 411 of silicon becomes a mirror surface having an inclination angle of 54 degrees and serves as a light reflection surface. FIG. 6A2 shows a state in which the silicon oxide film 180 is formed on the lower surface of the silicon substrate 173 and the photoresist 265 is formed on the upper surface. Silicon can be etched with an aqueous KOH solution using the photoresist 265 as a mask, and the position of the broken line 410 is the etching end surface. FIG. 6B2 shows a state in which the photoresist is removed after etching, and a microcavity 175 is formed. The inner wall surface 411 after etching has an angle of 54 ° determined by the silicon crystal plane. A silicon oxide film may be used instead of the photoresist. That is, a silicon oxide film is formed on the upper surface of the silicon substrate, and the silicon oxide film is etched to form a pattern similar to that of the photoresist 265. The silicon substrate can be etched using the formed silicon oxide film as a mask. The microcavity forming method using the silicon substrate shown in FIGS. 6A2 and 6B2 can be applied after removing the sapphire substrate when the substrate of the light emitting element is sapphire. In the case where the substrate of the light emitting element is silicon, the silicon of the element substrate can be used as it is as the base material of the microcavity, so that a simpler structure can be obtained. FIG. 6A1 shows a state in which the compound semiconductor layer (light emitting portion) 84 is formed using the silicon substrate 170 as an element substrate. A silicon oxide film 180 is provided between the silicon substrate 170 and the compound semiconductor layer 84. As a mask for etching the silicon substrate 170, a silicon oxide film 185 is formed instead of the photoresist, and the silicon substrate 170 is etched using a KOH aqueous solution or the like. FIG. 6B1 shows a state in which the microcavity 175 is formed by the etching. In any of the examples described above, the microcavity is formed using silicon. However, the microcavity can be formed using not only silicon but also metal. FIGS. 6A3 and 6B3 are cross-sectional views illustrating an example in which a copper stud frame is used. The base material 540 of the microcavity shown in FIG. 6 (a3) has a bottom 541 and an inclined side wall 544 formed by a forging technique using a copper plate having a thickness of about 0.2 mm. From this state, the entire surface can be etched from above by isotropic etching to form the stud frame shown in FIG. 6 (b3). The bottom portion 542 is a portion through which light is passed by etching away the metal. After this, by performing nickel plating, silver plating, or the like, a highly reflective inner wall surface 544 can be realized. Such a copper frame can be manufactured by a technique similar to a lead frame often used in a semiconductor package. By forming the stud frame in a region having the same size as the wafer, it can be bonded to the compound semiconductor wafer. A transparent adhesive or the like can be used for bonding.
 図7は、1次発光した側面方向の光を捕捉するために、発光素子内にマイクロミラーを設ける概念を説明する断面図である。図7(a)に示す発光素子は、サファイア基板200の上にN型半導体3、活性層4、P型半導体5からなる半導体層を備えている。活性層4から発生する光のうち、集光方向zに向かう光はそのまま放出され(p)、反対方向への光は背面反射膜6で集光方向へ反射されて放出され(q)、側面方向の光は発光層の近傍に設けられたマイクロミラー70により反射され集光方向へ向けて放出される(r)。ここで、マイクロミラーの傾斜角αは0度から90度以内の値である。本発明においては、発光セルの側面を囲んでマイクロミラー70を形成することができる。図7(b)はこの概念に基づいて構成する発光素子の例を表す。この発光素子は1つのサファイア基板200上に形成されており、複数の発光セル80を備えている。本図の発光素子は、横方向に4つ、奥方向に2つ(図示せず)、の合計8つの発光セルを備えている。各発光セル80は、図7(a)と同様の半導体層を備える。そして、各発光セル80は側面をマイクロミラー71によって囲まれ、それぞれ光マイクロセルを構成している。発光セルの側面方向に向かう光はマイクロミラー71により反射され、集光方向へ向けて放出される(r)。また、各光マイクロセルの下側には導電反射膜(背面反射膜)275が形成されている。各光マイクロセル内の半導体層には、フリップチップ電極7及び8から配線層90を経て電源が供給される。後述するように、シリコン基板を用いても同様の構造を形成することができる。 FIG. 7 is a cross-sectional view for explaining the concept of providing a micromirror in the light emitting element in order to capture the light emitted from the side surface that has undergone primary emission. The light emitting element shown in FIG. 7A includes a semiconductor layer made of an N-type semiconductor 3, an active layer 4, and a P-type semiconductor 5 on a sapphire substrate 200. Of the light generated from the active layer 4, the light directed in the light collecting direction z is emitted as it is (p), and the light in the opposite direction is reflected and emitted in the light collecting direction by the back reflecting film 6 (q). The light in the direction is reflected by the micromirror 70 provided in the vicinity of the light emitting layer and is emitted toward the light collecting direction (r). Here, the inclination angle α of the micromirror is a value within 0 to 90 degrees. In the present invention, the micromirror 70 can be formed by surrounding the side surface of the light emitting cell. FIG. 7B shows an example of a light emitting element configured based on this concept. The light emitting element is formed on one sapphire substrate 200 and includes a plurality of light emitting cells 80. The light emitting element of this figure is provided with a total of eight light emitting cells, four in the horizontal direction and two in the back direction (not shown). Each light emitting cell 80 includes a semiconductor layer similar to that shown in FIG. Each light emitting cell 80 is surrounded by a micromirror 71 on its side surface, and constitutes an optical microcell. The light directed toward the side surface of the light emitting cell is reflected by the micromirror 71 and emitted toward the light collecting direction (r). In addition, a conductive reflective film (back reflective film) 275 is formed below each optical microcell. Power is supplied to the semiconductor layer in each optical microcell from the flip chip electrodes 7 and 8 via the wiring layer 90. As will be described later, a similar structure can be formed using a silicon substrate.
 次に、図8を参照し、発光素子の輝度のばらつきの低減方法を説明する。図8(a)は、8個の光マイクロセルからなる発光素子を表わす斜視図である。各光マイクロセルは、発光セル80とそれを囲むマイクロミラー71を備えて構成されている。発光素子は、マイクロミラーを有しない発光セルを用いて構成されていてもよい。電源配線層310とフリップチップ電極との間に薄膜配線層315が設けられている。この薄膜配線層には、図8(c)に示す電源配線パターンからなる給電選択部が形成されている。8個の光マイクロセル1~8の発光部の面積は、例えば、図8(b)に示すような重み付けがしてある。すなわち、各光マイクロセルの発光部の面積は、光マイクロセル1(421)をAとして、光マイクロセル5(425)がA、光マイクロセル3(423)がA/2、光マイクロセル6(426)がA/4、光マイクロセル4(424)がA/8とされている。発光素子から出力される光量は発光部の面積に対応するため、通電する光マイクロセルの個数を変えることによって発光素子から放出される光の総量を調整することができる。例えば、当初に8個の光マイクロセルの全てに電源を供給して、全体の輝度を測定する。このときの光量すなわち発光部の総面積は(5+7/8)Aである。この状態で測定された輝度に応じて選択的に光マイクロセルへの電源供給を接続又は遮断することにより、(1/8)Aを最小単位として光量を調整することができる。図8(c)により電源接続の例を説明する。フリップチップN電極322と全ての光マイクロセルのN電極とは接続されている。フリップチップP電極321からは、図8(b)にP0と表示された全ての光マイクロセル(1、2、7及び8)のP電極に接続されている。また、P1、P2、P3、P4と表示された各光マイクロセル(5、3、6、4)のP電極には、それぞれ配線441、442、443、444によりフリップチップP電極321が接続されている。当初には、それらの配線によりP0~P4の全ての光マイクロセルへ電源が供給される。そして、全体の輝度を測定した後に、必要な光マイクロセル以外には電源を供給しないようにすることができる。すなわち、各光マイクロセルへ電源を供給する各配線部に電源切断部(445)を設け、光量に応じて配線441~444を選択的に切断する。本例では、最大使用面積(5+7/8)Aと最小使用面積4Aとの間で、発光面積すなわち出力される光量を適宜選択することができる。より広い範囲でばらつきを調整したい場合には、同様の考え方で発光セルの数や面積比等を設定し、それに応じた配線部を設けることにより可能である。また、各光マイクロセルへ電源を供給する各配線部を選択的に接続するようにしてもよい。また、各光マイクロセルの発光部の面積に重み付けをしないで、各光マイクロセルへ供給する電源を選択的に接続又は切断するようにしてもよい。 Next, with reference to FIG. 8, a method for reducing the luminance variation of the light emitting element will be described. FIG. 8A is a perspective view showing a light emitting element composed of eight optical microcells. Each optical microcell comprises a light emitting cell 80 and a micromirror 71 surrounding it. The light-emitting element may be configured using a light-emitting cell that does not have a micromirror. A thin film wiring layer 315 is provided between the power supply wiring layer 310 and the flip chip electrode. In this thin-film wiring layer, a power supply selection portion made up of a power supply wiring pattern shown in FIG. 8C is formed. The areas of the light emitting portions of the eight optical microcells 1 to 8 are weighted as shown in FIG. 8B, for example. That is, the area of the light emitting portion of each optical microcell is as follows: optical microcell 1 (421) is A, optical microcell 5 (425) is A, optical microcell 3 (423) is A / 2, and optical microcell 6 (426) is A / 4, and the optical microcell 4 (424) is A / 8. Since the amount of light output from the light emitting element corresponds to the area of the light emitting unit, the total amount of light emitted from the light emitting element can be adjusted by changing the number of energized optical microcells. For example, power is initially supplied to all eight optical microcells, and the overall luminance is measured. The light quantity at this time, that is, the total area of the light emitting part is (5 + 7/8) A. By selectively connecting or cutting off the power supply to the optical microcell according to the luminance measured in this state, the amount of light can be adjusted with (1/8) A as the minimum unit. An example of power connection will be described with reference to FIG. The flip chip N electrode 322 and the N electrodes of all the optical microcells are connected. The flip chip P electrode 321 is connected to the P electrodes of all the optical microcells (1, 2, 7, and 8) indicated as P0 in FIG. 8B. In addition, flip chip P electrodes 321 are connected to the P electrodes of the optical microcells (5, 3, 6, 4) labeled P1, P2, P3, and P4 by wirings 441, 442, 443, and 444, respectively. ing. Initially, power is supplied to all the optical microcells P0 to P4 through these wirings. And after measuring the whole brightness | luminance, it can be made not to supply power other than the required optical microcell. That is, a power cutting unit (445) is provided in each wiring unit that supplies power to each optical microcell, and the wirings 441 to 444 are selectively cut according to the amount of light. In this example, the light emission area, that is, the amount of light to be output can be appropriately selected between the maximum use area (5 + 7/8) A and the minimum use area 4A. When it is desired to adjust the variation in a wider range, it is possible to set the number of light emitting cells, the area ratio, and the like based on the same concept and to provide a wiring portion corresponding to the number. In addition, each wiring section that supplies power to each optical microcell may be selectively connected. Further, the power supplied to each optical microcell may be selectively connected or disconnected without weighting the area of the light emitting portion of each optical microcell.
 図9により、放射される光の広がりの調整手法を説明する。図9(a)はマザーボード340に実装された発光ダイオード37を示す。光は、マイクロ凸レンズ520がなければ広い角度範囲(w1-w1間)に放出されるところ、マイクロ凸レンズ520によって集光方向zを中心とする狭い角度範囲(w2-w2間)に絞られる。狭い角度範囲で光を照射する用途に適している。図9(b)は、上記発光ダイオードから集光方向に光拡散板又は光拡散レンズ600を設ける例を示す。発光ダイオードのマイクロ凸レンズ520により狭い角度範囲(w2-w2間)に絞られた光束は、光拡散レンズ600により広い角度(w3-w3間)に広げられる。このようにマイクロ凸レンズ520と拡散レンズ600とを組み合わせることによって、光の照射角度を精度よく設定することができる。この様な構成は、液晶テレビのバックライトのような広角で広い面積を均質に照射する用途に最適である。具体例として、図1に示したようなパッケージ内に発光ダイオード37を収容する場合を、図9(c)に示す。このパッケージの上面は、キャップの代わりに拡散レンズとして凹レンズ601が用いられている。このような構造にすれば、凹レンズ601と発光ダイオード37に備えられた凸レンズ520との組み合わせにより、所望の広がりをもった光束を作り出すことができる。 Referring to FIG. 9, a method for adjusting the spread of emitted light will be described. FIG. 9A shows the light emitting diode 37 mounted on the mother board 340. Without the micro convex lens 520, the light is emitted in a wide angle range (between w1 and w1), but is narrowed by the micro convex lens 520 into a narrow angle range (between w2 and w2) centering on the light collection direction z. Suitable for applications that irradiate light in a narrow angle range. FIG. 9B shows an example in which a light diffusing plate or a light diffusing lens 600 is provided in the light collecting direction from the light emitting diode. The light beam narrowed to a narrow angle range (between w2 and w2) by the micro convex lens 520 of the light emitting diode is spread to a wide angle (between w3 and w3) by the light diffusion lens 600. Thus, by combining the micro convex lens 520 and the diffusing lens 600, the light irradiation angle can be set with high accuracy. Such a configuration is optimal for applications that uniformly irradiate a wide area with a wide angle, such as a backlight of a liquid crystal television. As a specific example, FIG. 9C shows the case where the light emitting diode 37 is accommodated in the package as shown in FIG. On the upper surface of this package, a concave lens 601 is used as a diffusing lens instead of a cap. With such a structure, a light beam having a desired spread can be created by the combination of the concave lens 601 and the convex lens 520 provided in the light emitting diode 37.
 なお、静電気に関しては、特にGaN系の発光素子はサージに弱いため配慮が必要である。本発光素子及びそのチップサイズパッケージは、ウエーハ状態での加工や実装が可能であり、またウエーハ状態からエキスバンドテープに貼りつけた状態で取扱うこともできるため、ハンドリング中などに静電気にさらされる機会を減少させることができる。更なる静電気対策が必要な用途には、パッケージ基板に非直線性抵抗特性をもつ基材(バリスタ基板)を用いることにより、静電気吸収機能を持たせることができる。 Note that with regard to static electricity, GaN-based light-emitting elements are particularly sensitive to surges and need to be considered. This light emitting device and its chip size package can be processed and mounted in the wafer state, and can also be handled in the state of being attached to the extended tape from the wafer state, so it is exposed to static electricity during handling. Can be reduced. For applications that require further countermeasures against static electricity, a static electricity absorbing function can be provided by using a base material (varistor substrate) having non-linear resistance characteristics for the package substrate.
 発光素子の製造工程及び構造を、図10~12を参照しつつ説明する。図10は、素子基板としてシリコン基板を使用し、シリコン基板上に半導体層を形成する製造方法を示す。発光層はサファイア基板上に形成されることが多いが、シリコン基板上に単に化合物半導体を形成することは困難である。サファイア基板上ではなくシリコン基板上に半導体層を設ける意味は、後にシリコン基板をエッチングにより除去することが容易である点にある。サファイアの場合、極めて硬いために部分的除去は困難であり、また、レーザ等を用いて界面を部分的ながら高温で剥離するリフトオフ手法が必要になる。これに対し、シリコンの場合には、KOH液等を用いたエッチングにより100℃以下で容易に除去できる。図10(a)に示すように、公知の手法を用いて、サファイア基板201上に半導体層としてP型GaAlN層240、活性層230、N型GaAlN層220を形成する。その上に、新規の手法として、酸化インジウム膜190を形成し、更にその上にシリコン酸化膜180を形成する。酸化インジウム膜190は、N型半導体層を低抵抗にする目的、及び半導体エッチング時の終点管理の目的で備えられる。シリコン酸化膜180は、シリコン基板との貼り合わせ用に備えられる。貼り合わせの事前処理としてCMP(ケミカル・メカニカル・ポリッシ)加工することも可能である。しかし、本例の構成では、シリコン酸化膜の下地がすべて平坦であり、シリコン酸化膜も平坦な膜となるため、CMP加工は必ずしも要しない。図10(b)は、後に発光素子の基板となるシリコン基板170を示す。図10(c)に示すように、半導体層、酸化インジウム膜及びシリコン酸化膜が形成されたサファイア基板とシリコン基板170とを貼り合わせる。その後、図10(d)に示すように、サファイア基板201をリフトオフして除去する。図10(c)に示す状態では金属及び有機物が含まれていないため温度的制約が緩和され、容易にサファイアをリフトオフすることができる。図10(d)に示す状態で、シリコン基板170が発光素子用の基板となる。 The manufacturing process and structure of the light emitting element will be described with reference to FIGS. FIG. 10 shows a manufacturing method using a silicon substrate as an element substrate and forming a semiconductor layer on the silicon substrate. The light emitting layer is often formed on a sapphire substrate, but it is difficult to simply form a compound semiconductor on a silicon substrate. The meaning of providing the semiconductor layer on the silicon substrate instead of the sapphire substrate is that the silicon substrate can be easily removed later by etching. In the case of sapphire, since it is extremely hard, partial removal is difficult, and a lift-off method is required in which the interface is partially peeled off at a high temperature using a laser or the like. On the other hand, in the case of silicon, it can be easily removed at 100 ° C. or lower by etching using a KOH solution or the like. As shown in FIG. 10A, a P-type GaAlN layer 240, an active layer 230, and an N-type GaAlN layer 220 are formed as semiconductor layers on a sapphire substrate 201 using a known method. As a new technique, an indium oxide film 190 is formed thereon, and a silicon oxide film 180 is further formed thereon. The indium oxide film 190 is provided for the purpose of reducing the resistance of the N-type semiconductor layer and for the purpose of end point management during semiconductor etching. The silicon oxide film 180 is provided for bonding to the silicon substrate. It is also possible to perform CMP (Chemical Mechanical Polishing) as pre-bonding processing. However, in the configuration of this example, since the base of the silicon oxide film is all flat and the silicon oxide film is also a flat film, CMP processing is not necessarily required. FIG. 10B shows a silicon substrate 170 to be a substrate of the light emitting element later. As shown in FIG. 10C, the sapphire substrate on which the semiconductor layer, the indium oxide film, and the silicon oxide film are formed and the silicon substrate 170 are bonded together. Thereafter, as shown in FIG. 10 (d), the sapphire substrate 201 is lifted off and removed. In the state shown in FIG. 10C, since the metal and the organic substance are not included, the temperature restriction is eased, and the sapphire can be easily lifted off. In the state shown in FIG. 10D, the silicon substrate 170 becomes a substrate for a light emitting element.
 図11は、光マイクロセルの製造工程の例を表わす断面図である。図11(a)は、図10(d)に示した基板上の表面にフォトレジスト260のパターンを形成した状態を表している。図11(b)は、P型半導体層240、活性層230及びN型半導体層220を、テーパエッチング技術で傾斜面(テーパ部)250を設けるようにウエットエッチングした状態を示している。その後フォトレジスト260を除去し、導電反射膜270を全面に積層する。図11(c)は、フォトリソグラフィ技術により、その導電反射膜270がP型半導体層240部の上面に残るように加工した状態を示している。図11(d)は、その状態からシリコン酸化膜280を全面に形成した状態を示している。図11(e)は、その状態にフォトレジストを設け、電極部281及び282をテーパエッチング加工した後、フォトレジストを除去した状態を示している。電極部282の側面は、テーパエッチングにより傾斜面になっている。図11(f)は、全面に金属薄膜を積層した後、フォトリソグラフィ技術を用いて上記電極部にP型電極290及びN型電極291を形成した状態を示している。以上によって光マイクロセルが形成されている。 FIG. 11 is a cross-sectional view showing an example of a manufacturing process of an optical microcell. FIG. 11A shows a state in which a pattern of a photoresist 260 is formed on the surface of the substrate shown in FIG. FIG. 11B shows a state in which the P-type semiconductor layer 240, the active layer 230, and the N-type semiconductor layer 220 are wet-etched so as to provide an inclined surface (tapered portion) 250 by a taper etching technique. Thereafter, the photoresist 260 is removed, and a conductive reflective film 270 is laminated on the entire surface. FIG. 11C shows a state in which the conductive reflective film 270 is processed so as to remain on the upper surface of the P-type semiconductor layer 240 by photolithography. FIG. 11D shows a state in which the silicon oxide film 280 is formed on the entire surface from that state. FIG. 11E shows a state in which a photoresist is provided in this state, the electrode portions 281 and 282 are subjected to taper etching, and then the photoresist is removed. The side surface of the electrode part 282 is inclined by taper etching. FIG. 11F shows a state in which a metal thin film is laminated on the entire surface, and then a P-type electrode 290 and an N-type electrode 291 are formed on the electrode portion by using a photolithography technique. Thus, an optical microcell is formed.
 図12は、上記のように形成された光マイクロセルの構造を説明する図である。図12(a)は、上記光マイクロセルの断面を表わしている。テーパエッチングにより側面が傾斜して形成された半導体層が発光セル80となる。その半導体層の傾斜部を覆うシリコン酸化膜280上に形成されたN型電極291の金属膜が鏡面となり、マイクロミラー71が構成されている。このマイクロミラー71により発光セル80の全周が囲まれ、光マイクロセルが構成される。図12(a)において、集光方向zは下方となる。この状態ではシリコン基板170が光を通さないが、シリコン基板が除去された後に、光マイクロセルの活性層230で発生する光が進む方向をp、q及びrで表わしている。活性層230から集光方向zに向かう光はそのまま放出され(p)、集光方向zとは反対方向に向かう光は、導電反射膜270により反射されて集光方向zに放出される(q)。活性層230に沿った方向の光は、マイクロミラー71により反射されて集光方向に放出される(r)。図12(b)は、上記光マイクロセルが並べて形成されている平面図である。図中にP型電極290及びN型電極291の領域が示されている。また、各発光セルの活性層230の領域は境界231で示されている。これらの境界は、電界が集中しないように4隅が丸みを持つように形成されている。 FIG. 12 is a diagram for explaining the structure of the optical microcell formed as described above. FIG. 12A shows a cross section of the optical microcell. The semiconductor layer formed with the side surfaces inclined by the taper etching becomes the light emitting cell 80. The metal film of the N-type electrode 291 formed on the silicon oxide film 280 covering the inclined portion of the semiconductor layer becomes a mirror surface, and the micromirror 71 is configured. The micromirror 71 surrounds the entire circumference of the light emitting cell 80 to form an optical microcell. In FIG. 12A, the light collecting direction z is downward. In this state, although the silicon substrate 170 does not transmit light, p, q, and r indicate directions in which light generated in the active layer 230 of the optical microcell travels after the silicon substrate is removed. Light directed from the active layer 230 in the light collecting direction z is emitted as it is (p), and light directed in the direction opposite to the light collecting direction z is reflected by the conductive reflection film 270 and emitted in the light collecting direction z (q ). The light in the direction along the active layer 230 is reflected by the micromirror 71 and emitted in the light collecting direction (r). FIG. 12B is a plan view in which the optical microcells are formed side by side. In the drawing, regions of the P-type electrode 290 and the N-type electrode 291 are shown. The region of the active layer 230 of each light emitting cell is indicated by a boundary 231. These boundaries are formed with rounded corners so that the electric field is not concentrated.
 図13は発光素子全体を説明するための図である。図13(a)は発光素子の斜視図であり、(b)は断面図である。分かり易くするために、ウエーハ状態で形成されている発光素子のうちの1つを描いた図である。1つの発光素子は、素子基板上に1又は2以上の区画された発光部(発光セル)80を備えて構成される。1つの発光部は、図12に示したように、1つずつ区画して形成された半導体層からなる。そして1つの発光セルの側面をマイクロミラーによって囲むことにより、1つの光マイクロセルが構成されている。すなわち、1つの発光素子は1又は2以上の光マイクロセルから構成される。図13に示した発光素子は、横方向4×奥行方向2の計8つの光マイクロセルを備えている。この発光素子は、シリコン基板170の上に、複数の発光セル80とマイクロミラー71を備えた光マイクロセル層300が形成されており、その上に導電反射膜層275が形成されている。1つの発光セル80とその全周囲に設けられたマイクロミラー71とにより、1つの光マイクロセルが構成されている。各発光セル80のP型電極及びN型電極に接続される電源は配線層310において配線され、フリップチップ電極321及び322を具備するフリップチップ電極層320から各電源が供給される。フリップチップ電極は図11に示した工程には示されていないが、ウエーハ状態で金の薄膜を形成してメッキにより厚くし、エッチング加工することにより形成することができる。また、ウエーハ状態でスタッドバンプ手法により金バンプを設け、その後に平坦化して形成してもよい。また、配線層310とフリップチップ電極層320との間には薄膜配線層315が設けられている。薄膜配線層315は、図8で言及した給電選択部が設けられている。図13(a)及び(b)に示すシリコン基板170の集光方向側の面には、マイクロキャビティを形成するためのシリコン酸化膜185が形成されている。また、シリコン酸化膜180は、シリコンをKOH水溶液等によりエッチングする際のストッパーとなる。図13(c)は、エッチングにより形成されたシリコンの側壁面411に囲まれたキャビティ部に蛍光体330を充填し、更にマイクロ凸レンズ520を貼り合わせた状態を示している。図中に示す光の進行方向については前述のとおりである。図13(c)の状態までをウエーハ状態で形成した後、個別の発光素子として切り分ければ、ベアチップ実装可能な発光ダイオード34が完成する。 FIG. 13 is a diagram for explaining the entire light emitting element. FIG. 13A is a perspective view of the light emitting element, and FIG. 13B is a cross-sectional view. For the sake of clarity, it is a diagram depicting one of the light emitting elements formed in a wafer state. One light emitting element is configured to include one or two or more divided light emitting portions (light emitting cells) 80 on an element substrate. As shown in FIG. 12, one light emitting portion is formed of a semiconductor layer that is divided and formed one by one. One optical microcell is configured by surrounding the side surface of one light emitting cell with a micromirror. That is, one light emitting element is composed of one or more optical microcells. The light-emitting element shown in FIG. 13 includes a total of eight optical microcells of 4 × 2 in the horizontal direction. In this light emitting element, an optical microcell layer 300 including a plurality of light emitting cells 80 and micromirrors 71 is formed on a silicon substrate 170, and a conductive reflective film layer 275 is formed thereon. One light microcell is constituted by one light emitting cell 80 and the micromirror 71 provided on the entire periphery thereof. A power source connected to the P-type electrode and the N-type electrode of each light emitting cell 80 is wired in the wiring layer 310, and each power source is supplied from the flip chip electrode layer 320 including the flip chip electrodes 321 and 322. Although the flip-chip electrode is not shown in the process shown in FIG. 11, it can be formed by forming a gold thin film in a wafer state, thickening it by plating, and etching it. Alternatively, gold bumps may be provided by a stud bump method in the wafer state and then flattened. A thin film wiring layer 315 is provided between the wiring layer 310 and the flip chip electrode layer 320. The thin film wiring layer 315 is provided with the power supply selection unit referred to in FIG. A silicon oxide film 185 for forming a microcavity is formed on the condensing direction side surface of the silicon substrate 170 shown in FIGS. In addition, the silicon oxide film 180 serves as a stopper when etching silicon with a KOH aqueous solution or the like. FIG. 13C shows a state where the cavity 330 surrounded by the side wall surface 411 of silicon formed by etching is filled with the phosphor 330 and the micro convex lens 520 is further bonded. The traveling direction of light shown in the figure is as described above. After forming the state up to the state of FIG. 13C in the wafer state and separating it as individual light emitting elements, a light emitting diode 34 that can be mounted on a bare chip is completed.
 図14は、図11の工程により作成した発光素子を表す図であり、この発光素子19は後述するチップサイズパッケージに実装される。断面を表した図14(a)において、p、q及びrは発光層からの光の方向を示しているが、この状態ではシリコン基板170が光を通さないため、参考までに示したものである。後の工程でシリコン基板170をエッチングすることによりマイクロキャビティが形成され、光が通過するようにされる。図14(b)は発光素子19の斜視図である。本例では、8つの発光セルに給電するための素子電極としてフリップチップ電極321及び322が計6個具備されており、このフリップチップ電極は後にパッケージ用のパッケージ基板と接続される。 FIG. 14 is a diagram showing a light emitting device created by the process of FIG. 11, and this light emitting device 19 is mounted on a chip size package which will be described later. In FIG. 14A showing the cross section, p, q, and r indicate the directions of light from the light emitting layer. In this state, the silicon substrate 170 does not transmit light, and is shown for reference. is there. By etching the silicon substrate 170 in a later step, a microcavity is formed so that light can pass therethrough. FIG. 14B is a perspective view of the light emitting element 19. In this example, a total of six flip chip electrodes 321 and 322 are provided as element electrodes for supplying power to eight light emitting cells, and these flip chip electrodes are connected to a package substrate for a package later.
 図15はサファイア基板200上に光マイクロセルを形成する手順を示す。図11に示した工程とほぼ同様である。図15(b)に示す半導体層のテーパエッチングにおいて、N+型半導体膜210を化合物半導体エッチングのストッパーとすることができる。 FIG. 15 shows a procedure for forming an optical microcell on the sapphire substrate 200. This is almost the same as the process shown in FIG. In the taper etching of the semiconductor layer shown in FIG. 15B, the N + type semiconductor film 210 can be used as a stopper for the compound semiconductor etching.
 図16は、図15の工程により作成された発光素子18の断面図及び斜視図である。素子基板にサファイア基板を用いていることを除き、図14に示した発光素子とほぼ同様である。 FIG. 16 is a cross-sectional view and a perspective view of the light-emitting element 18 created by the process of FIG. Except that a sapphire substrate is used as the element substrate, it is almost the same as the light emitting element shown in FIG.
 図17は、前記発光素子18(図16)、前記発光素子19(図14)等を用いるチップサイズパッケージの基本構成を説明するための断面図である。図17(c)に示すサファイア基板を用いた発光素子18と、図17(e)に示すパッケージ基板40とが、図17(d)に示すインターポーザ350を介して貼り合わされる。それにより、発光素子18のフリップチップ電極320(前記321及び322)と、パッケージ基板40に設けられた内部電極61とが接し、電気的に接続される。その後に、発光素子18のサファイア基板をリフトオフ手法により除去し、代わりにマイクロキャビティの母材となるシリコン基板173(図17(b1))を透明接着剤480で貼り合わせる。発光素子として、シリコン基板を用いた発光素子19を用いる場合には、上記リフトオフ工程とシリコン基板173の貼り合わせは不要である。図17(b1)のシリコン基板173にはシリコン酸化膜180が形成されているが、発光素子19のシリコン基板170上には既にシリコン酸化膜180が形成されているため、シリコン基板173と同じ構成となる(以下、マイクロキャビティ用の「シリコン基板170又は173」をまとめて「シリコン基板173」という。)。いずれの発光素子を用いた場合にも、これ以降の工程は共通となる。この段階では、発光素子18を用いた場合には、パッケージ基板40と、サファイア基板が除去された発光素子と、シリコン基板173とが貼り合わされた状態である。また、発光素子19を用いた場合には、パッケージ基板40と、シリコン基板170上に形成された発光素子とが貼り合わされた状態である。いずれの場合も、この状態では、化合物半導体から集光方向にはシリコン酸化膜180及びシリコン基板173が存在する。図17(b1)に示すシリコン酸化膜185は、シリコン基板173をエッチングする為のマスクとなる部分である。シリコンのエッチングをKOH水溶液中で行うときには、パッケージ基板側を保護するために、ウエーハより大きなパッケージ基板にワックス等を塗布して耐アルカリ性とし、KOH液がエッチングすべきシリコン面だけに触れるようにする。以上は、シリコン基板173を用いてマイクロキャビティを形成する例を説明したが、マイクロキャビティとして図6で説明した銅のスタッドフレーム540を用いてもよい。図17(b2)に示す銅スタッドフレーム540を、サファイア基板がリフトオフにより除去された化合物半導体面に、透明接着剤480を用いて貼り合わせる。銅のエッチングを塩酸等で行うときには、パッケージ基板側を保護するために、ウエーハより大きなパッケージ基板にワックス等を塗布して耐酸性とし、塩酸等がエッチングすべき銅フレーム面だけに触れるようにする。これらのエッチング終了後にワックス等を取り除き、更に、ウエーハ状態で図17(a)に示すマイクロ凸レンズ520を透明接着剤480により貼り合わせる。これによりチップサイズパッケージがウエーハ状態で完成され、電気的検査及び光学的検査を行うことができる。そして発光素子ごとに分離すれば、個々の発光ダイオードが得られる。
 前記のとおり、マイクロキャビティ及び蛍光体を用いないで発光ダイオードを構成することもできる。その場合、素子基板が除去された発光素子上にマイクロ凸レンズを貼り合わせればよい。また、マイクロ凸レンズに代わり、凹レンズや透明プラスチック板等を用いることができる。また、パッケージ基板の外部電極60をパッケージ基板P電極331及びN電極332として形成し、図8において説明した給電選択部と同様な配線パターンにより給電選択部を設けておくことができる。
 また、マイクロキャビティを使用しないで、蛍光体が実装されてもよい。この場合、図17(b3)に示すような蛍光体330を、上記のマイクロキャビティの代わりに発光素子の発光面上に貼り付ければよい。この蛍光体の外周は、発光素子の素子基板の外周と同一サイズとすることができる。発光面上に載置した蛍光体の上に、マイクロ凸レンズ等透明部材を備えることができる。
FIG. 17 is a cross-sectional view for explaining a basic configuration of a chip size package using the light emitting element 18 (FIG. 16), the light emitting element 19 (FIG. 14), and the like. The light emitting element 18 using the sapphire substrate shown in FIG. 17C and the package substrate 40 shown in FIG. 17E are bonded together via an interposer 350 shown in FIG. As a result, the flip chip electrodes 320 (321 and 322) of the light emitting element 18 and the internal electrodes 61 provided on the package substrate 40 are in contact with each other and are electrically connected. Thereafter, the sapphire substrate of the light emitting element 18 is removed by a lift-off method, and a silicon substrate 173 (FIG. 17B1) serving as a base material for the microcavity is bonded with a transparent adhesive 480 instead. When the light emitting element 19 using a silicon substrate is used as the light emitting element, the lift-off process and the bonding of the silicon substrate 173 are not necessary. Although a silicon oxide film 180 is formed on the silicon substrate 173 in FIG. 17B1, since the silicon oxide film 180 is already formed on the silicon substrate 170 of the light emitting element 19, the same configuration as the silicon substrate 173 is formed. (Hereinafter, “ silicon substrate 170 or 173” for the microcavity is collectively referred to as “silicon substrate 173”). Regardless of which light emitting element is used, the subsequent steps are common. At this stage, when the light emitting element 18 is used, the package substrate 40, the light emitting element from which the sapphire substrate is removed, and the silicon substrate 173 are bonded together. When the light emitting element 19 is used, the package substrate 40 and the light emitting element formed on the silicon substrate 170 are bonded to each other. In any case, in this state, the silicon oxide film 180 and the silicon substrate 173 exist in the light collecting direction from the compound semiconductor. A silicon oxide film 185 shown in FIG. 17B1 is a portion serving as a mask for etching the silicon substrate 173. When silicon etching is performed in a KOH aqueous solution, in order to protect the package substrate side, wax or the like is applied to the package substrate larger than the wafer to make it alkali resistant so that the KOH solution touches only the silicon surface to be etched. . The example in which the microcavity is formed using the silicon substrate 173 has been described above, but the copper stud frame 540 described with reference to FIG. 6 may be used as the microcavity. A copper stud frame 540 shown in FIG. 17B2 is bonded to the compound semiconductor surface from which the sapphire substrate has been removed by lift-off using a transparent adhesive 480. When etching copper with hydrochloric acid, etc., to protect the package substrate side, apply wax etc. to the package substrate larger than the wafer to make it acid resistant, so that hydrochloric acid etc. touches only the copper frame surface to be etched. . After completion of these etchings, the wax or the like is removed, and a micro convex lens 520 shown in FIG. 17A is bonded with a transparent adhesive 480 in the wafer state. Thereby, the chip size package is completed in the wafer state, and electrical inspection and optical inspection can be performed. If each light emitting element is separated, individual light emitting diodes can be obtained.
As described above, a light emitting diode can be configured without using a microcavity and a phosphor. In that case, a micro convex lens may be bonded to the light emitting element from which the element substrate is removed. Moreover, a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens. Further, the external electrodes 60 of the package substrate can be formed as the package substrate P electrode 331 and the N electrode 332, and the power supply selection unit can be provided with the same wiring pattern as the power supply selection unit described in FIG.
Further, the phosphor may be mounted without using the microcavity. In this case, a phosphor 330 as shown in FIG. 17 (b3) may be attached on the light emitting surface of the light emitting element instead of the microcavity. The outer periphery of the phosphor can be the same size as the outer periphery of the element substrate of the light emitting element. A transparent member such as a micro convex lens can be provided on the phosphor placed on the light emitting surface.
 図17に示した構成において、発光素子、パッケージ基板及び接合材(インターポーザ)の種類や材料は、適宜に選択して組み合わせることが可能である。発光素子の基板として、サファイア等の透明基板を用いてもよいし、シリコン等の光を通さない基板を用いることもできる。1つの発光素子に備えられる発光セルの数は、1つでもよいし2以上でもよい。また、各発光セルの周囲にマイクロミラーを備えて光マイクロセルが構成されてもよいし、マイクロミラーを備えないで構成されてもよい。パッケージ基板としては、熱可塑性プリント基板、非直線性抵抗特性をもつ基板(バリスタ基板)、ガラスエポキシプリント基板、セラミックス基板、金属基板(金属ベース基板)等を選択することができる。接合材(インターポーザ)としては、使用するパッケージ基板に応じて、熱可塑性材料、異方性導電接着剤等を用いることができる。例えば、熱可塑性プリント基板や金属基板を用いる場合には、熱可塑性材料を接合材に使用することができる。また、ガラスエポキシプリント基板を用いる場合には、異方性導電接着剤を接合材に使用することができる。なお、発光素子、パッケージ基板及び接合材の材料、組み合わせ等は、ここに挙げた例に限定されない。
 熱可塑性プリント基板と発光素子とは、熱可塑性のインターポーザを用いて貼り合わせることができる。この場合、約300℃で貼り合わせるため、発光素子のフリップチップ電極を構成する金バンプと、パッケージ基板の内部電極の銅とが共晶結合し、理想的な金属接続が得られる。熱可塑性プリント基板の代わりに金属基板を用いる場合も同様である。特にアルミニウムや銅を素材に含む基板は熱伝導性に優れるため、高輝度の白色発光ダイオード等、高い放熱性が求められるチップサイズパッケージに適する。パッケージ基板として、普及しているガラスエポキシ基板を用いることもできる。但し、ガラスエポキシ基板はその耐熱温度が約200℃以下と低いため、前記熱可塑性のインターポーザを使うことができない。そこで、ウエーハ状態の発光素子とガラスエポキシ基板とを、異方性導電接着剤を介して貼り合わせる。これにより約100℃で貼り合わせを行うことができる。電極間の接続は、直径10μm程度の金粒子により行われる。この接合材料は、液晶におけるガラス基板と回路基板との接続に用いられているヒートシール材料と同じである。この電気接合は、金粒子を介するため0.1Ω程度の接触抵抗となり、大電流が必要な用途には適さないが、駆動電流が数十mA程度である用途(例えば、面発光の液晶バックライト等)では十分に用いることができる。この構成の特徴は、技術的には既存材料の組み合わせにより本チップサイズパッケージを形成できる点にある。また、発光素子の基板としてシリコン基板を用いる場合には、シリコンはKOH水溶液中で100℃以下と低い温度で除去できるため、耐熱性に劣るガラスエポキシ基板を用いても本チップサイズパッケージを容易に形成することができる。
In the configuration shown in FIG. 17, the types and materials of the light emitting element, the package substrate, and the bonding material (interposer) can be appropriately selected and combined. As the substrate of the light emitting element, a transparent substrate such as sapphire may be used, or a substrate such as silicon that does not transmit light may be used. The number of light emitting cells provided in one light emitting element may be one or two or more. In addition, an optical microcell may be configured with a micromirror around each light emitting cell, or may be configured without a micromirror. As the package substrate, a thermoplastic printed substrate, a substrate having a non-linear resistance characteristic (varistor substrate), a glass epoxy printed substrate, a ceramic substrate, a metal substrate (metal base substrate), or the like can be selected. As the bonding material (interposer), a thermoplastic material, an anisotropic conductive adhesive, or the like can be used depending on the package substrate to be used. For example, when a thermoplastic printed board or a metal board is used, a thermoplastic material can be used for the bonding material. Moreover, when using a glass epoxy printed circuit board, an anisotropic conductive adhesive can be used for a bonding material. Note that materials, combinations, and the like of the light-emitting element, the package substrate, and the bonding material are not limited to the examples given here.
The thermoplastic printed circuit board and the light emitting element can be bonded together using a thermoplastic interposer. In this case, since the bonding is performed at about 300 ° C., the gold bumps constituting the flip chip electrode of the light emitting element and the copper of the internal electrode of the package substrate are eutectic bonded, and an ideal metal connection is obtained. The same applies to the case where a metal substrate is used instead of the thermoplastic printed circuit board. In particular, a substrate containing aluminum or copper as a material is excellent in thermal conductivity, and thus is suitable for a chip size package that requires high heat dissipation, such as a high-intensity white light emitting diode. As the package substrate, a widely used glass epoxy substrate can be used. However, since the glass epoxy substrate has a low heat resistant temperature of about 200 ° C. or less, the thermoplastic interposer cannot be used. Therefore, the light emitting element in the wafer state and the glass epoxy substrate are bonded together with an anisotropic conductive adhesive. Thereby, bonding can be performed at about 100 degreeC. The connection between the electrodes is made by gold particles having a diameter of about 10 μm. This bonding material is the same as the heat seal material used for connecting the glass substrate and the circuit board in the liquid crystal. Since this electrical junction is caused by gold particles, it has a contact resistance of about 0.1Ω and is not suitable for applications requiring a large current, but is used for applications where the drive current is about several tens of mA (for example, surface emitting liquid crystal backlights). Etc.) can be used sufficiently. The feature of this configuration is technically that the chip size package can be formed by a combination of existing materials. In addition, when a silicon substrate is used as the substrate of the light emitting element, silicon can be removed in a KOH aqueous solution at a temperature as low as 100 ° C. or lower. Can be formed.
 図18は、図17に示した構成で、マイクロキャビティを形成するためのシリコンのエッチング工程を説明するための断面図である。図18(a)は、前記発光素子18とパッケージ基板40とがインターポーザ350により貼り合わされた状態を示す。図18(b)は、その後サファイア基板200が除去された状態を示す。図18(c)は、その後、片方の全面にシリコン酸化膜180が形成されたシリコン基板173を貼り合わせた状態を示す。図18(d1)は、次いでシリコンをエッチングするパターンに合わせてフォトレジスト265を形成した状態を示す。発光素子にシリコン基板170を用いている場合には、パッケージ基板との貼り合わせの前に、シリコン酸化膜185でこのマスクパターンを形成しておく方が便利である。図において、シリコンのエッチング終止面410が示されている。図18(e)は、シリコンのエッチング終了後、マスクの機能を果たしたフォトレジスト又はシリコン酸化膜を除去した状態を示している。このように、シリコンを用いて、傾斜した内側壁面411を備えたマイクロキャビティ175を形成することができる。前記のとおり、マイクロキャビティとして銅スタッドフレーム540を用いることも可能である。図18(d2)は、図18(b)の状態にスタッドフレーム540を透明接着剤480で貼り合わせた状態を示している。この状態から銅を塩酸などで等方エッチングすることによりマイクロキャビティ175を形成することができる。銅の傾斜した内側壁面に銀メッキを施すことにより反射率の高い側壁面を容易に形成できる。 FIG. 18 is a cross-sectional view for explaining a silicon etching process for forming a microcavity with the configuration shown in FIG. FIG. 18A shows a state in which the light emitting element 18 and the package substrate 40 are bonded together by an interposer 350. FIG. 18B shows a state where the sapphire substrate 200 is removed thereafter. FIG. 18C shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on one whole surface is bonded. FIG. 18D1 shows a state in which a photoresist 265 is formed in accordance with a pattern for etching silicon. In the case where the silicon substrate 170 is used for the light emitting element, it is more convenient to form this mask pattern with the silicon oxide film 185 before bonding to the package substrate. In the figure, a silicon etch stop 410 is shown. FIG. 18E shows a state where the photoresist or silicon oxide film that has functioned as a mask is removed after the etching of silicon is completed. Thus, the microcavity 175 provided with the inclined inner wall surface 411 can be formed using silicon. As described above, the copper stud frame 540 can be used as the microcavity. FIG. 18 (d2) shows a state where the stud frame 540 is bonded to the state of FIG. 18 (b) with a transparent adhesive 480. From this state, the microcavity 175 can be formed by isotropically etching copper with hydrochloric acid or the like. A side wall surface having high reflectivity can be easily formed by silver plating on the inner wall surface inclined by copper.
 図4、5及び17に示したマイクロ凸レンズ520は、透明樹脂材料を使用し、ウエーハ上に配列された発光素子に対応した位置に適宜の凸レンズ形状となるように樹脂成型することにより、ウエーハと同じサイズで作ることができる。透明部材を凸レンズとする代わりに凹レンズとしたり、透明プラスチック板としたりする場合も同様である。 The micro-convex lens 520 shown in FIGS. 4, 5 and 17 uses a transparent resin material and is molded by resin molding so as to have an appropriate convex lens shape at a position corresponding to the light-emitting elements arranged on the wafer. Can be made with the same size. The same applies when the transparent member is a concave lens instead of a convex lens or a transparent plastic plate.
 以上の様にして、図4及び5により説明した基本概念を実現するための基本的要素であるマイクロキャビティの形成、発光素子の発光面上又はマイクロキャビティ上への透明部材の貼り合わせ、マイクロミラーの形成、チップサイズパッケージの構造、及び複数の発光セルによる輝度の調整手段等が実現される。 As described above, formation of a microcavity which is a basic element for realizing the basic concept described with reference to FIGS. 4 and 5, bonding of a transparent member on the light emitting surface of the light emitting element or on the microcavity, a micromirror , The structure of the chip size package, and the brightness adjusting means using a plurality of light emitting cells.
 本チップサイズパッケージにより、完成品の持ち運びはウエーハ状態若しくはパッケージ基板が分離されていない状態、又はエキスパンションシートに貼った状態で行うことができ、また、マザーボードへの実装も同様な状態で行うことができる。これにより、静電気が極めて発生し難い状態でマザーボードへの実装までを行うことができるため、パッケージ内に静電気対策用の素子は必ずしも必要とされない。マザーボードに予め双方向ツェナーダイオードのような保護素子を実装しておけばよい。特に、液晶のバックライト用途の様に面発光で多数の発光ダイオードをマザー基板に実装するような用途ではこの手法がコスト面でもメリットが大きい。静電気対策が必要な場合には、チップサイズパッケージの基板にバリスタ基板を用いることにより、静電気吸収機能をバリスタ基板に持たせることができる。これにより、静電気に強いチップサイズパッケージとすることができる。 With this chip size package, the finished product can be carried in the wafer state, the package substrate is not separated, or attached to the expansion sheet, and can also be mounted on the motherboard in the same state. it can. As a result, it is possible to perform mounting on the motherboard in a state where static electricity is hardly generated, and thus an element for preventing static electricity is not necessarily required in the package. A protective element such as a bidirectional Zener diode may be mounted on the motherboard in advance. In particular, this method has a great merit in terms of cost in applications where a large number of light emitting diodes are mounted on a mother substrate by surface emission, such as in liquid crystal backlight applications. When countermeasures against static electricity are required, a varistor substrate can be provided with an electrostatic absorption function by using a varistor substrate as a substrate of a chip size package. Thereby, it can be set as the chip size package strong against static electricity.
 図19に、本発明の実施例として、チップサイズパッケージによる基本構成を示す。図19(e)に示す発光ダイオード39は、図18で説明した工程により、シリコン基板170を用いた発光素子19(図19(b))とパッケージ基板40(図19(d))とが貼り合わされ、その後シリコン基板170にマイクロキャビティが形成され、更にマイクロ凸レンズ520(図19(a))が貼り合わされて構成されている。発光素子19は、複数の光マイクロセルが形成された光マイクロセル層300を備えている。上記で、発光素子19とパッケージ基板40とは、インターポーザ350(図19(c))を挟んで、真空中で約300℃の温度に約30分間保つことにより貼り合わされる。その後、シリコン基板170をエッチング加工してマイクロキャビティ175が形成される。シリコンのエッチング手順については、図18により説明したとおりである。この後、マイクロキャビティ175の部分に蛍光体330を充填し、更にマイクロ凸レンズ520を貼り合わせる。マイクロ凸レンズは、近年普及した樹脂レンズをウエーハサイズで加工することにより形成できる。このように発光ダイオード39を形成する工程は、ウエーハ状態にて行うことができる。図19(f)はパッケージ基板40を下面視した図である。この下面には、外部から給電を受けるP電極331及びN電極332と、所定の光マイクロセルのP電極に接続されている電極(P0、P1、P2、P3、P4)が設けられている。P電極331(P0)と上記電極(P1、P2、P3、P4)との間の配線は、各光マイクロセルに供給する電源を選択的に接続又は切断するための給電選択部である。発光素子を所望の輝度とするように、どの光マイクロセルに給電するかを選択することができる。例えば、発光素子の輝度に応じて、電源を供給しない光マイクロセルに対しては、切断ライン445において該当する配線をレーザ等により切断する。この給電選択部により、図8において説明した輝度の調整と同様の輝度の調整が可能になる。これらの加工工程の後、発光素子ごとに分離することにより発光ダイオード39が得られる。マイクロキャビティ175は、前記のとおり銅のスタッドフレームを用いて形成されてもよい。すなわち、発光素子から素子基板(シリコン基板170又はサファイア基板200)を除去した後、露出した化合物半導体面に図18(d2)に示したようにスタッドフレーム540を透明接着剤により貼り合わせる。そして、スタッドフレームの底面部が無くなるまでエッチングすることによりマイクロキャビティ175の形状を作ることができ、図19(e)と同様の構造を得ることができる。また、マイクロキャビティ及び蛍光体を備えない発光ダイオードの構成とすることができる。その場合には、発光素子のシリコン基板をエッチングにより除去し、その除去した面にマイクロ凸レンズを貼るようにすればよい。また、マイクロ凸レンズの代わりに、凹レンズや透明プラスチック板等を用いることができる。 FIG. 19 shows a basic configuration using a chip size package as an embodiment of the present invention. In the light emitting diode 39 shown in FIG. 19 (e), the light emitting element 19 (FIG. 19 (b)) using the silicon substrate 170 and the package substrate 40 (FIG. 19 (d)) are bonded by the process described in FIG. Thereafter, a microcavity is formed in the silicon substrate 170, and a micro convex lens 520 (FIG. 19A) is further bonded thereto. The light emitting element 19 includes an optical microcell layer 300 in which a plurality of optical microcells are formed. As described above, the light emitting element 19 and the package substrate 40 are bonded together by holding the interposer 350 (FIG. 19C) at a temperature of about 300 ° C. for about 30 minutes in a vacuum. Thereafter, the microcavity 175 is formed by etching the silicon substrate 170. The silicon etching procedure is as described with reference to FIG. Thereafter, the phosphor 330 is filled in the microcavity 175, and the micro convex lens 520 is further bonded. The micro-convex lens can be formed by processing a resin lens that has become popular in recent years with a wafer size. Thus, the process of forming the light emitting diode 39 can be performed in a wafer state. FIG. 19F is a view of the package substrate 40 as viewed from below. On this lower surface, there are provided a P electrode 331 and an N electrode 332 that receive power from the outside, and electrodes (P0, P1, P2, P3, P4) connected to the P electrode of a predetermined optical microcell. The wiring between the P electrode 331 (P0) and the electrodes (P1, P2, P3, P4) is a power supply selection unit for selectively connecting or disconnecting the power supplied to each optical microcell. It is possible to select which optical microcell is supplied with power so that the light emitting element has a desired luminance. For example, according to the luminance of the light emitting element, the corresponding wiring in the cutting line 445 is cut by a laser or the like for an optical microcell that does not supply power. With this power supply selection unit, it is possible to adjust the luminance similar to the luminance adjustment described in FIG. After these processing steps, the light emitting diode 39 is obtained by separating each light emitting element. The microcavity 175 may be formed using a copper stud frame as described above. That is, after removing the element substrate (silicon substrate 170 or sapphire substrate 200) from the light emitting element, the stud frame 540 is bonded to the exposed compound semiconductor surface with a transparent adhesive as shown in FIG. 18 (d2). Then, the shape of the microcavity 175 can be made by etching until the bottom portion of the stud frame disappears, and a structure similar to that shown in FIG. Moreover, it can be set as the structure of the light emitting diode which does not have a microcavity and fluorescent substance. In that case, the silicon substrate of the light-emitting element may be removed by etching, and a micro convex lens may be attached to the removed surface. Moreover, a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens.
 本発明による発光ダイオードは、チップサイズパッケージとすることなく、発光素子をベアチップとして用いるように構成することもできる。その場合、上記の輝度の調整は、図8において説明したように、薄膜配線層315に設けた給電選択部により行うことができる。 The light-emitting diode according to the present invention can be configured to use a light-emitting element as a bare chip without using a chip-size package. In that case, the luminance adjustment can be performed by the power supply selection unit provided in the thin film wiring layer 315 as described in FIG.
 チップサイズパッケージに組み込む発光素子は、図19(b)に示したような光マイクロセルを備えるものに限られない。図20は、マイクロミラーを備えない複数の発光セルから構成される発光素子の例を示す。各発光セルは、化合物半導体層84によって構成されている。この場合にも、シリコン基板170により前記同様にマイクロキャビティを形成することができる。エッチング用のマスクとしてシリコン酸化膜185が設けられ、キャビティの内側壁面となるエッチング終止面410の位置を決めている。 The light emitting element incorporated in the chip size package is not limited to the one having the optical microcell as shown in FIG. FIG. 20 illustrates an example of a light-emitting element including a plurality of light-emitting cells that do not include a micromirror. Each light emitting cell is composed of a compound semiconductor layer 84. Also in this case, the microcavity can be formed by the silicon substrate 170 as described above. A silicon oxide film 185 is provided as an etching mask to determine the position of the etching end surface 410 that becomes the inner wall surface of the cavity.
 この様にしてパッケージの大きさが発光ダイオードの大きさとなり、発光層の近傍のマイクロミラー71、マイクロキャビティの側壁411及びマイクロ凸レンズ520により光が集光され、効率のよい発光ダイオードが実現できる。シリコン基板の多くの部分がマイクロキャビティとして刳りぬかれているため、シリコンの熱膨張係数がパッケージ基板の熱膨張係数と異なっていても、マザーボードへの実装時に応力が緩和されるという効果も大きい。また、ウエーハ状態で輝度を計測し、必要に応じて、薄膜配線層315又はパッケージ基板40に設けられた給電選択部により、ウエーハレベルで各発光ダイオードの輝度のバラツキを低減できる。 In this manner, the size of the package becomes the size of the light emitting diode, and the light is condensed by the micro mirror 71 near the light emitting layer, the side wall 411 of the micro cavity, and the micro convex lens 520, thereby realizing an efficient light emitting diode. Since many portions of the silicon substrate are perforated as microcavities, even when the thermal expansion coefficient of silicon is different from the thermal expansion coefficient of the package substrate, the effect of relieving stress when mounted on the mother board is great. Further, the luminance is measured in the wafer state, and if necessary, the luminance variation of each light emitting diode can be reduced at the wafer level by the power supply selection unit provided on the thin film wiring layer 315 or the package substrate 40.
 図21に、本発明の別の実施例を示す。図21(f)に示す発光ダイオード38は、図18で説明した工程により、サファイア基板200を用いた発光素子18(図21(c))とパッケージ基板40(図21(e))とが貼り合わされ、その後サファイア基板200が除去され、更に、マイクロキャビティ175を形成したシリコン基板173(図21(b1))及びマイクロ凸レンズ520(図21(a))が貼り合わされて構成されている。発光素子18は、複数の光マイクロセルが形成された光マイクロセル層300を備えている。上記で、発光素子18とパッケージ基板40とは、インターポーザ350(図21(d))を挟んで、真空中で約300℃の温度に約30分間保つことにより密着される。サファイア基板除去後の発光素子18と、シリコン酸化膜180を片面に備えるシリコン基板173とは、透明接着剤を用いて貼り合わせることができる。シリコン基板173にマイクロキャビティ175を形成する手順は、図18により説明したとおりである。マイクロキャビティ175は、発光素子18と貼り合わせる前に形成してもよい。その後、マイクロキャビティ175の部分に蛍光体330を充填し、更にマイクロ凸レンズ520を貼り合わせる。銅のスタッドフレーム540(図21(b2))を用いてもマイクロキャビティを形成できること、マイクロ凸レンズは樹脂をウエーハサイズで加工することにより形成できること、発光ダイオード38を形成する工程はウエーハ状態にて行うことができること等は、前記発光ダイオード39の場合と同様である。また、図21(g)は、発光ダイオード39の場合と同様に、パッケージ基板40の下面に設けられている電極及び配線を表わす図である。この発光ダイオードにおいても、マイクロキャビティ及び蛍光体を備えない構成とすることができる。その場合には、発光素子のサファイア基板を除去した後、その除去した面にマイクロ凸レンズを貼るようにすればよい。また、マイクロ凸レンズの代わりに、凹レンズや透明プラスチック板等を用いることができる。 FIG. 21 shows another embodiment of the present invention. In the light emitting diode 38 shown in FIG. 21 (f), the light emitting element 18 (FIG. 21 (c)) using the sapphire substrate 200 and the package substrate 40 (FIG. 21 (e)) are attached by the process described in FIG. Thereafter, the sapphire substrate 200 is removed, and a silicon substrate 173 (FIG. 21B1) on which a microcavity 175 is formed and a micro convex lens 520 (FIG. 21A) are bonded together. The light emitting element 18 includes an optical microcell layer 300 in which a plurality of optical microcells are formed. In the above, the light emitting element 18 and the package substrate 40 are brought into close contact with each other by holding the interposer 350 (FIG. 21D) at a temperature of about 300 ° C. for about 30 minutes in a vacuum. The light emitting element 18 after removal of the sapphire substrate and the silicon substrate 173 provided with the silicon oxide film 180 on one side can be bonded together using a transparent adhesive. The procedure for forming the microcavity 175 in the silicon substrate 173 is as described with reference to FIG. The microcavity 175 may be formed before being bonded to the light emitting element 18. Thereafter, the phosphor 330 is filled in the microcavity 175, and the micro convex lens 520 is further bonded. A microcavity can be formed using a copper stud frame 540 (FIG. 21B2), a microconvex lens can be formed by processing a resin in a wafer size, and a process of forming the light emitting diode 38 is performed in a wafer state. The same can be said for the light emitting diode 39. FIG. 21G shows the electrodes and wirings provided on the lower surface of the package substrate 40 as in the case of the light emitting diode 39. This light emitting diode can also be configured without the microcavity and the phosphor. In that case, after removing the sapphire substrate of the light emitting element, a micro convex lens may be attached to the removed surface. Moreover, a concave lens, a transparent plastic plate, etc. can be used instead of a micro convex lens.
 図22は、本発明による発光ダイオードを構成することができる各種態様の発光素子の断面を示している。これらは、ベアチップで用いることができ、又はチップサイズパッケージに実装することができる。図22(a)はサファイア基板に1つの発光セルを設けた前記発光素子16、(b)はシリコン基板に1つの発光セルを設けた発光素子17を示す。また、図22(c)はサファイア基板に複数の光マイクロセルを設けた前記発光素子18、(d)はシリコン基板に複数の光マイクロセルを設けた前記発光素子19を示す。各図中p、q及びrは、発光層からの光の方向を示している。シリコン基板を用いた発光素子では、この状態ではシリコンが光を透過しないため光の方向は参考までに示されている。後の工程にてシリコンが除去された後に光は透過するようになる。上記4種類の発光素子において、発光ダイオードを構成するための基本概念は同じである。発光素子の態様は上記4種類に限定されない。例えば、図20に示したような、マイクロミラーを有しないで複数の発光セルを備えた発光素子が挙げられる。また、1つの光マイクロセルを設けた発光素子が挙げられる。 FIG. 22 shows cross sections of various types of light emitting elements that can constitute the light emitting diode according to the present invention. These can be used in bare chips or can be mounted in a chip size package. FIG. 22A shows the light emitting element 16 in which one light emitting cell is provided on a sapphire substrate, and FIG. 22B shows the light emitting element 17 in which one light emitting cell is provided on a silicon substrate. FIG. 22C shows the light emitting element 18 in which a plurality of optical microcells are provided on a sapphire substrate, and FIG. 22D shows the light emitting element 19 in which a plurality of optical microcells are provided on a silicon substrate. In each figure, p, q, and r indicate the direction of light from the light emitting layer. In a light-emitting element using a silicon substrate, the direction of light is shown for reference because silicon does not transmit light in this state. Light is transmitted after the silicon is removed in a later step. In the above four types of light emitting elements, the basic concept for constructing a light emitting diode is the same. The mode of the light emitting element is not limited to the above four types. For example, a light-emitting element including a plurality of light-emitting cells without having a micromirror as shown in FIG. Further, a light emitting element provided with one optical microcell can be given.
 図23は、前記発光素子19を例にとり、発光素子とパッケージ基板とをパッケージ基板に適合するインターポーザを用いて貼り合せることにより構成されるチップサイズパッケージの断面を示す。パッケージ基板として、熱可塑性プリント基板、金属基板、ガラスエポキシプリント基板等を使用することができる。図23(a)は発光素子19と熱可塑性プリント基板41とを熱可塑性インターポーザ42により貼り合わせた構成、(b)は発光素子19と金属基板43とを熱可塑性インターポーザ42により貼り合わせた構成、(c)は発光素子19とガラスエポキシプリント基板45とを異方性導電接着剤370により貼り合わせた構成である。いずれも、シリコン基板170側が集光方向であり、パッケージ基板側がチップサイズパッケージの電極側である。構造上の重要点は、発光する光をできるだけ多く集光方向へ取り出すこと、パッケージ基板の内部電極61とフリップチップ電極321等との電気的接続が確実であること、発光素子の表面とパッケージ基板の表面との密着性を確保して熱可塑性インポーザ42や異方性導電接着剤370が湿気や異物などに対する保護機能を果たすこと、である。 FIG. 23 shows a cross-section of a chip size package configured by bonding the light emitting element and the package substrate using an interposer suitable for the package substrate, taking the light emitting element 19 as an example. As the package substrate, a thermoplastic printed circuit board, a metal substrate, a glass epoxy printed circuit board, or the like can be used. FIG. 23A shows a configuration in which the light emitting element 19 and the thermoplastic printed circuit board 41 are bonded together by the thermoplastic interposer 42, and FIG. 23B shows a configuration in which the light emitting element 19 and the metal substrate 43 are bonded together by the thermoplastic interposer 42. (C) is a configuration in which the light emitting element 19 and the glass epoxy printed board 45 are bonded together by an anisotropic conductive adhesive 370. In either case, the silicon substrate 170 side is the light collecting direction, and the package substrate side is the electrode side of the chip size package. The important points in the structure are to extract as much light as possible in the light collecting direction, to ensure the electrical connection between the internal electrode 61 of the package substrate and the flip chip electrode 321, etc., the surface of the light emitting element and the package substrate This ensures that the adhesiveness with the surface of the resin and the thermoplastic impose 42 and the anisotropic conductive adhesive 370 serve to protect against moisture and foreign matter.
 図24は、前記発光素子18及び熱可塑性プリント基板を用いる発光ダイオードの製造手順の例を示す。図24(a)は、発光素子18と熱可塑性プリント基板41とが熱可塑性のインターポーザ42により貼り合わされた状態の断面を示している。図24(b)は、その状態から、サファイア基板200をレーザリフトオフ手法にて除去して露出した化合物半導体面に、貼り合せ側の面にシリコン酸化膜180を形成したシリコン基板173を、透明接着剤480で貼り合わせた状態を示している。素子基板としてシリコン基板を用いた発光素子の場合には、この状態から工程が開始される。図24(b)のシリコン基板173にはシリコン酸化膜180が形成されているが、素子基板としてシリコン基板170を用いた発光素子の場合には、シリコン基板170上に既にシリコン酸化膜180が形成されているため、シリコン基板173と同じ構成となる(以下、マイクロキャビティ用の「シリコン基板170又は173」をまとめて「シリコン基板173」という。)。図24(c)は、シリコン基板173の表面に、マイクロキャビティをエッチングにより形成するためのフォトレジスト265を設けた状態を示している。シリコン基板を用いた発光素子の場合には、パッケージ基板と貼り合わせる前の工程で、上記フォトレジスト265の位置にシリコン酸化膜185を予め形成しておくことにより、この工程は不要となる。図24(c)の状態から、フォトレジスト265又はシリコン酸化膜185をマスクとしてシリコン基板173をエッチングすることによりマイクロキャビティ175が形成される。その後、フォトレジスト又はシリコン酸化膜を除去して、マイクロキャビティ175に蛍光体330を充填した状態が図29(d)である。この状態でチップサイズパッケージの発光ダイオード28が得られる。必要な場合には、更にマイクロ凸レンズ520を透明接着剤480で貼り合わせる。そして、ウエーハ状態で輝度の選別や電気的検査等を行い、フルカットして個別発光ダイオードに分離し、エキスパンドテープの状態で完成することができる。 FIG. 24 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 18 and a thermoplastic printed board. FIG. 24A shows a cross section in a state where the light emitting element 18 and the thermoplastic printed circuit board 41 are bonded together by a thermoplastic interposer 42. FIG. 24B shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on the bonding side surface is transparently bonded to a compound semiconductor surface exposed by removing the sapphire substrate 200 by a laser lift-off method. The state of being bonded with the agent 480 is shown. In the case of a light emitting element using a silicon substrate as the element substrate, the process starts from this state. Although a silicon oxide film 180 is formed on the silicon substrate 173 in FIG. 24B, in the case of a light emitting device using the silicon substrate 170 as an element substrate, the silicon oxide film 180 has already been formed on the silicon substrate 170. Therefore, the configuration is the same as that of the silicon substrate 173 (hereinafter, “ silicon substrate 170 or 173” for the microcavity is collectively referred to as “silicon substrate 173”). FIG. 24C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173. In the case of a light-emitting element using a silicon substrate, this step is unnecessary by forming the silicon oxide film 185 in advance at the position of the photoresist 265 in the step before being bonded to the package substrate. From the state of FIG. 24C, the microcavity 175 is formed by etching the silicon substrate 173 using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed and the microcavity 175 is filled with the phosphor 330 as shown in FIG. In this state, the light emitting diode 28 of the chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, a full cut is performed to separate the individual light emitting diodes, and the expanded tape state can be completed.
 図24に示した例ではパッケージ基板として熱可塑性プリント基板を用いたが、熱可塑性プリント基板の代わりにバリスタ基板又は金属基板を使用し、熱可塑性インターポーザを用いて発光素子と貼り合わせる場合も手順は全く同様である。また、マイクロミラーを有しない複数の発光セルを備えた発光素子を用いる場合も、全く同様な手順とすることができる。また、図24(b)の工程においては、エッチングによりマイクロキャビティを形成する際のマスクとなるシリコン酸化膜185を、シリコン基板173又は170に予め形成しておいてもよい。このマスクパターンは、パッケージ基板との合体前のシリコン基板のみの状態の方が容易に形成できる。 In the example shown in FIG. 24, a thermoplastic printed circuit board is used as the package substrate. However, the procedure is also applicable when a varistor substrate or a metal substrate is used instead of the thermoplastic printed circuit board and the light emitting element is bonded using a thermoplastic interposer. It is exactly the same. In addition, when using a light-emitting element including a plurality of light-emitting cells that do not have a micromirror, the same procedure can be used. In the step of FIG. 24B, a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed on the silicon substrate 173 or 170 in advance. This mask pattern can be easily formed only in the state of the silicon substrate before being combined with the package substrate.
 図25は、図24に示した手順の詳細である。図25(d)は、ウエーハ状態の発光素子18(図25(a))と熱可塑性プリント基板41(図25(b))との間に、熱可塑性インターポーザ42(図25(c))を挟んだ状態を示している。この状態で真空中にて約300℃で約30分、発光素子18側とプリント基板41側から加圧して保持することにより接着が完了する。熱可塑性材料の為に両者は密着すると共に、プリント基板の電極の銅と発光素子のフリップチップ材料の金とが共晶状態で接合する。その後、サファイア基板200が除去されて露出した化合物半導体の面に、シリコン酸化膜180を形成したシリコン基板173を透明接着剤480で貼り合わせ、フォトレジストパターン265を形成したのが図25(e)の状態である。その後、シリコン基板173をエッチングして、フォトレジストを除去する。それによって形成されたマイクロキャビティ175部に蛍光体330を充填したのが図25(g)に示す状態である。必要な場合には、更にマイクロ凸レンズ520を透明接着剤480で貼り合わせることができる。そして、図に示す分割線510に沿ってフルカットすれば、個別に分離された発光ダイオードが得られる。 FIG. 25 shows details of the procedure shown in FIG. FIG. 25D shows a thermoplastic interposer 42 (FIG. 25C) between the light emitting element 18 in the wafer state (FIG. 25A) and the thermoplastic printed circuit board 41 (FIG. 25B). The sandwiched state is shown. In this state, adhesion is completed by pressing and holding from the light emitting element 18 side and the printed circuit board 41 side in vacuum at about 300 ° C. for about 30 minutes. The two are in close contact with each other because of the thermoplastic material, and the copper of the electrode of the printed board and the gold of the flip chip material of the light emitting element are bonded together in a eutectic state. Thereafter, a silicon substrate 173 having a silicon oxide film 180 formed thereon is bonded to the surface of the compound semiconductor exposed by removing the sapphire substrate 200 with a transparent adhesive 480 to form a photoresist pattern 265, as shown in FIG. It is a state. Thereafter, the silicon substrate 173 is etched to remove the photoresist. The state shown in FIG. 25G is that the microcavity 175 formed thereby is filled with the phosphor 330. If necessary, a micro convex lens 520 can be further bonded with a transparent adhesive 480. And if it cuts fully along the division line 510 shown in the figure, the light emitting diode separated separately will be obtained.
 図26は、シリコン基板の前記発光素子19を用いる場合の製造手順の詳細を示す。図26(d)は、ウエーハ状態の発光素子19(図26(a))と熱可塑性プリント基板41(図26(b))との間に、熱可塑性インターポーザ42(図26(c))を挟んだ状態を示している。前図と同様に、高温・真空中で加圧保持することにより貼り合わせることができる。図26(e)に示すように、すでに形成されているシリコン酸化膜185をマスクとしてシリコン基板170をエッチングする。想定するエッチング終止面は破線410で示されている。これにより、マイクロキャビティ175が形成される。その後、マスクとして使用していたシリコン酸化膜185はフッ酸にて除去される。その後、前図の場合と同様に、蛍光体330を充填し(図26(f))、必要な場合には更にマイクロ凸レンズ520を貼り合せ、分割線510に沿ってフルカットすれば、個別に分離された発光ダイオードが得られる。 FIG. 26 shows the details of the manufacturing procedure when the light emitting element 19 of the silicon substrate is used. FIG. 26D shows a thermoplastic interposer 42 (FIG. 26C) between the light emitting element 19 in the wafer state (FIG. 26A) and the thermoplastic printed circuit board 41 (FIG. 26B). The sandwiched state is shown. As in the previous figure, they can be bonded together by holding under pressure at high temperature and in vacuum. As shown in FIG. 26E, the silicon substrate 170 is etched using the already formed silicon oxide film 185 as a mask. The assumed etching end surface is indicated by a broken line 410. Thereby, the microcavity 175 is formed. Thereafter, the silicon oxide film 185 used as a mask is removed with hydrofluoric acid. After that, as in the case of the previous figure, the phosphor 330 is filled (FIG. 26 (f)), and if necessary, a micro convex lens 520 is further bonded and a full cut is made along the dividing line 510, individually. A separated light emitting diode is obtained.
 図27は、前記発光素子16及び熱可塑性プリント基板を用いる発光ダイオードの製造手順の例を示す。図27(a)は、発光素子16と熱可塑性プリント基板41とが熱可塑性のインターポーザ42により貼り合わされた状態の断面を示している。図27(b)は、その状態から、サファイア基板200をリフトオフ手法にて除去して露出した化合物半導体面に、貼り合せ側の面にシリコン酸化膜180を形成したシリコン基板173を、透明接着剤480で貼り合わせた状態を示している。シリコン基板を用いた発光素子の場合には、この状態から工程が開始される。図27(c)は、シリコン基板173の表面に、マイクロキャビティをエッチングにより形成するためのフォトレジスト265を設けた状態を示している。素子基板としてシリコン基板を用いた発光素子の場合には、パッケージ基板と貼り合わせる前の工程で、上記フォトレジスト265の位置にシリコン酸化膜185を予め形成しておくことにより、この工程は不要となる。図27(c)の状態から、フォトレジスト265又はシリコン酸化膜185をマスクとしてシリコンをエッチングすることによりマイクロキャビティ175が形成される。その後、フォトレジスト又はシリコン酸化膜を除去して、マイクロキャビティ175に蛍光体330を充填した状態が図27(d)である。この状態でチップサイズパッケージの発光ダイオード22が得られる。必要な場合には、更にマイクロ凸レンズ520を透明接着剤480で貼り合わせることができる。そして、ウエーハ状態で輝度の選別や電気的検査等を行い、フルカットして個別発光ダイオードに分離し、エキスパンドテープの状態で完成することができる。 FIG. 27 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 16 and a thermoplastic printed board. FIG. 27A shows a cross section in a state where the light emitting element 16 and the thermoplastic printed circuit board 41 are bonded together by a thermoplastic interposer 42. FIG. 27B shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on a surface on the bonding side is formed on a compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method, and a transparent adhesive. 480 shows the state of being bonded together. In the case of a light emitting element using a silicon substrate, the process starts from this state. FIG. 27C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173. In the case of a light-emitting element using a silicon substrate as an element substrate, this step is unnecessary because a silicon oxide film 185 is formed in advance at the position of the photoresist 265 in a step before being bonded to the package substrate. Become. From the state of FIG. 27C, the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed and the phosphor 330 is filled in the microcavity 175 as shown in FIG. In this state, the light emitting diode 22 of the chip size package is obtained. If necessary, a micro convex lens 520 can be further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, a full cut is performed to separate the individual light emitting diodes, and the expanded tape state can be completed.
 図27に示した例ではパッケージ基板として熱可塑性プリント基板41を用いたが、熱可塑性プリント基板の代わりにバリスタ基板又は金属基板を使用し、熱可塑性インターポーザを用いて発光素子と貼り合わせる場合も手順は全く同様である。また、複数の発光セルを備えた発光素子を用いる場合も、全く同様な手順とすることができる。また、図27(b)の工程においては、エッチングによりマイクロキャビティを形成する際のマスクとなるシリコン酸化膜185を、シリコン基板173又は170に予め形成しておいてもよい。
 図27に示した手順の詳細は、発光素子の形態が異なる点を除き、図25及び26に示した製造手順と同様である。
In the example shown in FIG. 27, the thermoplastic printed circuit board 41 is used as the package substrate. However, a procedure may be used in the case where a varistor substrate or a metal substrate is used instead of the thermoplastic printed circuit board and the light emitting element is bonded using a thermoplastic interposer. Is exactly the same. The same procedure can be used when a light emitting element including a plurality of light emitting cells is used. In the step of FIG. 27B, a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed in advance on the silicon substrate 173 or 170.
The details of the procedure shown in FIG. 27 are the same as the manufacturing procedure shown in FIGS. 25 and 26 except that the form of the light emitting element is different.
 図28は、前記発光素子18及びガラスエポキシプリント基板を用いる発光ダイオードの製造手順の例を示す。図28(a)は、発光素子18と接着剤バッファ部375が設けられたガラスエポキシプリント基板45とが、異方性導電接着剤370により貼り合わされた状態の断面を示している。図28(b)は、その状態から、サファイア基板200をリフトオフ手法にて除去して露出した化合物半導体面に、貼り合せ側の面にシリコン酸化膜180を形成したシリコン基板173を、透明接着剤480で貼り合わせた状態を示している。素子基板としてシリコン基板を用いた発光素子の場合には、この状態から工程が開始される。図28(c)は、シリコン基板173の表面に、マイクロキャビティをエッチングにより形成するためのフォトレジスト265を設けた状態を示している。シリコン基板170を用いた発光素子の場合には、パッケージ基板と貼り合わせる前の工程で、上記フォトレジスト265の位置にシリコン酸化膜185を予め形成しておくことにより、この工程は不要となる。図28(c)の状態から、フォトレジスト265又はシリコン酸化膜185をマスクとしてシリコンをエッチングすることによりマイクロキャビティ175が形成される。その後、フォトレジスト又はシリコン酸化膜を除去して、マイクロキャビティ175に蛍光体330を充填した状態が図28(d)である。この状態でチップサイズパッケージの発光ダイオード32が得られる。必要な場合には、更にマイクロ凸レンズ520を透明接着剤480で貼り合わせる。そして、ウエーハ状態で輝度の選別や電気的検査等を行い、フルカットして個別の発光ダイオードに分離し、エキスパンドテープの状態で完成することができる。 FIG. 28 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 18 and the glass epoxy printed board. FIG. 28A shows a cross section in a state where the light emitting element 18 and the glass epoxy printed board 45 provided with the adhesive buffer portion 375 are bonded together by the anisotropic conductive adhesive 370. FIG. 28B shows a state in which the silicon substrate 173 in which the silicon oxide film 180 is formed on the surface on the bonding side is formed on the compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method. 480 shows the state of being bonded together. In the case of a light emitting element using a silicon substrate as the element substrate, the process starts from this state. FIG. 28C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the surface of the silicon substrate 173. In the case of a light-emitting element using the silicon substrate 170, this step is not necessary because the silicon oxide film 185 is formed in advance at the position of the photoresist 265 in the step before being bonded to the package substrate. From the state of FIG. 28C, the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed, and the phosphor 330 is filled in the microcavity 175 as shown in FIG. In this state, a light emitting diode 32 of a chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, and a full cut is performed to separate individual light emitting diodes, which can be completed in an expanded tape state.
 図28に示した例では複数の光マイクロセルを備えた発光素子を用いたが、マイクロミラーを有しない複数の発光セルを備えた発光素子を用いる場合も、全く同様な手順とすることができる。また、図28(b)の工程においては、エッチングによりマイクロキャビティを形成する際のマスクとなるシリコン酸化膜185を、シリコン基板173又は170に予め形成しておいてもよい。 In the example shown in FIG. 28, a light-emitting element having a plurality of light microcells is used. However, when a light-emitting element having a plurality of light-emitting cells not having a micromirror is used, the same procedure can be used. . In the step shown in FIG. 28B, a silicon oxide film 185 serving as a mask for forming a microcavity by etching may be formed on the silicon substrate 173 or 170 in advance.
 図29は、図28に示した手順の詳細を説明するための断面図である。図29(a)はウエーハ状態の発光素子18、(b)はガラスエポキシプリント基板45を示している。ガラスエポキシプリント基板45には、異方性導電接着剤の逃げ空間として接着剤バッファ部375が設けられている。図29(c)は、異方性導電接着剤370がガラスエポキシプリント基板45にシート状に貼り付けられた状態を示す。図29(d)は、その異方性導電接着剤370を挟んで発光素子18とガラスエポキシプリント基板45とが貼り合わされた状態を示している。約100℃で約30分、発光素子側とプリント基板側から加圧して保持することにより接着が完了する。異方性導電接着剤370の引張り応力により、両者が密着されると共に、プリント基板上の内部電極の銅と発光素子のフリップチップ材料の金とが直径約10μの金粒子を介して電気的に接合される。その後、サファイア基板200が除去されて露出した化合物半導体の面に、酸化膜180を形成したシリコン基板173を透明接着剤480で貼り合わせ、フォトレジストパターン265を形成したのが図29(e)の状態である。想定するエッチング終止面は破線410で示されている。次いで、シリコン基板173をエッチングした後、フォトレジストを除去する。それによって形成されたマイクロキャビティ175に蛍光体330を充填したのが図29(f)に示す状態である。そして、必要な場合には更にマイクロ凸レンズ520を透明接着剤480で貼り合わせることができる。その後、図に示す分割線510に沿ってフルカットすれば、個別の発光ダイオードに分離することができる。 FIG. 29 is a cross-sectional view for explaining details of the procedure shown in FIG. FIG. 29A shows the light emitting element 18 in the wafer state, and FIG. 29B shows the glass epoxy printed board 45. The glass epoxy printed circuit board 45 is provided with an adhesive buffer portion 375 as a relief space for the anisotropic conductive adhesive. FIG. 29C shows a state where the anisotropic conductive adhesive 370 is attached to the glass epoxy printed board 45 in a sheet form. FIG. 29D shows a state in which the light emitting element 18 and the glass epoxy printed board 45 are bonded to each other with the anisotropic conductive adhesive 370 interposed therebetween. Adhesion is completed by pressing and holding from the light emitting element side and the printed circuit board side at about 100 ° C. for about 30 minutes. Due to the tensile stress of the anisotropic conductive adhesive 370, the two are brought into close contact with each other, and the copper of the internal electrode on the printed circuit board and the gold of the flip chip material of the light emitting element are electrically connected via gold particles having a diameter of about 10 μm. Be joined. Thereafter, a silicon substrate 173 having an oxide film 180 formed thereon is bonded to the surface of the compound semiconductor exposed by removing the sapphire substrate 200 with a transparent adhesive 480 to form a photoresist pattern 265 as shown in FIG. State. The assumed etching end surface is indicated by a broken line 410. Next, after the silicon substrate 173 is etched, the photoresist is removed. The state shown in FIG. 29F is that the phosphor 330 is filled in the microcavity 175 formed thereby. If necessary, the micro convex lens 520 can be further bonded with a transparent adhesive 480. Then, if it cuts fully along the dividing line 510 shown in a figure, it can isolate | separate into an individual light emitting diode.
 図30は、シリコン基板の前記発光素子19を用いる場合の製造手順を示す。図30(d)は、ウエーハ状態の発光素子19(図30(a))と接着剤バッファ部375が設けられたガラスエポキシプリント基板45(図30(b))とを、異方性導電接着剤370を介して接着した状態を示している。前図の場合と同様に、高温で加圧保持することにより貼り合わせることができる。そして図30(e)に示すように、すでにパターンが形成されているシリコン酸化膜185をマスクとして、シリコン基板170をエッチングする。想定するエッチング終止面は破線410で示されている。これにより、マイクロキャビティ175を形成した後、マスクとして使用していたシリコン酸化膜185をフッ酸により除去する。その後、前図の場合と同様に、蛍光体330を充填し(図30(f))、必要な場合には更にマイクロ凸レンズ520を貼り合せることができる。その後、図に示す分割線510に沿ってフルカットすれば、個別の発光ダイオードに分離することができる。 FIG. 30 shows a manufacturing procedure in the case of using the light emitting element 19 of the silicon substrate. FIG. 30D shows an anisotropic conductive bonding between the light emitting element 19 in the wafer state (FIG. 30A) and the glass epoxy printed board 45 (FIG. 30B) provided with the adhesive buffer 375. The state where it is bonded via the agent 370 is shown. As in the case of the previous figure, they can be bonded together by holding under pressure at a high temperature. Then, as shown in FIG. 30E, the silicon substrate 170 is etched using the silicon oxide film 185 on which the pattern has already been formed as a mask. The assumed etching end surface is indicated by a broken line 410. Thus, after the microcavity 175 is formed, the silicon oxide film 185 used as a mask is removed with hydrofluoric acid. Thereafter, as in the case of the previous figure, the phosphor 330 is filled (FIG. 30 (f)), and if necessary, a micro convex lens 520 can be further bonded. Then, if it cuts fully along the dividing line 510 shown in a figure, it can isolate | separate into an individual light emitting diode.
 図31は、前記発光素子16及びガラスエポキシプリント基板を用いる発光ダイオードの製造手順の例を示す。図31(a)は、発光素子16とガラスエポキシプリント基板45とが異方性導電接着剤370により貼り合わされた状態の断面を示している。余分な異方性導電接着剤が内部に閉じ込められて貼り合わせの支障にならないように、ガラスエポキシ基板には接着剤バッファ部375が設けてある。図31(b)は、その状態から、サファイア基板200をリフトオフ手法にて除去して露出した化合物半導体面に、貼り合せ側の面にシリコン酸化膜180を形成したシリコン基板173を、透明接着剤480で貼り合わせた状態を示している。素子基板としてシリコン基板を用いた発光素子の場合には、この状態から工程が開始される。図31(c)は、シリコン表面に、マイクロキャビティをエッチングにより形成するためのフォトレジスト265を設けた状態を示している。シリコン基板170を用いた発光素子の場合には、パッケージ基板と貼り合わせる前の工程で、上記フォトレジスト265の位置にシリコン酸化膜185を予め形成しておくことにより、この工程は不要となる。図31(c)の状態から、フォトレジスト265又はシリコン酸化膜185をマスクとしてシリコンをエッチングすることによりマイクロキャビティ175が形成される。その後、フォトレジスト又はシリコン酸化膜を除去して、マイクロキャビティ175に蛍光体330を充填した状態が図31(d)である。この状態でチップサイズパッケージの発光ダイオード26が得られる。必要な場合には、更にマイクロ凸レンズ520を透明接着剤480で貼り合わせる。そして、ウエーハ状態で輝度の選別や電気的検査等を行い、フルカットして個別の発光ダイオードに分離し、エキスパンドテープの状態で完成することができる。 FIG. 31 shows an example of a manufacturing procedure of a light emitting diode using the light emitting element 16 and the glass epoxy printed board. FIG. 31A shows a cross section in a state where the light emitting element 16 and the glass epoxy printed board 45 are bonded together by the anisotropic conductive adhesive 370. An adhesive buffer 375 is provided on the glass epoxy substrate so that excess anisotropic conductive adhesive is confined inside and does not hinder the bonding. FIG. 31 (b) shows a state in which a silicon substrate 173 having a silicon oxide film 180 formed on the bonding side surface is exposed to a transparent adhesive on a compound semiconductor surface exposed by removing the sapphire substrate 200 by a lift-off method. 480 shows the state of being bonded together. In the case of a light emitting element using a silicon substrate as the element substrate, the process starts from this state. FIG. 31C shows a state in which a photoresist 265 for forming a microcavity by etching is provided on the silicon surface. In the case of a light-emitting element using the silicon substrate 170, this step is not necessary because the silicon oxide film 185 is formed in advance at the position of the photoresist 265 in the step before being bonded to the package substrate. From the state of FIG. 31C, the microcavity 175 is formed by etching silicon using the photoresist 265 or the silicon oxide film 185 as a mask. Thereafter, the photoresist or silicon oxide film is removed, and the microcavity 175 is filled with the phosphor 330 as shown in FIG. In this state, the light emitting diode 26 of the chip size package is obtained. If necessary, a micro convex lens 520 is further bonded with a transparent adhesive 480. Then, brightness selection, electrical inspection, and the like are performed in the wafer state, and a full cut is performed to separate individual light emitting diodes, which can be completed in an expanded tape state.
 図31に示した例では、マイクロミラーを有しない1つの発光セルを備えた発光素子を用いたが、1つの光マイクロセルを備えた発光素子を用いる場合も、全く同様な手順とすることができる。図31(b)の工程においては、エッチングによりマイクロキャビティを形成する際のマスクとなるシリコン酸化膜185を、シリコン基板173又は170に予め形成しておいてもよい。
 図31に示した手順の詳細は、発光素子の形態が異なる点を除き、図29及び30に示した製造手順と同様である。
In the example shown in FIG. 31, a light-emitting element including one light-emitting cell that does not have a micromirror is used. However, when a light-emitting element including one optical microcell is used, the same procedure may be used. it can. In the step of FIG. 31B, a silicon oxide film 185 serving as a mask when forming a microcavity by etching may be formed in advance on the silicon substrate 173 or 170.
The details of the procedure shown in FIG. 31 are the same as the manufacturing procedure shown in FIGS. 29 and 30 except that the form of the light emitting element is different.
 以上の例に挙げた異方性導電接着剤370を用いたヒートシール技術は、ガラス基板とフレキシブル基板との接続に多く使用されている技術であるが、ウエーハ状態の発光素子とパッケージ基板のように広い面積での接続に使用するためには、ヒートシール材の量が最適化される必要がある。すなわち、両者の電極間に必要な実装上の寸法は金粒子の寸法であり、それを超える樹脂成分の厚みは接触に障害となる。これを解決するため、以上に挙げた実施例においては、樹脂の逃げの部分としてプリント基板の一部に窪み(接着剤バッファ部375)を設けている。プリント基板の電極の銅と発光素子の電極の金は共晶結合されていないため接触抵抗はゼロではないが、数mΩと小さい。100℃の温度で加熱及び加圧することにより容易に接続できるため、駆動電流の小さい用途向けの発光ダイオードのパッケージとして、低コストに適用することができる。 The heat sealing technique using the anisotropic conductive adhesive 370 given in the above example is a technique that is often used for the connection between a glass substrate and a flexible substrate. In order to use for connection in a large area, the amount of heat seal material needs to be optimized. That is, the required mounting dimension between the two electrodes is the size of the gold particles, and the thickness of the resin component exceeding that is an obstacle to contact. In order to solve this problem, in the embodiment described above, a recess (adhesive buffer 375) is provided in a part of the printed circuit board as a resin escape portion. Since the copper of the printed circuit board electrode and the gold of the light emitting element electrode are not eutectic bonded, the contact resistance is not zero, but is as small as several mΩ. Since it can be easily connected by heating and pressurizing at a temperature of 100 ° C., it can be applied at low cost as a light emitting diode package for applications with a small driving current.
 以上では、パッケージ基板として熱可塑性プリント基板、金属基板、バリスタ基板、ガラスエポキシプリント基板を使用し、発光素子とパッケージ基板との接合材として熱可塑性のインターポーザ、異方性導電接着剤を使用する例を挙げた。パッケージ基板の材質や、接合材との組み合わせはこれに限定されない。例えば、金属基板と異方性導電接着剤との組み合わせ、セラミックス基板と熱可塑性のインターポーザとの組み合わせ、セラミックス基板と異方性導電接着剤との組み合わせ等によっても、チップサイズパッケージを構成することができる。各材料の熱伝導率、要求される電極間の接続抵抗値、作りやすさ等を考慮して適宜選択することができる。 In the above example, a thermoplastic printed board, a metal board, a varistor board, or a glass epoxy printed board is used as the package board, and a thermoplastic interposer or anisotropic conductive adhesive is used as the bonding material between the light emitting element and the package board. Mentioned. The material of the package substrate and the combination with the bonding material are not limited to this. For example, a chip size package can be configured by a combination of a metal substrate and an anisotropic conductive adhesive, a combination of a ceramic substrate and a thermoplastic interposer, a combination of a ceramic substrate and an anisotropic conductive adhesive, or the like. it can. The material can be appropriately selected in consideration of the thermal conductivity of each material, the required connection resistance value between the electrodes, ease of production, and the like.
シリコン基板を用いたマイクロキャビティは、シリコンをKOH水溶液等でエッチングしてその内側面にできる傾斜角54°の壁面を利用したが、光の反射率を一層高める為に、当該壁面に銀の薄膜等を設けることが有効である。マイクロキャビティ底面が絶縁物のシリコン酸化膜であり、側壁面は導電性のあるシリコンであることを利用して、そのまま電気メッキ技術により、銀薄膜又は銀を含む多層薄膜を形成して反射率を高めることが可能である。 The microcavity using a silicon substrate uses a wall surface with an inclination angle of 54 ° formed on the inner surface by etching silicon with a KOH aqueous solution or the like. In order to further increase the light reflectivity, a silver thin film is formed on the wall surface. Etc. are effective. By utilizing the fact that the bottom surface of the microcavity is an insulating silicon oxide film and the side wall surface is conductive silicon, a silver thin film or a multilayer thin film containing silver is formed as it is by electroplating technology to improve the reflectivity. It is possible to increase.
また、図6(a3)において言及したように、銅など金属の薄板を用いてマイクロキャビティを形成することも可能である。厚さ100μm程度の金属板をエッチング加工して、マイクロキャビティの内側面となる壁面の傾斜が約45°となるように鍛造することができる。更に、当該側壁面に銀メッキを形成することもできる。このような加工は、ICのリードフレームの作成と同様な設備や材料によって可能である。ウエーハと同じ大きさで、薄板に各発光素子に対応したマイクロキャビティを形成し、ウエーハ状態の発光素子と透明接着剤を用いて貼り合わせることができる。本チップサイズパッケージではパッケージ基板がパッケージの基板になっているため、安定に貼り合わせができる。又この工程以降は高温度とされることはないので構造的にも問題はない。銅のスタッドフレーム又はシリコンを用いたマイクロキャビティは、蛍光体を用いない発光ダイオードにも適用可能である。 Further, as mentioned in FIG. 6 (a3), a microcavity can be formed using a thin metal plate such as copper. A metal plate having a thickness of about 100 μm can be etched and forged so that the inclination of the wall surface serving as the inner surface of the microcavity is about 45 °. Furthermore, silver plating can also be formed on the side wall surface. Such processing is possible with the same equipment and materials as those used in the production of IC lead frames. A microcavity corresponding to each light emitting element is formed on a thin plate having the same size as the wafer, and can be bonded to the light emitting element in a wafer state using a transparent adhesive. In this chip size package, since the package substrate is the substrate of the package, it can be bonded stably. Further, there is no problem in terms of structure since the temperature is not increased after this step. A microcavity using a copper stud frame or silicon is also applicable to a light emitting diode not using a phosphor.
また、以上に挙げた事例において、発光ダイオードの輝度の調整の為に光マイクロセルへの給電を選択する手法を説明した。一般には、定電圧で輝度を一定にするというニーズと、定電流で輝度を一定にするというニーズの両方がある。すなわち、定電圧で複数個の発光ダイオードを駆動する用途では、一定の駆動電圧で輝度を一定の公差にすることが求められる。一方、定電流で複数個の発光ダイオードを駆動する用途では、一定の駆動電流での輝度を一定の公差にすることが求められる。本発明における発光ダイオードの輝度調整はその発光面積を調整する方法であるため、一定電圧の下での輝度に応じた調整に向いている。一定電圧を印加したときの輝度は、発光面積に比例して調整可能である。一方、一定電流で駆動する場合には、輝度に応じて発光面積を変更することは発光セルに流れる電流密度を変更することになり、大幅な調整は期待できない。したがって、定電流駆動の用途では、ウエーハ上の発光セルについて一定電流の下での輝度マップを作成して層別を行う必要がある。その層別の幅を減らすために、本手法による輝度調整は役立つ。 Further, in the above examples, the method of selecting the power supply to the optical microcell for adjusting the luminance of the light emitting diode has been described. In general, there are both a need for constant brightness at a constant voltage and a need for constant brightness at a constant current. That is, in an application where a plurality of light emitting diodes are driven with a constant voltage, it is required to make the luminance a certain tolerance with a certain driving voltage. On the other hand, in an application in which a plurality of light emitting diodes are driven with a constant current, it is required that the luminance at a constant driving current has a certain tolerance. Since the luminance adjustment of the light emitting diode in the present invention is a method of adjusting the light emitting area, it is suitable for adjustment according to the luminance under a constant voltage. The luminance when a constant voltage is applied can be adjusted in proportion to the light emitting area. On the other hand, in the case of driving with a constant current, changing the light emitting area according to the luminance changes the current density flowing in the light emitting cell, and a large adjustment cannot be expected. Therefore, in a constant current driving application, it is necessary to create a luminance map under a constant current for the light emitting cells on the wafer and perform layering. In order to reduce the width of each layer, the brightness adjustment by this method is useful.
 図32は、ウエーハと、ウエーハ状態の発光素子と、1つの発光ダイオードとの関係の例を示す図である。素子基板であるシリコン基板として、例えば図32(a)に示すような3インチウエーハ400を使用することができる。図32(b)の断面図に示すように、1つの発光素子は0.5mm×0.5mm程度とすることができる。ここでは発光素子として前記発光素子19を例示している。発光素子19はシリコン基板上に設けた光マイクロセル構造のものであり、例えば、横方向に4、奥行方向(図示せず)に2、の計8個の光マイクロセルから構成することができる。発光素子は、光マイクロセル層300、導電反射膜層275、電源配線層310、及びフリップチップ電極322を具備したフリップチップ電極層を備えている。光マイクロセル層300には断面視4つの光マイクロセルが形成されており、各光マイクロセルは、発光セル80とその側面を囲むマイクロミラー71を備えている。また、発光素子は熱可塑性のプリント基板41と貼り合わされ、シリコン基板170部にマイクロキャビティ175が形成されている。そしてマイクロキャビティ175に蛍光体330が充填され、更にマイクロ凸レンズ520が貼り合わされている。図32(c)は、上記のウエーハ状態から個別に分離された発光ダイオード39の断面を示している。図32(c)には、活性層で発生する光(1次発光)の進行方向がまとめて示されている(pqr)。前述のとおり、活性層から集光方向zに向かう光pはそのまま放出され、集光方向zと反対向きの光qは反射膜層275で反射され、活性層に沿った側面方向の光rはマイクロミラー71により反射され、いずれも蛍光体330に向けて放出される。蛍光体330内では、半導体層から到来する波長の短い1次発光の光により蛍光物質が励起され、波長の長い2次発光が生じる。図示されるように、2次発光のうち集光方向zに向かう光s1は、直進して発光ダイオードから放出される(s2)。斜め方向に向かう光t1は、マイクロ凸レンズにより集光方向に屈折されて放出される(t2)。集光方向zとは垂直の方向の光u0は、マイクロキャビティの側壁面411によって反射され(u1)、更にマイクロ凸レンズにより集光方向に屈折されて放出される(u2)。このように、2次発光した光は集光方向に向けられ、効率よく集光することができる。白色発光ダイオードの場合には、1次発光及び2次発光の波長と強度の組み合わせにより白色光が生成される。 FIG. 32 is a diagram illustrating an example of a relationship among a wafer, a light emitting element in a wafer state, and one light emitting diode. As a silicon substrate which is an element substrate, for example, a 3-inch wafer 400 as shown in FIG. 32A can be used. As shown in the cross-sectional view of FIG. 32B, one light emitting element can be about 0.5 mm × 0.5 mm. Here, the light emitting element 19 is illustrated as a light emitting element. The light-emitting element 19 has an optical microcell structure provided on a silicon substrate, and can be composed of a total of eight optical microcells, for example, 4 in the horizontal direction and 2 in the depth direction (not shown). . The light emitting element includes a flip chip electrode layer including an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode 322. The optical microcell layer 300 is formed with four optical microcells in cross-section, and each optical microcell includes a light emitting cell 80 and a micromirror 71 surrounding the side surface. The light emitting element is bonded to the thermoplastic printed circuit board 41, and a microcavity 175 is formed in 170 parts of the silicon substrate. The microcavity 175 is filled with the phosphor 330, and the micro convex lens 520 is further bonded. FIG. 32C shows a cross section of the light emitting diode 39 individually separated from the wafer state. FIG. 32C collectively shows the traveling direction of light (primary light emission) generated in the active layer (pqr). As described above, the light p directed from the active layer in the light collecting direction z is emitted as it is, the light q opposite to the light collecting direction z is reflected by the reflective film layer 275, and the light r in the side direction along the active layer is The light is reflected by the micromirror 71 and both are emitted toward the phosphor 330. In the phosphor 330, the fluorescent material is excited by the primary light having a short wavelength coming from the semiconductor layer, and secondary light having a long wavelength is generated. As shown in the drawing, light s1 in the secondary light emission toward the light collecting direction z travels straight and is emitted from the light emitting diode (s2). The light t1 traveling in the oblique direction is refracted and emitted in the light collecting direction by the micro convex lens (t2). Light u0 in a direction perpendicular to the light collecting direction z is reflected by the side wall surface 411 of the microcavity (u1), and further refracted in the light collecting direction by the micro convex lens and emitted (u2). Thus, the secondary emitted light is directed in the condensing direction and can be efficiently collected. In the case of a white light emitting diode, white light is generated by a combination of the wavelength and intensity of primary light emission and secondary light emission.
 本発光ダイオードの透明部材としてマイクロ凸レンズを用いる場合には、マイクロ凸レンズの効果により発光素子からの光は集光方向に集光され、図9(a)に示したように光束を大幅に絞ることができる。そして、図9(b)に示したように、更に別の拡散レンズにより所望の角度範囲に光束を拡散することができる。例えば、図9(c)に示したようにパッケージのキャップ部を凹レンズとすることによって、その凹レンズと発光ダイオード備えられたマイクロ凸レンズとの組み合わせにより、所望の広がりをもった光束を作り出すことができる。 When a micro convex lens is used as the transparent member of the present light emitting diode, the light from the light emitting element is condensed in the condensing direction due to the effect of the micro convex lens, and the light flux is greatly reduced as shown in FIG. Can do. And as shown in FIG.9 (b), a light beam can be spread | diffused in a desired angle range with another diffuser lens. For example, as shown in FIG. 9C, by making the cap portion of the package a concave lens, a light beam having a desired spread can be created by a combination of the concave lens and a micro convex lens provided with a light emitting diode. .
 以上に述べた手法により、輝度、色ムラ等の特性が総合的に優れた発光ダイオードを得ることができる。輝度については、特に発光層に沿った光をマイクロミラーにより反射させ、発光層で発光した全ての方向の光を集光方向に取り出すことができる。また、蛍光体で励起された光はマイクロキャビティにより集光方向に取り出すことができ、更にマイクロ凸レンズにより集束させて取り出すことができる。色ムラについては、波長の短い1次発光と波長の長い2次発光の光を合わせて集光方向に集めることにより、均質な白色光を得ることができる。更にその光を拡散させることにより、広がりを持ち且つ均質な白色光を得ることができる。 By the method described above, it is possible to obtain a light emitting diode having excellent overall characteristics such as luminance and color unevenness. Regarding the luminance, in particular, light along the light emitting layer can be reflected by the micromirror, and light in all directions emitted from the light emitting layer can be extracted in the light collecting direction. Further, the light excited by the phosphor can be taken out in the light collecting direction by the microcavity, and can be further taken out by being focused by the micro convex lens. Regarding color unevenness, uniform white light can be obtained by combining light of primary light emission having a short wavelength and light of secondary light emission having a long wavelength together in the light collecting direction. Further, by diffusing the light, it is possible to obtain a broad and uniform white light.
 図33(a)は、図32(b)に示した発光素子部の光マイクロセルの配設を表す平面図である。発光素子は、横方向に4、縦方向に2の計8個の光マイクロセルから構成されており、各光マイクロセルの領域は破線81で示されている。図33(b)は、その発光素子を用いた発光ダイオードの断面を表している。発光素子は光マイクロセル層300、導電反射膜層275、電源配線層310、及びフリップチップ電極321、322を具備したフリップチップ層(320)からなる。光マイクロセル層300には上記8個の光マイクロセルが設けられ、各光マイクロセルにはマイクロミラー71で囲まれた発光セル80が形成されている。フリップチップ層には、図20(a)に示された各光マイクロセルに共通のN電極に接続されたフリップチップN電極322と、各光マイクロセルのP電極をP0~P4に分けてそれぞれと接続されたフリップチップP電極321とを具備している。 FIG. 33 (a) is a plan view showing the arrangement of the optical microcells in the light emitting element section shown in FIG. 32 (b). The light emitting element is composed of a total of eight optical microcells, 4 in the horizontal direction and 2 in the vertical direction, and the area of each optical microcell is indicated by a broken line 81. FIG. 33B illustrates a cross section of a light emitting diode using the light emitting element. The light emitting element includes a flip chip layer (320) including an optical microcell layer 300, a conductive reflective film layer 275, a power supply wiring layer 310, and flip chip electrodes 321 and 322. The optical microcell layer 300 is provided with the eight optical microcells, and a light emitting cell 80 surrounded by the micromirror 71 is formed in each optical microcell. In the flip chip layer, the flip chip N electrode 322 connected to the N electrode common to each optical microcell shown in FIG. 20A and the P electrode of each optical microcell are divided into P0 to P4, respectively. And a flip chip P electrode 321 connected to each other.
 図34(a)は前図と同じ発光ダイオードの断面であり、図34(b)はその下面すなわちパッケージ基板41の外部電極60側の面を表わしている。8個の光マイクロセルは図8(b)にP0~P4で示したような発光面積の重みづけがなされている。プリント基板41の下面に設けられた基板N電極332は、各光マイクロセルのN電極に接続されている。また、基板P電極331は、光マイクロセルP0のP電極に接続されている。また、プリント基板41の下面で基板P電極331に接続されている端子P1~P4は、それぞれ光マイクロセルP1~P4のP電極に接続されている。そして、各配線を切断部445で選択的に切断することにより、それに対応する光マイクロセルへ給電しないようにし、発光ダイオードの輝度を調整することができる。チップサイズの本発光ダイオードのパッケージング、電気的検査、光学的検査、輝度の選別や調整等は、ウエーハ状態すなわち発光ダイオードを個別に分離する前に行うことができる。ウエーハ状態で取扱うことができるため、発光ダイオード内のサージ対策素子を不要とすることもできる。 34A is a cross-sectional view of the same light emitting diode as in the previous figure, and FIG. 34B represents the lower surface thereof, that is, the surface of the package substrate 41 on the external electrode 60 side. Eight optical microcells are weighted with light emitting areas as indicated by P0 to P4 in FIG. 8B. A substrate N electrode 332 provided on the lower surface of the printed circuit board 41 is connected to the N electrode of each optical microcell. The substrate P electrode 331 is connected to the P electrode of the optical microcell P0. The terminals P1 to P4 connected to the substrate P electrode 331 on the lower surface of the printed circuit board 41 are connected to the P electrodes of the optical microcells P1 to P4, respectively. Each wiring is selectively cut by the cutting unit 445 so that power is not supplied to the corresponding optical microcell, and the luminance of the light emitting diode can be adjusted. The packaging, electrical inspection, optical inspection, brightness selection and adjustment of the chip-sized light emitting diode can be performed before the wafer state, that is, the light emitting diodes are individually separated. Since it can be handled in a wafer state, a surge countermeasure element in the light emitting diode can be eliminated.
 尚、図32~34においては発光素子の基板としてシリコン基板を用いたが、既に説明したとおり、サファイア基板を使用しても同様の構成・作用を得ることができる。その場合、サファイア基板はそのまま残されてもよいし、除去されてもよい。また、マイクロキャビティやチップサイズパッケージを構成する部材も種々の選択が可能である。また、以上においては、マイクロキャビティ及び蛍光体を備える白色発光ダイオードの構成例を主として示したが、本発光ダイオードは白色用だけでなく、赤色その他すべての発光ダイオードに適用できる。その場合には、マイクロキャビティ(170又は173)及び蛍光体330は不要であり、その他の構成は全く同様となる。 32 to 34, the silicon substrate is used as the substrate of the light emitting element. However, as already described, the same configuration and operation can be obtained even when the sapphire substrate is used. In that case, the sapphire substrate may be left as it is or may be removed. Various members can also be selected for the microcavity and the chip size package. In the above, the configuration example of the white light emitting diode including the microcavity and the phosphor is mainly shown. However, the light emitting diode can be applied not only for white but also for all other red light emitting diodes. In that case, the microcavity (170 or 173) and the phosphor 330 are not necessary, and other configurations are exactly the same.
 図35は、マイクロキャビティを用いない場合の本発光ダイオードの構成例を表わす図であり、ウエーハと、ウエーハ状態の発光素子と、1つの発光ダイオードとの関係を表わしている。発光素子の素子基板であるサファイア基板又はシリコン基板として、例えば図35(a)に示すような3インチウエーハ400を使用することができる。図35(b)の断面図に示すように、1つの発光素子は0.5mm×0.5mm程度とすることができる。ここではシリコン基板を用いる前記発光素子19を示しているが、これまでに例示したすべての発光素子を使用することができる。すなわち、素子基板はサファイア基板でもシリコン基板でもよく、1つの発光素子には1又は2以上の発光セル80を備えることができ、その発光セルはマイクロミラーを備えていなくてもよいし、マイクロミラーを備えて光マイクロセルを構成していてもよい。図35(b)及び(c)に示した発光素子19の場合には、発光セル80及びその側面を囲むマイクロミラー71からなる光マイクロセルが、横方向に4、奥行方向(図示せず)に2、の計8個備えられている。そして、発光素子19は、光マイクロセルが形成された光マイクロセル層300、導電反射膜層275、電源配線層310、及びフリップチップ電極321及び322を具備したフリップチップ電極層を備えている。このような発光素子の発光面側に、透明部材521を貼り合わせ、その後個別の発光ダイオードに分離することができる。透明部材521として、マイクロ凸レンズや凹レンズの他、素子基板が除去された後の発光部の保護のための透明プラスチック板等を、適宜用いることができる。また、発光素子の発光面と透明部材521との間に、板状の蛍光体を挟んで構成することもできる。例えば、発光面上に蛍光体とマイクロ凸レンズを順に積層した場合には、発光素子からの1次発光及び蛍光体で励起される2次発光により白色光を生成し、マイクロ凸レンズによって集光方向に向かって光束を狭めることができる。また、発光素子が上記ウエーハに形成された状態において、その素子電極面側にパッケージ基板を貼り合わせて発光ダイオードを構成することができる。図35では、発光素子と熱可塑性のプリント基板41とを接合材42を介して貼り合わせて発光ダイオードを構成する例を示している。図35(c)は、ウエーハ状態から個別に分離された発光ダイオード139の断面を示している。ウエーハ状態では硬いサファイア基板を素子基板に用いた場合であっても、素子基板が除去されているため、容易にフルカットで各素子を分離することができる。図35(c)には、活性層で発生する光(1次発光)の進行方向が示されている。前述のとおり、活性層から集光方向zに向かう光pはそのまま放出され、集光方向zと反対向きの光qは反射膜層で反射されて放出され、活性層に沿った側面方向の光rはマイクロミラーにより反射されて放出される。このように、活性層で発生した各方向の光(p、q及びr)は、いずれも発光面から集光方向zへ放出される。透明部材521としてマイクロ凸レンズや凹レンズが形成されている場合には、上記発光面から放出された光の広がりを調整することができる。 FIG. 35 is a diagram illustrating a configuration example of the present light-emitting diode when a microcavity is not used, and illustrates a relationship among a wafer, a light-emitting element in a wafer state, and one light-emitting diode. As a sapphire substrate or silicon substrate that is an element substrate of the light emitting element, for example, a 3-inch wafer 400 as shown in FIG. 35A can be used. As shown in the cross-sectional view of FIG. 35B, one light emitting element can be about 0.5 mm × 0.5 mm. Although the light emitting element 19 using a silicon substrate is shown here, all the light emitting elements exemplified so far can be used. That is, the element substrate may be a sapphire substrate or a silicon substrate, and one light emitting element may include one or more light emitting cells 80, and the light emitting cell may not include a micromirror. An optical microcell may be configured. In the case of the light-emitting element 19 shown in FIGS. 35B and 35C, the optical microcell composed of the light-emitting cell 80 and the micromirror 71 surrounding the side surface thereof is 4 in the horizontal direction and in the depth direction (not shown). A total of eight are provided. The light emitting element 19 includes an optical microcell layer 300 on which optical microcells are formed, a conductive reflective film layer 275, a power supply wiring layer 310, and a flip chip electrode layer including flip chip electrodes 321 and 322. The transparent member 521 can be bonded to the light emitting surface side of such a light emitting element, and then separated into individual light emitting diodes. As the transparent member 521, in addition to the micro convex lens and the concave lens, a transparent plastic plate for protecting the light emitting portion after the element substrate is removed can be used as appropriate. Further, a plate-like phosphor may be sandwiched between the light emitting surface of the light emitting element and the transparent member 521. For example, when a phosphor and a micro convex lens are sequentially laminated on the light emitting surface, white light is generated by the primary light emission from the light emitting element and the secondary light emission excited by the phosphor, and the micro convex lens is used in the light collecting direction. The light flux can be narrowed toward the front. Further, in a state where the light emitting element is formed on the wafer, a light emitting diode can be configured by attaching a package substrate to the element electrode surface side. FIG. 35 shows an example in which a light emitting diode is configured by bonding a light emitting element and a thermoplastic printed circuit board 41 via a bonding material 42. FIG. 35C shows a cross section of the light emitting diode 139 individually separated from the wafer state. Even when a hard sapphire substrate is used as the element substrate in the wafer state, each element can be easily separated by full cut because the element substrate is removed. FIG. 35 (c) shows the traveling direction of light (primary light emission) generated in the active layer. As described above, the light p directed from the active layer in the light collecting direction z is emitted as it is, and the light q opposite to the light collecting direction z is reflected by the reflective film layer and emitted, and the light in the lateral direction along the active layer is emitted. r is reflected by the micromirror and emitted. Thus, all the light (p, q, and r) generated in the active layer in each direction is emitted from the light emitting surface in the light collecting direction z. When a micro convex lens or a concave lens is formed as the transparent member 521, the spread of light emitted from the light emitting surface can be adjusted.
 本発明の発光ダイオードは、発光素子をベアチップでマザーボード上に実装することもできるし、チップサイズパッケージに構成して実装することもできる。液晶のバックライト用途では、発光ダイオードが数十mmピッチで縦横に敷き詰められる。このような場合、本発明の発光ダイオードは0.5mm×0.5mm程度とごく小さいため、ウエーハ状態からスクライブし、そのままエキスパンドした状態又は同様なシート面に実装した状態でピックアップしてマザーボードに装着することが好ましい。この様にすれば静電気などのサージが最小限に抑えられ、マザーボードにサージ吸収素子を備えるだけでよい。また、本発光ダイオードから集光方向に光拡散板を設ければ、照射光を均等化することができる。 In the light-emitting diode of the present invention, the light-emitting element can be mounted on the motherboard with a bare chip, or can be mounted in a chip size package. In liquid crystal backlight applications, light emitting diodes are laid vertically and horizontally at a pitch of several tens of mm. In such a case, since the light emitting diode of the present invention is as small as about 0.5 mm × 0.5 mm, it is scribed from the wafer state and picked up in the expanded state or mounted on the same sheet surface and mounted on the motherboard. It is preferable to do. In this way, surges such as static electricity are minimized, and it is only necessary to provide a surge absorbing element on the motherboard. Further, if a light diffusing plate is provided in the light collecting direction from the light emitting diode, the irradiation light can be equalized.
 上記光拡散板等がない状態でも、発光ダイオードからの方向によらず照射光をできるだけ均一とすることが好ましい。例えば、発光ダイオードをマザーボード上に格子状に配列して使用する場合、個々の発光ダイオードからはマザーボード上のある高さでは限られた範囲に光が照射される。このため、例えば上記格子の対角線上の中間点で、照度が小さくなってしまう場合がある。この対策として、発光ダイオードから放射される光の方向分布を意図的に変更したいというニーズがある。このような場合、本発明の発光ダイオードにおいては、光源である発光部の形状やレイアウト、マイクロ凸レンズの形状や曲率等を工夫することにより、光の方向分布を均一化したり変えたりすることが容易に可能である。 Even in the absence of the light diffusion plate or the like, it is preferable to make the irradiation light as uniform as possible regardless of the direction from the light emitting diode. For example, when light emitting diodes are used in a grid pattern on a mother board, light is emitted from individual light emitting diodes to a limited range at a certain height on the mother board. For this reason, for example, the illuminance may decrease at an intermediate point on the diagonal line of the lattice. As a countermeasure, there is a need to intentionally change the direction distribution of light emitted from the light emitting diode. In such a case, in the light emitting diode of the present invention, it is easy to make uniform or change the light direction distribution by devising the shape and layout of the light emitting part as the light source, the shape and curvature of the micro convex lens, etc. Is possible.
 尚、本発明は以上で詳述した実施形態に限定されず、本発明の請求項に示した範囲で様々な変形または変更が可能である。 Note that the present invention is not limited to the embodiments described in detail above, and various modifications or changes can be made within the scope of the claims of the present invention.
 本発明の発光ダイオードは、灯具、液晶バックライト、食物工場の照明等、広範な分野で使用することができる。本発明は白色用だけではなく全ての発光ダイオードに適用することができる。 The light emitting diode of the present invention can be used in a wide range of fields such as lamps, liquid crystal backlights, and food factory lighting. The present invention can be applied not only to white light but also to all light emitting diodes.
 1;サファイア基板、2;N+型半導体(GaAlN)膜、3;N型半導体(GaAlN)膜、4;活性層、5;P型半導体(GaAlN)膜、6;導電反射膜(背面反射膜)、7;フリップチップ(P)電極、8;フリップチップ(N)電極、9;発光素子、10;パッケージ基板、11;パッケージ基板電極部、12;パッケージ内側壁、13;蛍光体、14;キャップ、15;シリコン酸化膜、16~19;発光素子、22~39;発光ダイオード(光半導体装置)、40;パッケージ基板、41;熱可塑性プリント基板、42;熱可塑性インターポーザ、43;金属基板、45;ガラスエポキシプリント基板、50;ビア、60;外部電極、61;内部電極、65;マザーボード電極、70、71;マイクロミラー(側面反射膜)、80;発光セル、81;発光セルの境界、84;化合物半導体層(発光部)、85;導電反射膜、90;配線層、137、139;発光ダイオード(光半導体装置)、150;外部反射板、170;シリコン基板(素子基板)、173;シリコン基板(マイクロキャビティ用)、175;マイクロキャビティ、180;シリコン酸化膜、185;エッチング用シリコン酸化膜(マスクパターン)、190;酸化インジウム膜、200;サファイア基板(素子基板)、201;サファイア基板、210;N+型半導体(GaAlN)膜、220;N型半導体(GaAlN)膜、230;活性層、231;活性層(発光セル)の境界、240;P型半導体(GaAlN)膜、250;傾斜部(テーパエッチ部)、260;フォトレジスト、265;マイクロキャビティ形成用フォトレジスト、270;導電反射膜、275;導電反射膜、280;シリコン酸化膜、281,282;傾斜(テーパ)付き電極部、290;P型電極、291;N型電極、300;光マイクロセル層、310;光マイクロセルへの電源配線層、315;薄膜配線層、320;フリップチップ電極層、321;フリップチップP電極、322;フリップチップN電極、330;蛍光体、331;パッケージ基板P電極、332;パッケージ基板N電極、340;マザーボード、350;インターポーザ、370;異方性導電接着材、375;接着材バッファ部、400;ウエーハ、410;シリコンのエッチング終止面、411;マイクロキャビティ(シリコン)の内側壁面、421~428;光マイクロセル、441~444;電源配線(給電選択部)、445;電源切断線、480;透明接着剤、510;素子分割線、520;マイクロ凸レンズ、521;透明部材、540;スタッドフレーム、541;スタッドフレーム底部、542;エッチング後のスタッドフレーム底部、543;スタッドフレームの上部、544;スタッドフレームの内側壁面、600;光拡散レンズ、601;凹レンズ。 DESCRIPTION OF SYMBOLS 1; Sapphire substrate, 2; N + type semiconductor (GaAlN) film | membrane, 3; N type semiconductor (GaAlN) film | membrane, 4; Active layer, 5: P type semiconductor (GaAlN) film | membrane, 6; Conductive reflection film (back surface reflection film) 7; Flip chip (P) electrode, 8; Flip chip (N) electrode, 9; Light emitting element, 10; Package substrate, 11; Package substrate electrode part, 12; Package inner wall, 13; 15; Silicon oxide film, 16 to 19; Light emitting element, 22 to 39; Light emitting diode (optical semiconductor device), 40; Package substrate, 41; Thermoplastic printed board, 42; Thermoplastic interposer, 43; Glass epoxy printed board, 50; via, 60; external electrode, 61; internal electrode, 65; motherboard electrode, 70, 71; micromirror (side reflective film) 80; light emitting cell, 81; boundary of light emitting cell, 84; compound semiconductor layer (light emitting portion), 85; conductive reflection film, 90; wiring layer, 137, 139; light emitting diode (photo semiconductor device), 150; , 170; silicon substrate (element substrate), 173; silicon substrate (for microcavity), 175; microcavity, 180; silicon oxide film, 185; silicon oxide film (mask pattern) for etching, 190; indium oxide film, 200 Sapphire substrate (element substrate), 201; sapphire substrate, 210; N + type semiconductor (GaAlN) film, 220; N type semiconductor (GaAlN) film, 230; active layer, 231; boundary of active layer (light emitting cell), 240 P-type semiconductor (GaAlN) film, 250; inclined portion (taper etched portion), 260; photoresist, 26 Microcavity forming photoresist, 270; conductive reflective film, 275; conductive reflective film, 280; silicon oxide films, 281 and 282; inclined (tapered) electrode portions, 290; P-type electrode, 291; N-type electrode, 300; Optical microcell layer, 310; Power wiring layer to optical microcell, 315; Thin film wiring layer, 320; Flip chip electrode layer, 321; Flip chip P electrode, 322; Flip chip N electrode, 330; 331; Package substrate P electrode, 332; Package substrate N electrode, 340; Mother board, 350; Interposer, 370; Anisotropic conductive adhesive, 375; Adhesive buffer part, 400; Wafer, 410; 411; inner wall surface of microcavity (silicon), 421 to 428; optical microcell 441 to 444; power supply wiring (power supply selection unit) 445; power supply disconnecting line 480; transparent adhesive 510; element dividing line 520; micro convex lens 521; transparent member 540; stud frame 541; Bottom, 542; Stud frame bottom after etching, 543; Top of stud frame, 544; Inner wall surface of stud frame, 600; Light diffusion lens, 601; Concave lens.

Claims (12)

  1.  素子基板面上に区画されて化合物半導体層により形成された1又は2以上の発光部と、該発光部からの光を取り出す発光面とは反対側の素子電極面に該発光部に電源を供給する素子電極とを具備し、該発光面に垂直な集光方向に光を取り出す発光素子と、
     前記発光素子の前記発光面側に、前記素子基板の外周と外周が同一サイズの透明部材と、
     を備え、
     複数の前記発光素子が前記素子基板となるウエーハに形成された状態において、前記透明部材が配設され、その後に該発光素子ごとに分離されて形成されることを特徴とする光半導体装置。
    Power is supplied to the light emitting portion on one or more light emitting portions that are partitioned by the compound semiconductor layer and formed on the surface of the element substrate, and the device electrode surface opposite to the light emitting surface that extracts light from the light emitting portion. A light emitting element that extracts light in a light collecting direction perpendicular to the light emitting surface;
    On the light emitting surface side of the light emitting element, the outer periphery and the outer periphery of the element substrate have the same size, and
    With
    An optical semiconductor device, wherein the transparent member is disposed in a state where a plurality of the light-emitting elements are formed on a wafer to be the element substrate, and then the light-emitting elements are separated and formed.
  2.  前記発光素子の外周と外周が同一サイズの基板であって、前記発光素子を搭載する素子搭載面に該発光素子の前記素子電極に対応した内部電極と、該素子搭載面とは反対面に該内部電極と接続された外部電極と、を具備するパッケージ基板を更に備え、
     前記発光素子の前記素子電極面と前記パッケージ基板の前記素子搭載面とを対向させて貼り合わせることにより、前記素子電極と前記内部電極とが電気的に接続される請求項1記載の光半導体装置。
    The outer periphery and the outer periphery of the light emitting element are substrates of the same size, the inner surface corresponding to the element electrode of the light emitting element is mounted on the element mounting surface on which the light emitting element is mounted, and the surface opposite to the element mounting surface is A package substrate comprising an external electrode connected to the internal electrode,
    2. The optical semiconductor device according to claim 1, wherein the element electrode and the internal electrode are electrically connected by bonding the element electrode surface of the light emitting element and the element mounting surface of the package substrate to face each other. .
  3.  前記発光素子の前記素子電極面と前記パッケージ基板の前記素子搭載面とを接合材を用いて貼り合わせることにより、前記素子電極と前記内部電極とが電気的に接続されるとともに、前記素子電極面と前記素子搭載面との間が該接合材により密閉される請求項2記載の光半導体装置。 By bonding the element electrode surface of the light emitting element and the element mounting surface of the package substrate using a bonding material, the element electrode and the internal electrode are electrically connected, and the element electrode surface The optical semiconductor device according to claim 2, wherein a space between the element mounting surface and the element mounting surface is sealed with the bonding material.
  4.  前記透明部材は、前記発光素子から取り出す光束を前記集光方向に向けて狭める凸レンズである請求項1乃至3のいずれかに記載の光半導体装置。 4. The optical semiconductor device according to claim 1, wherein the transparent member is a convex lens that narrows a light beam extracted from the light emitting element in the light collecting direction.
  5.  前記発光素子の前記発光面上に載置される枠体であって、該枠体の外周は前記素子基板の外周と同一サイズであり、該枠体の内側壁面は前記発光面から前記集光方向に向けて広がるように傾斜して形成されているキャビティ部材と、
     前記キャビティ部材の前記内側壁面に囲まれた空洞部に充填される蛍光体と、
     を更に備え、
     前記キャビティ部材の前記内側壁面は前記発光部及び前記蛍光体で発光した光を前記集光方向に反射し、
     前記発光素子の前記発光面上に前記キャビティ部材及び前記透明部材が順に積層されて形成される請求項1乃至4のいずれかに記載の光半導体装置。
    A frame body placed on the light emitting surface of the light emitting element, wherein an outer periphery of the frame body is the same size as an outer periphery of the element substrate, and an inner wall surface of the frame body is the light condensing from the light emitting surface A cavity member formed so as to be inclined toward the direction;
    A phosphor filled in a cavity surrounded by the inner wall surface of the cavity member;
    Further comprising
    The inner wall surface of the cavity member reflects light emitted from the light emitting unit and the phosphor in the light collecting direction,
    The optical semiconductor device according to claim 1, wherein the cavity member and the transparent member are sequentially stacked on the light emitting surface of the light emitting element.
  6.  前記発光部ごとにその側面を囲む側面反射膜を更に備え、
     前記側面反射膜は前記発光部で発光して前記素子基板と略平行に進む光を前記集光方向に反射する請求項1乃至5のいずれかに記載の光半導体装置。
    Further comprising a side reflection film surrounding the side surface of each light emitting unit,
    The optical semiconductor device according to claim 1, wherein the side-surface reflecting film reflects light that is emitted from the light-emitting portion and travels substantially parallel to the element substrate in the light collection direction.
  7.  前記キャビティ部材の前記内側壁面は、シリコン基板をエッチングすることにより形成される請求項5又は6に記載の光半導体装置。 The optical semiconductor device according to claim 5 or 6, wherein the inner wall surface of the cavity member is formed by etching a silicon substrate.
  8.  前記キャビティ部材は金属で形成されている請求項5又は6に記載の光半導体装置。 The optical semiconductor device according to claim 5 or 6, wherein the cavity member is made of metal.
  9.  前記発光素子と前記パッケージ基板とが貼り合わされた後に、該発光素子の前記素子基板が除去されて形成される請求項2乃至8のいずれかに記載の光半導体装置。 9. The optical semiconductor device according to claim 2, wherein the light emitting element and the package substrate are bonded together, and then the element substrate of the light emitting element is removed.
  10.  前記発光素子は複数の前記発光部を備え、
     前記素子基板の前記素子電極面又は前記パッケージ基板の前記外部電極が設けられる面には、各前記発光部に供給する電源を選択的に接続又は切断するための給電選択部を備え、
     前記給電選択部により前記発光素子ごとの輝度を調整可能とした請求項1乃至9のいずれかに記載の光半導体装置。
    The light emitting element includes a plurality of the light emitting units,
    The element electrode surface of the element substrate or the surface of the package substrate on which the external electrode is provided includes a power supply selection unit for selectively connecting or disconnecting power supplied to each light emitting unit,
    The optical semiconductor device according to claim 1, wherein brightness for each of the light emitting elements can be adjusted by the power feeding selection unit.
  11.  前記素子基板は透明基板である請求項1乃至10のいずれかに記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the element substrate is a transparent substrate.
  12.  前記素子基板はシリコン基板である請求項1乃至10のいずれかに記載の光半導体装置。 The optical semiconductor device according to claim 1, wherein the element substrate is a silicon substrate.
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