JPWO2010010802A1 - P-channel thin film transistor and manufacturing method thereof - Google Patents
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
ｐ型ＴＦＴが存在しないため、これまで、酸化物ＴＦＴでは、CMOS回路を作成することができなかった。また、陽極に直接ＴＦＴを接続させる単純なAM-OLEDの駆動回路を構成できなかった。Ｓｎ４＋及びＳｎ０（錫金属）の含有量が、合計で１０原子％未満である酸化第一スズ（ＳｎＯ）薄膜を薄膜トランジスタの基板上に堆積し、チャネル層としたことを特徴とするｐチャネル薄膜トランジスタ。気相法において、ＳｎＯをターゲットとして用いて、基板上に堆積するＳｎの酸化度合いを基板温度及び雰囲気酸素分圧により制御して成膜する。Since there is no p-type TFT, it has been impossible to form a CMOS circuit with an oxide TFT. In addition, a simple AM-OLED drive circuit in which the TFT is directly connected to the anode could not be constructed. A p-channel thin film transistor, wherein a stannous oxide (SnO) thin film having a total content of Sn4 + and Sn0 (tin metal) of less than 10 atomic% is deposited on a thin film transistor substrate to form a channel layer. In the vapor phase method, SnO is used as a target, and the degree of oxidation of Sn deposited on the substrate is controlled by the substrate temperature and the atmospheric oxygen partial pressure to form a film.
Description
本発明は、酸化第一スズ（ＳｎＯ）半導体を活性層としたｐチャネル薄膜トランジスタとその製造方法に関する。 The present invention relates to a p-channel thin film transistor having a stannous oxide (SnO) semiconductor as an active layer and a method for manufacturing the same.
アモルファスＳｉ又は多結晶Ｓｉに代り、酸化物を活性層とする薄膜トランジスタ(ＴＦＴ)については、近年、酸化亜鉛を活性層とするトランジスタの研究開発がなされている（非特許文献１〜３、特許文献１〜３）。酸化亜鉛を活性層とするＴＦＴはワイドギャップ半導体を活性層としているため、可視光を透過する透明ＴＦＴが作成できる。従って、液晶ディスプレイのスイッチングトランジスタとして、現在、広く実用化されているシリコンＴＦＴを、酸化亜鉛ＴＦＴで置き換えることにより、液晶素子の開口率を向上させることができると期待されている。しかし、酸化亜鉛は電子キャリア濃度が小さく、真性半導体に近い酸化亜鉛薄膜を得るためには、高価な単結晶基板の使用や高温成膜プロセスが必要となる（非特許文献４，５）。
As for thin film transistors (TFTs) using an oxide as an active layer instead of amorphous Si or polycrystalline Si, research and development of a transistor using zinc oxide as an active layer has recently been made (Non-Patent
本発明者らは2004年にアモルファス酸化物半導体を活性層とするＴＦＴを発表した（非特許文献６，７、特許文献４）。このＴＦＴはアモルファスのインジウム・ガリウム・亜鉛からなる酸化物(a-IGZO)を活性層として用いており、基板加熱なしにアモルファス状態のチャネル層を作製することが出来る。
In 2004, the present inventors announced a TFT using an amorphous oxide semiconductor as an active layer (
a-IGZOをチャネルとするＴＦＴはチャネル中のキャリアの動き易さを表す物性値である電界効果移動度（μＥＦ）が約１０cm2(Vs)-1、オン・オフ（On/Off）比が約１０6という優れたトランジスタ特性を示す。また、チャネルがアモルファス状態であり結晶粒界を含まないことから、試作されたＴＦＴ間のトランジスタ特性のばらつきが極めて少ないことが報告されている（非特許文献８）。従って、a-IGZOをチャネルとすれば、大面積でも特性が均一なＴＦＴが作製できるので、大面積ディスプレイのスイッチングＴＦＴとしての応用を目指した開発が精力的に進められている。TFT with a-IGZO as a channel has a field effect mobility (μ EF ) of about 10 cm 2 (Vs) −1 , which is a physical property value indicating the mobility of carriers in the channel, and an on / off ratio. Shows excellent transistor characteristics of about 10 6 . In addition, since the channel is in an amorphous state and does not include a crystal grain boundary, it has been reported that there is very little variation in transistor characteristics between the fabricated TFTs (Non-patent Document 8). Therefore, if a-IGZO is used as a channel, a TFT having uniform characteristics even in a large area can be manufactured. Therefore, development aiming at application as a switching TFT of a large area display has been vigorously advanced.
以上の様に、2000年以降、酸化物半導体をチャネルとするトランジスタが活発に研究され、実用レベルのｎ型チャンネルＴＦＴが作成されてきたが、ｐチャネルで動作するＴＦＴは作成されていない。その理由は金属酸化物では、伝導帯を構成する電子軌道は金属のｓ軌道であり、電子移動度の大きな化合物が多く存在するのに対して、価電子帯は酸素の２ｐ軌道で構成されているために、価電子帯に存在する正孔の局在性が強く、正孔注入が難しく、また、たとえ注入されても、正孔移動度が小さいためと考えられる。
As described above, since 2000, transistors using an oxide semiconductor as a channel have been actively researched and a practical level n-type channel TFT has been created, but a TFT operating in a p-channel has not been created. The reason for this is that in metal oxides, the electron orbits constituting the conduction band are metal s orbitals, and many compounds with high electron mobility exist, whereas the valence band is constituted by
ｐチャンネルＴＦＴの必要性は、次の二つがある。すなわち、第一に、ＣＭＯＳ回路を形成するためには、ｎチャネルＴＦＴ及びｐチャネルＴＦＴの両者が不可欠である。ＣＭＯＳ回路用ｐチャネルＴＦＴ用材料では、正孔移動度が、０．１ｃｍ２／Ｖ・秒以上あればよい。第二に、有機発光ダイオード（ＯＬＥＤ）の駆動には、ＯＬＥＤの正電極（カソード）とＴＦＴのアノードが結合できるｐチャネルトランジスタが、ｎチャネルトランジスタに比較して、優位性がある。この用途では、ＯＬＥＤは、電流駆動デバイスであるために、ｐチャネル材料のホール移動度が、０．５ｃｍ２／Ｖ・秒以上であることが必要となる。There are two necessity for the p-channel TFT as follows. That is, first, in order to form a CMOS circuit, both an n-channel TFT and a p-channel TFT are indispensable. In the material for p-channel TFTs for CMOS circuits, the hole mobility may be 0.1 cm 2 / V · second or more. Second, for driving an organic light emitting diode (OLED), a p-channel transistor that can couple the positive electrode (cathode) of the OLED and the anode of the TFT has an advantage over the n-channel transistor. In this application, since the OLED is a current-driven device, the hole mobility of the p-channel material needs to be 0.5 cm 2 / V · second or more.
本発明者らは、ｐチャネルのトランジスタに不可欠なｐ型伝導性酸化物化合物に関して、鋭意研究開発を行い、価電子帯を構成する酸素の２ｐ軌道に３ｄ電子軌道を混入させるという開発指針に沿って、これまでに、多くの新規のｐ型導電性酸化物を発見、報告してきた（非特許文献９〜１２）。 The present inventors have conducted intensive research and development on p-type conductive oxide compounds indispensable for p-channel transistors, and in line with the development guidelines for mixing 3d electron orbitals into 2p orbitals of oxygen constituting the valence band. So far, many novel p-type conductive oxides have been discovered and reported (Non-Patent Documents 9 to 12).
さらに、発明者らは、ｓ軌道から価電子帯が構成されるオキシカルコゲナイドは、ｐ型伝導性を示すことを報告してきた（非特許文献１３）。実際に、価電子帯トップが５ｓ軌道から構成される酸化第一スズ（ＳｎＯ）は、ｐ型半導体になると報告されている（非特許文献１４）。また、ＳｎＯの欠陥生成エネルギーについて報告されている（非特許文献１５）。 Furthermore, the inventors have reported that the oxychalcogenide whose valence band is composed of s orbitals exhibits p-type conductivity (Non-patent Document 13). In fact, it has been reported that stannous oxide (SnO) whose valence band top is composed of 5s orbitals becomes a p-type semiconductor (Non-Patent Document 14). In addition, the defect generation energy of SnO has been reported (Non-patent Document 15).
ＳｎＯの薄膜成長に関しては、ＮａＣｌ基板又はサファイヤ基板を用いたエピタキシャル薄膜成長がV.Krasevecらによって報告されている（非特許文献１６）。また、前記非特許文献１４で、X.Q.Panらは、焼成した酸化第二スズ（SnO2）をターゲットとして用い、電子線蒸着法で、ＳｎＯ薄膜の成長を行い、低温成長した場合はアモルファスであるが、約３５０℃の基板温度ではＰｂＯ構造のα−ＳｎＯ相が得られ、６００℃では、エピタキシャルα−ＳｎＯ薄膜が得られると報告している。また、ＳｎＦ2が溶解した溶液を基材の表面に吹き付けて多結晶のＳｎＯ膜を製造する方法が提案されている（特許文献５）。Regarding SnO thin film growth, epitaxial thin film growth using a NaCl substrate or a sapphire substrate has been reported by V. Krasevec et al. (Non-patent Document 16). Further, in Non-Patent Document 14, XQPan et al. Use sintered stannic oxide (SnO 2 ) as a target, grow an SnO thin film by an electron beam evaporation method, and are amorphous when grown at a low temperature. It is reported that an α-SnO phase having a PbO structure is obtained at a substrate temperature of about 350 ° C., and an epitaxial α-SnO thin film is obtained at 600 ° C. In addition, a method of manufacturing a polycrystalline SnO film by spraying a solution in which SnF 2 is dissolved on the surface of a substrate has been proposed (Patent Document 5).
しかし、これらの文献でＳｎＯと記載されている薄膜のホール移動度、キャリア濃度などの半導体電気特性は明らかにされておらず、さらに、これらの薄膜の伝導のタイプ（ｎ又はｐ）も示されていない。また、ＳｎＯ２薄膜をチャネルとするＴＦＴが報告されている（非特許文献１７）。C-W.Ouらは、酸化第二スズ（SnO2）をターゲットとして堆積後アニーリングしたＳｎＯ２薄膜をチャネルとするＴＦＴがｐ型ＴＦＴとして動作することを報告している（非特許文献１８）。しかし、得られたＴＦＴは、電界移動度は、０．１ｃｍ２／Ｖ・秒未満と小さい。However, semiconductor electrical properties such as hole mobility and carrier concentration of thin films described as SnO in these documents have not been clarified, and the conductivity type (n or p) of these thin films is also shown. Not. In addition, a TFT using a SnO 2 thin film as a channel has been reported (Non-patent Document 17). CW. Ou et al. Have reported that a TFT using a SnO 2 thin film annealed after deposition with stannic oxide (SnO 2 ) as a target operates as a p-type TFT (Non-patent Document 18). However, the obtained TFT has a small electric field mobility of less than 0.1 cm 2 / V · sec.
2000年以降、酸化物半導体をチャネルとする薄膜トランジスタ（TFT）は活発に研究されているが、その全てはｎチャネルＴＦＴであり、ｐチャネルで動作する、すなわち正孔をキャリアとして電気伝導する酸化物ＴＦＴは実現していない。その理由は金属酸化物の価電子帯は、主として、酸素の２ｐ軌道で構成されており強く局在しているために、ｐ型伝導性を実現しにくい、また、たとえｐ型伝導性を実現しても、正孔キャリアの電界効果移動度が小さく、トランジスタ動作しないためである。
Since 2000, thin film transistors (TFTs) using oxide semiconductors as channels have been actively researched, but all of them are n-channel TFTs that operate in p-channels, that is, oxides that conduct electricity using holes as carriers. TFT is not realized. The reason is that the valence band of the metal oxide is mainly composed of
ｐ型ＴＦＴが存在しないため、これまで、酸化物ＴＦＴでは、ＣＭＯＳ回路を作成することができなかった。また、陽極に直接ＴＦＴを接続させる単純なＡＭ−ＯＬＥＤの駆動回路を構成できなかった。C-W.Ouら（非特許文献１８）は、酸化第二スズ（SnO2）薄膜をチャネルとするｐ型ＴＦＴを報告しているが、その電界効果移動度は０．０１１cm2(Vs)-1と非常に小さい値であり、上記の様な実用回路には用いることができない。ＣＭＯＳ回路用には、正孔電界効果移動度は０．１cm2(Vs)-1以上であることが必要であり、そのためには、正孔移動度が０．１cm2(Vs)-1以上である薄膜を育成することが不可欠である。Since there is no p-type TFT, a CMOS circuit could not be formed with an oxide TFT until now. In addition, a simple AM-OLED drive circuit in which the TFT is directly connected to the anode could not be constructed. CW.Ou et al. (Non-patent Document 18) have reported a p-type TFT having a stannic oxide (SnO 2 ) thin film as a channel, and its field-effect mobility is 0.011 cm 2 (Vs) −1. This is a very small value and cannot be used in the practical circuit as described above. For CMOS circuits, the hole field-effect mobility needs to be 0.1 cm 2 (Vs) −1 or more, and for that purpose, the hole mobility is 0.1 cm 2 (Vs) −1 or more. It is essential to grow a thin film.
酸化スズには、ＳｎＯとＳｎＯ2の化合物があるが、スズの安定な価数は４価（Sn4+）であり、ＳｎＯ2の状態が一般的である。ＳｎＯ2の組成では、スズは４価陽イオンとして存在し、Ｓｎ４＋の電子配置は(Ｋｒ)５ｓ0５ｐ0であり、空の５ｓ５ｐ軌道が伝導帯を形成し、ｎ型伝導性を示す。５ｓ軌道を価電子帯として利用するためには、５ｓ軌道を電子で満たす必要があり、５ｓ軌道を全部電子で満たすとＳｎ２＋となる。すなわち、価電子帯がｓ軌道から構成されるｐ型伝導体を実現するためには、ＳｎＯ化合物薄膜を作成することが必要である。なお、ＳｎＯの結晶構造は空間群Ｐ４/ｎmmであるが、ＳｎＯ２の結晶構造は、空間群Ｐ４２／ｍｎｍであり、異なる結晶構造を有する。Tin oxide includes SnO and SnO 2 compounds, but the stable valence of tin is tetravalent (Sn 4+ ), and the state of SnO 2 is common. In the composition of SnO 2 , tin exists as a tetravalent cation, the electron configuration of Sn 4+ is (Kr) 5s 0 5p 0 , and an empty 5s5p orbital forms a conduction band and exhibits n-type conductivity. In order to use the 5s orbital as a valence band, it is necessary to fill the 5s orbital with electrons, and when all the 5s orbitals are filled with electrons, Sn 2+ is obtained. That is, in order to realize a p-type conductor whose valence band is composed of s orbitals, it is necessary to create a SnO compound thin film. The crystal structure of SnO is the space group P4 / nmm, but the crystal structure of SnO 2 is the space group P42 / mnm and has a different crystal structure.
酸化第一スズ（SnO）中の２価のスズイオン（Sn2+）は、酸化物として安定な４価と、金属として安定な０価（Sn0＝錫金属）の中間にあるために、酸素分圧が大きい強い酸化雰囲気でも、また、真空中で高温のような強い還元雰囲気でも、価数を２価に保つことが困難である。すなわち、酸素分圧が小さいときは、酸化度が弱く、Ｓｎ0が生じやすい。逆に、酸素分圧が大きいときは、酸化度が強く、Ｓｎ４＋が生成する。従って、成膜室内雰囲気の酸素分圧の制御可能な、すなわち、Ｓｎの酸化度合いの制御が可能なパルスレーザ堆積法(PLD法)やスパッタ法を用いることにより、Ｓｎ４＋及びＳｎ０（錫金属）の含有量が、合計で１０原子％未満のＳｎＯ薄膜を作製することが好ましい。なお、Ｓｎの酸化度合いの制御が可能な成膜法であれば、成膜方法はＰＬＤ法やスパッタ法に限られるものではない。The divalent tin ion (Sn 2+ ) in stannous oxide (SnO) is in the middle of the tetravalent metal oxide and the zero metal metal (Sn 0 = tin metal). Even in a strong oxidizing atmosphere with a large partial pressure or in a strong reducing atmosphere such as a high temperature in a vacuum, it is difficult to keep the valence to be divalent. That is, when the oxygen partial pressure is small, the degree of oxidation is weak and Sn 0 tends to occur. Conversely, when the oxygen partial pressure is large, the degree of oxidation is strong and Sn 4+ is generated. Therefore, Sn 4+ and Sn 0 (tin metal) can be controlled by using a pulsed laser deposition method (PLD method) or a sputtering method that can control the oxygen partial pressure in the film forming chamber atmosphere, that is, the degree of oxidation of Sn. It is preferable to produce a SnO thin film having a total content of less than 10 atomic%. Note that the film formation method is not limited to the PLD method or the sputtering method as long as the film formation method can control the degree of oxidation of Sn.
本発明者らは、後述の実験例１に示す方法で作成したＳｎＯ薄膜の硬Ｘ線光電子スペクトルを測定し、価電子帯として、０２ｐ準位の上にＳｎ５ｓ準位が存在することを確認した。すなわち、価電子帯トップは、５ｓ軌道から構成されていた。また、ＳｎＯ薄膜のゼーベック（Seebeck）係数及びホール（Hall）効果の測定から、該薄膜がｐ型伝導性を示すことを確認した。ホール移動度は、２．４cm2V-1s-1、正孔濃度は、２．５×１０17cm-3であった。得られたＳｎＯ薄膜の正孔移動度の大きさは、アモルファスシリコンより優れており、ｐ型ＺｎＯと同程度である。The present inventors measured the hard X-ray photoelectron spectrum of the SnO thin film prepared by the method shown in Experimental Example 1 described later, and confirmed that the Sn5s level was present above the 02p level as the valence band. . That is, the valence band top was composed of 5s orbitals. Further, from the measurement of the Seebeck coefficient and the Hall effect of the SnO thin film, it was confirmed that the thin film showed p-type conductivity. The hole mobility was 2.4 cm 2 V −1 s −1 and the hole concentration was 2.5 × 10 17 cm -3 . The magnitude of hole mobility of the obtained SnO thin film is superior to that of amorphous silicon and is comparable to that of p-type ZnO.
次に、本発明者らは、後述の実施例１に示す方法でＳｎＯ薄膜を活性層、アモルファスアルミナ薄膜を絶縁層とするトップゲート構造のトランジスタ（図１）を作製した。該トランジスタは、ゲート-ソース間の印加電圧が１０V、ドレイン-ソース間の印加電圧が１０Vの条件下で１４μAの電流変調が得られた。電界効果移動度は線形領域で１．０cm2V-1s-1、飽和領域で０．７cm2V-1s-1、オン・オフ（On/Off）比は１０2であった。該トランジスタは、正孔電界効果移動度が０．５cm2V-1s-1以上であり、ＣＭＯＳ回路用のｐチャネルＴＦＴ及びＯＬＥＤ駆動用のＴＦＴとして用いることができる。Next, the present inventors fabricated a top gate transistor (FIG. 1) having an SnO thin film as an active layer and an amorphous alumina thin film as an insulating layer by the method shown in Example 1 described later. In the transistor, a current modulation of 14 μA was obtained under the condition that the applied voltage between the gate and the source was 10V and the applied voltage between the drain and the source was 10V. The field-effect mobility 1.0 cm 2 V -1 s -1 in the linear region, 0.7 cm 2 V -1 s -1 in the saturation region, the ON-OFF (On / Off) ratio was 10 2. The transistor has a hole field effect mobility of 0.5 cm 2 V −1 s −1 or more, and can be used as a p-channel TFT for a CMOS circuit and a TFT for driving an OLED.
すなわち、本発明は、（１）酸化第一スズ（ＳｎＯ）薄膜を薄膜トランジスタの基板上に堆積し、チャネル層としたことを特徴とするｐチャネル薄膜トランジスタ、である。また、本発明は、（２）前記酸化第一スズ薄膜中のＳｎ４＋及びＳｎ０（錫金属）の含有量が、合計で１０原子％未満であることを特徴とする上記（１）のｐチャネル薄膜トランジスタ、である。また、本発明は、（３）基板が(001)ＹＳＺ単結晶基板であり、ＳｎＯ薄膜がエピタキシャル膜であることを特徴とする上記（１）のｐチャネル薄膜トランジスタ、である。また、本発明は、（４）基板がガラス又はプラスチックであり、ＳｎＯ薄膜がアモルファス膜であることを特徴とする上記（１）のｐチャネル薄膜トランジスタ、である。また、本発明は、（５）正孔移動度が０．１ｃｍ２／Ｖ・秒以上であることを特徴とする上記（１）のｐチャネル薄膜トランジスタ、である。
That is, the present invention is (1) a p-channel thin film transistor characterized in that a stannous oxide (SnO) thin film is deposited on a thin film transistor substrate to form a channel layer. In addition, the present invention provides: (2) the content of Sn 4+ and Sn 0 (tin metal) in the stannous oxide thin film is less than 10 atomic% in total; A channel thin film transistor. The present invention is also the p-channel thin film transistor according to (1) above, wherein (3) the substrate is a (001) YSZ single crystal substrate and the SnO thin film is an epitaxial film. The present invention is (4) the p-channel thin film transistor according to (1) above, wherein the substrate is made of glass or plastic, and the SnO thin film is an amorphous film. The present invention is also (5) the p-channel thin film transistor according to (1) above, wherein the hole mobility is 0.1 cm 2 / V · sec or more.
さらに、本発明は、（６）気相法において、ＳｎＯをターゲットとして用いて、基板上に堆積するＳｎの酸化度合いを基板温度及び雰囲気酸素分圧により制御し、Ｓｎ２＋イオンの含有量が９０原子％以上のＳｎＯ薄膜を成膜することによりチャネル層を形成することを特徴とする上記（１）のｐチャネル薄膜トランジスタの製造方法、である。Further, in the present invention, (6) in the vapor phase method, SnO is used as a target, the degree of oxidation of Sn deposited on the substrate is controlled by the substrate temperature and the atmospheric oxygen partial pressure, and the Sn 2+ ion content is 90%. A method for producing a p-channel thin film transistor according to (1) above, wherein a channel layer is formed by depositing a SnO thin film of at least atomic%.
また、本発明は、（７）上記（６）の方法において、気相法がパルスレーザ堆積法(PLD法)であり、 基板として(001)ＹＳＺ単結晶基板を用い、基板温度５５０℃以上、５９０℃以下としてエピタキシャル膜を堆積することを特徴とする上記（３）の構造のｐチャネル薄膜トランジスタの製造方法、である。 In the method of (7) and (6), the gas phase method is a pulsed laser deposition method (PLD method), a (001) YSZ single crystal substrate is used as a substrate, a substrate temperature of 550 ° C. or higher, An epitaxial film is deposited at a temperature of 590 ° C. or lower, which is a method for manufacturing a p-channel thin film transistor having the structure of (3) above.
また、本発明は、（８）上記（６）の方法において、気相法がパルスレーザ堆積法(PLD法)であり、 基板としてガラス又はプラスチック基板を用い、基板温度を意図的に加熱しない温度としてアモルファス膜を堆積することを特徴とする上記（４）の構造のｐチャネル薄膜トランジスタの製造方法、である。 In the method of (8), the gas phase method is a pulsed laser deposition method (PLD method), and a glass or plastic substrate is used as the substrate, and the substrate temperature is not intentionally heated. A method for producing a p-channel thin film transistor having the structure of (4) above, characterized in that an amorphous film is deposited.
本発明は、ＣＭＯＳ回路用など実用回路に用いることができるｐチャネルで動作する正孔移動度が０．１cm2(Vs)-1以上の酸化物ＴＦＴを提供できるという顕著な効果を奏する。The present invention has a remarkable effect that it can provide an oxide TFT having a hole mobility of 0.1 cm 2 (Vs) −1 or more which can be used in a practical circuit such as a CMOS circuit and operates in a p-channel.
図１は、本発明のＳｎＯエピタキシャル薄膜をチャネルとするＴＦＴの構造の一例であり、基板１上に成膜したチャネル層２、チャネル層の両側にゲート絶縁層３を挟んで形成したソース電極４、ドレイン電極５、ゲート絶縁層３上に形成したゲート電極６からなるトップゲート構造のトランジスタの模式図を示している。本発明は、チャネル層の材料に特徴を有するものであり、本発明のＴＦＴはトップゲート構造に限らず、種々の構造を採用し得る。薄膜トランジスタのチャネルとするＳｎＯ薄膜の膜厚は、１０ｎｍ以上６０ｎｍ以下、特に１５ｎｍ以上５０ｎｍ以下が好ましい。１０ｎｍ未満では、オン電流が減少し、また、６０ｎｍ超では、オフ電流が大きくなり、好ましくない。
FIG. 1 shows an example of the structure of a TFT having a SnO epitaxial thin film of the present invention as a channel, a
本発明の薄膜トランジスタのチャネル層２は、真空容器中で、好ましくは、(001)ＹＳＺ単結晶基板上に、ＳｎＯをターゲットとして用いて、ＳｎＯエピタキシャル薄膜をＰＬＤ法やスパッタ法などで堆積させる成膜工程により形成できる。ＳｎＯ薄膜中に、結晶粒界が存在しないアモルファス状態でもよい。この場合には、基板はガラスやプラスチックを用いることができる。
The
このＳｎＯエピタキシャル薄膜の成膜工程では、Ｓｎ２＋を安定化させ、純度の高い酸化第一スズを形成するために、基板温度を５５０℃から５９０℃以下の範囲とし、成膜室内雰囲気の酸素分圧を適正な範囲に設定する、すなわちＳｎの酸化度合いを純度の高い酸化第一スズを形成するようにコントロールする必要がある。なお、酸素分圧とは、流量制御装置により成膜室内に意図的に導入された酸素ガスの分圧のことを意味する。酸素分圧が小さ過ぎるときは、金属錫が析出し易く、また、酸素分圧が大きすぎるときは、Ｓｎ４＋が析出し易い。金属錫及びＳｎ４＋がそれぞれ５原子％以上析出すると、ＳｎＯエピタキシャル薄膜の結晶構造が変化し、ｐ型伝導性を示さなくなる。したがって、ＳｎＯ薄膜中のＳｎ４＋及びＳｎ０（錫金属）の含有量が、合計で１０原子％未満とする必要がある。ｐ型伝導性が得られる最も適切な酸素分圧の範囲は予め実験的に求めることができるが、好ましい範囲は１×１０-2Pa超、１×１０-1Pa未満である。 In this SnO epitaxial thin film formation process, in order to stabilize Sn 2+ and form high-purity stannous oxide, the substrate temperature is set to a range of 550 ° C. to 590 ° C. It is necessary to set the pressure within an appropriate range, that is, to control the oxidation degree of Sn so as to form stannous oxide having a high purity. Note that the oxygen partial pressure means a partial pressure of oxygen gas intentionally introduced into the film formation chamber by the flow control device. When the oxygen partial pressure is too low, metallic tin is likely to precipitate, and when the oxygen partial pressure is too high, Sn 4+ is likely to precipitate. When metal tin and Sn 4+ are each deposited in an amount of 5 atomic% or more, the crystal structure of the SnO epitaxial thin film changes, and p-type conductivity is not exhibited. Therefore, the total content of Sn 4+ and Sn 0 (tin metal) in the SnO thin film needs to be less than 10 atomic%. Although the most suitable range of oxygen partial pressure at which p-type conductivity can be obtained can be experimentally determined in advance, the preferred range is more than 1 × 10 −2 Pa and less than 1 × 10 −1 Pa.
ＳｎＯエピタキシャル薄膜の成膜方法としては、基板に対向して配置したターゲットに高エネルギー密度のレーザー光をパルス状に照射し、ターゲット表面から原子、分子をプラズマ化して対向する基板上に蒸着させるＰＬＤ
法が好ましい。しかし、Ｓｎ２＋を安定化するように酸化の度合いを制御できれば、スパッタ法など他の成膜法でもよい。As a method for forming a SnO epitaxial thin film, a PLD in which a target disposed opposite to a substrate is irradiated with a pulse of high energy density laser light, and atoms and molecules are converted into plasma from the target surface and deposited on the opposite substrate.
The method is preferred. However, other film forming methods such as sputtering may be used as long as the degree of oxidation can be controlled so as to stabilize Sn 2+ .
ＰＬＤ法の好ましい条件としては、５５０℃以上５９０℃以下に保持した(001)ＹＳＺ単結晶基板上にＳｎＯの焼結体や圧粉体などをターゲットとして用い、酸素分圧を適切な範囲に制御して成膜する。酸素ガスの分圧の制御は、流量計を通して、Ｏ２ガスを成膜室内に導入して行う。As a preferable condition of the PLD method, an oxygen partial pressure is controlled within an appropriate range by using a SnO sintered body or a green compact as a target on a (001) YSZ single crystal substrate maintained at 550 ° C. or more and 590 ° C. or less. To form a film. The partial pressure of oxygen gas is controlled by introducing O 2 gas into the film formation chamber through a flow meter.
基板温度が５５０℃未満では、ＳｎＯ相が得られず、基板温度が５９０℃超では、ＳｎＯ相は得られるものの、Ｓｎ４＋が析出しはじめ、基板温度７００℃の場合には成長速度が０．１nmt/min以下になりＳｎＯ膜が成長しなくなる。これはＳｎＯの融点が７００〜 ９５０℃であり、７００℃以上ではＳｎＯが分解することが理由であると考えられる。成膜時の酸素分圧が１×１０-2
Pa以下ではＳｎＯ相は存在するものの、膜内に金属Ｓｎが含まれる。また、１×１０-1 Pa以上の酸素分圧ではＳｎ４＋を多く含むＳｎＯ層が成長する。If the substrate temperature is less than 550 ° C., an SnO phase cannot be obtained. If the substrate temperature exceeds 590 ° C., an SnO phase is obtained, but Sn 4+ starts to precipitate, and when the substrate temperature is 700 ° C., the growth rate is 0. The SnO film does not grow at 1 nmt / min or less. This is considered to be because SnO has a melting point of 700 to 950 ° C., and SnO decomposes at 700 ° C. or higher. The oxygen partial pressure during film formation is 1 × 10 -2
Although the SnO phase exists below Pa, metal Sn is contained in the film. In addition, an SnO layer containing a large amount of Sn 4+ grows at an oxygen partial pressure of 1 × 10 −1 Pa or higher.
ＳｎＯエピタキシャル薄膜を成膜するには、基板は、これまで知られている成膜基板の中では(001)ＹＳＺ単結晶基板が最も好ましい。(001)ＭｇＯ、(001)ＳＴＯ、(1-102)Ａｌ2Ｏ3等の単結晶基板ではエピタキシャル膜は得られない。基板は、成膜工程に先立ち、高温における熱処理、酸によるエッチング処理などにより表面清浄化処理をしておくことが好ましい。この方法により、ＹＳＺ(100)面上にＳｎＯ(001)面が成長し、ＳｎＯ(100)面はＹＳＺ(1-10)面と同様の４回対称性を示し、ＳｎＯ膜がＹＳＺ単結晶基板上にヘテロエピタキシャル成長したことが分かる。面内では、ＹＳＺ(1-10)面とＳｎＯ(100)面が平行になるように成長する。In order to form a SnO epitaxial thin film, the (001) YSZ single crystal substrate is the most preferable among the known deposition substrates. An epitaxial film cannot be obtained with a single crystal substrate such as (001) MgO, (001) STO, (1-102) Al 2 O 3 or the like. Prior to the film formation step, the substrate is preferably subjected to a surface cleaning treatment by a heat treatment at a high temperature, an etching treatment with an acid, or the like. By this method, a SnO (001) plane grows on the YSZ (100) plane, the SnO (100) plane shows the same 4-fold symmetry as the YSZ (1-10) plane, and the SnO film is a YSZ single crystal substrate. It can be seen that heteroepitaxial growth has occurred. In the plane, the YSZ (1-10) plane and the SnO (100) plane grow in parallel.
以上説明したＳｎＯ薄膜の成長方法により、Ｓｎ２＋を９０原子％以上含む、空間群Ｐ４／ｎｍｍに属する結晶構造を有するＳｎＯ薄膜を得ることができる。得られた薄膜は、ｐ型伝導性を示し、正孔移動度が０．１cm2(Vs)-1以上、より好ましくは、０．５ｃm2(Vs)-1以上、さらには、２．０ｃm2(Vs)-1以上のＳｎＯ薄膜チャネルを形成することができる。By the SnO thin film growth method described above, it is possible to obtain a SnO thin film having a crystal structure belonging to the space group P4 / nmm, containing Sn 2+ of 90 atomic% or more. The obtained thin film exhibits p-type conductivity and has a hole mobility of 0.1 cm 2 (Vs) −1 or more, more preferably 0.5 cm 2 (Vs) −1 or more, and further 2.0 cm. An SnO thin film channel of 2 (Vs) −1 or more can be formed.
ＳｎＯアモルファス薄膜を成膜するには、基板は、ガラス、プラスチックなどを使用することができるが、価格、化学的安定性、表面平坦性の観点から、ガラスが最も好ましい。基板は、成膜工程に先立ち、高温における熱処理、酸によるエッチング処理などにより表面清浄化処理をしておくことが好ましい。ＳｎＯアモルファスの成膜方法としては、基板に対向して配置したターゲットに高エネルギー密度のレーザー光をパルス状に照射し、ターゲット表面から原子、分子をプラズマ化して対向する基板上に蒸着させるＰＬＤ
法が好ましい。しかし、Ｓｎ２＋を安定化するように酸化の度合いを制御できれば、スパッタ法など他の成膜法でもよい。In order to form a SnO amorphous thin film, glass, plastic, or the like can be used as the substrate, but glass is most preferable from the viewpoint of price, chemical stability, and surface flatness. Prior to the film formation step, the substrate is preferably subjected to a surface cleaning treatment by a heat treatment at a high temperature, an etching treatment with an acid, or the like. As a method for forming an SnO amorphous film, a PLD in which a target disposed opposite to a substrate is irradiated with a pulse of high energy density laser light, and atoms and molecules are converted into plasma from the target surface and deposited on the opposite substrate.
The method is preferred. However, other film forming methods such as sputtering may be used as long as the degree of oxidation can be controlled so as to stabilize Sn 2+ .
ＰＬＤ法の好ましい条件としては、基板温度を意図的に加熱しない温度とし、基板上にＳｎＯの焼結体や圧粉体などをターゲットとして用い、酸素分圧を適切な範囲に制御して成膜する。酸素ガスの分圧の制御は、流量計を通して、Ｏ２ガスを成膜室内に導入して行う。成膜時の酸素分圧が１×１０-2
Pa未満ではＳｎ２＋存在するものの、膜内に金属Ｓｎが含まれる。１×１０-2 Pa以上、１×Pa未満では、膜は黒色を呈し、Ｓｎ２＋が９０％超含まれており、ｐ型伝導性を示す。正孔移動度は、０．１ｃm2(Vs)-1超である。また、１Pa以上の酸素分圧ではＳｎ４＋を多く含むＳｎＯ膜が成長し、ｎ型伝導を示す。As a preferable condition of the PLD method, the substrate temperature is set to a temperature at which the substrate is not intentionally heated, a SnO sintered body or a green compact is used as a target on the substrate, and the oxygen partial pressure is controlled within an appropriate range to form a film. To do. The partial pressure of oxygen gas is controlled by introducing O 2 gas into the film formation chamber through a flow meter. The oxygen partial pressure during film formation is 1 × 10 -2
If it is less than Pa, Sn 2+ exists, but metal Sn is contained in the film. If it is 1 × 10 −2 Pa or more and less than 1 × Pa, the film is black and contains Sn 2+ in excess of 90%, indicating p-type conductivity. The hole mobility is greater than 0.1 cm 2 (Vs) −1 . In addition, when the oxygen partial pressure is 1 Pa or more, a SnO film containing a large amount of Sn 4+ grows and exhibits n-type conduction.
ソース電極、ドレイン電極、ゲート絶縁層の形成は通常採用されている材料、方法を用いればよい。ゲート絶縁層としては、アモルファスアルミナ（ａ−Ａｌ２Ｏ３）,Ｓｉ3Ｎ4,ＳｉＯ2を用いることができるが、ａ−Ａｌ２Ｏ３は誘電率(約9)が大きくないため、より誘電率の大きいHigh-k材料であるＨｆＯ2,Ｔａ2Ｏ5,ＺｒＯ2などをゲート絶縁層として用いることが好ましい。ソース電極、ドレイン電極及びゲート電極を形成した後に、ゲートリーク電流を低減するために真空中で、１５０〜３００℃程度の温度で熱処理を行うことが好ましい。さらに詳しく、実験例、比較実験例、実施例に基づいて本発明を説明する。
［実験例］The source electrode, the drain electrode, and the gate insulating layer may be formed using a commonly used material and method. As the gate insulating layer, amorphous alumina (a-Al 2 O 3 ), Si 3 N 4 , or SiO 2 can be used, but since a-Al 2 O 3 does not have a large dielectric constant (about 9), more It is preferable to use HfO 2 , Ta 2 O 5 , ZrO 2 or the like, which is a high-k material having a large dielectric constant, as the gate insulating layer. After forming the source electrode, the drain electrode, and the gate electrode, it is preferable to perform heat treatment at a temperature of about 150 to 300 ° C. in vacuum in order to reduce gate leakage current. In more detail, this invention is demonstrated based on an experiment example, a comparative experiment example, and an Example.
[Experimental example]
(001)ＹＳＺ単結晶基板上にＰＬＤ法でＳｎＯ薄膜を堆積した。(001)ＹＳＺ単結晶基板は、予め大気中にて１３８０℃で加熱処理を行なった。ＰＬＤ装置としてはULVAC社製レーザアブレーション成膜装置を用いた。ターゲットにはＳｎＯ焼結体（高純度化学研究所社製の粉末原料を焼結して作成）を用いて、ＫｒＦエキシマレーザ(波長248nm,パルス幅8ns)を照射してアブレーションを行った。基板とターゲット間の距離は４cmとした。基板温度５７５℃、酸素分圧４×１０-2Pa、繰り返し周波数２Hz、強度約１．５Jcm-2pulse-1の条件で成膜を行い、成膜速度は５．６nm/minであった。膜厚は、１９nmであった。
［比較実験例１〜３］A SnO thin film was deposited on a (001) YSZ single crystal substrate by the PLD method. The (001) YSZ single crystal substrate was previously heat-treated at 1380 ° C. in the air. As the PLD apparatus, a laser ablation film forming apparatus manufactured by ULVAC was used. Using a SnO sintered body (prepared by sintering powder raw material manufactured by Kojundo Chemical Laboratory Co., Ltd.) as a target, KrF excimer laser (wavelength 248 nm,
[Comparative Experimental Examples 1 to 3]
酸素分圧をそれぞれ、１×１０-１Pa（比較実験例１） 、１×１０-2Pa（比較実験例２）、４×１０-３Pa（比較実験例３）とした以外は実験例と同じ条件で成膜を行った。
［比較実験例４〜６］Experimental examples except that the oxygen partial pressures were 1 × 10 −1 Pa (Comparative Experimental Example 1), 1 × 10 −2 Pa (Comparative Experimental Example 2), and 4 × 10 −3 Pa (Comparative Experimental Example 3), respectively. Film formation was performed under the same conditions as those described above.
[Comparative Experimental Examples 4 to 6]
(001)ＹＳＺ単結晶基板に代えて、それぞれ、(001)ＭｇＯ単結晶基板（比較実験例４）、(001)ＳＴＯ単結晶基板（比較実験例５）、(102)Ａｌ2Ｏ3単結晶基板（比較実験例６）を用いた以外は実験例と同じ条件で成膜を行った。Instead of the (001) YSZ single crystal substrate, the (001) MgO single crystal substrate (Comparative Experimental Example 4), the (001) STO single crystal substrate (Comparative Experimental Example 5), and (102) Al 2 O 3 single crystal, respectively. Film formation was performed under the same conditions as in the experimental example except that the substrate (Comparative Experimental Example 6) was used.
作製した薄膜について、（１）Ｘ線回折計による相の同定、成長方位の確認、（２）ＳＰring8(兵庫県)のビームラインBL47XUでの硬Ｘ線光電子分光による価電子帯の観測、（３）原子間力顕微鏡による薄膜表面の観察、（４）紫外−近赤外域(波長範囲200〜2500nm)での光吸収スペクトルの測定、（５）van der pauw法による室温から８０Kまでの温度範囲でのホール(Hall)効果測定を行った。 (1) Phase identification by X-ray diffractometer, confirmation of growth orientation, (2) Observation of valence band by hard X-ray photoelectron spectroscopy at beam line BL47XU at SPring8 (Hyogo), (3 ) Observation of thin film surface with atomic force microscope, (4) Measurement of light absorption spectrum in ultraviolet-near infrared region (wavelength range 200-2500nm), (5) Temperature range from room temperature to 80K by van der pauw method Hall effect measurement was performed.
図２に、Ｘ線回折の結果を示す。Ｘ線回折の結果から成膜時の酸素分圧が１×１０-2 Pa（比較実験例２）以下ではＳｎＯ相は存在するものの、膜内に金属Ｓｎが含まれることが分かった。また、酸素分圧が４×１０-2Pa（実験例）ではＳｎＯ層がエピタキシャル成長した。しかし、酸素分圧を１×１０-1Pa（比較実験例１）以上にすると、Ｓｎ４＋を５原子％超含む多結晶ＳｎＯ層が成長しはじめ、ＳｎＯ２相が生成した。FIG. 2 shows the result of X-ray diffraction. From the results of X-ray diffraction, it was found that when the oxygen partial pressure during film formation was 1 × 10 −2 Pa (Comparative Experimental Example 2) or less, SnO phase was present but metal Sn was contained in the film. In addition, the SnO layer was epitaxially grown at an oxygen partial pressure of 4 × 10 −2 Pa (experimental example). However, when the oxygen partial pressure was set to 1 × 10 −1 Pa (Comparative Experimental Example 1) or higher, a polycrystalline SnO layer containing more than 5 atomic% of Sn 4+ began to grow, and a SnO 2 phase was generated.
次に、実験例の酸素分圧４×１０-2 Paで成膜しエピタキシャル成長したＳｎＯ薄膜について、４軸Ｘ線回折計により成長方位の確認を行った。図３に示すように、ＹＳＺ(100)面上にＳｎＯ(001)面が成長しており、ＹＳＺ(1-10)面とＳｎＯ(100)面が同じ方向を向いていることを示している。002ＳｎＯ回折、200ＳｎＯ回折のロッキングカーブの半値幅はそれぞれ０．４６°、０．７°であった。また、ＳｎＯ(100)面はＹＳＺ(1-10)面と同様の４回対称性を示しており（図３（ｄ））、ＳｎＯ膜がＹＳＺ単結晶基板上にヘテロエピタキシャル成長していることが分かった。エピタキシャル関係は、(001)ＳｎＯ//(001)ＹＳＺ,(100)ＳｎＯ//(1-10)ＹＳＺであった。Next, the growth orientation of the SnO thin film formed and epitaxially grown at an oxygen partial pressure of 4 × 10 −2 Pa in the experimental example was confirmed by a 4-axis X-ray diffractometer. As shown in FIG. 3, the SnO (001) plane has grown on the YSZ (100) plane, and the YSZ (1-10) plane and the SnO (100) plane are in the same direction. . The half-value widths of the rocking curves of 002SnO diffraction and 200SnO diffraction were 0.46 ° and 0.7 °, respectively. In addition, the SnO (100) plane shows the same four-fold symmetry as the YSZ (1-10) plane (FIG. 3 (d)), and the SnO film is heteroepitaxially grown on the YSZ single crystal substrate. I understood. The epitaxial relationship was (001) SnO // (001) YSZ, (100) SnO // (1-10) YSZ.
比較実験例４〜６の(001)ＭｇＯ、(001)ＳＴＯ、(1-102)Ａｌ2Ｏ3単結晶基板上にＳｎＯ薄膜成長を行なった場合は、図３（ａ）に示すとおり、いずれの場合もＹＳＺ基板上に比べて、Ｘ線回折強度で２桁程度低下しておりＹＳＺ基板上に作製した場合のようなエピタキシャル膜は得られなかった。When SnO thin film growth was performed on the (001) MgO, (001) STO, and (1-102) Al 2 O 3 single crystal substrates of Comparative Experimental Examples 4 to 6, as shown in FIG. In this case, the X-ray diffraction intensity was reduced by about two orders of magnitude compared with that on the YSZ substrate, and an epitaxial film as produced on the YSZ substrate could not be obtained.
図４に、０１sピークが５３１eVとなるように結合エネルギーを決定した場合のＳｎＯ薄膜の価電子帯硬Ｘ線光電子分光スペクトルを示す。参照試料として測定したＳｎＯ2のスペクトルと比較して、(Ｋｒ)５ｓ2電子配置であるＳｎＯのスペクトルでは０２ｐ軌道の上に新しい準位が形成された。また、ＳｎＯ薄膜のフェルミ準位は状態密度がゼロになる、すなわち価電子帯のトップの位置にある。代表的なｎ型導電性酸化物であるＳｎＯ2の場合は、フェルミ準位は、伝導帯のボトムの位置にある。硬Ｘ線光電子分光の測定結果は、ＳｎＯにおいて０２ｐ軌道の高エネルギー側にＳｎ５ｓ準位が存在し、価電子帯を形成したことを示すものである。 FIG. 4 shows a valence band hard X-ray photoelectron spectrum of the SnO thin film when the binding energy is determined so that the 01s peak is 531 eV. Compared with the spectrum of SnO 2 measured as a reference sample, a new level was formed on the 02p orbit in the spectrum of SnO having the (Kr) 5s 2 electron configuration. Further, the Fermi level of the SnO thin film has a density of states of zero, that is, is at the top position of the valence band. In the case of SnO 2 which is a typical n-type conductive oxide, the Fermi level is at the bottom of the conduction band. The measurement result of hard X-ray photoelectron spectroscopy shows that Sn5s level is present on the high energy side of the 02p orbital in SnO and a valence band is formed.
実験例に示す条件で作製したＳｎＯ薄膜表面の原子間力顕微鏡像を図５に示す。ＳｎＯのｃ軸長約０．５nmに相当する高さのステップが薄膜表面に見られる。１０μm四方の像では一様の表面が観察され、最大高低差は３．３nmであった。１μm四方で観察した像では細かい島状の構造が観察され、さらに拡大して断面高低差を見ると約０．５nm高さの段差が観察された。観察された段差の高さ０．５nmはＳｎＯ(001)面の間隔０．４８３６nmとよく一致しており、薄膜がステップ・テラス構造をしていることが分かった。 An atomic force microscope image of the surface of the SnO thin film produced under the conditions shown in the experimental example is shown in FIG. A step having a height corresponding to the c-axis length of SnO of about 0.5 nm is observed on the thin film surface. A uniform surface was observed in the 10 μm square image, and the maximum height difference was 3.3 nm. In the image observed at 1 μm square, a fine island-like structure was observed, and when the cross-sectional height difference was further enlarged, a step with a height of about 0.5 nm was observed. The observed height 0.5 nm of the step was in good agreement with the SnO (001) plane spacing of 0.4836 nm, indicating that the thin film had a step-and-terrace structure.
図６に、エピタキシャルＳｎＯ薄膜の光吸収係数αと光子エネルギーhνの関係を示す。図６(ｂ)に示す(αhν)2−hνプロットから見積もった直接遷移光学ギャップは２．７eV程度であり、報告されている（R. Sivaramasubramaniam et al., Phys. stat. sol.,(a)136,215(1993)）値と一致した。FIG. 6 shows the relationship between the light absorption coefficient α and the photon energy hν of the epitaxial SnO thin film. The direct transition optical gap estimated from the (αhν) 2 -hν plot shown in FIG. 6B is about 2.7 eV, which has been reported (R. Sivaramasubramaniam et al., Phys. Stat. Sol., (A ) 136,215 (1993)) values.
しかし、光吸収係数は光子エネルギー１．６eV付近から緩やかに立ち上がっており、遷移確率の低い間接遷移があることが考えられる。第一原理計算の結果は、間接ギャップの存在を示しており、間接ギャップは約０．３eV 、直接ギャップは約２．２eVと求められている（非特許文献１５）。第一原理計算は実験値よりもバンドギャップを小さく見積もる傾向があり、ＳｎＯは間接ギャップを有する間接半導体と考えられる。 However, the light absorption coefficient rises gently from around the photon energy of 1.6 eV, and it is considered that there is an indirect transition with a low transition probability. The result of the first principle calculation indicates the presence of an indirect gap, and the indirect gap is calculated to be about 0.3 eV and the direct gap is about 2.2 eV (Non-patent Document 15). The first-principles calculation tends to estimate the band gap smaller than the experimental value, and SnO is considered to be an indirect semiconductor having an indirect gap.
実験例において作製したＳｎＯエピタキシャル薄膜の電気特性を明らかにするためにゼーベック（Seebeck）効果測定、ホール（Hall）効果測定を行った。図７（ａ）に示すように、室温でのゼーベック（Seebeck）係数はＳ＝＋１０２４mVK-1であり、ＳｎＯ薄膜が正孔をキャリアとして電気伝導しているｐ型伝導体であることが示された。さらに、室温〜８０Kの温度範囲でホール（Hall）効果測定結果から、正孔移動度、正孔濃度を算出した。室温での正孔移動度、正孔濃度はそれぞれ２．４cm2(Vs)-1、２．５×１０17cm-3であった。図７（ｂ）に示すとおり、正孔濃度は、温度とともに増大する熱活性型を示し、正孔濃度の活性化エネルギーは４５．６mV/Kであった。また、正孔移動度も温度とともに増大した。In order to clarify the electrical characteristics of the SnO epitaxial thin film prepared in the experimental example, the Seebeck effect measurement and the Hall effect measurement were performed. As shown in FIG. 7A, the Seebeck coefficient at room temperature is S = + 1024 mVK −1 , indicating that the SnO thin film is a p-type conductor that conducts electricity using holes as carriers. It was. Furthermore, the hole mobility and hole concentration were calculated from the Hall effect measurement results in the temperature range of room temperature to 80K. The hole mobility and hole concentration at room temperature were 2.4 cm 2 (Vs) −1 and 2.5 × 10 17 cm -3 , respectively. As shown in FIG. 7B, the hole concentration showed a thermally activated type that increased with temperature, and the activation energy of the hole concentration was 45.6 mV / K. Also, the hole mobility increased with temperature.
エピタキシャルＳｎＯ薄膜をチャネルとして、図１に示す構造のトップゲート型ＴＦＴを作製した。まず、ＴＦＴのチャネルとして(001)ＹＳＺ単結晶基板上に実験例の条件で厚さ１９nmのＳｎＯ層を成膜した。次に、フォトリソグラフィーと電子線蒸着法によりＡｕ(20nmt)/Ｎｉ(8nmt)層からなるソース電極及びドレイン電極を作製した。その後、ソース電極、ドレイン電極及びチャネル上にＰＬＤ法によりアモルファスアルミナ（ａ−Ａｌ２Ｏ３）ゲート絶縁層を成膜した。Using the epitaxial SnO thin film as a channel, a top gate type TFT having the structure shown in FIG. 1 was produced. First, an SnO layer having a thickness of 19 nm was formed on a (001) YSZ single crystal substrate as a TFT channel under the conditions of the experimental example. Next, a source electrode and a drain electrode composed of an Au (20 nmt) / Ni (8 nmt) layer were produced by photolithography and electron beam evaporation. Thereafter, an amorphous alumina (a-Al 2 O 3 ) gate insulating layer was formed on the source electrode, the drain electrode, and the channel by a PLD method.
ａ−Ａｌ２Ｏ３ゲート絶縁層の成膜条件は、基板温度２０℃、酸素分圧２Pa、ＡｒＦレーザー繰り返し周波数１０Hz 、強度約２Jcm-2pulse-1として、絶縁層膜厚は２１０nmとした。その後、フォトリソグラフィーと電子線蒸着法によりＡｕ(20nmt)/Ｎｉ(8nmt)層からなるゲート電極を作製した。チャネル長(L)及びチャネル幅(W)はＬ／Ｗ＝５０／３００μmとした。ソース電極、ドレイン電極及びゲート電極を形成した後に、ゲートリーク電流を低減するために真空中で、１５０℃、５分間の条件と２００℃、５分間の条件で、赤外線ランプ加熱による高速熱処理を行った。図８に示すように、２００℃で熱処理することにより１０nAであったリーク電流を０．１nA未満に低減することが出来た。The film formation conditions for the a-Al 2 O 3 gate insulating layer were as follows: the substrate temperature was 20 ° C., the oxygen partial pressure was 2 Pa, the ArF laser repetition frequency was 10 Hz, the intensity was about 2 Jcm −2 pulse −1 , and the insulating layer thickness was 210 nm. Thereafter, a gate electrode composed of an Au (20 nmt) / Ni (8 nmt) layer was produced by photolithography and electron beam evaporation. The channel length (L) and channel width (W) were L / W = 50/300 μm. After forming the source electrode, drain electrode, and gate electrode, rapid heat treatment is performed by heating with an infrared lamp in vacuum at 150 ° C. for 5 minutes and at 200 ° C. for 5 minutes in order to reduce gate leakage current. It was. As shown in FIG. 8, the leakage current, which was 10 nA, was reduced to less than 0.1 nA by heat treatment at 200 ° C.
２００℃で熱処理したＴＦＴに関して、大気中、暗所にて、出力特性、伝達特性の解析を行った。図９に示すとおり、ｐチャネルで動作することが分かる。また、図９（ａ）に示す出力特性で示されるように、ゲート−ソース間の印加電圧が１０V、ドレイン−ソース間の印加電圧が１０Vのバイアス条件下で１４μAの電流変調が得られた。 Regarding the TFT heat-treated at 200 ° C., the output characteristics and transfer characteristics were analyzed in the air in the dark. As shown in FIG. 9, it can be seen that it operates on the p-channel. Further, as shown by the output characteristics shown in FIG. 9A, a current modulation of 14 μA was obtained under a bias condition in which the applied voltage between the gate and the source was 10V and the applied voltage between the drain and the source was 10V.
図９（ｃ）に示すように、(IDS)1/2−VGプロットから求めた閾値電圧は＋４．８V程度であり、該ＴＦＴはｐチャネルディプレッション型であることがわかる。As shown in FIG. 9 (c), (I DS ) threshold voltage obtained from 1/2 -V G plot is about + 4.8 V, it can be seen that the TFT is a p-channel depletion type.
ＴＦＴの電界効果移動度は、線形領域で１．２cm2(Vs)-1 、飽和領域で０．７cm2V-1s-1、オン・オフ比は約１０2であった。飽和領域の移動度が線形領域の移動度より小さくなっているが、これはゲートに印加した電圧ではチャネルをピンチオフさせることができないためと考えられる。すなわち、該ＴＦＴのチャネルには高濃度のキャリア（約2.5×1017cm-3）が含まれており、アモルファスアルミナゲート絶縁膜では誘電率が十分大きくない(誘電率＝約9)ために、チャネルをピンチオフすることができず、また、空乏層を作ることが出来なかったために、小さい飽和移動度、小さいオン・オフ比という結果をもたらしていると考えられる。The field effect mobility of the TFT was 1.2 cm 2 (Vs) −1 in the linear region, 0.7 cm 2 V −1 s −1 in the saturation region, and the on / off ratio was about 10 2 . The mobility of the saturation region is smaller than that of the linear region, which is considered to be because the channel cannot be pinched off by the voltage applied to the gate. That is, the channel of the TFT contains a high concentration of carriers (about 2.5 × 10 17 cm −3 ), and the dielectric constant of the amorphous alumina gate insulating film is not sufficiently large (dielectric constant = about 9). The channel could not be pinched off and a depletion layer could not be formed, which is considered to result in a low saturation mobility and a low on / off ratio.
線形領域、飽和領域での電界効果移動度μｌｉｎ．及びμｓａｔ．は、それぞれgm=(W/L)μlin.C0VGS、IDS=(Wμsat.C0/2L)(VGS−VT)2で定義される。ここで、gm、C0、VTは、それぞれ伝達コンダクタンス、単位面積あたりのゲート容量、閾値電圧であり、伝達コンダクタンスgmは、gm=∂IDS/∂VGSで与えられる。Field effect mobility in the linear region and saturation region μ lin. And μ sat. Are defined by g m = (W / L) μ lin. C 0 V GS and I DS = (W μ sat. C 0 / 2L) (V GS −V T ) 2 , respectively. Here, g m , C 0 , and V T are transfer conductance, gate capacitance per unit area, and threshold voltage, respectively, and transfer conductance g m is given by g m = ∂I DS / ∂V GS .
実施例１より誘電率の大きいHigh-k材料を絶縁層としてＴＦＴを作製した。ＹＳＺ(001)単結晶基板上にＳｎＯ(001)/ＺｒＯ2：ＹＳＺ(001)/ＩＴＯ(001)/ＹＳＺ(001)からなるチャネル層−絶縁層−ゲート電極層の全てをエピタキシャル成長させた１０mm角の積層膜を作製し、ボトムゲート型のＴＦＴを作製した。絶縁層以外の層の形成は実施例１と同様に行った。該ＴＦＴでは、誘電率が大きな（＝約２５）ＹＳＺ（Ｙ安定ジルコニア）エピタキシャル薄膜をゲート絶縁膜として使用しているため、飽和移動度及びオン・オフ比が増大した。A TFT was manufactured using a high-k material having a dielectric constant higher than that of Example 1 as an insulating layer. 10 mm square obtained by epitaxially growing all of channel layer-insulating layer-gate electrode layer made of SnO (001) / ZrO 2 : YSZ (001) / ITO (001) / YSZ (001) on a YSZ (001) single crystal substrate. A bottom gate type TFT was produced. Formation of layers other than the insulating layer was performed in the same manner as in Example 1. In the TFT, a YSZ (Y stable zirconia) epitaxial thin film having a large dielectric constant (= about 25) is used as a gate insulating film, so that the saturation mobility and the on / off ratio are increased.
有機ＬＥＤ（ＯＬＥＤ）デバイスは、ｐチャネルＴＦＴ駆動の方が、ｎチャネルＴＦＴ駆動に比べて、配線が容易である。また、フラットパネルディスプレイの周辺回路素子など、ＣＭＯＳ回路を構成するために、ｐチャネルＴＦＴは不可欠である。本発明は、特にこれらのデバイス、回路に有用である。 Organic LED (OLED) devices are easier to wire with p-channel TFT drive than with n-channel TFT drive. Further, a p-channel TFT is indispensable for constituting a CMOS circuit such as a peripheral circuit element of a flat panel display. The present invention is particularly useful for these devices and circuits.
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