JPWO2006068000A1 - COF substrate laminate, method for producing the same, and COF film carrier tape formed using this COF substrate laminate - Google Patents

COF substrate laminate, method for producing the same, and COF film carrier tape formed using this COF substrate laminate Download PDF

Info

Publication number
JPWO2006068000A1
JPWO2006068000A1 JP2006548842A JP2006548842A JPWO2006068000A1 JP WO2006068000 A1 JPWO2006068000 A1 JP WO2006068000A1 JP 2006548842 A JP2006548842 A JP 2006548842A JP 2006548842 A JP2006548842 A JP 2006548842A JP WO2006068000 A1 JPWO2006068000 A1 JP WO2006068000A1
Authority
JP
Japan
Prior art keywords
insulating layer
conductor
laminate
cof
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006548842A
Other languages
Japanese (ja)
Other versions
JP5064035B2 (en
Inventor
克也 岸田
克也 岸田
彰 嶋田
彰 嶋田
裕一 徳田
裕一 徳田
妙子 財部
妙子 財部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Chemical and Materials Co Ltd
Original Assignee
Nippon Steel Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Chemical Co Ltd filed Critical Nippon Steel Chemical Co Ltd
Priority to JP2006548842A priority Critical patent/JP5064035B2/en
Publication of JPWO2006068000A1 publication Critical patent/JPWO2006068000A1/en
Application granted granted Critical
Publication of JP5064035B2 publication Critical patent/JP5064035B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/002Etching of the substrate by chemical or physical means by liquid chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • H05K1/0269Marks, test patterns or identification means for visual or optical inspection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0108Transparent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0191Dielectric layers wherein the thickness of the dielectric plays an important role
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer

Abstract

絶縁層を透過してドライバICチップの配線を認識することが可能であると共に、導体と絶縁層との間の接着力が高く、耐エレクトロマイグレーション性に優れ、例えば30μmピッチ以下の微細加工可能な積層体とその製造方法を提供する。導電性金属箔よりなる導体の一方の面に絶縁性樹脂よりなる絶縁層が形成されたCOF基板用積層体であり、導体の厚みが1〜8μmであり、導体の絶縁層と接している面の表面粗さRzが1.0μm以下であり、かつ、導体の絶縁層と接していない面の表面粗さRzが1 .0μm以下であるCOF基板用積層体であり、また、少なくとも10μm以上の厚みを有し、かつ、一方の面の表面粗さRzが1.0μm以下である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接していない導電性金属箔の面を化学研摩しこの導電性金属箔の厚みを1〜8μmにすると共に、表面粗さRzを1.0μm以下にして導体を形成するCOF基板用積層体の製造方法である。It is possible to recognize the wiring of the driver IC chip through the insulating layer, and has a high adhesive force between the conductor and the insulating layer, and is excellent in electromigration resistance. For example, it can be finely processed with a pitch of 30 μm or less. A laminate and a method for manufacturing the same are provided. COF substrate laminate in which an insulating layer made of an insulating resin is formed on one side of a conductor made of conductive metal foil, the thickness of the conductor being 1-8 μm, and the surface in contact with the insulating layer of the conductor COF substrate laminate having a surface roughness Rz of 1.0 μm or less and a surface roughness Rz of the surface not contacting the conductor insulating layer of 1.0 μm or less, and a thickness of at least 10 μm or more An insulating layer is formed on the surface of the conductive metal foil having a surface roughness Rz of 1.0 μm or less on one surface, and the surface of the conductive metal foil not in contact with the insulating layer is chemically polished. This is a method for manufacturing a laminate for a COF substrate in which the conductive metal foil has a thickness of 1 to 8 μm and a surface roughness Rz of 1.0 μm or less to form a conductor.

Description

本発明は、COF用途として使用するフレキシブルプリント基板用の積層体とその製造方法に関するものである。   The present invention relates to a laminate for a flexible printed circuit board used for COF applications and a method for producing the same.

テープキャリアにドライバICを実装するTAB方式(テープ・オートメイティッド・ボンディング)は、液晶表示素子(LCD)を使用するような電子産業において広く用いられている。   A TAB method (tape automated bonding) in which a driver IC is mounted on a tape carrier is widely used in the electronic industry using a liquid crystal display element (LCD).

また、近時では、より小さいスペースで、より高密度の実装を行う実装方法として、裸のICチップをフィルムキャリアテープ上に直接搭載するCOF(チップ・オン・フィルム)が開発されている。   Recently, COF (chip-on-film), in which a bare IC chip is directly mounted on a film carrier tape, has been developed as a mounting method for mounting at a higher density in a smaller space.

このCOFに用いられるフレキシブルプリント基板(FPC)は、TAB方式で用いられてきたデバイスホールを有しないため、チップ実装時の相対位置を測定する際、絶縁層を透過してドライバICチップの配線を認識する必要がある。特に、このCOFに用いられるフレキシブルプリント基板(FPC)においては、配線の狭ピッチ化が進み、微細加工が可能である必要がある。   Since the flexible printed circuit board (FPC) used in this COF does not have the device holes that have been used in the TAB method, when measuring the relative position during chip mounting, the wiring of the driver IC chip is transmitted through the insulating layer. Need to recognize. In particular, in a flexible printed circuit board (FPC) used for this COF, it is necessary that the pitch of wiring advances and fine processing is possible.

このようなCOF用のFPCに用いられる積層体としては、ポリイミドフィルムなどの絶縁フィルムにニッケルなどの密着強化層をスパッタした後、銅メッキを施した積層体がある。このような銅メッキ積層体では、ポリイミドフィルムが比較的透明であるので、IC搭載の際の位置合わせが容易ではあるが、導体と絶縁層との間の接着力が弱く、また、耐エレクトロマイグレーション性に劣るといった問題がある。   As a laminated body used for such an FPC for COF, there is a laminated body obtained by sputtering an adhesion reinforcing layer such as nickel on an insulating film such as a polyimide film and then performing copper plating. In such a copper-plated laminate, since the polyimide film is relatively transparent, the alignment during IC mounting is easy, but the adhesive force between the conductor and the insulating layer is weak, and the electromigration resistance There is a problem of inferiority.

上記のような課題を解決する積層体としては、銅箔にポリイミドフィルムを塗布法により積層したキャスティングタイプのものや、銅箔に熱可塑性樹脂や熱硬化性樹脂などを介して絶縁フィルムを熱圧着した熱圧着タイプのものなどがある。   As a laminate that solves the above-mentioned problems, a cast-type laminate in which a polyimide film is laminated on a copper foil by a coating method, or an insulating film is thermocompression bonded to the copper foil via a thermoplastic resin or a thermosetting resin. There is a thermocompression bonding type.

しかしながら、キャスティングタイプの積層体や熱圧着タイプの積層体については、導体と絶縁層との接着力の問題をある程度解消するものの、例えば銅箔をエッチングで除去した領域については、銅箔の粗度(表面粗さ)が絶縁層側に転写されてしまい、絶縁層の表面が光を乱反射して絶縁層を透過して銅パターンが認識できないといった問題がある。   However, for casting-type laminates and thermocompression-type laminates, the problem of adhesion between the conductor and the insulating layer is solved to some extent. For example, in the region where the copper foil is removed by etching, the roughness of the copper foil There is a problem that the (surface roughness) is transferred to the insulating layer side, and the surface of the insulating layer irregularly reflects light and passes through the insulating layer so that the copper pattern cannot be recognized.

そこで、特開2003−23046号公報では、導体層と絶縁層とが積層された構造を有し、この導体層の絶縁層と接する面の表面粗さが0.1〜1.8μmである積層体が開示されている。しかしながら、上記積層体は、絶縁層を透過してドライバICチップの配線を認識する問題についてはある程度解消はされるものの、例えば30μmピッチ以下を必要とするような高密度基板材料としては必ずしも満足出来るものではない。一方、特開2004-142183号公報には絶縁層と接している面の表面粗さが1.0μm以下で裏面の表面粗さが2.0μm以下である積層体が記載されている。しかしながら、絶縁層と接していない面の表面粗さが大きい場合、レジスト形成時に厚みムラが生じ、その後の配線回路のパターニング工程で回路の直線性を良好にするのが困難であった。また、導体の厚さが厚い場合にも、同様に回路の直線性の確保が難しく、特に、30μmピッチ以下の微細加工が困難であった。すなわち、絶縁層側の粗度とレジスト面側の粗度とが適切であって、微細加工の要求を満足できる積層体はなかった。
特開2003−23046号公報 特開2004-142183号公報
Therefore, Japanese Patent Application Laid-Open No. 2003-23046 discloses a laminate having a structure in which a conductor layer and an insulating layer are laminated, and the surface roughness of the surface of the conductor layer in contact with the insulating layer is 0.1 to 1.8 μm. Has been. However, although the above-mentioned laminated body can solve the problem of recognizing the wiring of the driver IC chip through the insulating layer to some extent, it is not always satisfactory as a high-density substrate material that requires a pitch of 30 μm or less, for example. It is not a thing. On the other hand, Japanese Unexamined Patent Application Publication No. 2004-142183 describes a laminate in which the surface roughness of the surface in contact with the insulating layer is 1.0 μm or less and the surface roughness of the back surface is 2.0 μm or less. However, when the surface roughness of the surface not in contact with the insulating layer is large, thickness unevenness occurs during resist formation, and it is difficult to improve the linearity of the circuit in the subsequent patterning process of the wiring circuit. Also, when the conductor is thick, it is difficult to ensure the linearity of the circuit, and in particular, it is difficult to perform fine processing with a pitch of 30 μm or less. That is, there was no laminated body in which the roughness on the insulating layer side and the roughness on the resist surface side were appropriate and could satisfy the requirements for fine processing.
JP 2003-23046 A JP 2004-142183 A

そこで、本発明では、絶縁層を透過してドライバICチップの配線を認識することが可能であると共に、導体と絶縁層との間の接着力が高く、耐エレクトロマイグレーション性に優れ、例えば30μmピッチ以下の微細加工可能な積層体とその製造方法を提供することを目的とする。   Therefore, in the present invention, it is possible to recognize the wiring of the driver IC chip through the insulating layer, and the adhesive strength between the conductor and the insulating layer is high, and the electromigration resistance is excellent, for example, a pitch of 30 μm. An object of the present invention is to provide the following microfabricated laminate and a method for producing the same.

上記問題点を解決するために、本発明者等が鋭意検討した結果、積層体を形成する導体を所定の厚みにすると共に、この導体の絶縁層と直接接している面の表面粗さRzを1.0μm以下にし、かつ、絶縁層と接していない面の表面粗さRzを1.0μm以下にすることによって、上記課題を解決し得ることを見出し、本発明を完成した。なお、表面粗さRzは「10点平均粗さ」を表し、JIS B 0601に準じて測定される。   In order to solve the above problems, the present inventors have intensively studied. As a result, the conductor forming the laminated body has a predetermined thickness, and the surface roughness Rz of the surface in direct contact with the insulating layer of the conductor is set. The inventors have found that the above problem can be solved by setting the surface roughness Rz of the surface not in contact with the insulating layer to 1.0 μm or less and 1.0 μm or less, thereby completing the present invention. The surface roughness Rz represents “10-point average roughness” and is measured according to JIS B 0601.

したがって、本発明は、導電性金属箔よりなる導体の一方の面に絶縁性樹脂よりなる絶縁層が形成されたCOF基板用積層体であって、導体の厚みが1〜8μmであり、導体の絶縁層と接している面の表面粗さRzが1.0μm以下であり、かつ、導体の絶縁層と接していない面の表面粗さRzが1.0μm以下である、COF基板用積層体である。
また、本発明は、導体の一方の面に絶縁性樹脂よりなる絶縁層が形成されたCOF基板用積層体の製造方法であって、少なくとも10μm以上の厚みを有し、かつ、一方の面の表面粗さRzが1.0μm以下である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接していない導電性金属箔の面を化学研摩してこの導電性金属箔の厚みを1〜8μmにすると共に、表面粗さRzを1.0μm以下にして導体を形成する、COF基板用積層体の製造方法である。
Therefore, the present invention is a COF substrate laminate in which an insulating layer made of an insulating resin is formed on one surface of a conductor made of a conductive metal foil, the thickness of the conductor being 1 to 8 μm, This is a COF substrate laminate in which the surface roughness Rz of the surface in contact with the insulating layer is 1.0 μm or less and the surface roughness Rz of the surface not in contact with the insulating layer of the conductor is 1.0 μm or less.
Further, the present invention is a method for manufacturing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, and has a thickness of at least 10 μm or more. An insulating layer is formed on the surface of the conductive metal foil having a surface roughness Rz of 1.0 μm or less, and the surface of the conductive metal foil not in contact with the insulating layer is chemically polished to reduce the thickness of the conductive metal foil. This is a method for producing a laminated body for a COF substrate, wherein the conductor is formed with a surface roughness Rz of 1.0 μm or less while being 1-8 μm.

本発明では、絶縁層と直接接している導体の表面粗さRzを1.0μm以下とすることにより、仮に絶縁層との積層時に導体の粗度が絶縁層側に転写されても、絶縁層を透過してドライバICチップの配線を認識することが可能となる。また、絶縁層と直接接していない導体の表面粗度Rzが1.0μm以下とすることにより、高密度配線を必要とする場合において例えば30μmピッチ以下の加工が可能である。なお、絶縁層と直接接している導体の表面粗さRzは、絶縁層との密着性を確保するためRzは0.3μmが下限であり、絶縁層と直接接していない導体の表面粗度Rzは、後に積層される絶縁性保護膜との密着性を確保するためRzは0.1μmが下限である。   In the present invention, by setting the surface roughness Rz of the conductor in direct contact with the insulating layer to 1.0 μm or less, even if the roughness of the conductor is transferred to the insulating layer side during lamination with the insulating layer, the insulating layer The wiring of the driver IC chip can be recognized through the transmission. Further, by setting the surface roughness Rz of the conductor not in direct contact with the insulating layer to 1.0 μm or less, processing with a pitch of 30 μm or less is possible when high-density wiring is required. The surface roughness Rz of the conductor that is in direct contact with the insulating layer has a lower limit of 0.3 μm for ensuring the adhesion with the insulating layer, and the surface roughness Rz of the conductor that is not in direct contact with the insulating layer is The lower limit of Rz is 0.1 μm in order to ensure adhesion with an insulating protective film to be laminated later.

本発明における導電性金属箔よりなる導体については、例えば銅又は銅合金からなる銅箔のほか、金、銀等からなる金属箔を挙げることができ、好ましくは銅箔であるのがよい。銅箔については圧延銅箔、電解銅箔等を挙げることができるが、絶縁物である酸化物が混在するおそれを可及的に低減できる電解銅箔が更に好ましい。   Examples of the conductor made of the conductive metal foil in the present invention include a copper foil made of copper or a copper alloy, a metal foil made of gold, silver or the like, and preferably a copper foil. Examples of the copper foil include a rolled copper foil and an electrolytic copper foil, but an electrolytic copper foil that can reduce as much as possible the possibility of mixing an oxide that is an insulator is more preferable.

また、本発明においては、導体の厚みを1〜8μmとする。導体の厚みが1μmより小さいと化学研磨工程時に厚さ制御が困難であると共に信頼性を充分に得ることが出来ない。反対に8μmより大きくなると例えば30μmピッチ加工時に、導体の直線性を得る事が非常に難しくなる。   Moreover, in this invention, the thickness of a conductor shall be 1-8 micrometers. If the thickness of the conductor is smaller than 1 μm, it is difficult to control the thickness during the chemical polishing process and sufficient reliability cannot be obtained. On the other hand, if it is larger than 8 μm, it becomes very difficult to obtain the linearity of the conductor when processing a pitch of 30 μm, for example.

本発明によれば、絶縁層を透過してドライバICチップの配線を認識することが可能であり、導体と絶縁層との間の接着力が高く、耐エレクトロマイグレーション性に優れ、例えば30μmピッチ以下の微細加工が可能な積層体を得ることができる。   According to the present invention, it is possible to recognize the wiring of the driver IC chip through the insulating layer, the adhesive strength between the conductor and the insulating layer is high, the electromigration resistance is excellent, for example, 30 μm pitch or less It is possible to obtain a laminate that can be finely processed.

以下、本発明を詳細に説明する。尚、以下では電解銅箔を用いて積層体を形成する例を説明するが、本発明における積層体とこれを得るための方法については下記の内容に限定されるものではない。   Hereinafter, the present invention will be described in detail. In addition, although the example which forms a laminated body using electrolytic copper foil below is demonstrated, the laminated body in this invention and the method for obtaining this are not limited to the following content.

導電性金属箔よりなる導体として電解銅箔を用いる場合、この電解銅箔については、後に絶縁層を設ける側の面の表面粗さRzが1.0μm以下のものを使用する。これは、既に述べたように、この面に絶縁層を形成して導体を除去した際、絶縁層を透過してドライバICチップの配線の認識を可能とする為である。なお、絶縁層との密着性を確保するためにはRzは0.3μm以上であることが好ましい。また、最終的に得られる積層体における導体の厚みは1〜8μmであるが、この電解銅箔の厚みについては、後述する化学研摩を行うことから、用意する銅箔としては厚さ10μm以上、好ましくは12〜18μmの厚みのものを用いるようにするのがよい。   When an electrolytic copper foil is used as a conductor made of a conductive metal foil, the electrolytic copper foil having a surface roughness Rz of 1.0 μm or less on the surface on which an insulating layer will be provided later is used. This is because, as described above, when an insulating layer is formed on this surface and the conductor is removed, the wiring of the driver IC chip can be recognized through the insulating layer. In order to secure adhesion with the insulating layer, Rz is preferably 0.3 μm or more. Moreover, although the thickness of the conductor in the finally obtained laminate is 1 to 8 μm, the thickness of this electrolytic copper foil is subjected to chemical polishing described later, so that the prepared copper foil has a thickness of 10 μm or more, Preferably, a material having a thickness of 12 to 18 μm is used.

積層体を形成する絶縁層については、例えば熱可塑性樹脂層を有する絶縁フィルムから形成されたものであってもよく、熱硬化性樹脂層を有する絶縁フィルムから形成されたものであってもよい。また、ポリイミド前駆体樹脂溶液が導体に塗布され、このポリイミド前駆体樹脂溶液を乾燥及び硬化させることにより形成してもよい。これらのうち、好ましくは導体にポリイミド前駆体樹脂溶液が塗布された後、乾燥及び硬化させることにより絶縁層を形成したものであるのがよい。   About the insulating layer which forms a laminated body, it may be formed, for example from the insulating film which has a thermoplastic resin layer, and may be formed from the insulating film which has a thermosetting resin layer. Alternatively, the polyimide precursor resin solution may be applied to the conductor, and the polyimide precursor resin solution may be dried and cured. Of these, the insulating layer is preferably formed by drying and curing after the polyimide precursor resin solution is applied to the conductor.

上記絶縁層について、ポリイミド前駆体樹脂溶液を塗布した後、乾燥及び硬化することにより形成する場合には、公知のジアミンと酸無水物とを溶媒の存在下で重合して製造することができる。   About the said insulating layer, when apply | coating a polyimide precursor resin solution and forming by drying and hardening, it can manufacture by polymerizing a well-known diamine and an acid anhydride in presence of a solvent.

用いられるジアミンとしては、例えば、4,4’−ジアミノジフェニルエーテル、2’−メトキシ4,4’−ジアミノベンズアニリド、1,4−ビス(4−アミノフェノキシ)ベンゼン、1,3−ビス(4−アミノフェノキシ)ベンゼン、2,2’−ビス[4−(4−アミノフェノキシ)フェニル]プロパン、2,2’−ジメチル−4,4’−ジアミノビフェニル、3,3’−ジヒドロキシ−4,4’−ジアミノビフェニル、4,4’−ジアミノベンズアニリド等が挙げられる。また、酸無水物としては、例えば、無水ピロメリット酸、3,3’,4,4’−ビフェニルテトラカルボン酸二無水物、3,3’,4,4’−ジフェニルスルフォンテトラカルボン酸二無水物、4,4’−オキシジフタル酸無水物が挙げられる。ジアミン、酸無水物はそれぞれ、その1種のみを使用してもよく2種以上を併用して使用することも出来る。   Examples of the diamine used include 4,4′-diaminodiphenyl ether, 2′-methoxy 4,4′-diaminobenzanilide, 1,4-bis (4-aminophenoxy) benzene, and 1,3-bis (4- Aminophenoxy) benzene, 2,2′-bis [4- (4-aminophenoxy) phenyl] propane, 2,2′-dimethyl-4,4′-diaminobiphenyl, 3,3′-dihydroxy-4,4 ′ -Diaminobiphenyl, 4,4'-diaminobenzanilide and the like. Examples of the acid anhydride include pyromellitic anhydride, 3,3 ′, 4,4′-biphenyltetracarboxylic dianhydride, and 3,3 ′, 4,4′-diphenylsulfonetetracarboxylic dianhydride. And 4,4′-oxydiphthalic anhydride. Each of the diamine and acid anhydride may be used alone or in combination of two or more.

溶媒については、ジメチルアセトアミド、n−メチルピロリジノン、2−ブタノン、ジグライム、キシレン等が挙げられ、1種若しくは2種以上併用して使用することもできる。   Examples of the solvent include dimethylacetamide, n-methylpyrrolidinone, 2-butanone, diglyme, xylene and the like, and they can be used alone or in combination of two or more.

上記ポリイミド前駆体樹脂溶液については、前駆体状態で導体の一方の面に直接塗布することが好ましく、重合された樹脂粘度を500cps〜35,000cpsの範囲とすることが好ましい。塗布された樹脂液については熱処理を行う必要があるが、この熱処理については例えば100℃〜150℃を2分〜4分大気中で熱処理し、その後、真空加熱で室温から340℃まで昇温させ再び室温まで戻すといった処理を9時間程度行うのがよい。このようにして形成するポリイミド樹脂からなる絶縁層は、ポリイミド樹脂層の単層のみから形成してもよく、複数層から形成してもよい。ポリイミド樹脂層を複数層から形成する場合、ポリイミド樹脂層の上に異なる構成成分からなる他のポリイミド樹脂を順次塗布して形成してもよい。ポリイミド樹脂層が3層以上からなる場合、同一の構成成分からなるポリイミド樹脂を2回以上使用してもよい。   About the said polyimide precursor resin solution, it is preferable to apply | coat directly to one side of a conductor in a precursor state, and it is preferable to make the polymerized resin viscosity into the range of 500 cps-35,000 cps. The applied resin solution needs to be heat treated. For this heat treatment, for example, heat treatment is performed at 100 ° C. to 150 ° C. in the air for 2 minutes to 4 minutes, and then the temperature is raised from room temperature to 340 ° C. by vacuum heating. The process of returning to room temperature again should be performed for about 9 hours. The insulating layer made of the polyimide resin thus formed may be formed from only a single layer of the polyimide resin layer or may be formed from a plurality of layers. When the polyimide resin layer is formed from a plurality of layers, other polyimide resins made of different components may be sequentially applied on the polyimide resin layer. When the polyimide resin layer is composed of three or more layers, a polyimide resin composed of the same component may be used twice or more.

上記で得た絶縁層と導体との積層体については、絶縁層と直接接していない導体の面を化学研摩することによって、この導体の厚みを1〜8μmにすると共に、この面の表面粗さRzを1.0μm以下にする。この銅箔の表面粗さは、化学研磨の条件によっても変化するが、本発明においては、公知の研磨温度や研磨速度などの研磨条件を調整して、所望の積層体の銅箔表面粗さを調整することができる。但し、研磨液の種類と組成は、銅箔の表面粗さとの関係で重要な因子となるため、その研磨液は、過酸化水素と硫酸を主剤として含有する過酸化水素/硫酸系が好ましい。過酸化水素/硫酸系の研磨液を使用する場合、過酸化水素の濃度については70〜85g/L、硫酸の濃度については18〜22g/Lの範囲とすることが好ましい。濃度範囲が上記範囲にないと表面粗さの精密な制御が困難となる傾向にある。また、研磨温度は、20〜50℃の任意の温度で一定に保つことがよい。   For the laminate of the insulating layer and the conductor obtained above, the surface of the conductor not directly in contact with the insulating layer is chemically polished to reduce the thickness of the conductor to 1 to 8 μm and the surface roughness of this surface. Rz is set to 1.0 μm or less. The surface roughness of the copper foil varies depending on the conditions of chemical polishing. In the present invention, the copper foil surface roughness of a desired laminate is adjusted by adjusting polishing conditions such as a known polishing temperature and polishing rate. Can be adjusted. However, since the type and composition of the polishing liquid are important factors in relation to the surface roughness of the copper foil, the polishing liquid is preferably a hydrogen peroxide / sulfuric acid system containing hydrogen peroxide and sulfuric acid as main components. When using a hydrogen peroxide / sulfuric acid based polishing liquid, the concentration of hydrogen peroxide is preferably in the range of 70 to 85 g / L, and the concentration of sulfuric acid is preferably in the range of 18 to 22 g / L. If the concentration range is not within the above range, precise control of the surface roughness tends to be difficult. The polishing temperature is preferably kept constant at an arbitrary temperature of 20 to 50 ° C.

なお、上記の説明では、電解銅箔上にポリイミド樹脂を塗布することによって絶縁層を形成したが、例えば1層以上のポリイミドフィルムを電解銅箔にラミネートして絶縁層を形成し、その後、上記で説明したような化学研磨を行うようにしてもよい。   In the above description, the insulating layer is formed by applying a polyimide resin on the electrolytic copper foil. However, for example, an insulating layer is formed by laminating one or more polyimide films on the electrolytic copper foil, and then, Chemical polishing as described in (1) may be performed.

このようにして製造した積層体は、絶縁層の片面のみに電解銅箔を有する片面銅張り積層体としてもよく、また、絶縁層の両面に電解銅箔を有する両面銅張り積層体としてもよい。両面銅張り積層体については、片面銅張り積層体を形成した後、電解銅箔を熱プレスにより圧着する方法や2枚の電解銅箔の間にポリイミドフィルムを挟み熱プレスにより圧着する方法等を挙げることができる。いずれの方法においても、圧着後には、絶縁層と直接接していない電解銅箔の面の表面粗さRzを1.0μm以下にすると共にこの電解銅箔の厚みを1〜8μmの範囲となるように化学研磨を行うようにする。なお、絶縁層と直接接していない電解銅箔の表面粗さRzは後から積層される絶縁性保護膜との密着性を確保する観点から0.1μm以上であることが望ましい。   The laminate thus produced may be a single-sided copper-clad laminate having an electrolytic copper foil only on one side of the insulating layer, or a double-sided copper-clad laminate having an electrolytic copper foil on both sides of the insulating layer. . For double-sided copper-clad laminates, after forming a single-sided copper-clad laminate, a method of crimping electrolytic copper foil by hot pressing, a method of sandwiching a polyimide film between two electrolytic copper foils and crimping by hot pressing, etc. Can be mentioned. In any method, after crimping, the surface roughness Rz of the surface of the electrolytic copper foil that is not in direct contact with the insulating layer is made 1.0 μm or less and the thickness of the electrolytic copper foil is in the range of 1 to 8 μm. Do chemical polishing. Note that the surface roughness Rz of the electrolytic copper foil that is not in direct contact with the insulating layer is desirably 0.1 μm or more from the viewpoint of ensuring adhesion with an insulating protective film to be laminated later.

以下、本発明を実施例により更に詳細に説明する。   Hereinafter, the present invention will be described in more detail with reference to examples.

積層体の作成にあたり、下記4種類の銅箔を準備した。
1)銅箔1:電解銅箔 絶縁層側Rz0.7μm、レジスト面側Rz2.0μm
三井金属鉱業(株)製NA−VLP箔 厚さ15μm
2)銅箔2:電解銅箔 絶縁層側Rz1.6μm、レジスト面側Rz1.5μm
古河サーキットフォイル(株)製F2−WS箔 厚さ12μm
3)銅箔3:電解銅箔 絶縁層側Rz2.5μm、レジスト面側Rz1.5μm
三井金属鉱業(株)製SQ−VLP箔 厚さ12μm
4)銅箔4:電解銅箔 絶縁層側Rz0.8μm、レジスト面側Rz1.0μm
日本電解(株)製USLPS箔 厚さ18μm
In creating the laminate, the following four types of copper foils were prepared.
1) Copper foil 1: Electrolytic copper foil Insulation layer side Rz0.7μm, resist side Rz2.0μm
Mitsui Metal Mining Co., Ltd. NA-VLP foil thickness 15μm
2) Copper foil 2: Electrolytic copper foil Insulation layer side Rz 1.6μm, resist surface side Rz 1.5μm
F2-WS foil manufactured by Furukawa Circuit Foil Co., Ltd., thickness 12μm
3) Copper foil 3: Electrolytic copper foil Insulation layer side Rz2.5μm, resist surface side Rz1.5μm
Mitsui Kinzoku Mining Co., Ltd. SQ-VLP foil thickness 12μm
4) Copper foil 4: Electrolytic copper foil Insulation layer side Rz0.8μm, resist surface side Rz1.0μm
US Electrolytic Co., Ltd. USLPS foil thickness 18μm

[合成例1]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器にn-メチルピロリジノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器に無水ピロメリット酸(PMDA)を投入し、その後、4,4’-ジアミノジフェニルエーテル、(DAPE)と2 ’-メトキシ-4,4’-ジアミノベンズアニリド(MABA)を投入した。モノマーの投入総量が15wt%で、各ジアミンのモル比率(MABA:DAPE)が60:40であり、酸無水物とジアミンのモル比が0.98:1.0となるよう投入した。その後、更に攪拌を続け、反応容器内の温度が、室温から±5℃の範囲となった時に反応容器を氷水から外した。室温のまま3時間攪拌を続け、得られたポリアミック酸の溶液粘度は15,000cpsであった。
[Synthesis Example 1]
N-methylpyrrolidinone was put in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After soaking the reaction vessel in ice water contained in the vessel, pyromellitic anhydride (PMDA) was added to the reaction vessel, and then 4,4'-diaminodiphenyl ether, (DAPE) and 2'-methoxy-4,4 '-Diaminobenzanilide (MABA) was charged. The total amount of monomers charged was 15 wt%, the molar ratio of each diamine (MABA: DAPE) was 60:40, and the molar ratio of acid anhydride to diamine was 0.98: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the solution viscosity of the resulting polyamic acid was 15,000 cps.

[合成例2]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器にn-メチルピロリジノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器にPMDA/3, 3’,4,4’-ビフェニルテトラカルボン酸二無水物(BTDA)を投入し、その後、4,4’-ジアミノジフェニルエーテル(DAPE)を投入した。モノマーの投入総量が15wt%で、酸無水物とジアミンのモル比が1.03:1.0となるよう投入した。その後、更に攪拌を続け、反応容器内の温度が、室温から±5℃の範囲となった時に反応容器を氷水から外した。室温のまま3時間攪拌を続け、得られたポリアミック酸の溶液粘度は3,200cpsであった。
[Synthesis Example 2]
N-methylpyrrolidinone was put in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, PMDA / 3,3 ', 4,4'-biphenyltetracarboxylic dianhydride (BTDA) was charged into the reaction vessel, and then 4,4'- Diaminodiphenyl ether (DAPE) was added. The total monomer charge was 15 wt%, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the solution viscosity of the resulting polyamic acid was 3,200 cps.

[合成例3]
熱電対及び攪拌機を備えると共に窒素導入が可能な反応容器にn-メチルピロリジノンを入れた。この反応容器を容器に入った氷水に浸けた後、反応容器に3,3’4,4’-ジフェニルスルフォンテトラカルボン酸二無水物(DSDA)、PMDAを投入し、その後、1,3-ビス(4-アミノフェノキシ)ベンゼン(TPE-R)を投入した。モノマーの投入総量が15wt%で、各酸無水物のモル比率(DSDA:PMDA)が90:10であり、酸無水物とジアミンのモル比が1.03:1.0となるよう投入した。その後、更に攪拌を続け、反応容器内の温度が、室温から±5℃の範囲となった時に反応容器を氷水から外した。室温のまま3時間攪拌を続け、得られたポリアミック酸の溶液粘度は3,200cpsであった。
[Synthesis Example 3]
N-methylpyrrolidinone was put in a reaction vessel equipped with a thermocouple and a stirrer and capable of introducing nitrogen. After immersing this reaction vessel in ice water contained in the vessel, 3,3′4,4′-diphenylsulfonetetracarboxylic dianhydride (DSDA) and PMDA were charged into the reaction vessel, and then 1,3-bis (4-Aminophenoxy) benzene (TPE-R) was added. The total monomer charge was 15 wt%, the molar ratio of each acid anhydride (DSDA: PMDA) was 90:10, and the molar ratio of acid anhydride to diamine was 1.03: 1.0. Thereafter, stirring was further continued, and the reaction vessel was removed from the ice water when the temperature in the reaction vessel was in the range of room temperature to ± 5 ° C. Stirring was continued for 3 hours at room temperature, and the solution viscosity of the resulting polyamic acid was 3,200 cps.

上記銅箔1の絶縁層側の面に合成例1〜3のポリアミック酸溶液を順次塗布し、乾燥を繰り返し、銅箔上にポリイミド前駆体樹脂層を形成した積層体を得た。この積層体を340℃で、8時間かけて熱処理し、ポリイミド樹脂層の厚みが40μm(2μm/36μm/2μm)の片面銅箔の積層体を得た。この積層体を硫酸濃度20g/L、過酸化水素濃度80g/L、添加剤濃度3%の研磨液で化学研磨し、銅箔の厚みが8.0μmになるようにすると共に、ポリイミド樹脂層と接していない銅箔の表面粗さRzが0.8μmとなるようにして導体を形成し、導体と絶縁層とからなるCOF基板用積層体を得た。     The polyamic acid solutions of Synthesis Examples 1 to 3 were sequentially applied to the surface of the copper foil 1 on the insulating layer side, and drying was repeated to obtain a laminate in which a polyimide precursor resin layer was formed on the copper foil. This laminated body was heat-treated at 340 ° C. for 8 hours to obtain a single-sided copper foil laminated body having a polyimide resin layer thickness of 40 μm (2 μm / 36 μm / 2 μm). This laminate is chemically polished with a polishing solution having a sulfuric acid concentration of 20 g / L, a hydrogen peroxide concentration of 80 g / L, and an additive concentration of 3% so that the copper foil has a thickness of 8.0 μm and is in contact with the polyimide resin layer. A conductor was formed such that the surface roughness Rz of the copper foil not formed was 0.8 μm, and a COF substrate laminate comprising a conductor and an insulating layer was obtained.

上記で得たCOF基板用積層体に配線パターンを形成してCOFフィルムキャリアテープとした。この時、インナーリード部の回路パターンを30μmピッチで作成し、錫メッキを施した後、倍率50倍のレーザー顕微鏡にて目視で回路の直線性の確認を行いライン幅が不均一な状態が観察された場合をNGとした。その後、COFフィルムキャリアテープのインナーリード部へ金バンプを有するICを実装した。実装には、フリップチップボンダー「TFC-2100」芝浦メカトロニクス(株)製を使用し、ボンディングヘッドツール温度は100℃、ステージ温度は420℃、接合圧力は1バンプ当たりの荷重が20gfになるようにして行った。この実装の際、COFフィルムキャリアテープを通してICを画像認識してICの位置合わせに用いられるアライメントマークが認識可能であるかどうかで視認性評価を行った。実装後、HHBT試験機「ETAC HIFLEX」楠本化成(株)製にて(8 5℃、85%RT、150V、1000時間)を行い、信頼性評価を行った。結果を表1に示す。   A wiring pattern was formed on the laminate for a COF substrate obtained above to obtain a COF film carrier tape. At this time, the circuit pattern of the inner lead part was created at a pitch of 30μm, tin-plated, and then the linearity of the circuit was visually confirmed with a laser microscope with a magnification of 50 times, and the line width was observed to be uneven. NG was determined as NG. Thereafter, an IC having gold bumps was mounted on the inner lead portion of the COF film carrier tape. The flip chip bonder “TFC-2100” manufactured by Shibaura Mechatronics Co., Ltd. is used for mounting, and the bonding head tool temperature is 100 ° C, the stage temperature is 420 ° C, and the bonding pressure is 20 gf per bump. I went. At the time of this mounting, visibility was evaluated by recognizing whether or not an alignment mark used for IC alignment can be recognized by recognizing an image of the IC through a COF film carrier tape. After mounting, HHBT tester “ETAC HIFLEX” manufactured by Enomoto Kasei Co., Ltd. (85 ° C., 85% RT, 150 V, 1000 hours) was used for reliability evaluation. The results are shown in Table 1.

市販のポリイミド樹脂フィルム(東レ・デュポン(株)製、商品名:カプトン150EN)を用い、片面に合成例1のポリアミック酸溶液をロールコーターにより乾燥後の厚さで2.0μmになるように塗布して150℃で2分間乾燥させた後、もう一方の面に合成例2のポリアミック酸溶液をロールコーターにより乾燥後の厚さが2.0μmになるように塗布し、70℃で5分、110℃で5分乾燥後、140℃2分、180℃5分、265℃2分、エアーフロート方式の加熱炉にて硬化を行い、合成例1のポリアミック酸溶液を塗布した側が非熱可塑性ポリイミド樹脂層であり、合成例2のポリアミック酸溶液を塗布した側が熱可塑性ポリイミド樹脂層であるポリイミドの絶縁フィルムを得た。   Using a commercially available polyimide resin film (manufactured by Toray DuPont Co., Ltd., trade name: Kapton 150EN), apply the polyamic acid solution of Synthesis Example 1 on one side to a thickness of 2.0 μm after drying with a roll coater. After drying at 150 ° C. for 2 minutes, the polyamic acid solution of Synthesis Example 2 was applied to the other surface with a roll coater so that the thickness after drying was 2.0 μm, and at 70 ° C. for 5 minutes, 110 ° C. After drying for 5 minutes at 140 ° C. for 2 minutes, 180 ° C. for 5 minutes and 265 ° C. for 2 minutes, the side coated with the polyamic acid solution of Synthesis Example 1 is a non-thermoplastic polyimide resin layer. Thus, a polyimide insulating film having a thermoplastic polyimide resin layer on the side coated with the polyamic acid solution of Synthesis Example 2 was obtained.

次いで、上記で得られた絶縁フィルムの熱可塑性ポリイミド樹脂層側の面と上記銅箔4の絶縁層側の面とを重ね合わせ、シリコンゴムで覆われたロールラミネーターを用いて240℃、圧力1.5Mpaの条件で銅箔4と上記絶縁フィルムとを貼り合わせた。その後、バッチ式のオートクレーブにて温度340℃4時間窒素雰囲気下でアニールを行って積層体を得た。この得られた積層体を実施例1と同様にして化学研磨を行い、銅箔の厚みを8.0μmとし、絶縁フィルムと接していない銅箔の表面粗さRzを0.6μmとなるようにして導体を形成し、導体と絶縁層とからなるCOF基板用積層体を得た。このCOF基板用積層体について、実施例1と同様にして実装を行い、実装時の画像認識、インナーリードの直線性及びCOF実装後信頼性について評価した。結果を表1に示す。   Next, the surface of the insulating film obtained above on the side of the thermoplastic polyimide resin layer and the surface of the copper foil 4 on the side of the insulating layer are overlapped, and using a roll laminator covered with silicon rubber, 240 ° C., pressure 1 The copper foil 4 and the said insulating film were bonded together on condition of 0.5 Mpa. Thereafter, annealing was performed in a batch-type autoclave at a temperature of 340 ° C. for 4 hours in a nitrogen atmosphere to obtain a laminate. The obtained laminate was chemically polished in the same manner as in Example 1 so that the copper foil had a thickness of 8.0 μm and the surface roughness Rz of the copper foil not in contact with the insulating film was 0.6 μm. A laminate for a COF substrate composed of a conductor and an insulating layer was obtained. The COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.

[比較例1]
上記銅箔2を用い、実施例1と同様にして積層体を形成して化学研摩を行った。得られたCOF基板用積層体の導体の厚みは8.0μmであり、絶縁層と接している側の面の表面粗さRzが1.6μm、絶縁層と接していない側(レジスト面側)の表面粗さRzが1.2μmであった。このCOF基板用積層体について、実施例1と同様にして実装を行い、実装時の画像認識、インナーリードの直線性及びCOF実装後信頼性について評価した。結果を表1に示す。
[Comparative Example 1]
Using the copper foil 2, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed. The thickness of the conductor of the obtained laminate for COF substrate is 8.0 μm, the surface roughness Rz of the surface in contact with the insulating layer is 1.6 μm, the surface on the side not in contact with the insulating layer (resist surface side) The roughness Rz was 1.2 μm. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.

[比較例2]
上記銅箔3を用い、実施例1と同様にして積層体を形成して化学研摩を行った。得られたCOF基板用積層体の導体の厚みは8.0μmであり、絶縁層と接している側の面の表面粗さRzが2.5μm、絶縁層と接していない側(レジスト面側)の表面粗さRzが0.9μmであった。このCOF基板用積層体について、実施例1と同様にして実装を行い、実装時の画像認識、インナーリードの直線性及びCOF実装後信頼性について評価した。結果を表1に示す。
[Comparative Example 2]
Using the copper foil 3, a laminate was formed in the same manner as in Example 1, and chemical polishing was performed. The thickness of the conductor of the obtained laminate for COF substrate is 8.0 μm, the surface roughness Rz of the surface in contact with the insulating layer is 2.5 μm, and the surface not in contact with the insulating layer (resist surface side) The roughness Rz was 0.9 μm. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.

[比較例3]
銅箔4を用い、実施例1と同様にして積層体を形成した。この積層体については化学研磨を行わなかった。得られたCOF基板用積層体の導体の厚みは18μmであり、絶縁層と接している側の面の表面粗さRzが0.8μm、絶縁層と接していない側(レジスト面側)の表面粗さRzが1.0μmであった。このCOF基板用積層体について、実施例1と同様にして実装を行い、実装時の画像認識、インナーリードの直線性及びCOF実装後信頼性について評価した。結果を表1に示す。
[Comparative Example 3]
A laminated body was formed using the copper foil 4 in the same manner as in Example 1. This laminated body was not subjected to chemical polishing. The thickness of the conductor of the obtained laminate for COF substrate is 18 μm, the surface roughness Rz on the surface in contact with the insulating layer is 0.8 μm, and the surface roughness on the side not in contact with the insulating layer (resist surface side) The thickness Rz was 1.0 μm. The COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.

[比較例4]
銅箔1を用いて、化学研摩を行う手前まで実施例1と同様にして積層体を作成した。次いで、この積層体を硫酸濃度80g/L、過酸化水素濃度20g/L、添加剤濃度3%の研磨液を用いて化学研磨を行い、銅箔の厚みが8.0μmになるようにすると共に、ポリイミド樹脂層と接していない銅箔の表面粗さRzが1.6μmとなるようにして導体を形成し、導体と絶縁層とからなるCOF基板用積層体を得た。このCOF基板用積層体について、実施例1と同様にして実装を行い、実装時の画像認識、インナーリードの直線性及びCOF実装後信頼性について評価した。結果を表1に示す。
[Comparative Example 4]
Using the copper foil 1, a laminate was prepared in the same manner as in Example 1 until just before chemical polishing. Next, this laminate is subjected to chemical polishing using a polishing liquid having a sulfuric acid concentration of 80 g / L, a hydrogen peroxide concentration of 20 g / L, and an additive concentration of 3% so that the thickness of the copper foil becomes 8.0 μm, A conductor was formed so that the surface roughness Rz of the copper foil not in contact with the polyimide resin layer was 1.6 μm, and a COF substrate laminate comprising a conductor and an insulating layer was obtained. This COF substrate laminate was mounted in the same manner as in Example 1, and image recognition during mounting, linearity of the inner leads, and reliability after COF mounting were evaluated. The results are shown in Table 1.

Figure 2006068000
Figure 2006068000

Claims (6)

導電性金属箔よりなる導体の一方の面に絶縁性樹脂よりなる絶縁層が形成されたCOF基板用積層体であって、導体の厚みが1〜8μmであり、導体の絶縁層と接している面の表面粗さRzが1.0μm以下であり、かつ、導体の絶縁層と接していない面の表面粗さRzが1.0μm以下であることを特徴とするCOF基板用積層体。   A laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor made of a conductive metal foil, wherein the conductor has a thickness of 1 to 8 μm and is in contact with the insulating layer of the conductor A laminate for a COF substrate, wherein the surface roughness Rz of the surface is 1.0 μm or less, and the surface roughness Rz of the surface not in contact with the insulating layer of the conductor is 1.0 μm or less. 絶縁層が、ポリイミド前駆体樹脂溶液を導体に直接塗布した後、乾燥及び硬化させて形成したものであることを特徴とする請求項1記載のCOF基板用積層体。   2. The COF substrate laminate according to claim 1, wherein the insulating layer is formed by directly applying a polyimide precursor resin solution to a conductor, followed by drying and curing. 絶縁層が、熱可塑性樹脂層を有する絶縁フィルムを導体に熱圧着して形成したものであることを特徴とする請求項1又は2記載のCOF基板用積層体。   3. The COF substrate laminate according to claim 1, wherein the insulating layer is formed by thermocompression bonding an insulating film having a thermoplastic resin layer to a conductor. 少なくとも10μm以上の厚みを有し、かつ、一方の面の表面粗さRzが1.0μm以下である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接していない導電性金属箔の面を化学研摩してこの導電性金属箔の厚みを1〜8μmにすると共に、表面粗さRzを1.0μm以下にして導体が形成されることを特徴とする請求項1に記載のCOF基板用積層体。   Conductive metal foil having a thickness of at least 10 μm and having a surface roughness Rz on one surface of 1.0 μm or less and an insulating layer formed on the surface of the conductive metal foil, which is not in contact with the insulating layer 2. The COF substrate according to claim 1, wherein a conductor is formed by chemically polishing the surface of the conductive metal foil to a thickness of 1 to 8 μm and a surface roughness Rz of 1.0 μm or less. Laminated body. 請求項1〜4のいずれかに記載の積層体を用いて形成したことを特徴とするCOFフィルムキャリアテープ。   A COF film carrier tape formed using the laminate according to any one of claims 1 to 4. 導体の一方の面に絶縁性樹脂よりなる絶縁層が形成されたCOF基板用積層体の製造方法であって、少なくとも10μm以上の厚みを有し、かつ、一方の面の表面粗さRzが1.0μm以下である導電性金属箔の当該面に絶縁層を形成し、この絶縁層と接していない導電性金属箔の面を化学研摩してこの導電性金属箔の厚みを1〜8μmにすると共に、表面粗さRzを1.0μm以下にして導体を形成することを特徴とするCOF基板用積層体の製造方法。   A method for producing a laminate for a COF substrate in which an insulating layer made of an insulating resin is formed on one surface of a conductor, having a thickness of at least 10 μm and a surface roughness Rz of one surface of 1.0. An insulating layer is formed on the surface of the conductive metal foil having a thickness of μm or less, and the surface of the conductive metal foil not in contact with the insulating layer is chemically polished so that the thickness of the conductive metal foil is 1 to 8 μm. A method for producing a laminate for a COF substrate, wherein the conductor is formed with a surface roughness Rz of 1.0 μm or less.
JP2006548842A 2004-12-22 2005-12-13 Manufacturing method of laminate for COF substrate Expired - Fee Related JP5064035B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006548842A JP5064035B2 (en) 2004-12-22 2005-12-13 Manufacturing method of laminate for COF substrate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2004371080 2004-12-22
JP2004371080 2004-12-22
PCT/JP2005/022825 WO2006068000A1 (en) 2004-12-22 2005-12-13 Stacked body for cof substrate, method for manufacturing such stacked body for cof substrate, and cof film carrier tape formed by using such stacked body for cof substrate
JP2006548842A JP5064035B2 (en) 2004-12-22 2005-12-13 Manufacturing method of laminate for COF substrate

Publications (2)

Publication Number Publication Date
JPWO2006068000A1 true JPWO2006068000A1 (en) 2008-08-07
JP5064035B2 JP5064035B2 (en) 2012-10-31

Family

ID=36601601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006548842A Expired - Fee Related JP5064035B2 (en) 2004-12-22 2005-12-13 Manufacturing method of laminate for COF substrate

Country Status (5)

Country Link
JP (1) JP5064035B2 (en)
KR (1) KR101169829B1 (en)
CN (1) CN100468675C (en)
TW (1) TWI400742B (en)
WO (1) WO2006068000A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4823884B2 (en) * 2006-12-11 2011-11-24 新日鐵化学株式会社 Method for producing flexible copper-clad laminate
JP4828439B2 (en) * 2007-01-15 2011-11-30 新日鐵化学株式会社 Method for producing flexible laminate
US8238114B2 (en) 2007-09-20 2012-08-07 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
JP6094044B2 (en) * 2011-03-23 2017-03-15 大日本印刷株式会社 Heat dissipation board and element using the same
CN103442511A (en) * 2013-08-20 2013-12-11 珠海亚泰电子科技有限公司 High frequency substrate
JP6572083B2 (en) * 2015-09-30 2019-09-04 大日本印刷株式会社 Light emitting element substrate, module, and method for manufacturing light emitting element substrate
CN110868799A (en) * 2019-11-15 2020-03-06 江苏上达电子有限公司 Transparent COF design method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003289177A (en) * 2002-03-28 2003-10-10 Asahi Kasei Corp Method of manufacturing wiring board for cof
WO2003096776A1 (en) * 2002-05-13 2003-11-20 Mitsui Mining & Smelting Co.,Ltd. Flexible printed wiring board for chip-on-film
JP2004119961A (en) * 2002-09-02 2004-04-15 Furukawa Techno Research Kk Copper foil for chip-on film, plasma display panel, and high-frequency printed wiring board

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW476777B (en) * 1998-08-31 2002-02-21 Hitachi Chemical Co Ltd Abrasive liquid for metal and method for polishing
CN1803964B (en) * 1998-12-28 2010-12-15 日立化成工业株式会社 Materials for polishing liquid for metal, polishing liquid for metal, method for preparation thereof and polishing method using same
TW591089B (en) * 2001-08-09 2004-06-11 Cheil Ind Inc Slurry composition for use in chemical mechanical polishing of metal wiring
TW200404484A (en) * 2002-09-02 2004-03-16 Furukawa Circuit Foil Copper foil for soft circuit board package module, for plasma display, or for radio-frequency printed circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003289177A (en) * 2002-03-28 2003-10-10 Asahi Kasei Corp Method of manufacturing wiring board for cof
WO2003096776A1 (en) * 2002-05-13 2003-11-20 Mitsui Mining & Smelting Co.,Ltd. Flexible printed wiring board for chip-on-film
JP2004119961A (en) * 2002-09-02 2004-04-15 Furukawa Techno Research Kk Copper foil for chip-on film, plasma display panel, and high-frequency printed wiring board

Also Published As

Publication number Publication date
TW200634903A (en) 2006-10-01
CN101076885A (en) 2007-11-21
KR101169829B1 (en) 2012-07-30
CN100468675C (en) 2009-03-11
WO2006068000A1 (en) 2006-06-29
JP5064035B2 (en) 2012-10-31
TWI400742B (en) 2013-07-01
KR20070091027A (en) 2007-09-06

Similar Documents

Publication Publication Date Title
JP4804806B2 (en) Copper-clad laminate and manufacturing method thereof
JP5181618B2 (en) Metal foil laminated polyimide resin substrate
KR101078234B1 (en) Copper-clad laminate
JP5064035B2 (en) Manufacturing method of laminate for COF substrate
TWI500501B (en) Second layer double sided flexible metal laminated board and manufacturing method thereof
KR20030029956A (en) Resin Composition
US20050175824A1 (en) Method for forming multilayer circuit structure and base having multilayer circuit structure
JP4907580B2 (en) Flexible copper clad laminate
KR100955552B1 (en) Polyimide film, polyimide metal laminate and process for producing the same
TWI387017B (en) Copper clad laminate for cof and carrier tape for cof
JP4642479B2 (en) COF laminate and COF film carrier tape
JP5000310B2 (en) COF laminate, COF film carrier tape, and electronic device
KR20070087981A (en) Double side conductor laminates and its manufacture
TW584596B (en) Method for manufacturing a polyimide and metal compound sheet
JP4777206B2 (en) Method for producing flexible copper-clad laminate
JP2004237596A (en) Flexible copper-clad laminated plate and its production method
JP4828439B2 (en) Method for producing flexible laminate
KR101378052B1 (en) Laminate for cof, cof film carrier tape and electronic device
JP3664708B2 (en) Polyimide metal laminate and manufacturing method thereof
JP2005271449A (en) Laminate for flexible printed circuit board
JP5073801B2 (en) Method for producing copper-clad laminate
JP2005197532A (en) Multilayered circuit board, manufacturing method thereof, and circuit base material
WO2004049336A1 (en) Laminate for hdd suspension using thin copper foil and its manufacturing method
JP4987756B2 (en) Multilayer circuit board manufacturing method
JP2007296847A (en) Laminated film with metal layer, its manufacturing process, wiring substrate using this, and semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080828

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110531

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110801

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120508

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120706

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120807

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120808

R150 Certificate of patent or registration of utility model

Ref document number: 5064035

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150817

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150817

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150817

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees