JPWO2004021445A1 - Double-gate MOS field effect transistor and method for manufacturing the same - Google Patents

Abstract

Aiming to realize narrow channel formation with high precision, a truly practical double-gate MOSFET is provided. On the semiconductor substrate, ions are implanted into a planned area region where the first channel end region is to be formed in the future to form an ion implantation damaged region. A narrow columnar body that substantially becomes a channel region is formed under the ion implantation damaged region by wet etching using the ion implantation damaged region as an etching mask. Then, after forming the gate insulating film on both side surfaces of the columnar body, forming the first and second gates facing each channel while facing the direction orthogonal to the electron traveling direction across the channel on both side surfaces, A double-gate MOSFET is obtained.

Description

    The present invention is a so-called double-gate MOS field effect transistor (hereinafter referred to as MOSFET: simply “ And a manufacturing method thereof.

Such double-gate MOSFETs have been shown by theoretical calculations to exhibit better electrical characteristics than ordinary single-gate MOSFETs. Therefore, in order to realize this as an actual device, In general, two types of production methods have been proposed. Elements produced as a result of each method can be broadly classified from the viewpoint of structure, so-called lateral type (horizontal type) elements as shown in FIG. 9 (A) and so-called versatile elements as shown in FIG. 9 (B). It becomes a tikal type (vertical type) element.
The former lateral type element is described in Document 1: IEEE Trans. In ED47, 354 (2000), the latter vertical type element is described in Reference 2: VLSI Symp. Tech. Dig. , 2001, pp. Specific examples of production can be recognized at 55-56, respectively.
The lateral double-gate MOSFET 20 shown in FIG. 9A basically uses an SOI (Silicon On Insulator) substrate 21 as a construction substrate, and a surface silicon (Si) layer on the oxide film 22. A part of the channel 23 is used as a channel 24, and appropriate impurities are introduced into both lateral portions of the channel 24 to form a source 25 and a drain 26, respectively. On the channel 24, the first gate G1 faces through the gate insulating film 27. On the other hand, the substrate 21 forms the second gate G2 on the opposite side of the channel.
The source 25 and the drain 26 are respectively provided with appropriate extraction electrodes Es and Ed penetrating the surface insulating film layer. The second gate G2 is generally provided with a second extraction electrode Eg2 that is simply attached to the back surface of the substrate. Although not shown, an appropriate extraction electrode is also provided on the first gate electrode G1.
On the other hand, in the vertical element 30 shown in FIG. 9 (B), a columnar body standing up and down on the substrate 31 is formed by dry etching so that a part along the height direction is a channel 32 and sandwiched from above and below. A drain 33 and a source 34 (generally, the upper side of the columnar body is used as a drain) into which appropriate impurities are introduced are provided, and both side surfaces of the channel 32 that are orthogonal to the electron traveling direction are covered with a gate insulating film 35 made of Si thin film. The first and second gates G1 and G2 are provided so as to be in contact therewith. Although not shown in the figure, of course, each castle is appropriately provided with an extraction electrode.
However, such a conventional element has not yet obtained a result that the characteristics are clearly superior to those of a single gate type element. At least compared to the theoretically predicted characteristics, it is still far from satisfactory. The reason is mainly due to limitations and problems in the conventional manufacturing method.
First, in the existing manufacturing method of the lateral element 20, the original effect of the double gate type is lost unless the silicon thin film to be formed with a channel is reduced to a considerable extent. Therefore, even if various existing etching techniques are used, the desired thinning cannot be achieved. In addition, the drain and source regions are eventually formed in this thinned portion, but there is a contradiction between the low resistance and the thinning. The thinner the film, the smaller the volume of the drain and source regions and the higher the resistance, which adversely affects the device characteristics. This can be said to be a defect caused by the structural principle.
Further, since the lower gate insulating film desired for the channel is originally provided by the SOI substrate, it is difficult to reduce the thickness of the lower gate insulating film with good controllability. In addition, it is actually difficult to eliminate the uneven thickness of the upper and lower gate insulating films with high accuracy. This in turn makes it difficult to make the upper gate length and the lower gate length the same. After all, it can be said that this lateral element has more problems due to structural constraints than simply a manufacturing method.
On the other hand, the vertical element 30 has few restrictions on the structural principle. However, there are too many problems for the existing manufacturing methods. First, dry etching is used to form a columnar body, but the width, that is, the thickness of the channel is ultimately determined by the etching system, and therefore cannot necessarily be formed with high accuracy and a very narrow columnar body width. In addition, since the upper portion of the columnar body having such a narrow width generally becomes the drain 33 as it is, the volume is still insufficient, and for the same reason as the horizontal element, the smaller the width, the higher the resistance. Above all, the channel is finally cut out by dry etching, which tends to cause etching damage to the channel, resulting in deterioration of device characteristics.
However, from another point of view, there is an attempt to eliminate the above-described drawbacks by using a high dielectric constant insulating film as the gate insulating film. However, in the first place, there are still some unsatisfactory developments of high dielectric constant insulating films themselves, and low dielectric constant SiO ₂ due to carbon compound residual problems, high temperature treatment during film formation or after film formation (necessary for activation of implanted impurities). Problems such as an increase in leakage current due to layer formation and polycrystallization have occurred, and a satisfactory film formation method has not yet been established. In other words, the development of a double-gate MOSFET has been unsuccessful in which such an insulating film is grown at a low temperature and the device can be completed with a low temperature process thereafter.
Furthermore, even from a structural standpoint, a low resistance element cannot be provided because the vertical element cannot be separated from the structure in which the upper portion of the narrow columnar body is used as the drain region.
The present invention has been made from such a point of view, and proposes a high-performance double-gate MOS field effect transistor and a manufacturing method capable of providing the same. In this document, for convenience, one of a source and a drain provided at each end of a channel and electrically connected to the channel is referred to as a first channel end region, and the other is referred to as a second channel end region. In general, a source is provided on the substrate side, and a drain is provided above the standing channel. In principle, either of the source and drain may be used in the MOSFET structure.

In order to achieve the above object, the present invention uses a pair of gates facing each other through a gate insulating film from both sides of the channel from a direction orthogonal to the electron traveling direction in the channel, using narrow columnar bodies standing from a semiconductor substrate as a channel. A first channel end region that is one of a drain and a source is provided on the upper end side of the narrow columnar body, and a second channel end region that is the other of the drain and the source is provided on the lower end side. A vertical double-gate MOS field effect transistor having a width equal to the width of the narrow columnar body and a dimension that is a thickness of a channel sandwiched between a pair of gates via a gate insulating film. A double-gate MOS field effect transistor is proposed in which the width of the end region is increased.
Further, in the double gate MOS field effect transistor having such a structure, the thickness of the insulating film between the gate and the second channel end region and the thickness between the gate and the first channel end region with respect to the thickness of the gate insulating film. A double-gate MOS field effect transistor is also proposed in which the thickness of the insulating film is increased.
In order to achieve the above object, the present invention further provides a narrow columnar body standing up from a semiconductor substrate as a channel in order to achieve the above object. It has a pair of gates facing through the gate insulating film, and the first channel end region which is one of the drain and the source is on the upper end side of the narrow columnar body, and the other is the other of the drain and the source on the lower end side. As a method of manufacturing a vertical double-gate MOS field effect transistor provided with a second channel end region, the first channel end region should be formed in the future on the semiconductor substrate in the main process part. A step of implanting ions into a predetermined area region to form an ion implantation damage region having high wet etching resistance, and etching the ion implantation damage region under the ion implantation damage region A step of forming a columnar body having a narrow width substantially serving as a channel by wet etching as a mask, and then forming a gate insulating film on both side surfaces of the columnar body, and then sandwiching the channel between the both side surfaces Forming a first gate and a second gate facing each channel while facing each other from a direction orthogonal to the direction of electron travel, and a method for producing a double-gate MOS field effect transistor Propose.
While satisfying the basic structural requirements for the above manufacturing method, various modifications or substructures can be proposed. For example, the conductivity type of ions implanted to form the ion implantation damage region is the substrate conductivity type. It is possible to propose a configuration in which the ion implantation damage region is substantially the same as the first channel end region even after the device is completed.
Conversely, the conductivity type of ions implanted to form the ion implantation damaged region is the same conductivity type as the substrate conductivity type. After the columnar body is formed in the ion implantation damage region, the conductivity type opposite to the substrate conductivity type is formed. The first channel end region may be formed by introducing the impurity.
On the other hand, the second channel end region is formed by introducing an impurity having a conductivity type opposite to that of the substrate conductivity type after the columnar body is formed, or before the columnar body is formed, May be formed simultaneously with the reverse conductivity type ion implantation. When the columnar body is simultaneously formed by ion implantation of the conductivity type opposite to the substrate conductivity type in the predetermined area region before the columnar body is formed, this second channel end region also forms the first channel end region. Combined with the ion implantation damage region in the expected area area, it can function as an ion implantation damage region having high wet etching resistance, and can be used as an etching mask when the columnar body is formed by wet etching.
On the other hand, in the region to be the second channel end region, ion implantation of the same conductivity type as the substrate conductivity type is performed before the columnar body is formed, and this is used as an ion implantation damage region having resistance to wet etching. You can also. In this case, the region to be the second channel end region is coupled with the ion implantation damage region in the planned area region where the first channel end region is to be formed, and serves as an etching mask having high resistance when forming the columnar body by wet etching. After functioning, an impurity having a conductivity type opposite to the substrate conductivity type is introduced into this to finally form a second channel end region.
Further, the second channel end region is formed by introducing an impurity having a conductivity type opposite to the substrate conductivity type after the columnar body is formed, or before the columnar body is formed, the substrate conductivity type to the above-mentioned predetermined area region is formed. In the case of being formed at the same time as the reverse conductivity type ion implantation, before the formation of the gate insulating film after the columnar body is formed, the second channel end region is subjected to heat treatment at a relatively high temperature. After performing impurity activation and bringing the second channel end region into electrical contact with at least the lower part of the columnar body, a gate insulating film made of a high dielectric constant thin film can be formed by a relative low temperature process.
Furthermore, in the first place, the positive area and the negative resist may be used for the determination of the planned area area that should ultimately become the first channel end region. The invention can be combined appropriately. That is, the area of the planned area on the semiconductor substrate where ions are to be implanted is defined such that the surface portion is exposed at the opening portion patterned with the positive resist formed on the semiconductor substrate. One method is to form the columnar body under a predetermined area region which is an ion implantation damaged region by wet etching after removing the positive resist after ion implantation. Instead, the planned area region is an area region cut out by dry etching or wet etching in advance on the semiconductor substrate after exposing the planned area region using a negative resist, or on the semiconductor substrate. The oxide film formed in this step is patterned into an area corresponding to a predetermined area using a negative resist, and the remaining oxide film after removal of the negative resist is used as a mask in an area region cut out by dry etching or wet etching in advance. Then, after removing the negative resist or oxide film mask remaining on the planned area region, the planned area region is made an ion implantation damaged region by ion implantation, and is then made into an ion implantation damaged region by wet etching. A columnar body may be formed under the predetermined area area.
In the case of a general silicon substrate, the concentration of ion implantation for forming the ion implantation damage region is at least 10 ¹³ / cm ⁻² or more, preferably 10 ¹⁴ / cm ⁻² or more. Of course, this value is also desirable in the case of other semiconductor substrates, and even if this is not the case, the concentration at which at least the ion implantation damage region exhibits sufficient etching resistance during subsequent wet etching of the semiconductor substrate is experimental. Can be determined.

FIG. 1 (A) is an explanatory view of a step of ion implantation, which is a characteristic step in the first example of the method for manufacturing a double gate type MOS field effect transistor according to the present invention.
FIG. 1 (B) is an explanatory diagram of the steps taken after FIG. 1 (A).
FIG. 1 (C) is an explanatory view of an ion implantation step which is a characteristic step in the second example of the method for manufacturing a double gate type MOS field effect transistor according to the present invention.
FIG. 1 (D) is an explanatory diagram of the steps taken after FIG. 1 (C).
FIG. 1 (E) is an outline of an example of the double-gate MOS field effect transistor of the present invention produced through the steps of FIGS. 1 (A) and 1 (B) or FIGS. 1 (C) and 1 (D). It is a block diagram.
FIG. 2 (A) is an explanatory diagram of a process corresponding to the process shown in FIG. 1 (A) in a more specific embodiment of the method of the present invention.
FIG. 2 (B) is an explanatory diagram of a step that follows the step of FIG. 2 (A).
FIG. 2 (C) is an explanatory diagram of the step of cutting out a narrow columnar body, which is a step subsequent to FIG. 2 (B).
FIG. 2D is an explanatory diagram of a process of performing ion implantation to form the second channel end region.
FIG. 2E is an explanatory diagram of a process for forming an oxide film including a gate insulating film.
FIG. 2 (F) is an explanatory diagram of the process of depositing the electrode material.
FIG. 2G is an explanatory diagram of the process of forming a pair of gates.
FIG. 2 (H) is a schematic configuration diagram of a double gate type MOS field effect transistor fabricated as one embodiment of the present invention.
FIG. 3 (A) is an explanatory diagram of a step of patterning a region to be the first channel end region in a more specific embodiment of the method of the present invention.
FIG. 3 (B) is an explanatory diagram of a process corresponding to the process shown in FIG. 1 (C), following the process of FIG. 3 (A).
FIG. 3C is an explanatory diagram of a process of forming a narrow columnar body in a self-aligning manner.
FIG. 3D is an explanatory diagram of the step of depositing the gate insulating film.
FIG. 3E is an explanatory diagram of a process of depositing an electrode material.
FIG. 3F is an explanatory diagram of the process of forming a pair of gates.
FIG. 3 (G) is a schematic configuration diagram of a double gate type MOS field effect transistor fabricated as a second embodiment of the present invention.
FIG. 4 (A) is an explanatory diagram of a step of patterning a region to be the first channel end region in still another embodiment of the method of the present invention.
FIG. 4 (B) is an explanatory diagram of a process corresponding to the process shown in FIG. 1 (C), following the process of FIG. 4 (A).
FIG. 4C is an explanatory diagram of a process of forming a narrow columnar body in a self-aligning manner.
FIG. 4D is an explanatory diagram of a process of bringing a pair of second channel end regions on the semiconductor substrate surface close to each other by heat treatment.
FIG. 4E is an explanatory diagram of a process of depositing a high dielectric constant thin film as a gate insulating film.
FIG. 4 (F) is an explanatory diagram of the step of depositing the electrode material.
FIG. 4G is an explanatory diagram of the process of forming a pair of gates.
FIG. 4 (H) is a schematic configuration diagram of a double gate type MOS field effect transistor fabricated as a third embodiment of the present invention.
FIG. 5 is a drawing showing a specific example of the relationship between the amount of ion implantation into the semiconductor substrate and the etch rate of the semiconductor substrate in the TMAH solution.
FIG. 6 (A) is a structural diagram of the element of the present invention that substitutes for an electron micrograph after the step of FIG. 3 (B) in a specific production example according to the present invention.
FIG. 6 (B) is a structural diagram of the element of the present invention substituted for an electron micrograph showing a pattern in which a narrow columnar body is cut out after the step of FIG. 6 (A).
FIG. 7 is a cross-sectional structure diagram of an example of a double gate MOS field effect transistor of the present invention actually produced according to the present invention, which is substituted by an electron micrograph.
FIG. 8 is a characteristic diagram regarding a threshold voltage and a subthreshold coefficient obtained based on an element manufactured according to the present invention.
FIG. 9A is a schematic configuration diagram of a conventional lateral double-gate MOS field effect transistor.
FIG. 9B is a schematic configuration diagram of a conventional vertical double-gate MOS field effect transistor.

The present invention will be described in more detail with reference to the accompanying drawings.
FIG. 1 will be described later with more detailed embodiments, but generally, the vertical double-gate MOSFET 10 shown in FIG. 1 (E) is finally obtained by two different procedures. The concept of the present technique is shown. One is a procedure shown in FIGS. 1A and 1B, and the other is a procedure according to FIGS. 1C and 1D.
As shown in FIG. 1 (E), the fabricated device has a narrow columnar body 13 standing up from the semiconductor substrate 11 as a channel, and is perpendicular to the electron traveling direction in the channel with respect to both side surfaces of the channel. A pair of gates G1 and G2 facing each other through a gate insulating film from the direction of the first channel end region 12 on the upper end side of the columnar body 13 is provided on the lower end side. In this structure, the second channel end region 14 which is the other of the drain and the source is provided. Desirably, the width t12 of the first channel end region 12 formed at the upper end of the narrow columnar body 13 is larger than the width t13 of the narrow columnar body 13 (that is, the thickness of the channel). (T13 <t12)). Conventionally, an element having such a structure cannot be recognized.
In FIG. 1 (E), the gate insulating film is not shown, but is shown as a space or a gap in order to simplify the drawing.
However, in the manufacturing method according to FIGS. 1A and 1B, first, as shown in FIG. 1A, the first channel end region is formed in the future by patterning the positive resist Rp. An area of a predetermined area to be determined is determined, and ions are implanted therein to form an ion implantation damaged region 12 having high etching resistance against wet etching. Then, after removing the positive resist Rp, as shown in FIG. 1 (B), wet etching is performed using the ion implantation damaged region 12 as a wet etching mask. By etching and lateral etching, a narrow columnar body 13 that will be a channel region in the future is formed under the ion implantation damage region 12. Thereafter, as will be described in detail in the description of the embodiment in FIG. 2 described later, a gate insulating film, a gate, and a second channel end region are formed to obtain the element structure 10 shown in FIG. 1 (E).
On the other hand, in the case of conforming to FIGS. 1C and 1D, a negative resist is used although not shown in the figure. That is, the planned area region 12 to be the first channel end region in the future is an area region cut out by dry etching or wet etching in advance on the semiconductor substrate after exposing the planned area region using a negative resist. Alternatively, an oxide film (not shown) formed on the semiconductor substrate is patterned into an area region corresponding to a predetermined area region using a negative resist, and the remaining oxide film after removing the negative resist is previously used as a mask. After removing the negative resist or the oxide film mask, which is an area region cut out by dry etching or wet etching, and remaining on the predetermined area region 12, ion implantation as shown in FIG. As shown in FIG. 1 (D), the planned area area is changed to the ion implantation damage area 12 by wet etching. By performing, under the plan area region which is an ion implantation damage region 12 to form a columnar body 13. In this case, at the time of ion implantation to the planned area region, the ion implantation is similarly performed on the region to be the second channel end region 14 in the future to be an ion implantation damaged region, and a region having high wet etching resistance Thus, an effective mask for wet etching of the columnar body 13 is obtained.
Thereafter, a detailed description will be given later with reference to the embodiment according to FIGS. 3 and 4, but in principle, the gate insulating film and the gates G1 and G2 are formed by a well-known method using a known method, and FIG. The final target device structure 10 shown in E) is obtained.
FIG. 2 shows a first example of a more specific and specific embodiment of the present invention. First, as shown in FIG. 2A, after applying a positive resist Rp on a semiconductor substrate (typically a silicon substrate) 11, a first channel end region 12 that will be either a drain or a source in the future is formed. A surface portion of a predetermined area region to be formed is patterned and opened in a window shape. In other words, the area of the predetermined area is defined by the opening of the positive resist Rp. In this state, an ion species Di of an impurity having a conductivity type opposite to the substrate conductivity type is implanted to form an ion implantation damaged region 12 over a certain depth. In the case where the ion implantation damage region 12 has the conductivity type of the ion species used opposite to the substrate conductivity type as described above, the first channel end region 12 which is finally formed is substantially as it is. In general, this is the drain.
The amount of impurity implantation by the ion implantation is set to a level that exhibits high etching resistance in which the formed ion implantation damaged region 12 is desirably hardly etched in the next semiconductor substrate wet etching process, which will be described later.
When the ion implantation is completed, the resist Rp is peeled off as shown in FIG. 2B, and then immersed in a hydrazine or TMAH solution, and wet etching is performed. As a result, as shown with an arrow in FIG. 2 (C), the non-damaged region that is not damaged by the ion implantation is etched, and the semiconductor substrate 11 is etched away leaving the ion implantation damaged region 12. At the same time, the portion under the ion implantation damaged region 12 is also removed by lateral etching, and as a result, a narrow columnar body 13 is formed under the ion implantation damaged region 12 in a self-aligned manner. This wet etching itself may be in accordance with a known method, and the plane orientation and the like are selected so as to be accompanied by lateral etching. However, in this wet etching method, by setting the area size of the initial ion implantation damage region 12 appropriately, The width of the columnar body 13 formed under the ion implantation damage region 12 can be controlled to 10 nm or less, which is desirably narrower than that of the existing double gate type device. In addition, the columnar body 13, which is an important region that will become a channel in the future, is not easily damaged by dry etching.
The reason why the ion species having the conductivity type opposite to that of the substrate is implanted is that it is convenient to use the ion implantation damaged region 12 as the first channel end region (generally drain) 12 as it is. In constructing an n-channel MOSFET, n-type impurity ions such as P, As, and Sb may be selected as ion species for the p-type substrate 11, and the n-type substrate 11 is selected to construct the p-channel MOSFET. If so, p-type impurity ions such as B and BF2 may be selected as the ion species. As for the concentration or dose of ion implantation, in addition to those represented by the above-mentioned wet etching solution, if the implantation concentration is at least 10 ¹³ / cm ⁻² or more for various solutions for dissolving silicon, Since it is known that the etching resistance is so high that it is not etched, the concentration is made higher than this. Even with other semiconductor substrates, it is easy to control the ion implantation amount to a value exhibiting high etching resistance with respect to the etching solution used for dissolution.
Incidentally, as a specific example, as shown in the relationship diagram between the ion implantation amount into the semiconductor substrate and the etching rate of the semiconductor substrate in the TMAH solution in FIG. 5, the As ion implantation amount is 10 ¹³ / cm ^{−. It} can be seen that a rapid drop in the etching rate is observed from above about ² , that is, the portion of the semiconductor substrate that has received such an injection amount exhibits sufficient etching resistance to the TMAH solution. Of course, this is also true for the ion implantation damage region 12 as it is. Of course, when the ion implantation damage region 12 is finally used as the first channel end region 12 as it is, the lower limit of the implantation concentration (irradiation amount) is determined to be not less than the above level. As long as there are no other constraining factors, the higher is better. This is because the resistance of the first channel end region 12 can be further reduced. This is an incidental but significant effect that has not been recognized in the past. If the implantation concentration is 10 ¹⁴ / cm ⁻² or more, which is at least one digit above the lower limit, the impurity concentration is the same as that of the drain and source in the existing MOSFET, and is in a range that can be used satisfactorily. If it is higher than that, a more desirable low resistance can be achieved. This also applies to other embodiments described later. In addition, the ability to form the first channel end region 12 having a sufficiently large dimension t12, that is, a large volume, greatly contributes to the reduction in resistance.
When the formation of the columnar body 13 is finished, as shown in FIG. 2D, an impurity Fi having a conductivity type opposite to that of the substrate conductivity type is implanted exclusively for forming the second channel end region. As a result, a region 14 to be a second channel end region (generally a source) will be formed in the future in the substrate surface region located on both sides of the ion implantation damage region 12 as viewed from above. As shown in FIG. 5E, an insulating film that covers the side surface of the columnar body 13 and includes a portion that will become the gate insulating film 15 in the future is grown by a known and appropriate method. At this time, a pair of second channel end regions 14 which existed independently on both sides of the ion implantation damaged region 12 which is the first channel end region 12 as viewed from above by heat treatment which is generally accompanied or by intentional heat treatment. The implanted impurities are activated to cause lateral diffusion, and even if they contact each other or do not contact each other, they extend at least to the lower end portion of the columnar body 13 that effectively becomes the channel 13 and are electrically connected thereto. To be in a state where it can conduct.
Thereafter, as shown in FIG. 2 (F), a gate electrode material (high-concentration polysilicon, metal, etc.), which may be an appropriate known material, is deposited on the entire surface, and here, dry etching is used to form FIG. If the pair of gates G1 and G2 are cut out in a self-aligning manner as shown in FIG. 5), the main structural portion of the vertical double-gate MOSFET 10 according to the present invention is substantially completed. Thereafter, if necessary, according to a known existing technique, as shown in FIG. 2 (H), the drain electrode Ed is generally formed on the drain as the first channel end region 12, and the source as the second channel end region 14 is provided. On the other hand, the source electrode Es may be provided, and the whole may be covered with the protective insulating film 16. Of course, extraction electrodes are also attached to the first and second gates G1 and G2.
In the above-described process, an impurity having a conductivity type different from that of the substrate 11 is selected as the implanted ion species Di. This is for eliminating the need to form the first channel end region 12 and etching resistance. Impurities having the same conductivity type as that of the substrate 11 may be selected only for the purpose of increasing the thickness of the columnar body 13 with high controllability and good controllability. There is only one reverse conductivity type impurity introduction step for forming a drain and a source separately after forming the columnar body, and there is no problem in achieving the basic object of the present invention. However, in the process shown here, since the reverse conductivity type impurity Fi is introduced to form the second channel end region 14 which is generally the source region in FIG. 2D, from the meaning, If the concentration at the time of implantation is increased, the number of steps is not particularly increased even if the conductivity type of the ion species implanted in the region 12 to be the first channel end region is the same conductivity type as that of the substrate.
FIG. 3 shows another process example for realizing the present invention. A negative resist is applied on the semiconductor substrate 11, and the surface equivalent portion of the area region to be the first channel end region is exposed and patterned in the future. As shown in FIG. Dry etching or wet etching is performed using the region Rn as a mask. Even if dry etching is adopted at this time, it is still for cutting out a predetermined area region in advance, and it is not intended to cut out and determine a channel region which is an important component as an element. In this case, the characteristics of the surface of the first channel end region 12 (the linear shape of the rectangular side portion) are more improved than the wet etching. Further, instead of using the remaining negative resist Rn, an oxide film formed on the semiconductor substrate is patterned into an area region corresponding to a predetermined area region using a negative resist, and the remaining oxide film after removing the negative resist is used as a mask. The area region to be the first channel end region may be cut out by dry etching or wet etching in advance. In this case, what is necessary is just to see the part to which the code | symbol Rn was attached | subjected in a figure as said residual oxide film mask.
After removing the resist (or the remaining oxide film), as shown in FIG. 3 (B), it is preferable to irradiate the substrate 11 with the ion species Di of the opposite conductivity type in terms of simultaneous formation of the drain and the source. A first channel end region 12 as an ion implantation damaged region is formed on the columnar body, and an ion implantation damaged region 14 to be a second channel end region 14 in the future is formed on the semiconductor substrate surface on both sides thereof.
Thereafter, these ion implantation damage regions 12 and 14 are used as a mask having high etching resistance, and wet etching is performed with an appropriate solution as described above, so that an arrow is shown in FIG. Then, only the lateral etching proceeds, and an extremely narrow columnar body 13 can be formed under the first channel end region 12 with good controllability in a self-aligning manner and without etching damage.
Next, as shown in FIG. 3 (D), an insulating film that covers both sides of the columnar body 13 and includes a portion that will become the gate insulating film 15 in the future is deposited by an insulating film growth step on the entire surface accompanied by heat treatment. At the same time, however, the impurity introduced into the second channel end region 14 is also activated in this process, and the second channel end region 14 is brought into electrical contact with at least the root of the columnar body 13.
Next, as shown in FIG. 3 (E), after the gate electrode material is formed on the entire surface, here, by a well-known etching technique that is good by dry etching, as shown in FIG. A pair of gates G1 and G2 are formed in a self-aligned manner so as to face each other with the gate insulating film 15 interposed therebetween, thereby completing the element main part structure.
Thereafter, in the same manner as described above, if necessary, the drain electrode Ed is generally formed on the drain 12 as the first channel end region 12 and the second channel end region 14 as shown in FIG. A source electrode Es is provided for the source 14 as described above, and the whole is covered with a protective insulating film 16, and an appropriate extraction electrode is attached to the first and second gates G 1 and G 2 although not shown.
FIG. 6 shows, as a specific example, an electron micrograph in a specific process when the process of FIG. 3 is followed. FIG. 6 (A) corresponds to the result after the process of FIG. 3 (B), and ion implantation is performed by cutting out an area region to be the first channel end region 12 (portion 12 surrounded by a virtual line). In the process of finishing, a columnar body corresponding to the width of the first channel end region 12 is cut out. A portion 14 surrounded by an imaginary line on the semiconductor substrate side is a portion that is also ion-implanted and becomes the second channel end region 14 in the future. FIG. 6 (B) corresponds to the result of the process of FIG. 3 (C). The width of the columnar body is cut, and as shown in FIG. 1 (E), a relatively thick dimension t12 is obtained. A relatively narrow columnar body 13 having a dimension t13 is surely formed under the first channel end region 12. In other words, even if the thickness of the channel 13 (the dimension in the direction orthogonal to both the channel length and the channel width) is reduced, the volume of the first channel end region 12 is not greatly reduced, and the element is reduced. The structure can greatly contribute to resistance.
FIG. 7 shows an electron micrograph of a specific completed device example that has completed all the steps of FIG. 3, and the reference numerals are the same as those used in each of the drawings so far. Indicates the corresponding components. Although the width of the narrow columnar body 13 corresponding to the channel thickness is sufficiently narrow, the sufficiently large first channel end region 12 is formed. More desirably, the second channel end region is larger than the gate insulating films (oxide films) 15 and 15 between the pair of gates G1 and G2 and the narrow columnar body 13 (channel). 14 and the gates G1 and G2, the insulating film (oxide film) portion 18 is thick, and the insulating film (oxidation film) between each first channel end region 12 and each gate G1 and G2 is oxidized. The thickness of the (film) portion 18 is also increased. This is a result of the oxide growth rate being enhanced by damage due to ion implantation. With such a structure, the second channel end region 14 and the first channel end region for each of the gates G1 and G2 are used. Since the 12 separation distances can be obtained, the overlap capacitance between the gate and each channel end region can be reduced, which is effective for high-speed operation of the device.
FIG. 8 shows the characteristics of the device manufactured according to the present invention. As shown in Fig. 1 (E) and Fig. 6 (B), the threshold voltage and subthreshold coefficient in each of saturation mode and linear mode are shown as one of important device parameters of vertical double gate MOSFET. It shows how it depends on the columnar width t13 (channel thickness). As the columnar width t13 is reduced, the short channel effect is suppressed, and both the threshold voltage and the subthreshold coefficient are ideal values. The experimental result and the calculation result are in good agreement.
FIG. 4 shows still another embodiment of the present invention. A negative resist is applied on the semiconductor substrate 11 and exposed, and is patterned so as to cover the surface of a predetermined area region to be the first channel end region in the future, and as shown in FIG. Dry etching or wet etching is performed using the negative resist region Rn as a mask. Even if dry etching is used, it is for cutting out the planned area 12 as described with reference to FIG. 3 above, and not for cutting out the channel region which is an important component of the device. The characteristics of the finally produced device are not impaired, and the same effect as described above with reference to FIG. 3 is obtained. Similarly, as described with reference to FIG. 3, instead of using the remaining negative resist Rn, an oxide film formed on the semiconductor substrate is formed into an area region corresponding to a predetermined area region using a negative resist. The area region 12 to be the first channel end region may be cut out by patterning and performing dry etching or wet etching in advance using the remaining oxide film after removal of the negative resist as a mask. In this case, the portion denoted by the symbol Rn in the figure becomes the remaining oxide film mask.
After removing the resist (or the remaining oxide film), as shown in FIG. 4 (B), this is also the simultaneous formation of the drain and the source. A first channel end region 12 as an ion implantation damage region is formed on the upper part of the body, and an ion implantation damage region 14 to be a second channel end region 14 in the future is formed on the semiconductor substrate surface on both sides thereof.
Thereafter, these ion implantation damaged regions 12 and 14 are used as a mask having high etching resistance, and wet etching is performed with an appropriate solution as described above, so that an arrow is shown in FIG. Then, only the lateral etching proceeds, and an extremely narrow columnar body 13 can be formed under the first channel end region 12 with good controllability in a self-aligning manner and without etching damage.
Next, as a process different from the process described with reference to FIG. 3, the implanted impurities are activated by heat treatment or the like which may be performed at a relatively high temperature, and as shown in FIG. The second channel end regions 14 and 14 on the semiconductor surface on both sides are brought close to each other and brought into contact with each other, or at least electrically contacted with the lower portion of the columnar body 13.
In this case, since the high temperature heat treatment is no longer necessary, it is desirable to form the gate insulating film 15 with a high dielectric constant insulating film by a relatively low temperature process, as shown in FIG. The high dielectric constant film can be grown and deposited on the entire surface.
That is, the gate insulating film 15 may be a very thin thin film, and the device characteristics are greatly improved. After doing so, as in the process example described with reference to FIG. 3, a gate electrode material is formed on the entire surface as shown in FIG. As shown in FIG. 4 (G), a pair of gates G1 and G2 are formed in a self-aligning manner with the gate insulating film 15 sandwiched between both side surfaces of the columnar body 13 by a technique, and the element main part structure is Finalize.
This method can be adopted as necessary in the embodiment described with reference to FIG. If the impurity activation by the heat treatment at a relatively high temperature is performed in advance before moving to the next gate insulating film manufacturing step in the step of FIG. 2 (D), then it can be passed through a low-temperature process and manufactured. Similarly, a high dielectric constant thin film can be used for the power gate insulating film 15.
Returning to the fourth embodiment shown in FIG. 4, after forming the pair of gates G1 and G2, the first channel end region 12 is formed as shown in FIG. In general, the drain electrode Ed is provided for the drain 12, and the source electrode Es is provided for the source 14 as the second channel end region 14, and the whole is covered with the protective insulating film 16, etc. Appropriate lead electrodes are attached to the first and second gates G1 and G2.
As mentioned earlier, in any of the production process examples, if it is possible to increase the source and drain separate formation processes, that is, the impurity introduction process, an ion implantation damaged region is formed. The conductivity type of the ionic species may be the same as that of the substrate 11.
Although the embodiment according to FIG. 2 has already been described, in the embodiment described with reference to FIGS. 3 and 4, for example, the second channel end region is formed in the step of FIG. Even if the conductivity type of the ion species implanted in the region corresponding to is the same as the substrate conductivity type, it still functions as a wet etching mask due to the ion damage effect during the subsequent columnar body formation, and then reverses the substrate conductivity type. The second channel end region 14 can be formed by conductive type impurity implantation. The same applies to step (B) of FIG. 4, and after functioning as a wet etching mask, the second channel end region 14 may be formed by introducing impurities having a conductivity type opposite to the substrate conductivity type in an appropriate step. it can.
It should be noted that the columnar body 13 having a relationship of standing with respect to the semiconductor substrate 11 is also included in the present invention even when the complete verticality is not maintained. When intentionally tilting, it includes the case of unintentionally tilting.

According to the present invention, the following advantages can be expected as compared with the conventional double gate type MOSFET, and a truly practical device can be provided to the market.
1) Unlike the conventional case, the upper end portion of the thin channel portion is a narrow first channel end region (generally a drain) that is not so narrow as the thickness of the channel. Since the first channel end region has a sufficiently large width as compared with the width of the body, a sufficiently satisfactory low resistance region can be obtained.
2) Even when looking at the present invention as a manufacturing method, a columnar body constituting a channel can be formed in a self-aligned manner by wet etching using an ion implantation damaged region as a mask. The columnar body can be formed systematically in the width. That is, an element with a very thin channel can be provided.
3) In this method, unlike the conventional case, the upper end portion of the thin channel portion becomes the narrow first channel end region (generally the drain) as it is, compared to the width of the columnar body. Since the first channel end region has a sufficiently large width and can secure a necessary thickness depending on the amount of ion implantation, a sufficiently satisfactory low resistance region can be obtained. In addition, there is no problem even if the ion implantation amount is increased even if the concentration is higher than the concentration at which sufficient etching resistance can be exhibited in order to further increase the etching resistance, and this can further reduce the resistance.
4) Since the columnar body serving as a channel is formed by wet etching, it can be prevented from being severely damaged as in the case of dry etching, but can be almost undamaged, which ultimately contributes to improvement of device characteristics.
5) For example, as shown in FIG. 4, it is possible to adopt a step of depositing an insulating film to be a gate insulating film after a step requiring high-temperature heat treatment is completed. Henceforth, it becomes possible to use the high dielectric constant thin film without problems by using only the low temperature process, which can greatly contribute to the improvement of the device characteristics.

Claims (13)

A narrow columnar body standing up from a semiconductor substrate is used as a channel, and the columnar body has a pair of gates facing each other through a gate insulating film from both sides of the channel from a direction orthogonal to the electron traveling direction in the channel. A vertical double-gate MOS electric field in which a first channel end region that is one of a drain and a source is provided on the upper end side, and a second channel end region that is the other one of a drain and a source is provided on the lower end side An effect transistor;
The width of the first channel end region is larger than the width of the narrow columnar body and the dimension of the channel sandwiched between the pair of gates via the gate insulating film;
A double-gate MOS field effect transistor. The thickness of the insulating film between the gate and the second channel end region and the thickness of the insulating film between the gate and the first channel end region are larger than the thickness of the gate insulating film;
2. The double gate type MOS field effect transistor according to claim 1, wherein A narrow columnar body standing up from a semiconductor substrate is used as a channel, and the columnar body has a pair of gates facing each other through a gate insulating film from both sides of the channel from a direction orthogonal to the electron traveling direction in the channel. A vertical double-gate MOS electric field in which a first channel end region that is one of a drain and a source is provided on the upper end side, and a second channel end region that is the other one of a drain and a source is provided on the lower end side A method for producing an effect transistor;
A step of implanting ions into a planned area region to be used as the first channel end region in the future to be an ion implantation damaged region having high etching resistance to wet etching on the semiconductor substrate;
Forming the narrow columnar body substantially serving as a channel under the ion implantation damage region by wet etching using the ion implantation damage region as an etching mask;
Then, after forming a gate insulating film on both side surfaces of the columnar body, the both side surfaces are opposed to each other from the direction perpendicular to the electron traveling direction in the channel across the channel, and face each of the channels. Forming a second gate;
A process for producing a double-gate MOS field effect transistor comprising: The conductivity type of ions implanted to form the ion implantation damage region is opposite to the substrate conductivity type;
The ion implantation damage region is used as the first channel end region even after the device is completed;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The conductivity type of ions implanted to form the ion implantation damage region is the same conductivity type as the substrate conductivity type;
After the columnar body is formed in the ion implantation damaged region, an impurity having a conductivity type opposite to that of the substrate conductivity type is introduced to form the first channel end region;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The second channel end region is formed by introducing impurities having a conductivity type opposite to the substrate conductivity type after the columnar body is formed, or the substrate conductivity type to the predetermined area region is formed before the columnar body is formed. Are formed simultaneously with the reverse conductivity type ion implantation;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The second channel end region is formed simultaneously with the ion implantation of the conductivity type opposite to the substrate conductivity type to the predetermined area region before the columnar body is formed;
Accordingly, the second channel end region also functions as an ion implantation damage region having etching resistance in combination with the ion implantation damage region in the planned area region where the first channel end region is to be formed, and the columnar body is formed by the wet etching. To serve as an etching mask when
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The region to be the second channel end region is formed as an ion implantation damage region having resistance to wet etching by ion implantation of the same conductivity type as the substrate conductivity type before the columnar body is formed;
Accordingly, the region to be the second channel end region also functions as an ion implantation damage region having etching resistance in combination with the ion implantation damage region in the planned area region where the first channel end region is to be formed, and the columnar body is formed. When forming by the wet etching, it becomes an etching mask, and after the columnar body is formed, the second channel end region is formed by introducing an impurity having a conductivity type opposite to the substrate conductivity type;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The second channel end region is formed by introducing impurities having a conductivity type opposite to the substrate conductivity type after the columnar body is formed, or the substrate conductivity type to the predetermined area region is formed before the columnar body is formed. Are formed simultaneously with the reverse conductivity type ion implantation;
After the columnar body is formed and before the gate insulating film is formed, the second channel end region is activated by heat treatment so that the second channel end region is in electrical contact with at least the lower portion of the columnar body. rear;
Forming a gate dielectric film with a high dielectric constant thin film by a relative low temperature process;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The area of the predetermined area on the semiconductor substrate to which the ions are to be implanted is defined such that the surface portion is exposed in an opening portion obtained by patterning a positive resist formed on the semiconductor substrate;
After the ion implantation, the columnar body is formed under the predetermined area region as the ion implantation damaged region by wet etching after removing the positive resist;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The predetermined area region on the semiconductor substrate to which the ions are to be implanted was cut out by dry etching or wet etching in advance on the semiconductor substrate after the predetermined area region was exposed using a negative resist. An area region or an oxide film formed on the semiconductor substrate is patterned into an area region corresponding to the predetermined area region using a negative resist, and the remaining oxide film on the predetermined area region after removing the negative resist is used as a mask. Area area cut out by dry etching or wet etching in advance;
After making the predetermined area region into the ion implantation damaged region by the ion implantation after removing the negative resist or the mask of the oxide film remaining on the predetermined area region;
Forming the columnar body under the predetermined area region, which is the ion implantation damage region, by wet etching;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The semiconductor substrate is a silicon substrate;
The concentration of the ion implantation is at least 10 ¹³ / cm ⁻² or more;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein: The semiconductor substrate is a silicon substrate;
The concentration of the ion implantation is 10 ¹⁴ / cm ⁻² or more;
A method for manufacturing a double-gate MOS field effect transistor according to claim 3, wherein:

Images