JPS649564A - Processing system in plural processing circuits - Google Patents

Processing system in plural processing circuits

Info

Publication number
JPS649564A
JPS649564A JP16610187A JP16610187A JPS649564A JP S649564 A JPS649564 A JP S649564A JP 16610187 A JP16610187 A JP 16610187A JP 16610187 A JP16610187 A JP 16610187A JP S649564 A JPS649564 A JP S649564A
Authority
JP
Japan
Prior art keywords
processing
synchronizing signal
processing circuit
circuit
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16610187A
Other languages
Japanese (ja)
Inventor
Akira Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP16610187A priority Critical patent/JPS649564A/en
Publication of JPS649564A publication Critical patent/JPS649564A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To contrive the speed up of an arithmetic processing by giving a synchronizing signal from a synchronizing signal generating circuit in common to each processing circuit so as to allow the processing circuit to receive/give information in response to the synchronizing signal, thereby simplifying the program. CONSTITUTION:In applying decentralizing processing by using plural processing circuits 12-14, a synchronizing signal generating circuit 18 gives a synchronizing signal to the processing circuits 12-14 in common, which receive/give information in response to the synchronizing signal. Thus, each processing circuit applies transmission/reception of information and arithmetic processing based thereupon during a time equal to the period of the synchronizing signal. Thus, it is not required for the processor operation where a processing circuit discriminates the operating state of the other processing circuit and the time for arithmetic processing is shortened.
JP16610187A 1987-07-01 1987-07-01 Processing system in plural processing circuits Pending JPS649564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16610187A JPS649564A (en) 1987-07-01 1987-07-01 Processing system in plural processing circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16610187A JPS649564A (en) 1987-07-01 1987-07-01 Processing system in plural processing circuits

Publications (1)

Publication Number Publication Date
JPS649564A true JPS649564A (en) 1989-01-12

Family

ID=15825030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16610187A Pending JPS649564A (en) 1987-07-01 1987-07-01 Processing system in plural processing circuits

Country Status (1)

Country Link
JP (1) JPS649564A (en)

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