JPS6491272A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS6491272A
JPS6491272A JP24943787A JP24943787A JPS6491272A JP S6491272 A JPS6491272 A JP S6491272A JP 24943787 A JP24943787 A JP 24943787A JP 24943787 A JP24943787 A JP 24943787A JP S6491272 A JPS6491272 A JP S6491272A
Authority
JP
Japan
Prior art keywords
circuit
output
register
arithmetic
calculation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24943787A
Other languages
Japanese (ja)
Inventor
Yukio Endo
Takao Nishitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24943787A priority Critical patent/JPS6491272A/en
Publication of JPS6491272A publication Critical patent/JPS6491272A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain a calculation processing without the interruption of pipe lines in respective calculation stages by arranging respective arithmetic circuits in serial in accordance with processing contents. CONSTITUTION:In the case of subtraction square calculation accumulation, it is necessary to set the arrangement of an arithmetic circuit to be the serial connection of an arithmetic logical circuit a multiplication circuit an accumulating circuit. It is previously set that selection circuits 4 and 5 select the output 103 of a register 7 storing the output of the arithmetic logical circuit 3 and a selection circuit 9 selects the output 107 of a register 8 storing the output of the multiplying circuit 6 as an initial state. An input sample X0 is simultaneously inputted from an input terminal 1, and an input sample Y0 from an input terminal 2, and (X0-Y0) is calculated in the arithmetic logical circuit 3, whereby it is stored in the register 7. Since the amplification circuit 6 inputs the outputs 104 and 105 of the selection circuits 4 and 5 and executes multiplication, and the selecting circuits 4 and 5 select the output 103 of the register 7, (X0-Y0)<2> is outputted to the output 106 of the multiplying circuit 6. Thus, circuit structure is set to adjust to sequential calculation.
JP24943787A 1987-10-01 1987-10-01 Arithmetic circuit Pending JPS6491272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24943787A JPS6491272A (en) 1987-10-01 1987-10-01 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24943787A JPS6491272A (en) 1987-10-01 1987-10-01 Arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS6491272A true JPS6491272A (en) 1989-04-10

Family

ID=17192955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24943787A Pending JPS6491272A (en) 1987-10-01 1987-10-01 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS6491272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023384A1 (en) * 1993-03-31 1994-10-13 Sony Corporation Apparatus for adaptively processing video signals

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173382A (en) * 1985-01-28 1986-08-05 Matsushita Electric Ind Co Ltd Digital signal processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61173382A (en) * 1985-01-28 1986-08-05 Matsushita Electric Ind Co Ltd Digital signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023384A1 (en) * 1993-03-31 1994-10-13 Sony Corporation Apparatus for adaptively processing video signals

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