JPS6488768A - Bus monitoring device for multi-cpu system - Google Patents

Bus monitoring device for multi-cpu system

Info

Publication number
JPS6488768A
JPS6488768A JP62244108A JP24410887A JPS6488768A JP S6488768 A JPS6488768 A JP S6488768A JP 62244108 A JP62244108 A JP 62244108A JP 24410887 A JP24410887 A JP 24410887A JP S6488768 A JPS6488768 A JP S6488768A
Authority
JP
Japan
Prior art keywords
cpu
board
system bus
boards
bus monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62244108A
Other languages
Japanese (ja)
Inventor
Akira Oba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62244108A priority Critical patent/JPS6488768A/en
Publication of JPS6488768A publication Critical patent/JPS6488768A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To ensure successive actions for normal CPU boards by adding a system bus monitoring means to a multi-CPU system to produce a resetting signal so that the use of a system bus is inhibited for the CPU board having abnormality in case this defective CPU board is occupying the system bus. CONSTITUTION:A latch port 11 is added to a system bus monitoring device 9 and at the same time, NAND gates 12-15 are added to the input signal lines 2a-5a led from the CPU boards 25 respectively. In case the device 9 has abnormality in one of those CPU boards, e.g., a CPU board 2, '1' is given to the port 11 as an access inhibiting signal to the board 2. Thus the input of an access request signal is avoided to the board 2 and therefore, the access request signals are supplied to other three CPU boards 3-5 only. Thus these three normal CPU boards can perform their actions. In such a way, the availability of a multi-CPU system is improved.
JP62244108A 1987-09-30 1987-09-30 Bus monitoring device for multi-cpu system Pending JPS6488768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244108A JPS6488768A (en) 1987-09-30 1987-09-30 Bus monitoring device for multi-cpu system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244108A JPS6488768A (en) 1987-09-30 1987-09-30 Bus monitoring device for multi-cpu system

Publications (1)

Publication Number Publication Date
JPS6488768A true JPS6488768A (en) 1989-04-03

Family

ID=17113874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244108A Pending JPS6488768A (en) 1987-09-30 1987-09-30 Bus monitoring device for multi-cpu system

Country Status (1)

Country Link
JP (1) JPS6488768A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08161279A (en) * 1994-12-08 1996-06-21 Nec Corp Multiprocessor system
JPH0944378A (en) * 1995-07-28 1997-02-14 Nec Corp Bus fault detector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08161279A (en) * 1994-12-08 1996-06-21 Nec Corp Multiprocessor system
JPH0944378A (en) * 1995-07-28 1997-02-14 Nec Corp Bus fault detector

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