JPS6488658A - Precedence type cache transfer system - Google Patents

Precedence type cache transfer system

Info

Publication number
JPS6488658A
JPS6488658A JP62245425A JP24542587A JPS6488658A JP S6488658 A JPS6488658 A JP S6488658A JP 62245425 A JP62245425 A JP 62245425A JP 24542587 A JP24542587 A JP 24542587A JP S6488658 A JPS6488658 A JP S6488658A
Authority
JP
Japan
Prior art keywords
information
high speed
transfer
speed buffer
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62245425A
Other languages
Japanese (ja)
Inventor
Noriyuki Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62245425A priority Critical patent/JPS6488658A/en
Publication of JPS6488658A publication Critical patent/JPS6488658A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To improve the probability of objective information exists on a high speed buffer and to shorten a waiting time due to information transfer by generating a transfer request beforehand in precedence to the execution of an instruction in which the purpose information is necessary, for an information transferring means from an operation mechanism. CONSTITUTION:An operation mechanism 11 has a means to generate a transfer request instruction to instruct to transfer desired information on a memory mechanism 13 beforehand to a high speed buffer 14 and shifts to the execution of the instruction string of connection without the completion of the information transfer action of an information transfer mechanism 15. On the other hand, the information transfer mechanism 15, when the requested information does not exist at the high speed buffer 14, removes the information block including the information from the memory mechanism 13 and transfers to the high speed buffer 14. Thus, the necessary time is already transferred to the high speed buffer 14 or on the way and without a waiting time or with a small quantity of the waiting time, an instruction processing is executed.
JP62245425A 1987-09-29 1987-09-29 Precedence type cache transfer system Pending JPS6488658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245425A JPS6488658A (en) 1987-09-29 1987-09-29 Precedence type cache transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245425A JPS6488658A (en) 1987-09-29 1987-09-29 Precedence type cache transfer system

Publications (1)

Publication Number Publication Date
JPS6488658A true JPS6488658A (en) 1989-04-03

Family

ID=17133464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245425A Pending JPS6488658A (en) 1987-09-29 1987-09-29 Precedence type cache transfer system

Country Status (1)

Country Link
JP (1) JPS6488658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6912650B2 (en) 2000-03-21 2005-06-28 Fujitsu Limited Pre-prefetching target of following branch instruction based on past history

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6912650B2 (en) 2000-03-21 2005-06-28 Fujitsu Limited Pre-prefetching target of following branch instruction based on past history

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