JPS648863B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a replacement memory, and more specifically, in a storage device having a regular memory and a replacement memory used as a substitute for the memory, the present invention relates to a method for controlling a replacement memory from a regular memory to a replacement memory. The present invention relates to a switching control method when switching to use.

Conventionally, replacement memory is switched from normal memory when an error correction circuit (ECC) detects an error in data read from a storage device in response to an access request from a channel device, CPU, or the like.

In other words, as shown in FIG. 1, an access request source 1 such as a CPU or a channel to the storage device 2
When the storage control unit 4 detects an error in the data read out from the storage module 3 by 1, 1 _{2 .} . . 1n, switching from the normal memory to the alternate memory _is executed.

The conventional switching method will be explained in more detail using FIG.

In Figure 2, 10 ₁ , 10 ₂ ,...10 _o are
This is a start signal (GO) corresponding to the access request sources 1 ₁ , 1 ₂ , . . . 1 _o and is input to the selector 30 . The selector 30 performs preferential selection control of the activation signal, and its output 11 is input to address/control circuits 31 and 32. 31 is an address/control circuit for the normal memory, and 32 is that for the alternate memory. The outputs 12 and 13 of 31 and 32 drive the normal memory 33 and the alternate memory 34. The data 14 and 15 read from it are
The data are stored in data registers 35 and 36, respectively. On the other hand, the _write data _{20 1 , 20 2 , .} The signal is input to the selector 42. The selector 42 selects and outputs the bit position to be replaced in the data 21 using the output 19 of the replacement control register 39, which will be described later.
The data is stored in the write data register 43 for spare memory. The outputs 22 and 23 of the registers 41 and 43 are input to a normal memory 33 and an alternate memory 34, and data is written therein when the address/control circuits 31 and 32 are activated. Now, let us assume that there is no error in the normal memory 33. In such a case, the output 19 of the alternation control register 39 causes the selector 37 to
Output 1 of normal memory read data register 35
6 and the output 17 of the read data register 36 for spare memory, the output 16 is selected and output. In the circuits 42 and 32, the output 18 of the selector 37, which can execute or inhibit the operation of these circuits, is input to an error correction circuit 38, which detects whether or not there is an error. The correction is executed, and the output 24 is input to the read data sending circuit 44 and sends out the read data 25 ₁ , ... 25 _o corresponding to the request sources ₁ 1 , 1 ₂ , ... 1 _o , and at the same time, the output 24 is sent to the alternation control register 39. , to notify information on alternate bit locations.

In this state, access request sources 1 ₁ , 1 ₂ ,
..., 1 _o , writing or reading is executed.

Let us now assume that an error occurs in the data read from the normal memory 33 while operating in the access mode described above. The error is detected by the error correction circuit 38
Needless to say, this is confirmed by. Then, the replacement control register 39 sends the replacement bit location information to its output 19, the selector 42 selects a given bit from the data 21, and the selector 37 selects a given bit from the output 16. select a given bit from output 17 and address/control circuit 32
In this case, activation of the output 11 is enabled.
In this way, errors occurring in the normal memory can be removed from the system by switching to the spare memory to take over. However, in the above-mentioned conventional method, only errors in addresses of the storage device that are read and accessed by the access request source are subject to replacement, so errors inherent in addresses that are not accessed are left unattended. There is. Furthermore, in the case where one processing cycle includes a fixed amount of time for performing a switching operation, for example, if the switching operation is not performed, the data transfer efficiency decreases and the access time increases from the perspective of the access source. There are drawbacks. Furthermore, it is conceivable that one processing cycle of normal access does not include time for a replacement operation, and the access time is extended only when an error that is a target of the replacement operation is detected, but this would complicate control.

The present invention eliminates the above-mentioned drawbacks, provides a replacement control method for replacement memory that targets errors latent in addresses corresponding to all addresses of a storage device, and does not cause an increase in access time compared to an access request source. It provides:

Therefore, the present invention switches from the normal memory to the spare memory when the storage control unit detects an error in data read in response to an access request from an access request source. In the alternate memory switching control system, a cyclic access generation circuit is provided that cyclically generates addresses corresponding to all addresses of the normal memory and operates independently of an access request operation from the access request source, and In addition to the access requests from the request source, the storage control unit processes access requests that are always generated at a predetermined period from the cyclic access generation circuit, and the spare memory is used as a replacement for the error in the normal memory. , is characterized in that it is performed only when an error occurs in the data read by the access request from the cyclic access generation circuit.

The operation of the present invention will be explained using FIGS. 3 and 4.

In FIG. 3, 1 to 3 are completely the same as in FIG. 1, except that a cyclic access generation circuit 51 is provided, and in addition to access request sources 1 ₁ to ₁ The difference is that requests are also processed in the storage control unit 50. Furthermore,
The circuit 51 issues an access request at a predetermined period, and the control unit 50 performs selection control with a high priority, and if an error is detected in the data read by the access from the circuit 51, and The present invention is fundamentally different from conventional inventions in that only this case is targeted for switching to the spare memory.

Referring to FIG. 4, the operation of the present invention will be explained in more detail.

Circuits and output lines with the same numbers as in FIG. 2 operate exactly the same as in FIG. Cyclic access generation circuit 10
0 is provided, and the difference is that this output 10p is input to the selector 30 and the alternation control register 39. In this circuit 100, accesses are periodically generated while sequentially incrementing addresses corresponding to all addresses in the normal memory.

The configuration of this circuit is a very general circuit that can be easily assembled using ordinary logic circuits such as counters, so it will not be described further. When the error correction circuit 38 recognizes that there is an error in the data read from the normal memory 33 due to the access request 10p generated by the circuit 100, it switches to the alternate memory 34 using the same procedure as the conventional method described above. Ru. Normal access request source 1 ₁ , 1 ₂ ,...1 _o
Even if there is an error in the read data, the error correction circuit 38 only detects the presence or absence of the error and corrects it, and does not control switching to the alternate memory at all.

According to the present invention described above, in response to an error inherent in the normal memory, switching to the alternate memory is performed regardless of whether or not there is an access from the access request source.
There is an advantage that not only errors in the storage device are eliminated, but also the disadvantage that the access time from the normal access source is lengthened due to the process of switching to the alternate memory can be avoided.

[Brief explanation of the drawing]

1 and 2 are block diagrams for inventing a conventional alternation control, and FIGS. 3 and 4 are block diagrams for explaining an embodiment of alternation control of the present invention. 30, 37, 40, 42...Selector, 31,
32...Address/control circuit, 33...Normal memory, 34...Alternative memory, 35, 36, 41, 4
3...Data register, 38...Error correction circuit,
39...Alternative control register, 44...Data sending circuit, 100...Cyclic access generation circuit.

Claims (1)

[Claims] 1. Switching of the spare memory, which switches from the normal memory to the spare memory when an error is detected in the storage control unit in data read in response to an access request from an access request source. In the control method, a cyclic access generation circuit is provided that cyclically generates addresses corresponding to all addresses of the normal memory and operates independently of the access request operation from the access request source, and In addition to access requests, the storage control unit processes access requests that are always generated at predetermined intervals from the cyclic access generation circuit, and the switching control from the normal memory to the alternate memory is performed based on the access requests from the cyclic access generation circuit. A switching control method for a spare memory is characterized in that switching is performed only when an error occurs in data read by.