JPS648825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display output information generation circuit for generating display output information to be supplied to a liquid crystal display device in a digital processing circuit such as a calculator or a digital counter.

Conventional display methods of this type include a static drive method and a dynamic drive method. The static driving method is to light all segments at the same time, and the dynamic driving method is to selectively light segments in groups. In either method, as the number of display digits increases, the number of segment groups increases, and therefore the number of data latches that determine the display state of the segments also increases. This is because basically a data latch corresponding to each individual segment is required. As the number of data latches increases, the state control of these data latches becomes complicated. Normally, in software-oriented electronic circuits such as microcomputers, digits are read out one by one from main memory such as RAM, and then converted directly or through appropriate conversion to the latch group corresponding to that digit in the data latch group. Write selectively. Therefore, in order to select the corresponding latch group, selection signals must be generated for the number of digits. Various methods have been implemented, but most of them require a dedicated decoder. This results in an increase in the number of components of the electronic circuit, which has a direct impact on cost, especially when integrated circuits are implemented.

A conventional example will be described below with reference to the drawings.

FIG. 1 is an example of the prior art. 1 is a RAM where displayed information is stored, 2 is a data bus,
3 is a latch that temporarily holds the displayed information, 4 is a digit signal output circuit corresponding to the displayed information, 5 is a displayed information transfer bus, 6 is a group of segment latches for displayed information, and 7 is a liquid crystal segment group. It is. RAM
The displayed information stored in latch 1 is first transferred to latch 3. Next, by the digit signal output circuit 4,
By decoding the displayed digit information transferred from the RAM 1 and selecting a desired latch group from the display information segment latch group 6 using the decoded output, the contents of the latch 3 are transferred via the transfer bus 5. Then, the data is transferred to the selected desired latch group and held. The contents of this latch 6 are used as they are as lighting/non-lighting information for the liquid crystal segment group 7. Thereafter, the displayed information is transferred to the remaining latch groups 6 in the same manner.

As described above, the digit signal output circuit 4 is essential, but it is a dedicated circuit for selecting the segment latch group 6 for displayed information and has no other purpose. Therefore, it is not used at all except during the display information operation period. In other words, the circuit is useless outside of this period.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a display system output circuit that can supply display information signals and display digit signals with a simple circuit configuration and with a reduced amount of hardware.

A more specific object of the present invention is to eliminate a dedicated decoder for supplying display digit signals and provide a flexible and efficient circuit configuration.

The display circuit according to the present invention is an electronic circuit including a central processing unit (CPU) that executes arithmetic control, a RAM that stores and memorizes various data, and a latch for displaying a liquid crystal segment. Means for logically multiplying the address line of the RAM and the common strobe signal for reading the segment latch output from the CPU is provided, and the output signal of the logical product means becomes the strobe signal for writing the segment latch. It is configured.

According to the above configuration, there is no need to use a dedicated decoder, and the object of the present invention is completely achieved.
The present invention will be explained in more detail with reference to the upper and lower drawings.

FIG. 2 shows an embodiment of the present invention. 1 is a RAM in which the information to be displayed is stored, 2 is a data bus to which the information in RAM ₁ is transferred, 3 is a latch that temporarily stores the contents of data bus 2, and 5 is a latch in which the contents of latch 3 are transferred to the display circuit. 6 is a segment latch group for display information, 7 is a liquid crystal segment group, 8 is an address decoder for RAM ₁ , 9 is a display information transfer bus.
1 is a system control CPU; 10 is a common strobe signal for reading segment latch output from the CPU 9; and 11 is a group of logical product means for the output of the address decoder 8 and the common strobe signal 10. As a result of various logical operations, display data is first stored in RAM ₁ . Next, RAM ₁ indicated by address decoder 8
data is primarily stored in latch 3 through data bus 2. Since the output of this latch 3 is sent to the transfer bus 5, an arbitrary specified partial latch group among the segment latch group 6 is connected to the logical product means group 1.
1 is selected, and the transfer bus 5, that is, the data to be displayed, is read here. The data thus written to the segment latch group 6 is sent as is to the liquid crystal segment group 7, where the display character shape is determined. As can be seen, no dedicated decoder is required to select any particular partial latch group of the segment latch group 6. in particular,
For example, in address decoder 8, address 8-1
If 8-1 is selected, only this address 8-1 is active, that is, in an active state. Next, when the common strobe signal becomes active, the AND gate 11-1 of the logical product means group 11 performs the product and becomes active. This AND gate 11-1
The output of is the partial latch group 6 of the segment latch group 6.
-1 read signal. The number of latches included in the partial latch group 6-1 may be singular or plural. If there are multiple, AND gate 11
The output of -1 becomes a common read signal only for the partial latch group 6-1, and is supplied to all latches included in the partial latch group 6-1.

In this way, the displayed data on the transfer bus 5 is
It is written to the corresponding latch of partial segment latch group 6-1. Furthermore, the written results are led to each corresponding segment of the liquid crystal partial segment group 7-1 to determine the lighting state. This partial segment group corresponds to the actual digit.

In the above explanation, the timing at which the latch 3 is latched, the timing at which the address decoder 8 of the RAM is determined, and the timing at which the common strobe signal 10 is output are described as being shifted in time, but this is not limited to this. It doesn't matter, and it can be any time relationship. For example, all of the above timings may coincide. In this case, the output of address decoder 8 indicates the data address to be displayed in RAM ₁ and also selects the partial segment latches of segment latches 6. i.e. RAM ₁
The data storage address and segment display digit can be made to correspond on a 1:1 basis. Also latch 3
may include a decoder, and even if it includes only a decoder, it does not depart from the scope of the claims of this patent. Furthermore, although it is described that there is a 1:1 correspondence between the address decoder 8 and the AND means 11, it goes without saying that the correspondence is not limited to 1:1. For example, a plurality of outputs of the address decoder 8 are logically summed, and the output of this logical sum is input to the logical product group 11, and the common strobe signal 10 is
It is also possible to perform a logical product with

As explained above, according to the present invention, there is no need for a dedicated digit selection decoder for data transfer to the display circuit, the circuit configuration is simple, and a free digit selection method can be achieved with only a command or a slight modification of the circuit. Since the circuit structure can be selected, a highly flexible circuit configuration can be realized, which is very advantageous in terms of design cost, and the effects of the present invention are significant.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of a conventional circuit example. FIG. 2 is a basic block diagram of an embodiment according to the present invention. 1... Display data storage RAM, 2... Data bus, 3... Latch, 4... Decoder, 5... Display data transfer bus, 6... Display information segment latch group, 7... Liquid crystal segment group, 8 ……RAM
Address decoder, 9... CPU, 10... common strobe signal, 11... logical product means group.

Claims (1)

[Claims] 1. A display section having a plurality of display digits, a memory section including a plurality of memory areas in which display data to be displayed on each of the plurality of display digits is stored, and an address for individually selecting the plurality of memory areas. address generating means for generating a signal; a first latch circuit for temporarily storing display data read from the plurality of memory areas; and a plurality of latch circuits provided corresponding to each of the plurality of display digits. a display data transfer bus that commonly connects the first latch circuit and the plurality of second latch circuits; and a display data transfer bus that connects the first latch circuit to the plurality of second latch circuits; means for generating a strobe signal for instructing the timing of reading the output display data into the second latch circuit; one input terminal commonly receiving the strobe signal; the other input terminal receiving the plurality of memory areas; a group of gate circuits each independently receiving an address signal to select one of the plurality of memory areas, the gate circuit receiving the address signal when the strobe signal is generated in response to an address signal selecting one of the plurality of memory areas; A display circuit characterized in that the display data stored in the first latch circuit is written only to a corresponding second latch circuit among the plurality of second latch circuits based on the output of the plurality of second latch circuits.