JPS61156195A - Image data rotation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a rotation circuit that rotates image data by ±90° in an apparatus that displays or prints image data on a page-by-page basis.

(Prior Art) Conventionally, there has been a device of this type as described in Japanese Patent Laid-Open No. 57-1301.44, and FIG. 2 shows its configuration. In the figure, 1 is an image data memory that stores image data, 2 is a word address generation circuit that writes image data read from the image data memory 1 into an image data storage memory 5 (described later) in word units, and 3 is a word address generation circuit that writes the image data read from the image data memory 1 in units of words. A read bit address generation circuit for reading image data bit by bit from the image data storage memory 5; 4 a multiplexer for switching between the output of the write word address generation circuit 2 and the output of the read bit address generation circuit 3; 5 a multiplexer for image data; This is an image data storage memory that stores the output of the memory 1.

Next, the operation will be explained. In other words, image data memory! If the image data storage memory 5 is composed of m words from word (0) to word (m-1), with n bits as one word, as shown in the address allocation shown in FIG. The image data is composed of m addresses from word address (0) to word address (m-1). Therefore, the image data is ±9
In order to perform zero rotation, the multiplexer 4 first selects the output of the write word address generation circuit 2, and writes the contents of the image data memory 1 into the same position of the image data storage memory 5 in units of words. Then, after writing all the words (m words), switch the multiplexer 4 to the read bit address generation circuit 3, set the read bit addresses as p-q, and read out the bits according to the procedures shown in FIGS. 4 and 5, respectively. This rotates the image data by +90 or -90''.

(Problems to be Solved by the Invention) However, in the device with this conventional configuration, in order to rotate the image data by ±90°, a high-speed image data storage memory is inevitably required, and the peripheral circuitry is therefore complicated. , and because it becomes physically larger,
This method has drawbacks such as not being applicable to small devices.

Therefore, in order to eliminate these drawbacks, the present invention provides a high speed, compact and economical image data rotation circuit of ±90° using an image data memory and a simple peripheral circuit.

(Means for Solving the Problems) The present invention provides an address generation circuit for generating an address for an image data memory and switching between writing and reading in an image data upper rotation circuit.
This image forming apparatus is provided with a division control circuit for writing and reading data into and from a data memory in units of predetermined bits, and an output control circuit for switching the bit direction of read image data.

(Function) Therefore, the address generation circuit and the division control circuit perform writing/reading to/from the image data memory in predetermined bit units according to the generated address in response to a writing/reading switching instruction for the image data memory, and the output control circuit Under the control of this division control circuit, the bit direction of the read image data is switched and outputted as predetermined data.

(Embodiment) Now, one embodiment of the present invention will be explained with reference to the drawings. Note that elements having the same function are given the same reference numerals.

FIG. 1 is a block diagram and waveform diagram showing an embodiment of the present invention, and the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 6 to 27.

Figure 1 is a block diagram, and 1a is a pitch in the X direction (a
is an integer multiple of 2), and a' pitch) in the Y direction (a' is an integer multiple of 2). Images are stored, the structure of which is shown in the explanatory diagrams of FIGS. 6 to 8. 6 is an address generation circuit that generates and switches write/read addresses depending on whether or not the image data memory 1a is rotated by ±90 degrees; 7 is an address generation circuit that generates one word in units of a bit in the X direction;
It is divided into a' pit units in the Y direction, and writing/reading to and from the image data memory is performed in the a pit unit or a even in the ±90 rotation mode and in the non-rotation mode.
A division control circuit 8 performs division in units of bits, whether the image data outputted from the image data memory 1a remains in units of a bits or a' bits, is aligned to l words, or is divided into bits depending on whether rotation is performed or not. This is an output control circuit that switches the direction or controls according to the demands of the circuit connected to the next stage. Note that a division instruction is given to the address generation circuit 6 and the output control circuit 8 by the division control circuit 7.

FIG. 1(B) is a detailed view of the embodiment shown in FIG. 1(A), and FIG. 1(C) is a waveform diagram of each part shown in FIG. 1(B).

That is, the address generation circuit 6 converts the logical address signal into a physical address signal and generates the image data memory 1a.
multiplexer 9, image data memory 1
A non-rotating decoder 10 and a rotating decoder 11 specifying each address in the X direction and Y direction of a, and a read/write circuit that supplies memory read/write signals to the image data memory 1a using a counter enable signal and a counter output signal.
It is composed of a light controller 12. The division control circuit 7 includes a division counter 13 that counts and outputs a clock signal using a counter enable signal, and a decoder 1 that controls a logical address signal using this output signal.
Ma supplying 0.11.

It consists of a multiplexer 14. The output control circuit 8 includes a multiplexer 15 that supplies image data outputted from the image data memory 1a according to the output of the division counter 13 to a next stage circuit (not shown) in response to a switching instruction signal. Note that the input/output waveforms of each part are shown corresponding to (a) to (f).

Next, a method of rotating image data according to the above configuration will be explained with reference to FIGS. 6 to 27.

FIG. 6 is a diagram showing the physical structure of the image data memory 1a, which is a matrix-like memory with 6 bits in the x direction (n=an integer multiple of 2) and a' in the Y direction (a': an integer multiple of 2) pits. It is. For ease of explanation, a =
Proceed with a' = 4.

The shaded areas in FIGS. 7 and 8 indicate that 4 bits in the X direction or 4 bits in the Y direction can be selected at one time.

FIG. 9 shows the logical storage space when the image data memory 1a is not rotated by ±90.
Klv K2 K(j-2)*K(j-1) is one page of image data for each line, and FIG. 10 shows the logical space when the contents of the image data memory in FIG. 2 indicates the printing paper, 22 indicates the effective printing range, X indicates printing in the X direction,
Y indicates printing in the Y direction. To make the explanation easier to understand, FIG. 9 will be replaced with FIG. 11, and FIG. 10 will be replaced with FIG. 12. That is, n=151k-1=31j-
1=7. In Figure 11, the length of one word is 16 bits, the logical storage space is at address 311 starting from the O number, and in Figure 12, the length of one digit of the effective printing range is 4 words (64 bits), and the number of printed lines is 8 lines. It is. FIGS. 13 to 16 show how the image data in the logical storage space shown in FIG. 11 is written to the image data memory 1a, and the image data is read 4 bits in the Y direction at once when rotated by 90 degrees. must be written so that it can be issued.

For example, when reading and printing after rotating +90 degrees, first read b15 of the data at logical addresses 28, 24, 20, and 16 at once, then read data at logical addresses 12, 8, 4, and 0 at once. b15 is read out sequentially in units of 4 bits, and finally bO at addresses 15, 11, 7, and 3 are read out, completing the reading.

The first writing to the image data memo IJ 1a is to divide the image data at the logical address O, b15 to b12, into the image data memory 1 as shown in FIG.
The second write to address 0 of physical address θth line (Yo) of a is performed by sequentially writing bll to b8 at address 0 to physical address 1, and writing b3 to bo to address 3. As shown in FIG. 14, writing of one word is completed. , sequentially writes logical address 1 to physical addresses 4 to 7, and writes logical address 3 b3 to bO to physical address 155 as shown in Figure 15, writing one line. Complete.

Similarly, image data from logical addresses 4 to 7 is sequentially performed from 0 to 15 on the first physical address line (Yl), and b3 to bo at logical address 15 are transferred to physical address 3rd line (Y3). 155 logical address 3
1 address b3 to bO to physical address 7th line (Y3) 3
Writing to address 11 As shown in FIG. 16, writing for one page is completed.

Next, a method for reading one page of written image data will be explained.

FIGS. 17 to 20 show a reading method when rotated by +90°, and logical addresses 28, 24, and 20 in FIG. 12.

As explained above, b15 at the 16th location can be read at the same time, but by switching the address generation circuit 6 and division control circuit 7 to Y-direction printing, the physical address corresponds to address 166 of Xo, and the logical address 1
b15 at addresses 2, 8, 4, and 0 correspond to address 0 of the physical address Xo and can be read, and as shown in FIG. 18, the O dot line printed in the Y direction has been read.

Similarly, perform the logical addresses 12, 8, 4 in sequence.
Address, address 0 b12Jc Address 0 of the corresponding physical address are read out and the logical address 1 is read out sequentially.
No. 5, No. 11.

Address 155 of physical address X3, which corresponds to address 7 and bO of address 3, is read out, and as shown in FIG. 20, one address is read out.

Figures 21 to 23 show an example of the reading method during -90' rotation, and Figures 24 and 25 show the divided 1
Word image data b15. b12° is physical space 0
This shows the case where addresses 0-30-3 l-b8 are written in addresses 4-7, b7-b4 are written in addresses 8-11, and b3-bo are written in addresses 12-15. Figure 24, 2nd
This is an example in which reading is performed by rotating +90° with respect to the writing method shown in FIG.

Note that the description of writing and reading is based on the above-mentioned case of +90' rotation.

Now, to simplify the explanation, the length of one word of image data is assumed to be 16 bits, but it goes without saying that this can also be achieved by changing the address switching method even if the length is 4 bits, 8 bits, 32 bits, etc. .

Also included in Figure 1 is an image data memo I) Ia.

Address generation circuit 6, division control circuit? , and can be switched by a multiplexer to realize an even faster image rotor rotation circuit of ±90'.

(Effects of the Invention) As described above in detail, according to the present invention, when image data is rotated by +90', a (an integer multiple of a=2) bit in the X direction and a'(a'=2) in the Y direction are used. image data memory arranged in a matrix of bits (an integer multiple of
Words are divided into a pit units in the X direction or a' bit units in the Y direction, and writing and reading to and from the image data memory is performed in a bit units or a' one bit in both the +90' rotation mode and the non-rotation mode. By having a division control circuit and an address generation circuit that can be made at the same time, high-speed image data storage memory and peripheral circuits can be removed and the device can be made smaller. Therefore, by applying the present invention, the device can be made smaller. It is measured. Furthermore, by configuring the image data memory as a matrix of 4 bits in the X direction and 4 bits in the Y direction, it is possible to use at least 16 chips of dynamic random access memory without losing high speed.
In addition, a 906-rotation circuit can be realized on image data of 16 bits per word, in which the speed during rotation and non-rotation does not change, and economical effects can be expected.

The present invention is applicable to printing devices and display devices that print in negative units.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram according to an embodiment of the present invention, (
(b) is its detailed diagram, (c) is its waveform diagram, Fig. 2 is a block diagram of a conventional image data rotation circuit, and Fig. 3 shows address allocation of a conventional image data memory and image data expansion memory. An explanatory diagram, FIG. 4 is a flowchart showing the read procedure of the image data memo memory when conventional image data is rotated by 190 degrees, and FIG. Flowchart showing the read procedure, FIG. 6 is a structural diagram of the image data memory, FIG. 7 is an explanatory diagram showing that the image data memory can be accessed in units of 4 bits in the X direction, and FIG. 8 is a diagram showing how the image data memory can be accessed in the Y direction. Explanatory diagram showing that access is possible in 4-bit units, No. 9
The figure is a layout diagram showing the logical address space of the image data memory when 90 rotations are not performed, FIG. 10 is an explanatory diagram showing the relationship between the logical address space of the image data memory of FIG. 9 and printing, and FIG. In contrast to Figure 9, the first layout diagram shows the case where the length is 1 word and the address space is set to a certain value.
Fig. 2 is an explanatory diagram showing the relationship between the logical address space of the image data memory in Fig. 11 and printing; Figs. 13 to 16 are explanatory diagrams showing an example of a method of writing to the image data memory; ~ Figure 20 is +90
FIGS. 21 to 23 are explanatory diagrams showing an example of a method for reading out an image data memory during 190 rotations; FIG. 24; FIG. 25 is an explanatory diagram showing a method of writing to an image data memory, and is an explanatory diagram showing an embodiment other than those shown in FIGS. 13 to 16, and FIG. FIG. 27 is a diagram showing a +90 rotation reading method for the image data writing method shown in FIGS. 24 and 25. 7g is an image data memory, 6 is an address generation circuit,
7 is a division control circuit, 8 is an output control circuit, 9 is a multi-breather, 10 is a non-rotation decoder, 11
1 is a rotation decoder, 12 is a read/write controller, 13 is a dividing connector, and 14 is a multi-branch. Patent Applicant: Oki Electric Industry Co., Ltd. (1st Open-) Figure 1 (C) (l 'cut') 1 Figure 2 Figure 3 it Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] X direction a where image data is stored (a = integer multiple of 2)
The image data memory is arranged in a matrix of bits in the Y direction a'(a' = an integer multiple of 2) and the image data is written and read in units of a bits in the X direction or in units of a' bits in the Y direction. Instructs the address generation circuit and an output control circuit, which will be described later, to perform divided writing and reading to the image data memory in units of a bits in the X direction or in units of a' bits in the Y direction. It is equipped with a division control circuit and an output control circuit that switches the bit direction of the read image data according to instructions from the division control circuit and instructions on whether or not to rotate the image data by ±90 degrees, and rotates the image data by ±90 degrees in negative units. An image data rotation circuit characterized by: