JPS6486717A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- JPS6486717A JPS6486717A JP62245107A JP24510787A JPS6486717A JP S6486717 A JPS6486717 A JP S6486717A JP 62245107 A JP62245107 A JP 62245107A JP 24510787 A JP24510787 A JP 24510787A JP S6486717 A JPS6486717 A JP S6486717A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- frequency divider
- frequency
- output
- clearing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To shorten a phase leading-in time by clearing the count of a frequency divider in case of a considerable deviation between the phase of an input signal and that of the frequency divider output and releasing this clearing at the next phase lock point. CONSTITUTION:A voltage proportional to the phase difference between an input signal and the output of a frequency divider 5 is outputted by a phase comparator 1 and has a high frequency component eliminated by a low-pass filter 3, and the oscillation frequency of a voltage controlled oscillator 4 is controlled by the output voltage of the low-pass filter 3, and the frequency divider 5 divides the frequency of the output of the voltage controlled oscillator 4. If phase deviation is detected by a phase deviation detecting part 2, the count of the fre quency divider 5 is cleared, and this clearing is released at the next phase lock point to start counting of the frequency divider 5 again. Thus, the phase leadingin time at the time of operation start is shortened even in case of a PLL circuit which has the frequency divider having a high frequency division ratio in the feedback loop.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62245107A JPS6486717A (en) | 1987-09-29 | 1987-09-29 | Phase locked loop circuit |
US07/248,799 US5068752A (en) | 1987-09-29 | 1988-09-26 | Apparatus for recording/reproducing a digital audio signal with a video signal |
DE88308932T DE3883907T2 (en) | 1987-09-29 | 1988-09-27 | Device for recording and reproducing digital signals. |
KR1019880012485A KR920008110B1 (en) | 1987-09-29 | 1988-09-27 | Digital signal recording and reproducing device |
EP88308932A EP0310330B1 (en) | 1987-09-29 | 1988-09-27 | Digital signal recording/reproducing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62245107A JPS6486717A (en) | 1987-09-29 | 1987-09-29 | Phase locked loop circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6486717A true JPS6486717A (en) | 1989-03-31 |
Family
ID=17128721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62245107A Pending JPS6486717A (en) | 1987-09-29 | 1987-09-29 | Phase locked loop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6486717A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0575454A (en) * | 1991-09-13 | 1993-03-26 | Sanyo Electric Co Ltd | Pll circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5115391A (en) * | 1974-07-29 | 1976-02-06 | Tokyo Shibaura Electric Co |
-
1987
- 1987-09-29 JP JP62245107A patent/JPS6486717A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5115391A (en) * | 1974-07-29 | 1976-02-06 | Tokyo Shibaura Electric Co |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0575454A (en) * | 1991-09-13 | 1993-03-26 | Sanyo Electric Co Ltd | Pll circuit |
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