JPS6486076A - Ic testing system - Google Patents

Ic testing system

Info

Publication number
JPS6486076A
JPS6486076A JP62244823A JP24482387A JPS6486076A JP S6486076 A JPS6486076 A JP S6486076A JP 62244823 A JP62244823 A JP 62244823A JP 24482387 A JP24482387 A JP 24482387A JP S6486076 A JPS6486076 A JP S6486076A
Authority
JP
Japan
Prior art keywords
rank processing
processing apparatuses
program line
test
lower rank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62244823A
Other languages
Japanese (ja)
Other versions
JP2627751B2 (en
Inventor
Motoo Ueda
Shinpei Hasegawa
Toshiyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP62244823A priority Critical patent/JP2627751B2/en
Publication of JPS6486076A publication Critical patent/JPS6486076A/en
Application granted granted Critical
Publication of JP2627751B2 publication Critical patent/JP2627751B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To rapidly perform the DC test to an element to be tested, by employing a hierarchical structure wherein a higher rank processing apparatus exclusively controls whether a program line is executed and the actual execution of the program line is performed so as to be dispersed to a plurality of lower rank processing apparatuses. CONSTITUTION:An IC testing system employing a hierarchical structure is constituted using a plurality of processing apparatuses 21, 23 and the higher rank processing apparatus 21 controls that a test program is executed at a program line unit and the actual reading and execution of the control content described in the program line are entrusted to the lower rank processing apparatuses 23A-N controlled by the higher rank processing apparatus 21. Exclusive memory devices 27A-N storing the statuses relating to hardware modules 25 to be connected are provided to the lower rank processing apparatuses 23A-N and the lower rank processing apparatuses 23A-N use the exclusive orders thereof to access the hardware modules or to renew the test statuses.
JP62244823A 1987-09-28 1987-09-28 IC test system Expired - Fee Related JP2627751B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62244823A JP2627751B2 (en) 1987-09-28 1987-09-28 IC test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244823A JP2627751B2 (en) 1987-09-28 1987-09-28 IC test system

Publications (2)

Publication Number Publication Date
JPS6486076A true JPS6486076A (en) 1989-03-30
JP2627751B2 JP2627751B2 (en) 1997-07-09

Family

ID=17124484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62244823A Expired - Fee Related JP2627751B2 (en) 1987-09-28 1987-09-28 IC test system

Country Status (1)

Country Link
JP (1) JP2627751B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011001462A1 (en) * 2009-06-29 2011-01-06 株式会社アドバンテスト Test apparatus
KR101138196B1 (en) * 2008-01-23 2012-05-14 가부시키가이샤 어드밴티스트 Testing apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7290192B2 (en) 2003-03-31 2007-10-30 Advantest Corporation Test apparatus and test method for testing plurality of devices in parallel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5186368A (en) * 1975-01-27 1976-07-28 Suwa Seikosha Kk Handotaisochinoshikensochi

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5186368A (en) * 1975-01-27 1976-07-28 Suwa Seikosha Kk Handotaisochinoshikensochi

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101138196B1 (en) * 2008-01-23 2012-05-14 가부시키가이샤 어드밴티스트 Testing apparatus
WO2011001462A1 (en) * 2009-06-29 2011-01-06 株式会社アドバンテスト Test apparatus
JPWO2011001462A1 (en) * 2009-06-29 2012-12-10 株式会社アドバンテスト Test equipment
KR101239658B1 (en) * 2009-06-29 2013-03-11 가부시키가이샤 어드밴티스트 Test apparatus

Also Published As

Publication number Publication date
JP2627751B2 (en) 1997-07-09

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