JPS6484921A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPS6484921A
JPS6484921A JP24214287A JP24214287A JPS6484921A JP S6484921 A JPS6484921 A JP S6484921A JP 24214287 A JP24214287 A JP 24214287A JP 24214287 A JP24214287 A JP 24214287A JP S6484921 A JPS6484921 A JP S6484921A
Authority
JP
Japan
Prior art keywords
output
input
comparator
inverter
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24214287A
Other languages
Japanese (ja)
Inventor
Akira Yugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24214287A priority Critical patent/JPS6484921A/en
Priority to DE3854414T priority patent/DE3854414T2/en
Priority to US07/249,158 priority patent/US5010347A/en
Priority to EP88115804A priority patent/EP0308982B1/en
Publication of JPS6484921A publication Critical patent/JPS6484921A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a delta/sigma modulator for operating satisfactorily even in case of a small signal by providing a means for generating a white noise of one bit, and a means for superposing the difference of values at two continuous sampling time points of its noise, to the input of a comparator. CONSTITUTION:With respect to the input of a comparator 8 in the delta/sigma modulator A, a noise generating part B constituted of a means for taking a difference at two continuous sampling time points of the output of an inverter 15 by taking the sum of a white noise generating means 13 of one bit, a D-type FF14 for delaying its output 11 by 1 sampling time, an inverter 15, the output 11 and the output of the inverter 15 is provided, and its output is superposed to the input of the comparator 8. The output 4 of an adder 16 can take three kinds of values of '0', '1', and 2, and in case of superposing them, '0', '1', and 2 correspond to -1, '0' and '1', respectively. In such a way, by adding a noise component, even when an input signal is small, a satisfactory S/N characteristic can be obtained, and an A/D converter for satisfying various specifications can be realized.
JP24214287A 1987-09-25 1987-09-25 A/d converter Pending JPS6484921A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP24214287A JPS6484921A (en) 1987-09-25 1987-09-25 A/d converter
DE3854414T DE3854414T2 (en) 1987-09-25 1988-09-26 AD converter with excellent signal-to-noise ratio for small signals.
US07/249,158 US5010347A (en) 1987-09-25 1988-09-26 Analog-to-digital converter having an excellent signal-to-noise ratio for small signals
EP88115804A EP0308982B1 (en) 1987-09-25 1988-09-26 Analog-to-digital converter having an excellent signal-to-noise ratio for small signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24214287A JPS6484921A (en) 1987-09-25 1987-09-25 A/d converter

Publications (1)

Publication Number Publication Date
JPS6484921A true JPS6484921A (en) 1989-03-30

Family

ID=17084939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24214287A Pending JPS6484921A (en) 1987-09-25 1987-09-25 A/d converter

Country Status (1)

Country Link
JP (1) JPS6484921A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008221418A (en) * 2007-03-14 2008-09-25 Nachi Fujikoshi Corp Broach for internal gear machining
JP2009510912A (en) * 2005-09-30 2009-03-12 エヌエックスピー ビー ヴィ System and method for adjusting dither in a delta-sigma modulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009510912A (en) * 2005-09-30 2009-03-12 エヌエックスピー ビー ヴィ System and method for adjusting dither in a delta-sigma modulator
JP2008221418A (en) * 2007-03-14 2008-09-25 Nachi Fujikoshi Corp Broach for internal gear machining

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