JPS6484494A - Address level holding circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of the titled circuit even when the high level of the holding data is reduced by adding a high level holding circuit to a flip flop circuit currently in use, and supplementing the reduced high level. CONSTITUTION:At a t1 time when an X address data bus and the inverse of X are in a level holding condition, when a noise signal to exceed a transistor (Tr) threshold generates at a signal SW, or when the level of a data bus the inverse of XY turns from low to high, and the signal SW temporarily changes from a low condition to a high condition, Trs Q1 and Q2 are turned on. As this result, the level of the data bus X is reduced down to that of the data bus XY. The level of the data bus the inverse of XY is transferred, Tr QA of an FF circuit is turned on, and the level of the data bus X is reduced. Therefore, a Tr QF1 of the high level holding circuit is turned on, and the level of the data bus X is supplemented up to the original high level. Thus, the malfunction due to the noise, etc., can be prevented.