JPS6481521A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS6481521A
JPS6481521A JP62239820A JP23982087A JPS6481521A JP S6481521 A JPS6481521 A JP S6481521A JP 62239820 A JP62239820 A JP 62239820A JP 23982087 A JP23982087 A JP 23982087A JP S6481521 A JPS6481521 A JP S6481521A
Authority
JP
Japan
Prior art keywords
circuit
primary
switch
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62239820A
Other languages
Japanese (ja)
Other versions
JPH0436605B2 (en
Inventor
Yoshio Oida
Hisashi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62239820A priority Critical patent/JPS6481521A/en
Publication of JPS6481521A publication Critical patent/JPS6481521A/en
Publication of JPH0436605B2 publication Critical patent/JPH0436605B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To realize an interface circuit with low power consumption by providing a switch circuit to a 1st current mirror circuit, controlling the switch circuit by an output of a CMOS circuit so as to couple and separate the primary and secondary sides. CONSTITUTION:The 1st current mirror circuit consists of N-channel DMOS D3, D4 and switch circuits T1, T2 are provided between a common connecting point between the gate and drain of a TR D3 of the primary side and the gate of the TR D4 of the secondary side. Then the primary and secondary sides are controlled to be separated and coupled by the switch circuit thereby utilizing the primary side in common as a constant voltage generating circuit at circuit sections 101, 10n. Thus, a current flowing between the terminal VDD and a ground GND terminal is always Iref independently of the number of output bits, that is, the number of output stages, then the interface of multi-bit is constituted without increasing the current consumption.
JP62239820A 1987-09-24 1987-09-24 Interface circuit Granted JPS6481521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62239820A JPS6481521A (en) 1987-09-24 1987-09-24 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62239820A JPS6481521A (en) 1987-09-24 1987-09-24 Interface circuit

Publications (2)

Publication Number Publication Date
JPS6481521A true JPS6481521A (en) 1989-03-27
JPH0436605B2 JPH0436605B2 (en) 1992-06-16

Family

ID=17050335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62239820A Granted JPS6481521A (en) 1987-09-24 1987-09-24 Interface circuit

Country Status (1)

Country Link
JP (1) JPS6481521A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177816B1 (en) 1997-06-17 2001-01-23 Nec Corporation Interface circuit and method of setting determination level therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177816B1 (en) 1997-06-17 2001-01-23 Nec Corporation Interface circuit and method of setting determination level therefor

Also Published As

Publication number Publication date
JPH0436605B2 (en) 1992-06-16

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees