JPS6461117A - Semiconductor output circuit - Google Patents

Semiconductor output circuit

Info

Publication number
JPS6461117A
JPS6461117A JP62216411A JP21641187A JPS6461117A JP S6461117 A JPS6461117 A JP S6461117A JP 62216411 A JP62216411 A JP 62216411A JP 21641187 A JP21641187 A JP 21641187A JP S6461117 A JPS6461117 A JP S6461117A
Authority
JP
Japan
Prior art keywords
trs
level
channel
turned
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62216411A
Other languages
Japanese (ja)
Inventor
Kazumasa Matsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62216411A priority Critical patent/JPS6461117A/en
Publication of JPS6461117A publication Critical patent/JPS6461117A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce power noise and ground noise by providing plural output transistors(TRs) deciding the potential at an output terminal and a control circuit for an inverter controlling the output TRs with a different timing. CONSTITUTION:In bringing a node A from 'H' level to 'L' level, an N-channel TR tr is turned off and a power supply VDD and an output terminal 0 are disconnected. In bringing the level of the node I from 'H' to 'L' level, P-channel TRs tB1, tB2,...tBi are turned on and N-channel TRs tC1, tC2,...tCi are turned off. Since the resistance of resistors R1, R2...Ri is in the relation of r1<r2<...<ri in this case, a delay of leading is caused in the order of nodes 1, 2-i. As a result, the current flowing from the output terminal 0 to ground GND is shared to i-set of the N-channel TRs tA1, tA2, tAi, thereby reducing the peak current and reducing ground noise.
JP62216411A 1987-09-01 1987-09-01 Semiconductor output circuit Pending JPS6461117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62216411A JPS6461117A (en) 1987-09-01 1987-09-01 Semiconductor output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62216411A JPS6461117A (en) 1987-09-01 1987-09-01 Semiconductor output circuit

Publications (1)

Publication Number Publication Date
JPS6461117A true JPS6461117A (en) 1989-03-08

Family

ID=16688138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62216411A Pending JPS6461117A (en) 1987-09-01 1987-09-01 Semiconductor output circuit

Country Status (1)

Country Link
JP (1) JPS6461117A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950002233A (en) * 1993-06-22 1995-01-04 프레데릭 얀 스미트 Integrated circuit with output stage to reduce noise

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950002233A (en) * 1993-06-22 1995-01-04 프레데릭 얀 스미트 Integrated circuit with output stage to reduce noise

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